TWM288055U - Phase lock circuit for switching power supplies - Google Patents

Description

:M288055 VIII. New description: [New technical field] This creation side is a kind of switching controller with phase lock and phase locking device, especially one used in switching type electric device - The device and controller of the valley bottom voltage of the resonant rake generated on the city switch. [Prior Art], switching power supply is used to convert unregulated power into a stably adjustable voltage or electric two-switching power supply t, should mainly include - transformer or - magnetic component, with - secondary side The windings and the side windings are used to provide electrical isolation. A switch surface is connected to the primary winding of the transformer for controlling the transmission of power between the side of the person and the side windings. Switching power supplies operate at high cost, reduced V volume and weight. However, the switching action of the diverter switch generates switching loss and electromagnetic interference (MI). The first figure is a conventional flyback power supply. The second figure is a schematic diagram of the working waveform of the first figure. As shown in the first figure, _OFF Qi causes the switching to transform it T1, and controls the transmission of power between the primary side of the transformer T1, ΛΝρ曰', and a residual Ns. When the control signal vG controls the switch q to be turned on, the second day is stored in 趟α. When the control ship Vg is switched off, the amount of t is stored in the variable pressure device and will be released through the rectifier D〇 to the fly-off power supply. At the same time, the reflected voltage vR is generated at the primary side winding NP of the transformer 1 in accordance with the output voltage v 返 of the flyback power supply and the transformer Τ. Therefore, when the switching M Q1 is turned off, the voltage % across the switching switch 〇 1 is equal to the input power, V: plus the reflected voltage Vr. The voltage stored on the switch _ Qi is stored in the switch (4). After the Tds on the valley Cj, the stored energy of the transformer D is completely released, and the energy stored in the parasitic capacitance Cj is transmitted. The transformer Τι-sub-side winding Np is transmitted back to the input cake. This day = the electricity generation valley Cj and the Weier Τι-the secondary winding called the inductance ^ composition - resonance group _ plus tank) 'The resonance word 4 can be from below Equation (1) means: 6 M288055 fR=_1_

2^^/Lp x Q ------------------------------(l) During the period of V and vibration, 'parasitic The energy stored in the electric valley CjJl will be transferred back and forth to the inductance Lp of the secondary side of the transformer Ti. The delay time Tq is the time at which the terminal voltage ν 寄生 on the parasitic capacitance q starts to discharge from the peak voltage to the valley voltage. The time delay time Tq in which the delay time % is a quasi-resonance (quasi_rcs_t) can be expressed by the following formula (2): '=丄4XfR-..................... . . . (2) Referring back to the second figure, the switching switch Qi used by the conventional flyback power supply will perform the switching operation under high pressure, and the switching loss will occur, and the resonance period will be generated. Electromagnetic interference. If the voltage VD at the Cj terminal of the power transmission valley is at the bottom of the valley _ conduction switching _ Q1, then the switching can be performed at the terminal voltage of the switching switch Q , to reduce the switching loss and reduce the electromagnetic interference, and the switching can be achieved. Improve system efficiency of power converters. Wood [new content]

There are ^^柳嫩—__, 姆-顺娜应器=switching_stop, the wire lock is an example of the resonance generated by the switching. The peak of the wave to be measured, and then the resonance voltage is at The bottom of the valley is used to achieve flexible switching and improve the system efficiency of the switched power supply. , Khan Ge's creation of a phase-locking device, including a run-time test - ☆ After the delay time, the signal to be tested is sampled and controlled - the start signal is sampled, and the "post-to-process" signal is sampled by Obtained - the second sampling power, - the extension surface unit, touches the first - sampling voltage 赖 ~ * early series connected to the Ming - connected to the lower unit, the number of the lower t shouting, the output is adjusted Signal, · a delay circuit connection early to receive the up and down counting signal - capacitor domain, "flow control in _ _ ^ ^ ^, gamma - current source series capacitor for charging action, charging time is the size of the variable wheel current 'To delay the control circuit, the delay control circuit is connected to the 7 M288055 delay circuit, controlled by the start signal to discharge the capacitor, and compare the charging voltage value of the capacitor to output a control signal When the first sampling voltage is close to the second sampling voltage, it is determined that the signal to be tested has reached the peak value. The above summary and the following detailed description are exemplary in order to further illustrate the scope of the patent application of this creation. Other purposes and advantages related to this creation will be explained in the following descriptions and illustrations. </ br> [Embodiment] Please refer to the third figure, which is a schematic diagram of the switching power supply circuit of the preferred embodiment of the present invention. The switching control device 50 includes at least a feedback terminal FB, a current sensing terminal cs, an input terminal %, and an output terminal. The output terminal generates a drive 5 to drive the switch Q. The switch Q is used to switch-transformer TR (or - magnetic element), and a switching current signal j vcs is generated on the current sensing resistor Rs. The transformer ^ includes a primary winding 沁, a secondary winding Ns and an auxiliary winding Να. The primary side winding is depleted to the diverter switch Qi. The secondary winding Ns passes through the rectifier D〇 and the output capacitor to the output of the switching power supply. The auxiliary winding na is supplied with power through the other-rectifying n Da and the capacitor CsT rib to the switching control band = resistance ra is between the auxiliary winding Na and the input terminal of the switching control device 5: through the resistance rk face is reduced to The output of the switching power supply is used to obtain the output and output the return Vfb to the feedback terminal fb of the switching control device 5〇. Cut Qing: Set the receiving feedback signal Vfb and switch the current signal, and the rib output-switching signal 2 drive 5«VPWM' to stabilize the output voltage V of the Na-type electric wire. . With the third figure, please refer to the fourth figure, which is a schematic diagram of the preferred embodiment of the present invention. The switch-type control key with the phase-locking device is set to 50 packs - the electric knife flow is 9 turns. In: 贞 phase 』 produces 単 70 104, a phase-locking device (10) and - pulse width generating circuit through the resistance &amp; touch the egTR_Wei (four) to the living unit (10) • the shredded (10) generated resonance voltage signal, and then with 8 M288055 Different, used to output - start signal sDS. T^«-^Na, the positive terminal (1) of the operational amplifier 中 in the A-turn voltage unit 102 is connected to the second one: 'The negative terminal (1) is reduced to the resistance Ra', and the output terminal thereof controls the transistor (3): 50 : The source of the body (3) is trained to the resistance &amp; In this way, the switching control device with the phase locking device is composed of the minimum current on the resistor Ra, which is composed of the input current mirror 曰, 曰曰 _ Q4Q3, and the transistor Q2 is connected through the transistor Q4. The resistor RA, the electric Γ τ - 1 into the step - connected with - R3. The current is transferred to the unit 102 resistor and the electric power on the device. The signal to be measured is the voltage drop generated by the electric crystal dream body Q3 outputting current ι3 to the resistor r3. The pulse width generating circuit 9A includes at least a flip-flop 53, a comparator Μ, and a resistance shift %. The resistor Rs is mixed with the feedback terminal fb of the switching control device having the phase locking device to pull back the signal VpB to the high level. The positive terminal (+) of the comparator 55 is retracted by the offset power %. The offset voltage V57 provides a level shift for the feedback signal Vfb. ^^ (-) 5〇 = The knife replaces the current signal Vcs and achieves pulse width modulation control. The output of comparator % is switched to the reset terminal R of positive and negative 53. The output terminal Q of the flip-flop 53 outputs a switching signal and the path 54 generates a driving signal ν_. The team pulls out the power phase lock device and connects to the current power switch, the start signal generates a single A and t=G, and when the switch Q1 is cut off, it is controlled by the start signal Sds, _ test the test signal%

The peak value of the wave, and then the output-control signal is informed to the clock terminal (3) of the flip-flop 53 to control the flip-flop B: the switching signal Sw' output from the output terminal Q to turn on the switching switch Qi. The phase lock device is based on the voltage signal &amp; generated on the auxiliary winding Na of the transformer TR to enable the switching signal Sw of the output of the flip-flop %. The voltage signal % generated on the auxiliary winding Na is proportional to the health VD across the switching ON. Therefore, the switching operation of the switching switch Q! is turned on according to the valley voltage across the switching gate. Please refer to the fourth figure, referring to the fifth figure, for the purpose of creating a phase-locked circuit block of the preferred embodiment of the present invention. The phase lock device 100 includes a sampling unit 106, a comparison unit 1〇8, an up and down counting unit 1〇7, a delay circuit 1 and a delay control circuit 1〇9〇. The sampling unit A 1〇6 is connected to the start signal generating unit 104 and the current converting voltage unit 1〇2, and is controlled by the start signal sDS of the start signal generating unit 1〇4, which is a delay-first delay. After the time Tp, the current-to-voltage unit 1〇2 output=the sfl number VM to be tested is sampled to obtain a first sampling voltage Vi' and then passed a second delay time I. After that, the signal to be tested is sampled to obtain a second sampling voltage v2. The comparison unit 108 is connected to the sampling unit 106, and receives the first sampling voltage % and the second sampling voltage V2, and compares and calculates the first sampling voltage Vi and the second sampling voltage % to output an up-down counting signal UP. /DOWN. The up-and-down counting unit 107 is connected to the comparing unit, receives the _up-down counting signal UP/DOWN, and outputs an adjustment signal sA. A delay circuit 1091 is connected to the upper and lower counting unit 107, and is composed of a current source connected in series with a capacitor Q. The current source Is is controlled by the adjustment signal Sa to change the current value and charge the capacitor core. The charging time is the first delay time Tp. A delay control circuit 1 is connected to the delay circuit 1091, controlled by the start signal sDS and a switching signal Sw, and is discharged through a general discharge of a discharge switch &amp; to discharge the capacitor Q, and compare the capacitor Q The charging voltage value on the output to output the control signal SN. In summary, when the first sampling voltage % is close to the second sampling voltage %, it is determined that the signal to be tested VM has reached the peak value. When the first sampling voltage is less than the second sampling voltage, the spring up and down counting unit 107 controls the current source Is to reduce the current value for extending the first delay time τΡ. On the contrary, the up-and-down counting unit 107 controls the current source Is to increase the current value for shortening the first delay time Tp.

In the above description, the delay control circuit 1090 includes at least a comparator 1096, a discharge switch S3, a reverse phase inverter 1092, and a reverse gate 1 〇 94. The first end of the gate 1094 receives the start signal sDS, the second end receives the switching signal Sw through the inverter 1092, and the output terminal controls the conduction switch S3 to be turned on or off. The discharge switch S3 is turned on to discharge the capacitor c3. The positive terminal (+) of the comparator 1096 is coupled to the capacitor Q. A threshold voltage Vy is supplied to the negative terminal (1) of the comparator 1096. When the discharge switch S3 is turned off and the voltage on the capacitor Q is charged by the current source is higher than the threshold voltage vy, the comparator 1096 rotates the high potential control signal SN. The current source Is and the capacitor C3 determine a first delay time τ 之间 between the start signal sDS and the control signal SN M288055. Referring to the fifth figure, the sampling unit 106 includes a sample signal generator 1〇62 for outputting the first sample signal 8 (31 and the second sample signal Sq2. The sample signal generator 1062 is composed of the flip-flops 32, 33组成 and inverters 325, 335. The clock terminals CK of the flip-flops 320 and 33 接收 receive the start signal s 〇 s. The reset terminal R of the positive and negative 320 receives the switching signal through the inverter 325 The reset terminal R of the flip-flop 330 receives the driving signal VpwM through the inverter 335. At the same time, referring to the fourth figure, the driving signal VPWM is generated by the transmission delay of the switching signal Sw through the output circuit 54, thus driving the signal The phase is different from the switching signal sw by the second delay time Tdi. Therefore, the sampling signal generator 1〇62 is enabled according to the start signal sDS, and the first sampling signal and the second sampling signal SQ2 are sequentially outputted at intervals of the second delay time Tdi. The sampling unit 70 106 further includes a first sampling switch &amp; coupled between the resistor R3 of the current-turning voltage unit 1〇2 and the first capacitor C, the first sampling switch s! is controlled by the first sampling signal Sqi, used to capture the signal to be tested VM, and a first sampling voltage Vi is generated on the first capacitor q; and a second sampling switch S2 is coupled between the resistor R3 of the current-turning voltage unit 102 and the second capacitor &amp; the second sampling switch S2 is controlled by the first The second sampling signal Sq2 is used to capture the signal Vm to be tested, and generate a second sampling voltage V! on the second capacitor q. The negative terminal (-) of the comparing unit 108 is connected to the first capacitor 〇1, The positive terminal (+) is connected to the first electric valley q through the offset electric voltage V0FT. The comparison unit 1〇8 receives the first sampling voltage % and the second sampling voltage %, and then compares the output upper and lower signals UP/D〇. WN. Next, the up-and-down counting unit ι〇7 receives the up-and-down signal UP/DOWN, and when the switching signal Sw is turned on before the valley voltage of the switch (ie, before the peak of the signal to be tested vM), the up-and-down signal up/D 〇WN will enable up and down counting early το 107 up counting. When the switching signal Sw is turned on after switching the bottom voltage of the switch (ie after the peak value of the signal to be tested vM), the up and down signals UP/D0WN will be enabled The counting unit 107 counts down. With the fourth figure, please refer to the Working waveform schematic diagram creation system of the present preferred embodiment of the lock apparatus in accordance with a current flowing through the resistor RA Ias current generating transistor Q3 is a current l3 l3 table may not:. 11 (3) M288055

—Vref — Va R, VA is a transformer. I2 is the current of the transistor Q2; Ra is the voltage of the auxiliary winding NA of the resistance Tr of the resistor ^. The start signal generating unit 104 is connected to the output start signal SDS on the auxiliary winding team. When the voltage signal V is lower than: β狁A is used for (^t.)〇? WSDS#^^ The current mirror V consisting of Q2 and Q3 is the current mirror V, pm, _ resistance 3 to produce a ratio of electricity to the signal

^^ shouts VM. In view of the waveform of the electric M signal Va, the valley bottom Vv is interesting, and the f direction of the object flows from the input terminal % of the switching control device 5〇 to the auxiliary winding Να, so the peak value of the VM is the voltage signal%. The bottom of the valley. In conjunction with the red map, please go to the seventh A map and the seventh c map, for the purpose of the peak electric breakdown of the paste. #启始职%顾启嶋蝴蝶, and a delay time TP read, take the fresh 1G6 towel chowder generator (10) to produce the first - take view =, and then through the second delay time Tdi to produce the: sample signal ^. The first sampling signal ^ J-sampling woven SQ2 separately controlled - sampling off &amp; two sampling off &amp;, obtaining the first sampling voltage Vl and the second sampling voltage % from the signal to be tested % when the second sampling voltage ^ is higher than At the first sampling voltage %, the 'first-delay time Tp will increase. When the second sampling voltage is not higher than the first sampling voltage %, the first delay time Tp will be reduced. When the first sampling voltage % is close to the second sampling voltage V2, it is determined that the signal to be tested Vm has reached the peak value. Since the voltage waveform of the switch Qd is proportional to the voltage waveform on the auxiliary winding of the transformer, when the voltage Vd on the switch Q1 is judged, it also represents the voltage city VA $ on the auxiliary winding Na of the transformer A. At the same time, it means that the system has reached the peak value. At this time, the phase-locking device 100 outputs the control signal Sn to control the switching of the switch Qi. In this way, a phase-locking device can be used to lock the peak value of the resonance signal generated by the switching signal when the switching switch is turned off, and the resonance voltage signal is at the bottom of the valley. The next pass through the city gate, with the New Zealand switching type electric hybrid (4) switch loss 12 M288055 and electromagnetic interference 'to achieve flexible switching and improve the system efficiency of the switched power supply. However, the above description is only a detailed description and a detailed description of the specific embodiment of the present invention, but the features of the present invention are not limited thereto, and are not intended to limit the creation, and all the scope of the creation should be as follows. The application of Shen Qing is subject to her, and the embodiment of the spirit and money that changes in the spirit of this book is included in the towel of this _, and the domain is known to be in the field of Lai. Changes or modifications that can be easily considered are covered by the following patents in this case. M288055 [Simple description of the drawing] The first figure is a conventional flyback power supply; the second figure is a schematic diagram of the working waveform of the first figure; The third figure is a circuit diagram of the switching power supply of the preferred embodiment of the present invention. The fourth picture is a block diagram of a domain-controlled woven circuit with a phase-locked device for better creation; the fifth picture is a block diagram of the circuit of the phase-locked device with better compensation; A schematic diagram of the operational waveforms of the phase lock device of the preferred embodiment; and seventh to seventh. Figure _ The best implementation of the sigma peak lag phase lock waveform is not intended. [Main component symbol description] Description of the figure: Convention: Switching transformer TR rectifier D〇 output voltage V〇 input voltage VIN This creation: Parasitic capacitance Cj Photocoupler 45 Switching control device 50 Forward and reverse device 53 Output circuit 54 Comparison Device 55 Resistor R56 Offset voltage v57 Pulse width generation circuit 90 Phase lock device 100 Current to voltage unit 102 Operational amplifier 1022 Start signal generation unit 104 Sampling unit 106 Sample signal generator 1062 Up and down counting unit 107 Comparison unit 108 14 M288055 Delay control Circuit 1090 Inverter 1092 Comparator 1096 Inverter 325, 335 Delay Circuit 1091 Reverse Gate 1094 Reversible 320, 330

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Claims (1)

M288055 IX. Patent application scope: 1. The lock phase is set, controlled by a start signal, used to detect the peak value of a signal to be tested, and then rotates a control signal, including: sampling unit, fork control After the first delay time, the signal to be tested is sampled to obtain the first-sampling voltage, and after the second delay time, the sample to be scrambled is sampled to Obtaining a second sampling voltage; comparing the single 7C, connecting to the sampling unit, receiving the first sampling voltage and the second sampling voltage 'comparing the first sampling voltage and the second sampling voltage, and outputting an up-down count The upper and lower counting unit 70 is connected to the comparing unit and receives the up and down counting signal to output an adjustment signal. The delay circuit is connected to the upper and lower counting unit and is composed of a current source connected in series with a capacitor. The motor source is controlled by the adjustment signal to change the current value, and the charging operation is performed, the charging time is the first delay time; and the L delay control circuit is connected to the delay power Controlled by the start and the switching signal, the capacitor is discharged through the conduction of the discharge switch, and the charging voltage 0 value of the capacitor is compared to output the control signal; the eighth sampling voltage of the Yachida When the second sampling voltage is close, it is determined that the signal to be tested has reached the peak value. 2. The phase-locking device as described in the scope of the patent scope of the cap, the sampling material enters the _step receiving-drive signal, and the switch is switched. According to the switch, the ribbed mosquito is delayed. 3. If the first sampling voltage is less than the second sampling voltage, the upper and lower counting units control the current source to reduce the current value, for extending the The first delay is 16 M288055. If the phase-locking device described in claim 1 is used, the first sampling voltage is greater than the second sampling voltage %'. The upper and lower counting units control the current source to increase the current value. Used to shorten the first delay time. 5. - Switching control with a phase-locking device, so that the switch-switching type of the device is connected to a switch-off signal, controlled by the start signal, for controlling the start signal Extracting the peak value of the __ signal of the -resonance voltage signal generated on the switch, and then outputting a control signal to turn on the switch, including: starting and generating a single 70, transmitting through a resistor The resonant voltage signal is a comparison between the resonant voltage signal and the -threshold voltage for outputting the start signal; - a current-to-voltage unit connected to the resistor to convert the current flowing through the resistor into a ratio to the resonance a signal to be tested of the voltage signal; a sampling unit connected to the start signal generating unit and the current-to-voltage unit, controlled by the start signal, after the first-delay time, sampling the signal to be tested In order to obtain a first sampling voltage, and after a second delay time, the signal to be tested is sampled to obtain a second sampling voltage; the stomach unit is connected to the sampling unit, and the first unit is received. And the second sampling electric power ««' comparison operation of the first sampling voltage and the second sampling power, output - up and down counting signal; an upper and lower counting unit connected to the comparison unit integer signal; receiving the up and down counting Signal, output one-control 3-way, connected to the delay circuit, controlled by the start signal and the -switch signal, the off-conductor is used to discharge the capacitor, and compare the charging voltage value of the capacitor to Outputting the control signal; packet 17 M288055, wherein when the first sampling voltage is close to the second sampling voltage, it is determined that the signal to be tested has reached a peak value. 6. The phase-locking device of claim 5, wherein the sampling unit further receives a driving signal and the switching signal, and determines a second delay time according to a phase difference between the driving signal and the switching signal. 7. The switching controller with a phase locking device according to claim 5, wherein the upper and lower counting units control the current source to reduce the current value when the first sampling voltage is less than the second sampling voltage, Extend the first delay time. Lu Rushen: The phase-locking device according to Item 5 of the patent, wherein the first sampling voltage is greater than the second sampling, and the electric holding λ upper and lower units control the current source to increase the current value, thereby shortening the The first delay time. 18