TWI856552B - Memory device and compensation method of data retention thereof - Google Patents

Abstract

A memory device, such as a 3D AND type flash memory, and a compensation method of data retention thereof are provided. The compensation method includes: performing a reading operation on each of a plurality of programmed memory cells of the memory device; judging whether each of the programmed memory cells occurs charge loss phenomenon to set each of the programmed memory cells to be a charge loss memory cell; and, performing a refill program operation on the charge loss memory cells.

Description

Memory device and data retention compensation method thereof

The present invention relates to a memory device and a compensation method thereof, and in particular to a memory device and a compensation method thereof that compensates for data retention by supplementing programmed actions.

With the advancement of electronic technology, electronic products have become an important tool in people's lives. In order to provide reliable and large amounts of data information, it is an inevitable trend to install high-reliability memory devices in electronic products.

In today's technology, flash memory devices have become a mainstream data storage medium in electronic devices. However, flash memory cells may have reduced reliability under high program and erase cycles (PE cycles). Flash memory cells with reduced reliability may have reduced charge retention capacity. Under long-term storage conditions, the charge in the memory cell may be lost (charge loss) and cause data retention to decrease.

The present invention provides a memory device and a data retention compensation method thereof, which can effectively maintain the storage charge of programmed memory cells.

The data retention compensation method of the present invention includes: performing a read operation on each of a plurality of programmed memory cells in a memory device; determining whether charge loss occurs in each programmed memory cell through the read operation to set each programmed memory cell as a charge loss memory cell; and performing a supplementary programming operation on the charge loss memory cell.

The memory device of the present invention includes a memory block and a controller. The controller is coupled to the memory block. The controller is used to: perform a read operation on each of a plurality of programmed memory cells in the memory device; determine whether charge loss occurs in each programmed memory cell through the read operation to set each programmed memory cell as a charge loss memory cell; and perform a supplementary programming operation on the charge loss memory cell.

Based on the above, the memory device of the present invention detects the charge loss state of the memory cell, and when the charge loss phenomenon of the memory cell is detected, the memory cell is supplemented with a programmed action. In this way, the charge loss phenomenon of the memory cell can be compensated and the reliability of the data can be maintained.

Please refer to FIG. 1, which shows a flow chart of a data retention compensation method of an embodiment of the present invention. In step S110, a read operation can be performed for each of the multiple programmed memory cells in the memory device, and in step S120, the above-mentioned read operation is used to determine whether each programmed memory cell has a charge loss phenomenon. And according to whether each programmed memory cell has a charge loss phenomenon, each programmed memory cell is set as a charge loss memory cell. In detail, in the embodiment of the present invention, a detection operation can be performed on all programmed memory cells in the entire memory device to determine whether a charge loss phenomenon has occurred. The above-mentioned charge loss phenomenon detection operation can be performed by performing a read operation on each programmed memory cell. Through the read operation, the drift state of the critical voltage of each programmed memory cell can be detected. In the embodiment of the present invention, a first threshold voltage and a second threshold voltage can be set in the memory device, wherein the second threshold voltage is greater than the first threshold voltage, and the second threshold voltage can be less than the programming verification voltage of the programmed memory cell in the previous execution of the programming operation. The memory device can also determine whether the critical voltage of the detected programmed memory cell falls between the first threshold voltage and the second threshold voltage. When the critical voltage of the detected programmed memory cell falls between the first threshold voltage and the second threshold voltage, the memory device can determine that the detected programmed memory cell has charge loss and can be set as a charge loss memory cell. When the critical voltage of the detected programmed memory cell does not fall between the first threshold voltage and the second threshold voltage, the memory device does not set the detected programmed memory cell as a charge loss memory cell.

In other embodiments of the present invention, the charge loss phenomenon detection operation can be performed based on multiple partitions in the memory device. Each partition in the memory device can be an erased partition and a programmed partition. The memory device can perform a read operation on the programmed memory cells in the programmed partition to determine whether each programmed memory cell is a charge loss memory cell. The memory device may not perform a read operation on the erased partition.

Next, in step S130, the memory device may perform a supplementary programming operation on the charge-loss memory cell, and perform a charge refill operation on the charge-loss memory cell through the supplementary programming operation, and complete the data retention compensation operation of the memory cell.

In this embodiment, in the supplementary programming action, the memory device can set a programming voltage and provide a single pulse with the programming voltage to perform the supplementary programming action on the charge loss memory cell. In this embodiment, the programmable voltage of the supplementary programming action can be greater than the programming verification voltage of the supplementary programming verification action. The above-mentioned programming verification voltage can be set according to the above-mentioned second threshold value, for example, the programming verification voltage is equal to the above-mentioned second threshold value.

In other implementations, the memory device may also perform the supplemental programming operation on the charge-loss memory cells through an incremental step pulse programming (ISPP) mechanism. The operation details of the ISPP mechanism may be performed in a manner known to those skilled in the art without any limitation.

Please refer to Figure 2 below, which shows a flow chart of a method for compensating the data retention of a memory device according to another embodiment of the present invention. In step S210, the power of the memory device is turned on. In step S220, the memory device can perform a verification operation on the programmed memory cells to determine whether charge loss has occurred. Reference can be made here simultaneously to the schematic diagrams of the data retention compensation operation of the memory device shown in Figure 2 and Figures 3A to 3C. In Figures 3A to 3C, the horizontal axis represents the voltage value of the critical voltage of the memory cell, and the vertical axis represents the number of memory cells. In FIG3A , the distribution curve of the memory cells in the memory device is divided into an erased memory cell distribution curve ER and a programmed memory cell distribution curve PGM. The critical voltages of the memory cells in the programmed memory cell distribution curve PGM are all greater than the programming verification voltage VPV. The read reference voltage VRD for each memory cell to perform a read operation is set between the erased memory cell distribution curve ER and the programmed memory cell distribution curve PGM, and has a sufficiently large distance from the programmed memory cell distribution curve PGM to serve as a read margin.

In FIG3B , some of the programmed memory cells in the programmed memory cell distribution curve PGM may have charge loss due to at least one of environmental factors, usage time, or read times, thereby generating a programmed memory cell distribution curve 310. At this time, by executing step S220, the controller in the memory device can set the first threshold voltage V1 and the second threshold voltage V2, and by performing a read operation on the programmed memory cells, a plurality of charge loss memory cells 320 with a critical voltage between the first threshold voltage V1 and the second threshold voltage V2 are determined.

Please refer to FIG. 2 again. In step S230, when the verification action of step S220 is passed (indicating that the verified programmed memory cell is not a charge loss memory cell), step S230 may be executed to perform normal actions.

When the verification action of step S220 fails (indicating that the verified programmed memory cell is a charge loss memory cell), step S240 may be executed to perform a supplementary programming action on the charge loss memory cell.

For details of the supplementary programming action, please refer to FIG. 3C . Following the implementation of FIG. 3B , when the controller of the memory device determines that the charge loss memory cell 320 is present, the controller may perform a supplementary programming action on the charge loss memory cell 320. The controller may set a programming verification voltage equal to the second threshold voltage V2, and perform a supplementary programming action on the charge loss memory cell 320 by providing a pulse having a programming voltage to the charge loss memory cell 320. Here, the programming voltage may be greater than the second threshold voltage V2. Alternatively, the controller may perform supplemental programming actions on the charge loss memory cell 320 by providing multiple pulses with increasing voltages through an increasing step pulse programming mechanism.

After completing the supplementary programming action, the distribution curve 310' of the programmed memory cells can be obtained.

Please refer to FIG. 4A and FIG. 4B below, which are schematic diagrams showing another implementation of the data retention compensation action of the memory device of the embodiment of the present invention. In FIG. 4A, the controller of the memory device can set the first threshold voltage V1, the second threshold voltage V2 and the third threshold voltage V3 to perform a verification action on each programmed memory cell in the programmed memory cell distribution curve 410, wherein the third threshold voltage V3 is greater than the second threshold voltage V2, and the second threshold voltage V2 is greater than the first threshold voltage V1. The controller of the memory device reads each programmed memory cell according to the first threshold voltage V1, the second threshold voltage V2 and the third threshold voltage V3, and thereby verifies a plurality of charge loss memory cells whose critical voltages are between the first threshold voltage V1 and the third threshold voltage V3.

In FIG4B , the controller of the memory device may set a programming verification voltage equal to the third threshold voltage V3, and perform a replenishment programming action on the charge loss memory cells based on the set programming verification voltage. By performing the charge replenishment action on the charge loss memory cells, a new programmed memory cell distribution curve 410 ' may be generated.

Please refer to FIG. 5 and FIG. 6 below, which are flowcharts of different implementation methods of the data storage compensation action of the embodiment of the present invention. In FIG. 5, in step S510, the memory device can read the programmed memory cell through the controller according to the second threshold voltage V2 under the condition of the error checking and correction (ECC) mechanism. If the above-mentioned reading action is passed, it means that the programmed memory cell has not suffered from serious charge loss and can operate normally (step S530). If the reading action of step S510 fails, step S520 may be executed, and the memory device may read the programmed memory cell according to the first threshold voltage V1 and the third threshold voltage V3 through the controller. The third threshold voltage V3 is greater than the second threshold voltage V2, and the second threshold voltage V2 is greater than the first threshold voltage V1.

If the critical voltage of the programmed memory cell is between the first threshold voltage V1 and the third threshold voltage V3, the reading result of step S520 is a failure. Conversely, if the critical voltage of the programmed memory cell is not between the first threshold voltage V1 and the third threshold voltage V3, the reading result of step S520 is a pass. When the reading result of step S520 is a failure, step S540 may be executed; conversely, when the reading result of step S520 is a pass, step S530 may be executed.

In step S540, the memory controller may perform a replenishment programming operation for the charge-loss memory cell whose critical voltage is between the first threshold voltage V1 and the third threshold voltage V3, thereby performing a charge refill operation on the charge-loss memory cell.

In FIG6 , in step S610, the memory device can read the programmed memory cell through the controller according to the first threshold voltage V1 and the second threshold voltage V2 without the use of an error checking and correction (ECC) mechanism. If the above-mentioned reading action is passed, it means that the programmed memory cell does not suffer from serious charge loss and can operate normally (step S630). If the reading action of step S610 fails, step S620 can be executed, and the memory device can read the programmed memory cell through the controller according to the third threshold voltage V3. The third threshold voltage V3 is greater than the second threshold voltage V2, and the second threshold voltage V2 is greater than the first threshold voltage V1.

Through the reading result of step S620, the charge loss memory cell whose critical voltage is between the first threshold voltage V1 and the third threshold voltage V3 can be verified. In step S640, the memory controller can perform a supplement programming action for the charge loss memory cell whose critical voltage is between the first threshold voltage V1 and the third threshold voltage V3, and thereby perform a charge refill action on the charge loss memory cell.

Please refer to FIG. 7 below, which is a schematic diagram of a memory device of an embodiment of the present invention. The memory device 700 includes a memory block 710 and a controller 720. The memory block 710 and the controller 720 are coupled to each other. The controller 720 is used to execute the data retention compensation method of the programmed memory cell mentioned in the aforementioned multiple embodiments and implementation methods for the memory block 710. The relevant action details have been described in detail in the aforementioned embodiments and implementation methods, and will not be repeated here.

It is worth mentioning that in the embodiment of the present invention, the memory block 710 can be an AND or NOR flash memory block. The memory block 710 can be a two-dimensional or three-dimensional memory block. The memory block 710 can have multiple partitions. Each partition can be divided into an erased memory cell block and a programmed memory cell block according to the write status of the memory cell.

In addition, the controller 720 may be a processor with computing capabilities. Alternatively, the controller 720 may be a hardware circuit designed by a hardware description language (HDL) or any other digital circuit design method known to those skilled in the art, and implemented by a field programmable gate array (FPGA), a complex programmable logic device (CPLD), or an application-specific integrated circuit (ASIC), without any specific limitation.

Please refer to FIG8 below, which shows a schematic diagram of the architecture of a memory cell of a memory device of an embodiment of the present invention. In the memory device of the embodiment of the present invention, multiple memory cells MCs in a memory cell block can be constructed in a stacked manner to form a memory cell string with a three-dimensional structure. Each memory cell may have a silicon oxide-silicon nitride-silicon oxide layer ONO as an insulating layer. And it has a channel structure CH and a gate structure GS. The regional bit line BL and the regional source line SL are connected to all the memory cells MCs in the memory cell string through conductive pins PG1 and PG2, respectively.

In summary, the memory device of the present invention determines whether the programmed memory cell has charge loss through the reading action. And through the supplementary programming action, the charge is refilled for the charge-loss memory cell, which can effectively maintain the data preservation of the memory cell and ensure the accuracy of the data.

310, 310', 410, 410': Programmed memory cell distribution curve 320: Charge loss memory cell 700: Memory device 710: Memory block 720: Controller BL: Regional bit line CH: Channel structure ER: Erased memory cell distribution curve GS: Gate structure MCs: Memory cell ONO: Silicon oxide-silicon nitride-silicon oxide layer PG1, PG2: Conductive pins PGM: Programmed memory cell distribution curve S110~S130, S210~S230, S510~S540, S610~S640: Steps SL: Local source line V1~V3: Threshold voltage VPV: Programming verification voltage VRD: Read reference voltage

FIG. 1 is a flowchart of a method for compensating data preservation of an embodiment of the present invention. FIG. 2 is a flowchart of a method for compensating data preservation of a memory device of another embodiment of the present invention. FIG. 3A to FIG. 3C are schematic diagrams of a compensation action for data preservation of a memory device. FIG. 4A and FIG. 4B are schematic diagrams of another implementation of a compensation action for data preservation of a memory device of an embodiment of the present invention. FIG. 5 and FIG. 6 are flowcharts of different implementations of a compensation action for data preservation of an embodiment of the present invention, respectively. FIG. 7 is a schematic diagram of a memory device of an embodiment of the present invention. FIG8 is a schematic diagram showing the structure of a memory cell of a memory device according to an embodiment of the present invention.

S110~S130: Steps

Claims (18)

A method for compensating data retention includes: performing a read operation on each of a plurality of programmed memory cells in a memory device; determining whether charge loss occurs in each of the programmed memory cells by the read operation to set each of the programmed memory cells as a charge loss memory cell, including: setting a first threshold voltage and a first Two threshold voltages, wherein the second threshold voltage is greater than the first threshold voltage; and the read operation is performed on each of the programmed memory cells, and it is determined whether the critical voltage of each of the programmed memory cells is between the first threshold voltage and the second threshold voltage; and a supplementary programming operation is performed on the charge loss memory cells. The compensation method as described in claim 1, wherein the step of determining whether each programmed memory cell has charge loss through the reading action to set each programmed memory cell as each charge loss memory cell further includes: when the critical voltage of each programmed memory cell is between the first threshold voltage and the second threshold voltage, setting each programmed memory cell as each charge loss memory cell. The compensation method as described in claim 1, wherein the step of performing the supplementary programming action on the charge loss memory cells comprises: Setting a programming verification voltage in the supplementary programming action according to the second threshold voltage; and performing the supplementary programming action on the charge loss memory cells according to the programming verification voltage. The compensation method as described in claim 1, wherein the step of performing the supplementary programming action on the charge loss memory cells includes: setting a programming voltage, providing a pulse with the programming voltage to perform the supplementary programming action on the charge loss memory cells, wherein the programming voltage is greater than the second threshold voltage. The compensation method as described in claim 1, wherein the step of performing the supplementary programming action on the charge loss memory cells includes: performing the supplementary programming action on the charge loss memory cells according to an incremental step pulse programming mechanism. The compensation method as described in claim 1, wherein the step of performing the read operation on the programmed memory cells in the memory device comprises: setting a first threshold voltage, a second threshold voltage and a third threshold voltage, wherein the third threshold voltage is greater than the second threshold voltage, and the second threshold voltage is greater than the first threshold voltage; and based on an error detection and correction mechanism, A first read operation is performed on each programmed memory cell according to the first threshold voltage and the third threshold voltage; When the first read operation fails, a second read operation is performed on each programmed memory cell according to the first threshold voltage and the third threshold voltage; and each programmed memory cell having a critical voltage between the first threshold voltage and the third threshold voltage is set as a charge loss memory cell. The compensation method as described in claim 6, wherein the step of performing the supplementary programming action on the charge loss memory cells includes: setting a programming verification voltage in the supplementary programming action according to the third threshold voltage; and performing the supplementary programming action on the charge loss memory cells according to the programming verification voltage. The compensation method as described in claim 1, wherein the step of performing the read operation on the programmed memory cells in the memory device comprises: setting a first threshold voltage, a second threshold voltage and a third threshold voltage, wherein the third threshold voltage is greater than the second threshold voltage, and the second threshold voltage is greater than the first threshold voltage; and The first threshold voltage and the second threshold voltage are used to perform a first read operation on each of the memory cells; when the first read operation fails, a second read operation is performed on each of the memory cells according to the third threshold voltage; and each of the programmed memory cells having a critical voltage between the first threshold voltage and the third threshold voltage is set as the charge loss memory cell. A memory device includes: a memory block; and a controller coupled to the memory block, for: performing a read operation on each of a plurality of programmed memory cells in the memory device; determining through the read operation whether each programmed memory cell has charge loss to set each programmed memory cell as a charge loss memory cell; and The lost memory cell performs a supplementary programming action, wherein the controller is further used to: set a first threshold voltage and a second threshold voltage, wherein the second threshold voltage is greater than the first threshold voltage; and perform the reading action on each of the programmed memory cells, and determine whether the critical voltage of each of the programmed memory cells is between the first threshold voltage and the second threshold voltage. The memory device as described in claim 9, wherein the controller is further used to: when the critical voltage of each programmed memory cell is between the first threshold voltage and the second threshold voltage, set each programmed memory cell as each charge loss memory cell. The memory device as described in claim 9, wherein the controller is further used to: Set a programming verification voltage in the supplementary programming action according to the second threshold voltage; and perform the supplementary programming action on the charge loss memory cells according to the programming verification voltage. The memory device as described in claim 9, wherein the controller is further used to: set a programming voltage, provide a pulse with the programming voltage to perform the supplementary programming action on the charge loss memory cells, wherein the programming voltage is greater than the second threshold voltage. A memory device as described in claim 9, wherein the controller is further used to: perform the supplementary programming action on the charge loss memory cells according to an incremental step pulse programming mechanism. The memory device as described in claim 9, wherein the controller is further used to: set a first threshold voltage, a second threshold voltage and a third threshold voltage, wherein the third threshold voltage is greater than the second threshold voltage, and the second threshold voltage is greater than the first threshold voltage; and based on an error detection and correction mechanism, according to the second threshold voltage for each programmed The programmable memory cell performs a first read operation; When the first read operation fails, a second read operation is performed on each of the programmed memory cells according to the first threshold voltage and the third threshold voltage; and each of the programmed memory cells having a critical voltage between the first threshold voltage and the third threshold voltage is set as each of the charge loss memory cells. The memory device as described in claim 14, wherein the controller is further used to: set a programming verification voltage in the supplementary programming action according to the third threshold voltage; and perform the supplementary programming action on the charge loss memory cells according to the programming verification voltage. The memory device as described in claim 9, wherein the controller is further used to: set a first threshold voltage, a second threshold voltage and a third threshold voltage, wherein the third threshold voltage is greater than the second threshold voltage, and the second threshold voltage is greater than the first threshold voltage; and A first reading operation is performed on each of the memory cells; when the first reading operation fails, a second reading operation is performed on each of the memory cells according to the third threshold voltage; and each of the programmed memory cells having a critical voltage between the first threshold voltage and the third threshold voltage is set as each of the charge loss memory cells. A memory device as described in claim 9, wherein the memory block is an AND or NOR flash memory block. A memory device as described in claim 9, wherein the memory block is a two-dimensional or three-dimensional memory block.

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