TWI847912B - 半導體結構以及半導體結構製造方法 - Google Patents

半導體結構以及半導體結構製造方法

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Publication number
TWI847912B
TWI847912B TW112143948A TW112143948A TWI847912B TW I847912 B TWI847912 B TW I847912B TW 112143948 A TW112143948 A TW 112143948A TW 112143948 A TW112143948 A TW 112143948A TW I847912 B TWI847912 B TW I847912B
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TW
Taiwan
Prior art keywords
semiconductor structure
manufacturing
semiconductor
Prior art date
Application number
TW112143948A
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English (en)
Inventor
林君明
Original Assignee
林君明
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Publication date
Application filed by 林君明 filed Critical 林君明
Application granted granted Critical
Publication of TWI847912B publication Critical patent/TWI847912B/zh

Links

TW112143948A 2023-10-04 2023-11-14 半導體結構以及半導體結構製造方法 TWI847912B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US18/480,567 2023-10-04

Publications (1)

Publication Number Publication Date
TWI847912B true TWI847912B (zh) 2024-07-01

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230138988A1 (en) 2021-10-29 2023-05-04 International Business Machines Corporation Dual damascene fully-aligned via interconnects with dual etch layers

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230138988A1 (en) 2021-10-29 2023-05-04 International Business Machines Corporation Dual damascene fully-aligned via interconnects with dual etch layers

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