TWI845096B - Phase detection system and method of use thereof - Google Patents

Abstract

A phase detection system for parallel measurement of a relative phase value of an RF signal flowing through a node of a circuit under test, comprising: a high impedance probe that touches the node and outputs a measured phase signal; a signal analyzer receives the measured phase signal and plots the waveform of the measured phase signal and the waveform of a predefined signal to generate an XY quadrant chart; and a pattern recognition unit reads the XY axis quadrant chart and compares the XY quadrant chart with a known standard reference chart to determine whether the phase value of the node is within a margin of error to detect the yield of the circuit under test.

Description

Phase detection system and method of using the same

The present invention relates to a detection system, in particular a phase detection system for determining whether a radio frequency phased element and a phased array antenna system are damaged.

Figure 1 is from the product documentation "Evaluating the ADAR1000 8GHz to 16GHz, 4-Channel, X Band and Ku Band Beamformer" from ANALOG DEVICES. From Figure 1, we can see that the way to detect a beamforming chip BFIC is to connect the network analyzer VNA in series to the connector on the evaluation board of the beamforming chip BFIC to measure the amplitude and phase of each port.

FIG2 shows the implementation of the above-mentioned serial detection method in a phased array antenna system AR. The phased array antenna system AR includes a plurality of antenna elements 11, a plurality of phase shifters PS, and a plurality of variable attenuators 12. Usually, in the design of a large-scale phased array antenna, the number of the antenna elements 11 is thousands. If the detection method of FIG1 is adopted, the lines before and after the thousands of phase shifters PS must be disconnected, and thousands of adapters (not shown in FIG2) must be connected to perform the detection. This is not only too large but also difficult to operate. The engineering practice is not feasible, and there is not enough space to weld the measurement connectors for the phased array antenna system AR in the millimeter wave band. In addition, the amplitude and phase measured by the phase shifters PS without the influence of the antennas 11 and the variable attenuators 12 in FIG2 are usually inconsistent with the performance of the phase shifters PS connected to the antennas 11 and the variable attenuators 12 in FIG3 and in actual working state.

In order to solve the above problems, this application proposes a phase detection system and its use method, which can perform phase detection of each continuous node 13 of the phased array antenna system AR in the actual working state as shown in Figure 3, and the phase detection system and its use method will not affect the normal operation of the phased array antenna system AR.

In order to solve the problems of the prior art, the first preferred embodiment of the present invention proposes a phase detection system for parallel measurement of a relative phase value of a radio frequency signal flowing through a node of a circuit to be tested.

The phase detection system of the first preferred embodiment includes a high impedance probe, an analyzer and a pattern recognition unit.

The high impedance probe includes a ground terminal, a detection terminal, and a measurement signal output terminal. The ground terminal is used to electrically connect to a ground plane of the circuit to be tested, the detection terminal is used to touch the node of the circuit to be tested, and the measurement signal output terminal outputs a measurement phase signal that depends on the radio frequency signal at the node.

The analyzer is electrically connected to the high impedance probe and receives the measured phase signal, and performs continuous plotting for at least one cycle time according to the waveform of the measured phase signal and the waveform of a preset signal to generate an XY axis four-quadrant diagram, wherein the preset signal has the same frequency as the measured phase signal, and the amplitudes of the preset signal and the measured phase signal at the same time are respectively used as an X-axis value and a Y-axis value in the XY axis four-quadrant diagram.

The graphic recognition unit is electrically connected to the analyzer. The graphic recognition unit is used to read the XY axis four-quadrant diagram and compare the XY axis four-quadrant diagram with a preset standard reference diagram to determine whether the relative phase value on the node is within an error range. When the relative phase value of the node is within the error range, the graphic recognition unit determines that the node of the circuit to be tested meets the yield. When the relative phase value of the node exceeds the error range, the graphic recognition unit determines that the node of the circuit to be tested does not meet the yield.

The second preferred embodiment of the phase detection system of the present invention is used to measure in parallel a relative phase value between a first node and a second node of a circuit to be tested, and the second preferred embodiment includes a first high impedance probe, a second high impedance probe, an analyzer and a graphic recognition unit.

The first high impedance probe includes a first ground terminal, a first detection terminal and a first measurement signal output terminal. The first ground terminal is used to electrically connect to a ground plane of the circuit to be tested, the first detection terminal is used to touch the first node, and a first measurement phase signal outputted by the first measurement signal output terminal depends on a first radio frequency signal flowing through the first node.

The second high impedance probe includes a second ground terminal, a second detection terminal and a second measurement signal output terminal. The second ground terminal is used to electrically connect to the ground plane of the circuit to be tested, the second detection terminal is used to touch the second node, and a second measurement phase signal outputted by the second measurement signal output terminal depends on a second radio frequency signal at the second node.

The analyzer is electrically connected to the first high impedance probe and receives the first measured phase signal, and is electrically connected to the second high impedance probe and receives the second measured phase signal, and performs continuous plotting for at least one cycle time according to the waveform of the first measured phase signal and the waveform of the second measured phase signal to generate an XY axis four-quadrant diagram, wherein the first measured phase signal and the second measured phase signal have the same frequency, and the amplitudes of the first measured phase signal and the second measured phase signal at the same time are respectively used as an X-axis value and a Y-axis value in the XY axis four-quadrant diagram.

The graphic recognition unit is electrically connected to the analyzer. The graphic recognition unit is used to read the XY axis four-quadrant diagram and compare the XY axis four-quadrant diagram with a standard reference diagram to determine whether the relative phase value on the node is within an error range. When the relative phase value of the node is within the error range, the graphic recognition unit determines that the node of the circuit to be tested meets the yield. When the relative phase value of the node exceeds the error range, the graphic recognition unit determines that the node of the circuit to be tested does not meet the yield.

The phase detection method of the present invention is used to detect a relative phase value of a radio frequency signal flowing through a node of a circuit to be tested. The first preferred embodiment of the phase detection method includes the following steps: step (A): measuring the node of the circuit to be tested with a high impedance probe to obtain a measured phase signal dependent on the radio frequency signal; step (B): electrically connecting an analyzer to the high impedance probe and receiving the measured phase signal, the analyzer continuously plotting the waveform of the measured phase signal and the waveform of a preset signal for at least one cycle time to generate an XY axis four-quadrant diagram, wherein the preset signal has the same frequency as the measured phase signal, and the preset signal and the measured phase signal are the same frequency. The amplitudes of the two at the same time are respectively used as an X-axis value and a Y-axis value in the XY-axis four-quadrant diagram; and step (C): a graphic recognition unit is electrically connected to the analyzer, the graphic recognition unit is used to read the XY-axis four-quadrant diagram, and compare the XY-axis four-quadrant diagram with a preset standard reference diagram to determine whether the relative phase value on the node is within an error range. When the relative phase value of the node is within the error range, the graphic recognition unit determines that the node of the circuit to be tested meets the yield rate. When the relative phase value of the node exceeds the error range, the graphic recognition unit determines that the node of the circuit to be tested does not meet the yield rate.

The phase detection method of the present invention is used to detect a relative phase value between a first node and a second node of a circuit to be tested. The second preferred embodiment of the phase detection method includes the following steps: Step (A): measuring the first node of the circuit to be tested with a first high impedance probe to obtain a first measurement phase signal; Step (B): measuring the second node of the circuit to be tested with a second high impedance probe to obtain a second measurement phase signal; Step (C): electrically connecting the analyzer to the first high impedance probe and receiving the first measurement phase signal, and electrically connecting the analyzer to the second high impedance probe and receiving the second measurement phase signal; Step (D): respectively measuring the first measurement phase signal and the second measurement phase signal at the same time. an amplitude as an X-axis value and a Y-axis value in an XY-axis four-quadrant graph, respectively, and continuously plotting for at least one cycle time to generate an XY-axis four-quadrant graph; and step (E): electrically connecting a graphic recognition unit to the analyzer, and reading the XY-axis four-quadrant graph with the graphic recognition unit, and using the graphic recognition unit to compare the XY-axis four-quadrant graph with a standard reference The graph is compared to determine whether the relative phase value on the node is within an error range. When the relative phase value of the node is within the error range, the graph recognition unit determines that the node of the circuit to be tested meets the yield rate. When the relative phase value of the node exceeds the error range, the graph recognition unit determines that the node of the circuit to be tested does not meet the yield rate.

The effects of the present invention are:

(1) The high impedance probe is used. Therefore, the impedance of the high impedance probe seen from the circuit to be tested is extremely large (at least greater than 1k ohm) and can be regarded as an open circuit. Therefore, the impact of the high impedance probe on the circuit to be tested can be almost ignored, thereby solving the disadvantage of the previous technology of Figures 1 and 2 that the circuit components must be disconnected and then connected in series for measurement.

(2) The first high-impedance probe or the second high-impedance probe and the high-impedance probe in this application are the same high-impedance probes, and are given different numbers for the sake of convenience. Therefore, each embodiment has the effect of the above (1).

(3) By using the graphic recognition unit, the relative phase value can be quickly compared in a graphic recognition manner to see if it is within the error range. Therefore, the analyzer can use an oscilloscope that can output time domain signals or a signal analyzer with a frequency domain to time domain conversion function. It is not necessary to use a network analyzer for measurement as in the previous technology shown in Figure 1, which can achieve more flexible instrument selection.

BFIC: Beamforming Chip

VNA: Network Analyzer

AR: Phased Array Antenna System

PS: Phase shifter

11: Antenna components

12: Variable attenuator

13: Node

2: Circuit to be tested

21: Ground contact surface

3: High impedance probe

3’: First high impedance probe

3”: Second highest impedance probe

31: Ground terminal

31’: First ground terminal

31”: Second ground terminal

32: Detection end

32’: First detection end

32”: Second detection end

33: Measurement signal output terminal

33’: First measurement signal output terminal

33”: Second measurement signal output terminal

4:Analyzer

5: Graphics recognition unit

N: Node

N’: first node

N”: Second node

AR: Phased Array Antenna System

PS: Phase shifter

PA: Power amplifier

[Figure 1] is a schematic diagram of the evaluation board and network analyzer of the known detection beamforming chip.

[Figure 2] is a schematic diagram of applying the technology in Figure 1 to phased array antenna system detection.

[Figure 3] is a schematic diagram of a phased array antenna system, which shows that the phase shifter in the phased array antenna system needs to be connected to the antenna and the variable attenuator when the system is actually operating.

[Figure 4] is a schematic diagram of the first preferred embodiment of the present invention for parallel measurement of the circuit to be tested.

[Figure 5] is a four-quadrant diagram of the XY axis, which shows that different phase differences between the Y axis and the X axis will produce different curves.

[Figure 6] is a schematic diagram of the four-quadrant XY axis diagram, which explains how the error range is defined.

[Figure 7] is a schematic diagram of the second preferred embodiment of the present invention for parallel measurement of the circuit to be tested.

[Figure 8] is a flow chart of the first preferred embodiment of the phase detection method of the present invention.

[Figure 9] is a flow chart of the second preferred embodiment of the phase detection method of the present invention.

Referring to FIG. 4 , in order to solve the problems of the prior art, the first preferred embodiment of the present invention proposes a phase detection system for parallel measurement of a relative phase value of a radio frequency signal flowing through any node N on a circuit 2 to be tested. For example, the circuit 2 to be tested is used in a phased array antenna system AR, and the circuit 2 to be tested includes a plurality of phase shifters PS, a plurality of variable attenuators 12, and a power amplifier PA, and each phase shifter PS corresponds to an antenna element 11 in series.

The phase detection system of the first preferred embodiment includes a high impedance probe 3, an analyzer 4 and a graphic recognition unit 5.

The high impedance probe 3 includes a ground terminal 31, a detection terminal 32, and a measurement signal output terminal 33. The ground terminal 31 is used to electrically connect to a ground plane 21 of the circuit 2 to be tested, the detection terminal 32 is used to touch the node N of the circuit 2 to be tested, and the measurement signal output terminal 33 outputs a measurement phase signal that depends on the RF signal at the node N.

The analyzer 4 is electrically connected to the high impedance probe 3 and receives the measured phase signal, and performs continuous plotting for at least one cycle time according to the waveform of the measured phase signal and the waveform of a preset signal to generate an XY axis four-quadrant diagram, wherein the preset signal has the same frequency as the measured phase signal, and the amplitudes of the preset signal and the measured phase signal at the same time are respectively used as an X-axis value and a Y-axis value in the XY axis four-quadrant diagram.

The graphic recognition unit 5 is electrically connected to the analyzer 4. The graphic recognition unit 5 is used to read the XY axis four-quadrant diagram and compare the XY axis four-quadrant diagram with a preset standard reference diagram to determine whether the relative phase value on the node N is within an error range. When the relative phase value of the node N is within the error range, the graphic recognition unit 5 determines that the node N of the circuit 2 to be tested meets the yield. When the relative phase value of the node N exceeds the error range, the graphic recognition unit 5 determines that the node N of the circuit 2 to be tested does not meet the yield.

To supplement, since "phase" is a relative value rather than an absolute value, the phase at any node N on the circuit to be tested 2 must be defined relative to a reference standard. For example, in the preferred embodiment, the relative phase value is obtained relative to the preset signal. To further explain, if the preset signal is used as a reference standard with a phase of 0, the time domain waveform of the preset signal can be expressed by the mathematical formula x = cos( ωt ). The time domain waveform of the measured phase signal read by the analyzer 4 is expressed in the mathematical formula y = cos( ωt +θ°). Then, x = cos( ωt ) and y = cos( ωt ) can be expressed in the mathematical formula y = cos(ωt +θ°). t+θ°), the XY-axis four-quadrant diagram can be obtained, for example, as shown in FIG5 . It can be found that as θ changes, the XY-axis four-quadrant diagram obtained by continuous plotting from t=0 to T will have different shapes. The parameter T is a cycle time of the RF signal.

Referring to FIG. 6 , assuming that the expected relative phase value at the measured node N is 45°, an elliptical curve S1 can be obtained by continuously plotting y = cos(ω t +45°) relative to x = cos(ω t ) for a time period, and the XY axis four-quadrant diagram containing the elliptical curve S1 is used as the standard reference diagram. If the relative phase value at the measured node N is 40° or 50°, different elliptical curves S2 and S3 will be obtained. Therefore, the graphic recognition unit 5 can use the above-mentioned graphic recognition method to determine whether the measured relative phase value is within the error range. If it is within the error range, the measured node N meets the yield, otherwise it does not meet the yield. In addition, Figure 6 can also illustrate how to define the error range. For example, the relative phase value corresponding to the node N that meets the yield is expected to meet the condition of 40°<θ°<50°, so the curve y = cos(ω t +θ°) must be between the two elliptical curves S2 and S3 of y = cos(ω t +40°) and y = cos(ω t +45°).

Referring back to FIG. 4 , in the first preferred embodiment, an output impedance of the high impedance probe 3 is 50 ohms, an input impedance is at least greater than 1 k ohms, and the analyzer 4 is an oscilloscope, but can also be a signal analyzer, and the signal analyzer has the function of signal conversion between frequency domain and time domain.

Referring to FIG. 7 , the second preferred embodiment of the phase detection system of the present invention is used to measure in parallel a relative phase value between a first node N’ and a second node N” of a circuit 2 to be tested. The second preferred embodiment includes a first high impedance probe 3’, a second high impedance probe 3”, an analyzer 4 and a graphic recognition unit 5.

The first high impedance probe 3' includes a first ground terminal 31', a first detection terminal 32' and a first measurement signal output terminal 33'. The first ground terminal 31' is used to electrically connect to a ground plane 21 of the circuit 2 to be tested, the first detection terminal 32' is used to touch the first node N', and the first measurement signal output terminal 33' outputs a first measurement phase signal that depends on a first radio frequency signal flowing through the first node N'.

The second high impedance probe 3" includes a second ground terminal 31", a second detection terminal 32" and a second measurement signal output terminal 33". The second ground terminal 31" is used to electrically connect to the ground plane 21 of the circuit 2 to be tested, the second detection terminal 32" is used to touch the second node N", and the second measurement signal output terminal 33" outputs a second measurement phase signal that depends on a second RF signal at the second node N".

The analyzer 4 is electrically connected to the first high impedance probe 3' and receives the first measured phase signal cos(ω t +θ ₁ °), and is electrically connected to the second high impedance probe 3" and receives the second measured phase signal cos(ω t +θ ₂ °), and performs continuous plotting for at least one cycle time based on the waveform x = cos(ω t +θ ₁ °) of the first measured phase signal and the waveform y = cos(ω t +θ ₂ °) of the second measured phase signal to generate an XY axis four-quadrant diagram, wherein the first measured phase signal and the second measured phase signal have the same frequency, and the amplitudes of the first measured phase signal and the second measured phase signal at the same time are respectively used as an X-axis value and a Y-axis value in the XY axis four-quadrant diagram.

The graphic recognition unit 5 is electrically connected to the analyzer 4. The graphic recognition unit 5 is used to read the XY axis four-quadrant diagram and compare the XY axis four-quadrant diagram with a standard reference diagram to determine whether the relative phase value on the node N is within an error range. When the relative phase value of the node N is within the error range, the graphic recognition unit 5 determines that the node N of the circuit 2 to be tested meets the yield. When the relative phase value of the node N exceeds the error range, the graphic recognition unit 5 determines that the node N of the circuit 2 to be tested does not meet the yield.

Referring to FIG. 4 and FIG. 7 at the same time, it can be seen that the main difference between the first preferred embodiment and the second preferred embodiment is that the second preferred embodiment requires the use of two high impedance probes (the first high impedance probe 3' and the second high impedance probe 3"), while the first preferred embodiment only requires one high impedance probe 3. Although the system cost of the second preferred embodiment is higher, the second preferred embodiment can conveniently measure the relative phase value between any two nodes N without the preset signal. In addition, the first high impedance probe 3' and the second high impedance probe 3" of the second preferred embodiment can use the same high impedance probe 3 as the first preferred embodiment.

Referring to Figures 4 and 8, the first preferred embodiment of the phase detection method of the present invention is used to detect a relative phase value of a radio frequency signal flowing through a node N of a circuit 2 to be tested. The first preferred embodiment of the phase detection method includes the following steps:

Step (A): Use a high impedance probe 3 to measure the node N of the circuit under test 2 to obtain a measurement phase signal y = cos(ω t +θ°) that depends on the RF signal.

Step (B): An analyzer 4 is electrically connected to the high impedance probe 3 and receives the measured phase signal. The analyzer 4 continuously plots the waveform of the measured phase signal and the waveform of a preset signal for at least one cycle to generate an XY axis four-quadrant diagram, wherein the preset signal x = cos(ω t ) and the measured phase signal y = cos(ω t +θ°) have the same frequency, and the amplitudes of the preset signal and the measured phase signal at the same time are respectively used as an X-axis value and a Y-axis value in the XY axis four-quadrant diagram.

Step (C): A graphic recognition unit 5 is electrically connected to the analyzer 4. The graphic recognition unit 5 is used to read the XY axis four-quadrant diagram and compare the XY axis four-quadrant diagram with a preset standard reference diagram to determine whether the relative phase value on the node N is within an error range. When the relative phase value of the node N is within the error range, the graphic recognition unit 5 determines that the node N of the circuit 2 to be tested meets the yield. When the relative phase value of the node N exceeds the error range, the graphic recognition unit 5 determines that the node N of the circuit 2 to be tested does not meet the yield.

Referring to Figures 7 and 9, the second preferred embodiment of the phase detection method of the present invention is used to detect a relative phase value between a first node N' and a second node N" of a circuit 2 to be tested. The second preferred embodiment of the phase detection method includes the following steps:

Step (A): Use a first high impedance probe 3' to measure the first node N' of the circuit under test 2 to obtain a first measurement phase signal cos(ω t +θ ₁ °).

Step (B): Use a second high impedance probe 3" to measure the second node N" of the circuit under test 2 to obtain a second measurement phase signal cos(ω t +θ ₂ °).

Step (C): The analyzer 4 is electrically connected to the first high impedance probe 3' and receives the first measurement phase signal cos( ωt + _θ1 °), and is electrically connected to the second high impedance probe 3" and receives the second measurement phase signal cos( ωt + _θ2 °).

Step (D): taking the amplitudes of the first measured phase signal and the second measured phase signal at the same time as the X-axis value x = cos(ω t +θ ₁ °) and the Y-axis value y = cos(ω t +θ ₂ °) in an XY-axis four-quadrant diagram, and performing continuous plotting for at least one cycle time to generate an XY-axis four-quadrant diagram; and

Step (E): A graphic recognition unit 5 is electrically connected to the analyzer 4, and the graphic recognition unit 5 is used to read the XY axis four-quadrant diagram, and the graphic recognition unit 5 is used to compare the XY axis four-quadrant diagram with a standard reference diagram to determine whether the relative phase value on the node N is within an error range. When the relative phase value of the node N is within the error range, the graphic recognition unit 5 determines that the node N of the circuit 2 to be tested meets the yield rate. When the relative phase value of the node N exceeds the error range, the graphic recognition unit 5 determines that the node N of the circuit 2 to be tested does not meet the yield rate.

The effects of the present invention are:

(1) The high impedance probe 3 is used. Therefore, the impedance of the high impedance probe 3 seen from the circuit 2 to be tested is extremely large (at least greater than 1k ohm) and can be regarded as an open circuit. Therefore, the influence of the high impedance probe 3 on the circuit 2 to be tested can be almost ignored, thereby solving the disadvantage of the prior art of Figures 1 and 2 that the circuit components must be disconnected and then connected in series for measurement.

(2) The first high-impedance probe 3' or the second high-impedance probe 3" in this application are the same high-impedance probes as the high-impedance probe 3. They are given different numbers for the sake of convenience. Therefore, each embodiment has the effect of the above (1).

(3) The graphic recognition unit 5 can be used to quickly compare whether the relative phase value is within the error range by means of graphic recognition. Therefore, the analyzer 4 can adopt an oscilloscope that can output time domain signals or a signal analyzer with a frequency domain to time domain conversion function. It is not necessary to use a network analyzer for measurement as in the prior art shown in FIG. 1, which can achieve more flexible instrument selection.

However, the above is only a preferred embodiment of the present invention, and it cannot be used to limit the scope of implementation of the present invention. All simple equivalent changes and modifications made according to the scope of the patent application of the present invention and the content of the patent specification are still within the scope of the present invention.

11: Antenna components

12: Variable attenuator

2: Circuit to be tested

21: Ground contact surface

3: High impedance probe

31: Ground terminal

32: Detection end

33: Measurement signal output terminal

4:Analyzer

5: Graphics recognition unit

N: Node

AR: Phased Array Antenna System

PS: Phase shifter

PA: Power amplifier

Claims (10)

A phase detection system is used to measure in parallel a relative phase value of a radio frequency signal flowing through a node of a circuit to be tested, the system comprising: A high impedance probe, including a ground terminal, a detection terminal, and a measurement signal output terminal, the ground terminal is used to electrically connect to a ground plane of the circuit to be tested, the detection terminal is used to touch the node of the circuit to be tested, and a measurement phase signal output by the measurement signal output terminal depends on the radio frequency signal at the node; An analyzer is electrically connected to the high impedance probe and receives the measured phase signal, and continuously plots the waveform of the measured phase signal and the waveform of a preset signal for at least one cycle to generate an XY axis four-quadrant diagram, wherein the preset signal has the same frequency as the measured phase signal, and the amplitudes of the preset signal and the measured phase signal at the same time are respectively used as an X-axis value and a Y-axis value in the XY axis four-quadrant diagram; and A graphic recognition unit is electrically connected to the analyzer, and the graphic recognition unit is used to read the XY axis four-quadrant diagram and compare the XY axis four-quadrant diagram with a preset standard reference diagram to determine whether the relative phase value at the node is within an error range, When the relative phase value of the node is within the error range, the graphic recognition unit determines that the node of the circuit to be tested meets the yield rate. When the relative phase value of the node exceeds the error range, the graphic recognition unit determines that the node of the circuit to be tested does not meet the yield rate. According to the phase detection system of item 1 of the patent application scope, an output impedance of the high-impedance probe is 50 ohms and an input impedance is at least greater than 1k ohms. According to the phase detection system of item 1 of the patent application scope, the analyzer is an oscilloscope. According to the phase detection system of item 1 of the patent application scope, the analyzer is a signal analyzer. A phase detection system is used to measure a relative phase value between a first node and a second node of a circuit to be tested in parallel, the system comprising: A first high impedance probe, including a first ground terminal, a first detection terminal, and a first measurement signal output terminal, the first ground terminal is used to electrically connect to a ground plane of the circuit to be tested, the first detection terminal is used to touch the first node, and a first measurement phase signal output by the first measurement signal output terminal depends on a first radio frequency signal flowing through the first node; A second high impedance probe, including a second ground terminal, a second detection terminal, and a second measurement signal output terminal, wherein the second ground terminal is used to electrically connect to the ground plane of the circuit to be tested, the second detection terminal is used to touch the second node, and a second measurement phase signal outputted by the second measurement signal output terminal is dependent on a second radio frequency signal at the second node; An analyzer is electrically connected to the first high impedance probe and receives the first measurement phase signal, and is electrically connected to the second high impedance probe and receives the second measurement phase signal, and performs continuous plotting for at least one cycle time according to the waveform of the first measurement phase signal and the waveform of the second measurement phase signal to generate an XY axis four-quadrant diagram, wherein the first measurement phase signal and the second measurement phase signal have the same frequency, and the amplitudes of the first measurement phase signal and the second measurement phase signal at the same time are respectively used as an X-axis value and a Y-axis value in the XY axis four-quadrant diagram; and A graphic recognition unit is electrically connected to the analyzer. The graphic recognition unit is used to read the XY axis four-quadrant diagram and compare the XY axis four-quadrant diagram with a standard reference diagram to determine whether the relative phase value on the node is within an error range. When the relative phase value of the node is within the error range, the graphic recognition unit determines that the node of the circuit to be tested meets the yield. When the relative phase value of the node exceeds the error range, the graphic recognition unit determines that the node of the circuit to be tested does not meet the yield. According to the phase detection system of item 5 of the patent application scope, an output impedance of the first high-impedance probe is 50 ohms and an input impedance is at least greater than 1k ohms, and an output impedance of the second high-impedance probe is 50 ohms and an input impedance is at least greater than 1k ohms. According to the phase detection system of item 5 of the patent application scope, the analyzer is an oscilloscope. According to the phase detection system of item 5 of the patent application scope, the analyzer is a signal analyzer. A phase detection method is used to detect a relative phase value of a radio frequency signal flowing through a node of a circuit to be tested, the phase detection method comprising: Measuring the node of the circuit to be tested with a high impedance probe to obtain a measured phase signal dependent on the radio frequency signal; Electrically connecting the high impedance probe with an analyzer to receive the measured phase signal, the analyzer continuously plotting the waveform of the measured phase signal and the waveform of a preset signal for at least one cycle time to generate an XY axis four-quadrant diagram, wherein the preset signal and the measured phase signal have the same frequency, and the amplitudes of the preset signal and the measured phase signal at the same time are respectively used as an X-axis value and a Y-axis value in the XY axis four-quadrant diagram; and The analyzer is electrically connected to a graphic recognition unit, which is used to read the XY axis four-quadrant diagram and compare the XY axis four-quadrant diagram with a preset standard reference diagram to determine whether the relative phase value on the node is within an error range. When the relative phase value of the node is within the error range, the graphic recognition unit determines that the node of the circuit to be tested meets the yield. When the relative phase value of the node exceeds the error range, the graphic recognition unit determines that the node of the circuit to be tested does not meet the yield. A phase detection method for detecting a relative phase value between a first node and a second node of a circuit to be tested, the phase detection method comprising: Measuring the first node of the circuit to be tested with a first high impedance probe to obtain a first measurement phase signal; Measuring the second node of the circuit to be tested with a second high impedance probe to obtain a second measurement phase signal; Electrically connecting the analyzer to the first high impedance probe and receiving the first measurement phase signal, and electrically connecting the analyzer to the second high impedance probe and receiving the second measurement phase signal; Using the amplitudes of the first measurement phase signal and the second measurement phase signal at the same time as the X-axis value and the Y-axis value in an XY-axis four-quadrant diagram, and continuously plotting for at least one cycle to generate an XY-axis four-quadrant diagram; and A graphic recognition unit is electrically connected to the analyzer, and the graphic recognition unit is used to read the XY axis four-quadrant diagram, and the graphic recognition unit is used to compare the XY axis four-quadrant diagram with a standard reference diagram to determine whether the relative phase value on the node is within an error range. When the relative phase value of the node is within the error range, the graphic recognition unit determines that the node of the circuit to be tested meets the yield rate. When the relative phase value of the node exceeds the error range, the graphic recognition unit determines that the node of the circuit to be tested does not meet the yield rate.