TWI838315B - Dual active bridge converter - Google Patents

Abstract

A dual active bridge converter is disclosed. The dual active bridge converter includes a high-voltage side bridge rectifier set, a DC power grid port, a low-voltage side bridge rectifier set, an energy storage and release port, a transformer, a leakage inductance and a magnetizing inductance. The high-voltage side bridge rectifier set connects to the DC power grid port and the low-voltage side bridge rectifier set connects to the energy storage and release port. The transformer is disposed between the high-voltage side bridge rectifier set and the low-voltage side bridge rectifier set. The leakage inductance and the magnetizing inductance are disposed between the high-voltage side bridge rectifier set and the transformer. When the load is in light load mode, the bridge rectifier sets are controlled by the pulse width modulation method; when the load is in the medium and heavy load mode, the bridge rectifier sets are controlled by the single phase shift control method.

Description

Dual active axle converter

The present invention relates to a dual active bridge converter, and more particularly to a dual active bridge converter which is operated by a pulse width modulation control method in a light load mode and by a single phase shift control method in a medium and heavy load mode.

With the rapid development of science and technology, energy shortage and environmental pollution have become the focus of attention of countries around the world. All countries are looking for more efficient ways to use energy to reduce the impact of carbon emissions on the environment. For example, various distributed power sources such as solar energy, wind power generation, and hydropower generation, as well as energy storage architectures have become solutions for continued promotion and development, while smart grids effectively provide customers with sustainable, reliable, economical and environmentally friendly power grids. However, these solutions all need to be connected to the power grid through a power conversion system. Among them, switching power converters have higher power supply reliability, lower initial investment costs, smaller transmission losses, and are suitable for the application of renewable energy, becoming one of the important development goals in the construction of smart grids and energy interconnections.

In recent years, the most common bidirectional transmission is the dual active bridge converter architecture and its topology, which is used in energy storage and release systems and bidirectional power grids, such as electric vehicles and electric locomotives. The dual active bridge converter has the characteristics of bidirectional energy transmission, and its control method generally adopts phase shift control method, which uses the phase modulation mode to control the leading or lagging of the switch signal to determine the energy transmission direction and change its transmission power. In this control method, there is a period of time when the transformer voltage and the inductor current are opposite during power transmission, generating reflux power, causing the energy stored in the inductor to be transmitted back to the input end, increasing the current stress of the switch, increasing the conduction loss and the magnetic loss of the transformer, resulting in a decrease in converter efficiency. Existing technologies attempt to improve the above shortcomings by extending the control strategies of phase-shift technology and resonance technology. However, extended phase-shift technology requires more complex control timing, which makes the algorithm difficult to implement. Resonance technology must use variable frequency control, which causes voltage and current to generate high-order harmonics, which is more serious especially in low-power operation, making it difficult to effectively solve the problem of low conversion efficiency.

In summary, the inventor of the present invention has considered and designed a dual active bridge converter, hoping to improve the problems of the prior art and thereby promote its implementation and utilization in the industry.

In view of the problems described in the prior art, an object of the present invention is to provide a dual active-bridge converter that improves the efficiency of the converter by switching between different control modes when the load is light load or medium-heavy load.

Based on the above purpose, the present invention provides a dual active bridge converter, which includes a high-voltage side bridge rectifier group, a DC power grid port, a low-voltage side bridge rectifier group, an energy storage port, a transformer, a leakage inductance, and an excitation inductance. The high-voltage side bridge rectifier group includes a first power switch, a second power switch, a third power switch, and a fourth power switch. The first end of the first power switch and the third power switch are coupled to the first node, the second end of the first power switch and the first end of the second power switch are coupled to the second node, the second end of the third power switch and the first end of the fourth power switch are coupled to the third node, and the second end of the second power switch and the fourth power switch are coupled to the fourth node. The first end of the DC power grid port is coupled to the first node, and the second end of the DC power grid port is coupled to the fourth node. The low-voltage side bridge rectifier group includes a fifth power switch, a sixth power switch, a seventh power switch and an eighth power switch. The first ends of the fifth power switch and the seventh power switch are coupled to the fifth node. The second end of the fifth power switch and the first end of the sixth power switch are coupled to the sixth node. The second end of the seventh power switch and the first end of the eighth power switch are coupled to the seventh node. The second ends of the sixth power switch and the eighth power switch are coupled to the eighth node. The first end of the energy storage port is coupled to the fifth node, and the second end of the energy storage port is coupled to the eighth node. The transformer is arranged between the high-voltage side bridge rectifier group and the low-voltage side bridge rectifier group. The transformer includes a first coil and a second coil. The two ends of the second coil are coupled to the sixth node and the seventh node respectively. The leakage inductor is arranged between the high-voltage side bridge rectifier group and the transformer, one end of the leakage inductor is coupled to the second node, the other end of the leakage inductor is coupled to the first coil, and the other end of the first coil is coupled to the third node. The excitation inductor is arranged in parallel with the transformer, one end of the excitation inductor is coupled to the leakage inductor and the first coil, and the other end of the excitation inductor is coupled to the third node and the first coil. When the load of the dual active bridge converter is in light load mode, the dual active bridge converter controls the high voltage side bridge rectifier group and the low voltage side bridge rectifier group by pulse width modulation method. When the load is in medium and heavy load mode, the dual active bridge converter controls the high voltage side bridge rectifier group and the low voltage side bridge rectifier group by single phase shift control method.

Preferably, the dual active bridge converter may further include a digital controller, which is coupled to the high-voltage side bridge rectifier group and the low-voltage side bridge rectifier group respectively, and the digital controller controls the conduction or cutoff of the first power switch to the eighth power switch.

Preferably, the digital controller can be provided with a high-voltage side current detector and a low-voltage side current detector. The high-voltage side current detector is coupled to the DC grid port to detect the high-voltage side current, and the low-voltage side current detector is coupled to the energy storage port to detect the low-voltage side current. The digital controller determines whether the load of the dual active bridge converter is a light load mode or a medium-heavy load mode based on the high-voltage side current and the low-voltage side current.

Preferably, when the energy transmission direction is from the DC grid port to the energy storage port, the light load mode is an output power of less than 200W and the medium-to-heavy load mode is an output power of more than 200W; when the energy transmission direction is from the energy storage port to the DC grid port, the light load mode is an output power of less than 100W and the medium-to-heavy load mode is an output power of more than 100W.

Preferably, the digital controller can be provided with a high-voltage side feedback circuit and a low-voltage side feedback circuit, the high-voltage side feedback circuit is coupled to the DC power grid port, and the low-voltage side feedback circuit is coupled to the energy storage port.

Preferably, when the energy transfer direction is from the DC power grid port to the energy storage port, the low-voltage side feedback circuit transmits the low-voltage side voltage signal to the digital controller to adjust the voltage of the energy storage port; when the energy transfer direction is from the energy storage port to the DC power grid port, the high-voltage side feedback circuit transmits the high-voltage side voltage signal to the digital controller to adjust the voltage of the DC power grid port.

Preferably, the high-voltage side bridge rectifier group may include a first intrinsic diode and a first parasitic capacitor arranged in parallel with the first power switch, a second intrinsic diode and a second parasitic capacitor arranged in parallel with the second power switch, a third intrinsic diode and a third parasitic capacitor arranged in parallel with the third power switch, and a fourth intrinsic diode and a fourth parasitic capacitor arranged in parallel with the fourth power switch; the low-voltage side bridge rectifier group may include a fifth intrinsic diode and a fifth parasitic capacitor arranged in parallel with the fifth power switch, a sixth intrinsic diode and a sixth parasitic capacitor arranged in parallel with the sixth power switch, a seventh intrinsic diode and a seventh parasitic capacitor arranged in parallel with the seventh power switch, and an eighth intrinsic diode and an eighth parasitic capacitor arranged in parallel with the eighth power switch.

Preferably, the dual active bridge converter may further include a high-voltage side output capacitor and a low-voltage side output capacitor, one end of the high-voltage side output capacitor is coupled to the first end and the first node of the DC grid port, the other end of the high-voltage side output capacitor is coupled to the second end and the fourth node of the DC grid port, one end of the low-voltage side output capacitor is coupled to the first end and the fifth node of the energy storage port, and the other end of the low-voltage side output capacitor is coupled to the second end and the eighth node of the energy storage port.

Preferably, the turns ratio of the first coil to the second coil is 8:1.

As described above, the dual active-axle converter of the present invention may have one or more of the following advantages:

(1) This dual-active bridge converter can achieve bidirectional power transmission and has the advantages of zero voltage switching, zero current switching, fast dynamic response, high power density, electrical isolation, and a simple and symmetrical circuit architecture.

(2) The dual active bridge converter can improve the conversion efficiency of the dual active bridge converter in the forward and reverse states by switching between a pulse width modulation control method in a light load mode and a single phase shift control method in a medium and heavy load mode.

In order to facilitate understanding of the technical features, contents and advantages of the present invention and the effects that can be achieved, the present invention is hereby described in detail as follows with the accompanying drawings and in the form of embodiments. The drawings used therein are only for illustration and auxiliary description, and may not be the true proportions and precise configurations after the implementation of the present invention. Therefore, the proportions and configurations of the attached drawings should not be interpreted, and the scope of rights of the present invention in actual implementation should be limited.

Please refer to FIG. 1, which is a schematic diagram of a dual active bridge converter of an embodiment of the present invention. As shown in the figure, the dual active bridge converter 10 includes a high voltage side bridge rectifier group 11, a DC grid terminal V _grid , a low voltage side bridge rectifier group 12, a storage energy terminal V _bat , a transformer 13, a leakage inductance L _K and an excitation inductance L _M. The high voltage side bridge rectifier group 11 includes a first power switch S ₁ , a second power switch S ₂ , a third power switch S ₃ and a fourth power switch S ₄ , and the low voltage side bridge rectifier group 12 includes a fifth power switch S ₅ , a sixth power switch S ₆ , a seventh power switch S ₇ and an eighth power switch S ₈ .

The first end of the first power switch _S1 is coupled to the first node n1 and the second end is coupled to the second node n2, the first end of the second power switch _S2 is coupled to the second node n2 and the second end is coupled to the fourth node n4, the first end of the third power switch _S3 is coupled to the first node n1 and the second end is coupled to the third node n3, the first end of the fourth power switch _S4 is coupled to the third node n3 and the second end is coupled to the fourth node n4. The first end of the fifth power switch _S5 is coupled to the fifth node n5 and the second end is coupled to the sixth node n6, the first end of the sixth power switch _S6 is coupled to the sixth node n6 and the second end is coupled to the eighth node n8, the first end of the seventh power switch _S7 is coupled to the fifth node n5 and the second end is coupled to the seventh node n7, the first end of the eighth power switch _S8 is coupled to the seventh node n7 and the second end is coupled to the eighth node n8.

In the high-voltage side bridge rectifier group 11, a first intrinsic diode _D1 and a first parasitic capacitor C _oss1 are arranged in parallel with the first power switch _S1 , a second intrinsic diode _D2 and a second parasitic capacitor C _oss2 are arranged in parallel with the second power switch _S2 , a third intrinsic diode _D3 and a third parasitic capacitor C _oss3 are arranged in parallel with the third power switch _S3 , and a fourth intrinsic diode _D4 and a fourth parasitic capacitor C _oss4 are arranged in parallel with the fourth power switch _S4 . In addition, a high voltage side output capacitor _C1 is also provided on the high voltage side. One end of the high voltage side output capacitor _C1 is coupled to the first end of the DC grid port V _grid and the first node n1, and the other end of the high voltage side output capacitor _C1 is coupled to the second end of the DC grid port V _grid and the fourth node n4. In the low-voltage side bridge rectifier group 12, a fifth intrinsic diode _D5 and a fifth parasitic capacitor C _oss5 are arranged in parallel with the fifth power switch _S5 , a sixth intrinsic diode _D6 and a sixth parasitic capacitor C _oss6 are arranged in parallel with the sixth power switch _S6 , a seventh intrinsic diode _D7 and a seventh parasitic capacitor C _oss7 are arranged in parallel with the seventh power switch _S7 , and an eighth intrinsic diode _D8 and an eighth parasitic capacitor C _oss8 are arranged in parallel with the eighth power switch _S8 . In addition, a low-voltage output capacitor C ₂ is also provided on the low-voltage side. One end of the low-voltage output capacitor C ₂ is coupled to the first end of the energy storage port V _bat and the fifth node n5, and the other end of the low-voltage output capacitor C ₂ is coupled to the second end of the energy storage port V _bat and the eighth node n8. The output capacitor can be used for output voltage regulation and filtering. The larger the capacitance, the smaller the equivalent series resistance (ESR) inside the capacitor, and the smaller the help in reducing voltage ripples.

The first end of the DC grid port V _grid is coupled to the first node n1, the second end of the DC grid port V _grid is coupled to the fourth node n4, the first end of the energy storage port V _bat is coupled to the fifth node n5, and the second end of the energy storage port V _bat is coupled to the eighth node n8. The transformer 13 is disposed between the high-voltage side bridge rectifier group 11 and the low-voltage side bridge rectifier group 12, and the transformer 13 includes a first coil 13A and a second coil 13B, and the two ends of the second coil 13B are respectively coupled to the sixth node n6 and the seventh node n7. The voltage of the DC grid port V _grid can be 400V, the voltage of the energy storage port V _bat can be 50V, the maximum transmission power is 1kW, the switching frequency is 100kHz, and the transformer 13 can be designed based on the voltage of the DC grid port V _grid and the voltage of the energy storage port V _bat . The turns ratio of the first coil 13A and the second coil 13B is 8:1.

The leakage inductor L _K is arranged between the high-voltage side bridge rectifier group 11 and the transformer 13, one end of the leakage inductor L _K is coupled to the second node n2, the other end of the leakage inductor L _K is coupled to the first coil 13A, and the other end of the first coil 13A is coupled to the third node n3. The magnetizing inductor _LM is arranged in parallel with the transformer 13, one end of the magnetizing inductor _LM is coupled to the leakage inductor L _K and the first coil 13A, and the other end of the magnetizing inductor _LM is coupled to the third node n3 and the first coil 13A. When the load of the dual active bridge converter 10 is in light load mode, the dual active bridge converter 10 controls the high voltage side bridge rectifier group 11 and the low voltage side bridge rectifier group 12 by pulse width modulation. When the load is in medium or heavy load mode, the dual active bridge converter 10 controls the high voltage side bridge rectifier group 11 and the low voltage side bridge rectifier group 12 by single phase shift control.

Please refer to FIG. 2, which is a schematic diagram of a digital controller of an embodiment of the present invention. Please also refer to FIG. 1. The same reference numerals as in FIG. 1 refer to the same elements, and the same contents will not be repeated. As shown in the figure, the dual active bridge converter includes a digital controller 21, which is coupled to the high-voltage side bridge rectifier group 11 and the low-voltage side bridge rectifier group 12, respectively. The digital controller 21 can control the conduction or cutoff of the first power switch _S1 to the eighth power switch _S8 through the insulated gate driver 22.

In order to determine whether the load is in a light load mode or a medium to heavy load mode, the digital controller 21 may be provided with a high voltage side current detector 23 and a low voltage side current detector 24. The high voltage side current detector 23 is coupled to the DC grid port V _grid to detect the high voltage side current, and the low voltage side current detector 24 is coupled to the energy storage port V _bat to detect the low voltage side current. The digital controller 21 determines whether the load of the dual active bridge converter is in a light load mode or a medium to heavy load mode according to the high voltage side current and the low voltage side current. For example, when the energy transfer direction is from the DC grid port V _grid to the energy storage port V _bat , the light load mode is an output power of less than 200W and the medium and heavy load mode is an output power of more than 200W; when the energy transfer direction is from the energy storage port V _bat to the DC grid port V _grid , the light load mode is an output power of less than 100W and the medium and heavy load mode is an output power of more than 100W.

The digital controller 21 may be provided with a high-voltage side feedback circuit 25 and a low-voltage side feedback circuit 26. The high-voltage side feedback circuit 25 is coupled to the DC power grid port V _grid , and the low-voltage side feedback circuit 26 is coupled to the energy storage port V _bat . When the energy transfer direction is from the DC power grid port V _grid to the energy storage port V _bat , the low-voltage side feedback circuit 26 transmits a low-voltage side voltage signal to the digital controller 21 to adjust the voltage of the energy storage port V _bat ; when the energy transfer direction is from the energy storage port V _bat to the DC power grid port V _grid , the high-voltage side feedback circuit 25 transmits a high-voltage side voltage signal to the digital controller 21 to adjust the voltage of the DC power grid port V _grid .

Please refer to FIG. 3, which is a waveform diagram of the light load mode of the embodiment of the present invention. Please also refer to FIG. 1. The same reference numerals as in FIG. 1 refer to the same elements, and the same contents are not repeated. As shown in the figure, the first power switch _S1 and the fourth power switch _S4 have the same control signal waveform, the second power switch _S2 and the third power switch _S3 have the same control signal waveform, the fifth power switch _S5 and the eighth power switch _S8 have the same control signal waveform, and the sixth power switch _S6 and the seventh power switch _S7 have the same control signal waveform. The transformer high-side voltage V _p , transformer low-side voltage V _s , leakage inductance current i _LK and magnetizing inductance current i _LM in each timing sequence (t ₀ ~t ₈ ) are shown in the figure. Each timing segment is explained with the following diagram.

Please refer to Figures 4A to 4F, which are schematic diagrams of the operation of the light load mode of the embodiment of the present invention. Please also refer to Figure 3. In Figure 4A, when the timing is the first state (t ₀ ≤ t ≤ t ₁ ), the first power switch S ₁ , the fourth power switch S ₄ , the fifth power switch S ₅ and the eighth power switch S ₈ are turned on. Because the energy of the parasitic capacitance C _oss of the first power switch S ₁ , the fourth power switch S ₄ , the fifth power switch S ₅ and the eighth power switch S ₈ has been released to zero during the previous dead time, a zero voltage switching characteristic is achieved. However, the energy of the magnetizing inductance _LM and the leakage inductance _LK has not been released to zero, so the magnetizing inductance current i _LM and the leakage inductance current i _LK continue to flow until the energy is released to zero.

In Figure 4B, when the timing _is in the second state ( _t1≤t≤t2 ), when the timing reaches _t1 , the first power switch _S1 , the fourth power switch _S4 , the fifth power switch _S5 and the eighth power switch _S8 continue to be turned on. At this time, the energy of the leakage inductance _LK has been released to zero, so the leakage inductance _LK will change from releasing energy to storing energy, but the energy of the magnetizing inductance _LM has not been released to zero. At this time, the DC grid port _Vgrid will charge the leakage inductance _LK and transfer the energy to the low voltage side together with the magnetizing inductance _LM to provide load energy.

In Figure 4C, when the timing is in the third state ( _t2≤t≤t3 ), when the timing reaches _t2 , the first power switch _S1 , the fourth power switch _S4 , the fifth power switch _S5 and the eighth power switch _S8 continue to be turned on. At this time, the energy of the magnetizing inductance _LM has been released to zero, so the magnetizing inductance _LM will _change from energy release to energy storage. At this time, the DC grid port _Vgrid will charge the magnetizing inductance _LM and the leakage inductance _LK and transfer the energy to the low-voltage side to provide load energy.

In FIG. 4D, when the timing is in the fourth state ( _t3 ≤ t ≤ _t4 ), when the timing reaches _t3 , the first power switch _S1 , the fourth power switch _S4 , the fifth power switch _S5 and the eighth power switch _S8 are turned off, and the high-voltage side and the low-voltage side enter the dead time together. At this time, the magnetizing inductance _LM and the leakage inductance _LK continue to flow, and the current on the high-voltage side will follow the energy of the second parasitic capacitor _Coss2 and the third parasitic capacitor _Coss3 of the second power switch _S2 and the third power switch _S3 to charge the first parasitic capacitor _Coss1 and the fourth parasitic capacitor _Coss4 of the first power switch _S1 and the fourth power switch _S4 , and the magnetizing inductance L _M transfers energy to the low voltage side, and the low voltage side current follows the sixth parasitic capacitor C _oss6 and the seventh parasitic capacitor C _oss7 of the sixth power switch S ₆ and the seventh power switch S ₇ to charge the fifth power switch S ₅ and the eighth power switch S ₈ and provide load energy.

In FIG. 4E , when the parasitic capacitance energy of the second power switch S ₂ , the third power switch S ₃ , the sixth power switch S ₆ and the seventh power switch S ₇ is released to zero, the intrinsic diodes of the second power switch S ₂ , the third power switch S ₃ , the sixth power switch S ₆ and the seventh power switch S ₇ are turned on, and current flows through the second intrinsic diode D ₂ , the third intrinsic diode D ₃ , the sixth intrinsic diode D ₆ and the seventh intrinsic diode D ₇ .

In Figure 4F, when the timing is the fifth state (t ₄ ≤ t ≤ t ₅ ), after the timing reaches t ₄ , the second power switch S ₂ , the third power switch S ₃ , the sixth power switch S ₆ and the seventh power switch S ₇ are turned on and achieve zero-voltage switching. This is because the fourth state has released the parasitic capacitance energy of the second power switch S ₂ , the third power switch S ₃ , the sixth power switch S ₆ and the seventh power switch S ₇ to zero, and made their current flow through the intrinsic diode, thereby achieving this characteristic and the energy of the magnetizing inductance _LM and the leakage inductance _LK is not released to zero, so the magnetizing inductance current i _LM and the leakage inductance current i _LK continue to flow until the energy is released to zero.

The fifth state and the subsequent sixth state (t ₄ ≤ t ≤ t ₅ ), seventh state (t ₅ ≤ t ≤ t ₆ ) and eighth state (t ₆ ≤ t ≤ t ₇ ) are similar to the operations from the first state to the fourth state, and the difference is that the first power switch S ₁ , the fourth power switch S ₄ , the fifth power switch S ₅ and the eighth power switch S ₈ are turned on instead of the second power switch S ₂ , the third power switch S ₃ , the sixth power switch S ₆ and the seventh power switch S _7. Therefore, the operations from the sixth state to the eighth state refer to the waveforms of FIG. 3 and the contents of FIG. 4A to FIG. 4F.

Please refer to FIG. 5, which is a waveform diagram of energy transmitted from the DC power grid port to the energy storage and release terminal in the heavy load mode of the embodiment of the present invention. Please also refer to FIG. 1, the same reference numerals as in FIG. 1 refer to the same elements, and the same contents are not repeated. As shown in the figure, the first power switch _S1 and the fourth power switch _S4 have the same control signal waveform, the second power switch _S2 and the third power switch _S3 have the same control signal waveform, the fifth power switch _S5 and the eighth power switch _S8 have the same control signal waveform, and the sixth power switch _S6 and the seventh power switch _S7 have the same control signal waveform. The transformer high voltage side voltage _Vp , transformer low voltage side voltage _Vs , leakage inductance current _iLK and magnetizing inductance current _iLM in each time sequence ( _t0 ~ _t10 ) are shown in the figure. When the load condition changes from light load to medium and heavy load, the operation mode of the dual active bridge converter will change from pulse width modulation to single phase shift control. This control method uses phase modulation technology to control the control signal of the switch to cause phase shift, thereby controlling the direction of power flow and the amount of transmitted power. The detailed operation is explained with the following diagram.

Please refer to Figures 6A to 6G, which are schematic diagrams of the operation of energy being transferred from the DC grid port to the energy storage and release terminal in the heavy load mode of the embodiment of the present invention. Please also refer to Figure 5. In Figure 6A, when the timing is the first interval (t ₀ ≤ t ≤ t ₁ ), the sixth power switch S ₆ and the seventh power switch S ₇ are continuously turned on. Because the energy of the first power switch S ₁ and the fourth power switch S ₄ and the first parasitic capacitor _Coss1 and the fourth parasitic capacitor _Coss4 have been released to zero during the dead time, the first power switch S ₁ and the fourth power switch S ₄ are turned on and zero voltage switching is achieved. However, the energy of the leakage inductance L _K has not been released to zero, so the leakage inductance current i _LK continues to flow until the energy is released to zero.

In FIG. 6B , when the timing is in the second interval (t ₁ ≤ t ≤ t ₂ ), when the timing reaches t ₁ , the first power switch S ₁ , the fourth power switch S ₄ , the sixth power switch S ₆ and the seventh power switch S ₇ continue to be turned on. At this time, the energy of the leakage inductance L _K has been released to zero, so the leakage inductance L _K will change from energy release to energy storage. At this time, the low-voltage side output capacitor C ₂ will provide load energy and will charge the leakage inductance L _K with the DC grid port V _grid , so the leakage inductance current i _LK shows a linear increase.

In FIG. 6C , when the timing is in the third interval (t ₂ ≤ t ≤ t ₃ ), when the timing reaches t ₂ , the first power switch S ₁ and the fourth power switch S ₄ continue to be turned on, the sixth power switch S ₆ and the seventh power switch S ₇ are turned off, and the low-voltage side enters the dead time. At this time, the current on the low-voltage side will follow the energy of the fifth parasitic capacitor C _oss5 and the eighth parasitic capacitor C _oss8 of the fifth power switch S ₅ and the eighth power switch S ₈ to charge the sixth parasitic capacitor C _oss6 and the seventh parasitic capacitor C _oss7 of the sixth power switch S ₆ and the seventh power switch S ₇ and provide load energy until the energy of the fifth parasitic capacitor C _oss5 and the eighth parasitic capacitor C _oss8 is released to zero.

In FIG. 6D , when the energy of the fifth parasitic capacitor C _oss5 and the eighth parasitic capacitor C _oss8 of the fifth power switch S ₅ and the eighth power switch S ₈ is released to zero, the fifth intrinsic diode D ₅ and the eighth intrinsic diode D ₈ of the fifth power switch S ₅ and the eighth power switch S ₈ are turned on, and the low-voltage side current flows through the fifth intrinsic diode D ₅ and the eighth intrinsic diode D ₈ of the fifth power switch S ₅ and the eighth power switch S ₈ .

In FIG. 6E , when the timing is in the fourth interval (t ₃ ≤ t ≤ t ₄ ), when the timing reaches t ₃ , the first power switch S ₁ and the fourth power switch S ₄ continue to be turned on, because the third interval has released the energy of the fifth parasitic capacitor C _oss5 and the eighth parasitic capacitor C _oss8 of the fifth power switch S ₅ and the eighth power switch S ₈ to zero, and made their current flow through the intrinsic diode, so the fifth power switch S ₅ and the eighth power switch S ₈ achieve zero voltage switching characteristics.

In FIG. 6F, when the timing is the fifth interval ( _t4 ≤ t ≤ _t5 ), when the timing reaches _t4 , the fifth power switch _S5 and the eighth power switch _S8 continue to be turned on, the first power switch _S1 and the fourth power switch _S4 are turned off, and the high-voltage side enters the dead time. At this time, the current on the high-voltage side will follow the second parasitic capacitor _Coss2 and the third parasitic capacitor _Coss3 energy of the second power switch _S2 and the third power switch _S3 to charge the first parasitic capacitor _Coss1 and the fourth parasitic capacitor _Coss4 of the first power switch _S1 and the fourth power switch _S4 , and transfer the energy to the low-voltage side to provide load energy and send it back to the DC grid port _Vgrid until the second power switch _S2 and the third power switch S The parasitic capacitance energy of ₃ is released to zero.

In FIG. 6G , since the fifth power switch S ₅ and the eighth power switch S ₈ are continuously turned on, when the energy of the second power switch S ₂ and the third power switch S ₃ is released to zero, the intrinsic diodes of the second power switch S ₂ and the third power switch S ₃ are turned on, and the high-voltage side current flows through the second intrinsic diode D ₂ and the third intrinsic diode D ₃ .

The sixth interval (t ₅ ≤ t ≤ t ₆ ), the seventh interval (t ₆ ≤ t ≤ t ₇ ), the eighth interval (t ₇ ≤ t ≤ t ₈ ), the ninth interval (t ₈ ≤ t ≤ t ₉ ) and the tenth interval (t ₉ ≤ t ≤ t ₁₀ ) after the fifth interval are similar to the operations of the first interval to the fourth interval, the only difference being that the first power switch S ₁ , the fourth power switch S ₄ , the sixth power switch S ₆ and the seventh power switch S ₇ in the first interval are turned on and the second power switch S ₂ , the third power switch S ₃ , the fifth power switch S ₅ and the eighth power switch S ₈ in the sixth interval are turned on. The first power switch _S1 , the fourth power switch _S4 , the fifth power switch _S5 and the eighth power switch _S8 in the fourth section are turned on, and the second power switch _S2 , the third power switch _S3 , the sixth power switch _S6 and the seventh power switch _S7 in the ninth section are turned on. Therefore, the operation in the sixth section to the tenth section can refer to the waveform of Figure 5 and the contents of Figures 6A to 6G.

Please refer to FIG. 7, which is a waveform diagram of energy transmitted from the energy storage and release end to the DC power grid port in the heavy load mode of the embodiment of the present invention. Please also refer to FIG. 1, the same reference numerals as in FIG. 1 refer to the same elements, and the same contents are not repeated. As shown in the figure, the first power switch _S1 and the fourth power switch _S4 have the same control signal waveform, the second power switch _S2 and the third power switch _S3 have the same control signal waveform, the fifth power switch _S5 and the eighth power switch _S8 have the same control signal waveform, and the sixth power switch _S6 and the seventh power switch _S7 have the same control signal waveform. The transformer high voltage _Vp , transformer low voltage _Vs , leakage inductance current _iLK and magnetizing inductance current _iLM in each time sequence ( _t0 ~ _t10 ) are shown in the figure. When the load condition is medium or heavy load, the operation mode of the dual active bridge converter is to use the single phase shift control method to control the control signal of the switch by phase modulation technology to generate phase shift, thereby controlling the direction of power flow and the amount of transmitted power. Compared with the above-mentioned embodiment in which energy is transmitted from the DC grid port to the energy storage and release terminal, in this embodiment, due to the different energy transmission direction, the order of switches is different, and the corresponding transformer high voltage side voltage _Vp and transformer low voltage side voltage _Vs are also different. The detailed operation is explained with the following diagram.

Please refer to Figures 8A to 8G, which are schematic diagrams of the operation of energy being transferred from the energy storage and release end to the DC power grid port in the heavy load mode of the embodiment of the present invention. Please also refer to Figure 7. In Figure 8A, when the timing is the first interval (t ₀ ≤ t ≤ t ₁ ), when the timing is at t ₀ , the second power switch S ₂ and the third power switch S ₃ are continuously turned on. The fifth power switch S ₅ and the eighth power switch S ₈ are turned on and achieve zero voltage switching. Due to the dead time before t ₀ , the energy of the fifth power switch S ₅ and the eighth power switch S ₈ and the parasitic capacitance has been released to zero, while the energy of the leakage inductance L _K has not been released to zero, so the leakage inductance current i _LK continues to flow until the energy is released to zero.

In FIG. 8B , when the timing is in the second interval (t ₁ ≤ t ≤ t ₂ ), when the timing reaches t ₁ , the second power switch S ₂ , the third power switch S ₃ , the fifth power switch S ₅ and the eighth power switch S ₈ are continuously turned on. At this time, the energy of the leakage inductance L _K has been released to zero, so the leakage inductance L _K will change from energy release to energy storage. At this time, the high-voltage side output capacitor C ₁ will provide load energy and will charge the leakage inductance L _K with the energy storage terminal V _bat , so the leakage inductance current i _LK shows a linear increase.

In FIG. 8C , when the timing is in the third interval (t ₂ ≤ t ≤ t ₃ ), when the timing reaches t ₂ , the fifth power switch S ₅ and the eighth power switch S ₈ continue to be turned on, the second power switch S ₂ and the third power switch S ₃ are turned off, and the high-voltage side enters the dead time. At this time, the current on the high-voltage side will follow the energy of the first parasitic capacitor _Coss1 and the fourth parasitic capacitor _Coss4 of the first power switch S ₁ and the fourth power switch S ₄ to charge the second parasitic capacitor _Coss2 and the third parasitic capacitor _Coss3 of the second power switch S ₂ and the third power switch S ₃ and provide load energy until the energy of the first parasitic capacitor _Coss1 and the fourth parasitic capacitor _Coss4 is released to zero.

In FIG. 8D , the fifth power switch S ₅ and the eighth power switch S ₈ are continuously turned on. When the energy of the first parasitic capacitor C _oss1 and the fourth parasitic capacitor C _oss4 of the first power switch S ₁ and the fourth power switch S ₄ is released to zero, the first intrinsic diode D ₁ and the fourth intrinsic diode D ₄ of the first power switch S ₁ and the fourth power switch S ₄ are turned on, and the high-voltage side current flows through the first intrinsic diode D ₁ and the fourth intrinsic diode D ₄ of the first power switch S ₁ and the fourth power switch S ₄ .

In Figure 8E, when the timing is in the fourth interval ( _t3 ≤ t ≤ _t4 ), when the timing reaches _t3 , the fifth power switch _S5 and the eighth power switch _S8 continue to be turned on, because the third interval has released the energy of the first parasitic capacitor _Coss1 and the fourth parasitic capacitor _Coss4 of the first power switch _S1 and the fourth power switch _S4 to zero and made their current flow through the intrinsic diode, so the first power switch _S1 and the fourth power switch _S4 achieve zero voltage switching.

In FIG. 8F, when the timing is the fifth interval (t ₄ ≤ t ≤ t ₅ ), when the timing reaches t ₄ , the first power switch S ₁ and the fourth power switch S ₄ continue to be turned on, the fifth power switch S ₅ and the eighth power switch S ₈ are turned off, and the low-voltage side enters the dead time. At this time, the current on the low-voltage side will follow the sixth parasitic capacitor C _oss6 and the seventh parasitic capacitor C _oss7 energy of the sixth power switch S ₆ and the seventh power switch S ₇ to charge the fifth parasitic capacitor C _oss5 and the eighth parasitic capacitor C _oss8 of _the fifth power switch S ₅ and the eighth power switch S 8, and transfer the energy to the high-voltage side to provide load energy and return it to the energy storage terminal V _bat until the sixth power switch S ₆ and the seventh power switch S The parasitic capacitance energy of ₇ is released to zero.

In FIG. 8G , since the first power switch S ₁ and the fourth power switch S ₄ are continuously turned on, when the sixth parasitic capacitor C _oss6 and the seventh parasitic capacitor C _oss7 of the sixth power switch S ₆ and the seventh power switch S ₇ release their energies to zero, the intrinsic diodes of the sixth power switch S ₆ and the seventh power switch S ₇ are turned on, and the low-voltage side current flows through the sixth intrinsic diode D ₆ and the seventh intrinsic diode D ₇ .

The sixth interval (t ₅ ≤ t ≤ t ₆ ), the seventh interval (t ₆ ≤ t ≤ t ₇ ), the eighth interval (t ₇ ≤ t ≤ t ₈ ), the ninth interval (t ₈ ≤ t ≤ t ₉ ) and the tenth interval (t ₉ ≤ t ≤ t ₁₀ ) after the fifth interval are similar to the operations of the first to fourth intervals, with the only difference that the second power switch S ₂ , the third power switch S ₃ , the fifth power switch S ₅ and the eighth power switch S ₈ in the first interval are turned on instead of the first power switch S ₁ , the fourth power switch S ₄ , the sixth power switch S ₆ and the seventh power switch S ₇ in the sixth interval. The first power switch _S1 , the fourth power switch _S4 , the fifth power switch _S5 and the eighth power switch _S8 in the fourth section are turned on, and the second power switch _S2 , the third power switch _S3 , the sixth power switch _S6 and the seventh power switch _S7 in the ninth section are turned on. Therefore, the operation in the sixth section to the tenth section can refer to the waveform of Figure 7 and the contents of Figures 8A to 8G.

Please refer to FIG. 9A and FIG. 9B, which are schematic diagrams of the conversion efficiency of the embodiments of the present invention, wherein FIG. 9A is a comparison diagram of the efficiency of the dual active bridge converter in the forward state, and FIG. 9B is a comparison diagram of the efficiency of the dual active bridge converter in the reverse state. The dual active bridge converter according to the aforementioned embodiment was tested, and the waveforms were measured in the forward state (energy is transferred from the high voltage side to the low voltage side) and the reverse state (energy is transferred from the low voltage side to the high voltage side), and the efficiency of the single phase shift control method was compared with the efficiency of the mixed pulse width strip variation method and the single phase shift control method.

In Figure 9A, the forward state measured waveform part, according to the load conditions, under light load (output power below 200W), the dual active bridge converter operates in the pulse width modulation control mode, and under medium and heavy load (output power rises to more than 200W), the dual active bridge converter operation changes from the pulse width modulation control mode to the phase modulation control mode. Compared with the simple single phase shift control method operation, the efficiency is improved by about 10%, and the maximum efficiency can reach 96.267%.

In Figure 9B, the reverse state measured waveform part, according to the load conditions, under light load (output power below 100W), the dual active bridge converter operates in the pulse width modulation control mode, and under medium and heavy load (output power rises above 100W), the dual active bridge converter operation changes from the pulse width modulation control mode to the phase modulation control mode. Compared with the simple single phase shift control method operation, the efficiency is improved by about 5%, and the maximum efficiency can reach 97.331%.

The above description is for illustrative purposes only and is not intended to be limiting. Any equivalent modifications or changes made to the invention without departing from the spirit and scope of the invention shall be included in the scope of the attached patent application.

10: Dual active bridge converter 11: High voltage side bridge rectifier group 12: Low voltage side bridge rectifier group 13: Transformer 13A: First coil 13B: Second coil 21: Digital controller 22: Insulated gate driver 23: High voltage side current detector 24: Low voltage side current detector 25: High voltage side feedback circuit 26: Low voltage side feedback circuit _C1 : High voltage side output capacitor _C2 : Low voltage side output capacitor _Coss1 : First parasitic capacitor _Coss2 : Second parasitic capacitor _Coss3 : Third parasitic capacitor _Coss4 : Fourth parasitic capacitor _Coss5 : fifth parasitic capacitor C _oss6 : sixth parasitic capacitor C _oss7 : seventh parasitic capacitor C _oss8 : eighth parasitic capacitor D ₁ : first intrinsic diode D ₂ : second intrinsic diode D ₃ : third intrinsic diode D ₄ : fourth intrinsic diode D ₅ : fifth intrinsic diode D ₆ : sixth intrinsic diode D ₇ : seventh intrinsic diode D ₈ : eighth intrinsic diode i _LK : leakage inductance current i _LM : magnetizing inductance current L _K : leakage inductance L _M : magnetizing inductance n1 : first node n2 : second node n3 : third node n4 : fourth node n5 : fifth node n6 : sixth node n7 : seventh node n8 : eighth node S ₁ : first power switch S ₂ : second power switch S ₃ : third power switch S ₄ : fourth power switch S ₅ : fifth power switch S ₆ : sixth power switch S ₇ : seventh power switch S ₈ : eighth power switch V _bat : energy storage port V _grid : DC power grid port V _p : transformer high voltage side voltage V _s : transformer low voltage side voltage

In order to make the technical features, contents and advantages of the present invention and the effects that can be achieved more obvious, the present invention is explained with the following figures: Figure 1 is a schematic diagram of the dual active bridge converter of the embodiment of the present invention. Figure 2 is a schematic diagram of the digital controller of the embodiment of the present invention. Figure 3 is a waveform diagram of the light load mode of the embodiment of the present invention. Figures 4A to 4F are operation diagrams of the light load mode of the embodiment of the present invention. Figure 5 is a waveform diagram of energy transmitted from the DC power grid port to the energy storage and release end in the heavy load mode of the embodiment of the present invention. Figures 6A to 6G are operation diagrams of energy transmitted from the DC power grid port to the energy storage and release end in the heavy load mode of the embodiment of the present invention. Figure 7 is a waveform diagram of energy being transferred from the energy storage and release end to the DC power grid port in the overload mode of the embodiment of the present invention. Figures 8A to 8G are operation diagrams of energy being transferred from the energy storage and release end to the DC power grid port in the overload mode of the embodiment of the present invention. Figures 9A and 9B are diagrams of conversion efficiency of the embodiment of the present invention.

10: Dual active axle converter

11: High voltage side bridge rectifier group

12: Low voltage side bridge rectifier group

13: Transformer

13A: First coil

13B: Second coil

C ₁ : High voltage side output capacitor

C ₂ : Low voltage side output capacitor

C _oss1 : First parasitic capacitance

C _oss2 : Second parasitic capacitance

C _oss3 : The third parasitic capacitance

C _oss4 : Fourth parasitic capacitance

C _oss5 : Fifth parasitic capacitance

C _oss6 : Sixth parasitic capacitance

C _oss7 : Seventh parasitic capacitance

C _oss8 : Eighth parasitic capacitance

D ₁ : First intrinsic diode

D ₂ : Second intrinsic diode

D ₃ : The third intrinsic diode

D ₄ : The fourth essential diode

D ₅ : The fifth essential diode

D ₆ : Sixth essential diode

D ₇ : Seventh Essence Diode

D ₈ : The eighth essential diode

i _LK : Leakage inductance current

i _LM : Magnetizing inductance current

L _K : Leakage inductance

L _M : Magnetizing inductance

n1: first node

n2: The second node

n3: The third node

n4: The fourth node

n5: The fifth node

n6: sixth node

n7: seventh node

n8: The eighth node

S ₁ : First power switch

S ₂ : Second power switch

S ₃ : The third power switch

S ₄ : Fourth power switch

S ₅ : Fifth power switch

S ₆ : Sixth power switch

S ₇ : Seventh power switch

S ₈ : Eighth power switch

V _bat : Energy storage port

V _grid : DC grid port

V _p : Transformer high voltage side voltage

V _s : Transformer low voltage side voltage

Claims (9)

A dual active bridge converter, comprising: A high voltage side bridge rectifier group, comprising a first power switch, a second power switch, a third power switch and a fourth power switch, wherein the first end of the first power switch and the third power switch are coupled to a first node, the second end of the first power switch and the first end of the second power switch are coupled to a second node, the second end of the third power switch and the first end of the fourth power switch are coupled to a third node, and the second end of the second power switch and the fourth power switch are coupled to a fourth node; A DC grid port, wherein the first end of the DC grid port is coupled to the first node, and the second end of the DC grid port is coupled to the fourth node; A low-voltage side bridge rectifier group, comprising a fifth power switch, a sixth power switch, a seventh power switch and an eighth power switch, wherein the first ends of the fifth power switch and the seventh power switch are coupled to a fifth node, the second end of the fifth power switch and the first end of the sixth power switch are coupled to a sixth node, the second end of the seventh power switch and the first end of the eighth power switch are coupled to a seventh node, and the second ends of the sixth power switch and the eighth power switch are coupled to an eighth node; A storage energy port, wherein the first end of the storage energy port is coupled to the fifth node, and the second end of the storage energy port is coupled to the eighth node; A transformer is arranged between the high-voltage side bridge rectifier group and the low-voltage side bridge rectifier group, and the transformer includes a first coil and a second coil, and the two ends of the second coil are coupled to the sixth node and the seventh node respectively; A leakage inductor is arranged between the high-voltage side bridge rectifier group and the transformer, one end of the leakage inductor is coupled to the second node, the other end of the leakage inductor is coupled to the first coil, and the other end of the first coil is coupled to the third node; and A magnetizing inductor is arranged in parallel with the transformer, one end of the magnetizing inductor is coupled to the leakage inductor and the first coil, and the other end of the magnetizing inductor is coupled to the third node and the first coil; When the load of the dual active bridge converter is a light load mode, the dual active bridge converter controls the high voltage side bridge rectifier group and the low voltage side bridge rectifier group by a pulse width modulation method. When the load is a medium to heavy load mode, the dual active bridge converter controls the high voltage side bridge rectifier group and the low voltage side bridge rectifier group by a single phase shift control method. The dual active bridge converter as described in claim 1 further includes a digital controller, which is coupled to the high-voltage side bridge rectifier group and the low-voltage side bridge rectifier group respectively, and the digital controller controls the conduction or cutoff of the first power switch to the eighth power switch. A dual active bridge converter as described in claim 2, wherein the digital controller is provided with a high voltage side current detector and a low voltage side current detector, the high voltage side current detector is coupled to the DC grid port to detect a high voltage side current, the low voltage side current detector is coupled to the energy storage port to detect a low voltage side current, and the digital controller determines whether the load of the dual active bridge converter is the light load mode or the medium to heavy load mode based on the high voltage side current and the low voltage side current. A dual-active bridge converter as described in claim 3, wherein when the energy transfer direction is from the DC grid port to the energy storage and release port, the light load mode has an output power of less than 200W and the medium-to-heavy load mode has an output power of more than 200W; when the energy transfer direction is from the energy storage and release port to the DC grid port, the light load mode has an output power of less than 100W and the medium-to-heavy load mode has an output power of more than 100W. A dual active bridge converter as described in claim 2, wherein the digital controller is provided with a high voltage side feedback circuit and a low voltage side feedback circuit, the high voltage side feedback circuit is coupled to the DC grid port, and the low voltage side feedback circuit is coupled to the energy storage port. A dual active bridge converter as described in claim 5, wherein when the energy transfer direction is from the DC power grid port to the energy storage port, the low-voltage side feedback circuit transmits a low-voltage side voltage signal to the digital controller to adjust the voltage of the energy storage port; when the energy transfer direction is from the energy storage port to the DC power grid port, the high-voltage side feedback circuit transmits a high-voltage side voltage signal to the digital controller to adjust the voltage of the DC power grid port. A dual active bridge converter as described in claim 1, wherein the high voltage side bridge rectifier group includes a first intrinsic diode and a first parasitic capacitor arranged in parallel with the first power switch, a second intrinsic diode and a second parasitic capacitor arranged in parallel with the second power switch, a third intrinsic diode and a third parasitic capacitor arranged in parallel with the third power switch, and a fourth intrinsic diode arranged in parallel with the fourth power switch. and a fourth parasitic capacitor, the low-voltage side bridge rectifier group includes a fifth intrinsic diode and a fifth parasitic capacitor arranged in parallel with the fifth power switch, a sixth intrinsic diode and a sixth parasitic capacitor arranged in parallel with the sixth power switch, a seventh intrinsic diode and a seventh parasitic capacitor arranged in parallel with the seventh power switch, and an eighth intrinsic diode and an eighth parasitic capacitor arranged in parallel with the eighth power switch. The dual active bridge converter as described in claim 1 further includes a high-voltage side output capacitor and a low-voltage side output capacitor, one end of the high-voltage side output capacitor is coupled to the first end of the DC grid port and the first node, the other end of the high-voltage side output capacitor is coupled to the second end of the DC grid port and the fourth node, one end of the low-voltage side output capacitor is coupled to the first end of the energy storage port and the fifth node, and the other end of the low-voltage side output capacitor is coupled to the second end of the energy storage port and the eighth node. A dual active bridge converter as described in claim 1, wherein the turns ratio of the first coil to the second coil is 8:1.