TWI837743B - Memory device using semiconductor components - Google Patents

Abstract

A memory device using a semiconductor component is formed of a plurality of pages arranged in a column direction, and the page is composed of a plurality of memory cells arranged in a row direction on a substrate. Each memory cell contained in each page has a belt-shaped P layer 2. Moreover, a N⁺ layer 3a connected to a source line SL and a N⁺ layer 3b connected to a bit line are provided on two sides of the P layer 2. Moreover, a first gate insulating layer 4a surrounding a portion of the P layer 2 connected to the N⁺ layer 3a, and a second gate insulating layer 4b surrounding the P layer 2 connected to the N⁺ layer 3b are provided. Moreover, a first gate conductor layer 5a connected to a first plate line and a second gate conductor layer 5b connected to a second plate line which cover each of the two sides of the first gate insulating layer 4a and are separated from each other, are included. Moreover, a third gate conductor layer 5c connected to a word line and surrounding the second gate insulating layer 4b is provided. The voltages applied to the word line, the first plate line, the second plate line, the source line and the bit line are controlled, to perform a page write operation for maintaining a group of electrical holes formed by the impact ionization phenomenon inside the P layer 2. The voltages applied to the word line, the first plate line, the second plate line, the source line and the bit line are controlled, to perform a page erase operation for removing the group of electrical holes inside the P layer 2 from one or both of the N⁺ layer 3a connected to the source line SL and the N⁺ layer 3b connected to the bit line. The bit line is connected to a sense amplifier circuit, and the voltages applied to the word line, the first plate line, the second plate line, the source line, and the bit line are controlled during a page read operation, so that the page data of a group of the memory cells selected by the word line is read out to the sense amplifier circuit. In one or both of the page write operation and the page read operation, a pulse voltage of positive bias equal to or lower than the voltage of the first plate line is input to the second plate line.

Description

Memory devices using semiconductor components

The present invention relates to a memory device using semiconductor elements.

In recent years, the development of LSI (Large Scale Integration) technology has required higher integration and higher performance of memory components.

As memory elements without capacitors, there are PCM (Phase Change Memory) connected to a resistance change element. For example, refer to non-patent document 1), RRAM (Resistive Random Access Memory). For example, refer to non-patent document 2), and MRAM (Magneto-resistive Random Access Memory) that changes the direction of magnetic spin by electric current to change the resistance. For example, refer to non-patent document 3). Since these do not require capacitors, memory elements can be highly integrated. In addition, there is a DRAM memory cell composed of a MOS transistor without a capacitor (refer to patent document 1 and non-patent document 4). This case is about a dynamic flash memory that does not have a resistance variable element or a capacitor and can be composed only of MOS (Metal Oxide Semiconductor) transistors.

FIG8 shows the write operation of the aforementioned DRAM memory cell composed of a MOS transistor without a capacitor, FIG9 shows the operational problems, and FIG10 shows the read operation (refer to non-patent documents 7 to 10).

FIG8 shows the write operation of the DRAM memory cell. FIG8(a) shows the "1" write state. Here, the memory cell is formed on the SOI substrate 100, and is composed of a source N ⁺ layer 103 (hereinafter, the semiconductor region containing a high concentration of donor impurities is referred to as the "N ⁺ layer") connected to the active line SL, a drain N ⁺ layer 104 connected to the bit line BL, a gate conductor layer 105 connected to the word line WL, and a floating body 102 of a MOS transistor 110a. It does not have a capacitor, and a DRAM memory cell is composed of a MOS transistor 110a. In addition, directly below the floating body 102 of the P layer (hereinafter, the semiconductor region containing acceptor impurities is referred to as the "P layer"), there is a _SiO2 layer 101 in contact with the SOI substrate. When writing "1" to the memory cell composed of a MOS transistor 110a, the MOS transistor 110a is operated in the linear region. That is, there is a pinch off 108 in the channel 107 of the electrons extending from the source N ⁺ layer 103, and they will not reach the drain N ⁺ layer 104 connected to the bit line. In this way, if the bit line BL connected to the drain N ⁺ layer 104 and the word line WL connected to the gate conductive layer 105 are both set to high voltage, and the gate voltage is set to about 1/2 of the drain voltage to operate the MOS transistor 110a, the electric field intensity will become maximum in the clamping point 108 near the drain N ⁺ layer 104. As a result, the accelerated electrons flowing from the source N ⁺ layer 103 toward the drain N ⁺ layer 104 will collide with the Si lattice, and will generate electron-hole pairs (impact ionization phenomenon) due to the motion energy lost at this point. Most of the generated electrons (not shown) reach the drain N ⁺ layer 104. In addition, a very small portion of the extremely hot electrons pass through the gate oxide film 109 and reach the gate conductor layer 105. Furthermore, the holes 106 generated at the same time charge the floating body 102. At this time, the holes generated help to increase the majority of carriers because the floating body 102 is P-type Si. The floating body 102 is filled with the generated holes 106. If the high voltage of the floating body 102 is higher than the source N ⁺ layer 103 to above Vb, further generated holes will discharge to the source N ⁺ layer 103. Here, Vb is the built-in voltage of the PN junction between the source N ⁺ layer 103 and the P-layer floating body 102, which is about 0.7V. FIG8( b ) shows the situation where the float 102 has been saturated and charged by the generated holes 106.

Next, Figure 8(c) is used to illustrate the "0" write operation of the memory cell 110. For the common selection word line WL, there are randomly a memory cell 110a with "1" written and a memory cell 110b with "0" written. In Figure 8(c), the situation of changing from a "1" write state to a "0" write state is shown. When "0" is written, the voltage of the bit line BL is set to a negative bias, and the PN junction between the drain N ⁺ layer 104 and the P-layer floating body 102 is set to a positive bias. As a result, the hole 106 generated in the floating body 102 in the previous cycle flows to the drain N ⁺ layer 104 connected to the bit line BL. If the write operation is completed, two memory cells will be obtained: a memory cell 110a (FIG. 8(b)) filled with generated holes 106, and a memory cell 110b (FIG. 8(c)) from which generated holes have been discharged. The potential of the floating body 102 of the memory cell 110a filled with holes 106 is higher than that of the floating body 102 without generated holes. Therefore, the critical voltage of the memory cell 110a is lower than the critical voltage of the memory cell 110b. The situation is shown in FIG8(d).

Next, use Figure 9 to explain the operational problems of the memory cell composed of a MOS transistor. As shown in Figure 9(a), the capacitance C _FB of the floating body 102 is the sum of the capacitance C _WL , the junction capacitance C _SL , and the junction capacitance C _BL . The capacitance C _WL is the capacitance between the gate connected to the word line and the floating body 102. The junction capacitance C _SL is the junction capacitance of the PN junction between the source N ⁺ layer 103 connected to the active electrode line and the floating body 102. The junction capacitance C _BL is the junction capacitance of the PN junction between the drain layer 104 connected to the bit line and the floating body 102. The capacitance C _FB of the floating body 102 can be expressed as

C _FB =C _WL +C _BL +C _SL (1). Therefore, if the word line voltage V _WL oscillates during writing, the voltage of the floating body 102, which becomes the memory node (contact) of the memory cell, will also be affected. The situation is shown in Figure 9(b). If the word line voltage V _WL rises from 0V to V _ProgWL during writing, the voltage V _FB of the floating body 102 rises from the initial state voltage V _FB1 before the word line voltage changes to V _FB2 due to the capacitive coupling with the word line. The voltage change △V _FB can be expressed as

△V _FB =V _FB2 -V _FB1 =C _WL /(C _WL +C _BL +C _SL )×V _ProgWL (2).

Here, β is called the coupling ratio, and can be expressed as β=C _WL /(C _WL +C _BL +C _SL )(3). In this memory cell, the contribution rate of C _WL is relatively large, for example, C _WL :C _BL :C _SL =8:1:1. At this time, β=0.8. If the word line, for example, changes from 5V during writing to 0V after the writing is completed, the float 102 will be subjected to oscillation noise of 5V×β=4V due to the capacitive coupling between the word line and the float 102. Therefore, there is a problem that the potential difference margin between the floating body "1" potential and the "0" potential during writing cannot be fully obtained.

Figure 10 shows the read operation. Figure 10(a) shows the "1" write state, and Figure 10(b) shows the "0" write state. However, in reality, even if Vb is written into the float 102 in the "1" write state, when the word line returns to 0V due to the end of writing, the float 102 will be reduced to a negative bias. When "0" is written, it will become more negatively biased, so as shown in Figure 10(c), the potential difference margin between "1" and "0" cannot be fully increased during writing. This situation where the action margin is small is a major problem of this DRAM memory cell. In addition, there is also the issue of making this DRAM memory cell high-density.

In addition, on the SOI (Silicon on Insulator) layer, there is a Twin-Transistor memory element that uses two MOS transistors to form a memory cell (for example, refer to Patent Documents 4 and 5). In these elements, the N ⁺ layer that serves as the source or drain of the floating channels that distinguish the two MOS transistors is formed by contacting the insulating layer. By this N ⁺ layer contacting the insulating layer, the floating channels of the two MOS transistors are electrically separated. Therefore, the hole group belonging to the signal charge is accumulated in the floating channel of one transistor. As mentioned above, the voltage of the floating channel with holes accumulated therein will vary greatly as shown in equations (2) and (3) due to the pulse voltage applied to the gate electrode by the adjacent MOS transistor. As a result, as explained using FIGS. 8 to 10 , the operating margin of “1” and “0” during writing cannot be sufficiently increased (for example, refer to non-patent document 8 and FIG. 8 ).

[Prior Art Literature]

[Patent Literature]

Patent document 1: Japanese Patent Publication No. 3-171768

Patent document 2: US2008/0137394A1

Patent document 3: US2003/0111681A1

[Non-patent literature]

Non-patent literature 1: H. S. Philip Wong, S. Raoux, S. Kim, Jiale Liang, J. R. Reifenberg, B. Rajendran, M. Asheghi and K. E. Goodson: “Phase Change Memory,” Proceeding of IEEE, Vol.98, No 12, December, pp.2201-2227 (2010)

Non-patent literature 2: T. Tsunoda, K. Kinoshita, H. Noshiro, Y. Yamazaki, T. Iizuka, Y. Ito, A. Takahashi, A. Okano, Y. Sato, T. Fukano, M. Aoki, and Y.Sugiyama: “Low Power and high Speed Switching of Ti-doped NiO ReRAM under the Unipolar Voltage Source of less than 3V,” IEDM (2007)

Non-patent document 3: W. Kang, L. Zhang, J. Klein, Y. Zhang, D. Ravelosona, and W. Zhao: “Reconfigurable Codesign of STT-MRAM Under Process Variations in Deeply Scaled Technology,” IEEE Transaction on Electron Devices, pp.1-9 (2015)

Non-patent document 4: M. G. Ertosum, K. Lim, C. Park, J. Oh, P. Kirsch, and K. C. Saraswat: “Novel Capacitorless Single-Transistor Charge-Trap DRAM (1T CT DRAM) Utilizing Electron,” IEEE Electron Device Letter, Vol. 31, No.5, pp.405-407 (2010)

Non-patent document 5: E. Yoshida, and T. Tanaka: “A Capacitorless 1T-DRAM Technology Using Gate-Induced Drain-Leakage (GIDL) Current for Low-Power and High-Speed Embedded Memory,” IEEE Transactions on Electron Devices, Vol. 53, No. 4, pp. 692-697,Apr. 2006.

Non-patent document 6: Hiroshi Takato, Kazumasa Sunouchi, Naoko Okabe, Akihiro Nitayama, Katsuhiko Hieda, Fumio Horiguchi, and Fujio Masuoka: IEEE Transaction on Electron Devices, Vol.38, No.3, pp.573-578 (1991)

Non-patent document 7: N.Loubet, et al.: “Stacked Nanosheet Gate-All-Around Transistor to Enable Scaling Beyond FinFET,” 2017 IEEE Symposium on VLSI Technology Digest of Technical Papers, T17-5, T230-T231, June 2017.

Non-patent literature 8: F. Morishita, H. Noda, I. Hayashi, T. Gyohten, M. Oksmoto, T. Ipposhi, S. Maegawa, K. Dosaka, and K. Arimoto: “Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI,” IEICE Trans. Electron., Vol. E90-c., No.4 pp.765-771 (2007)

Non-patent literature 9: T. Ohsawa, K. Fujita, T. Higashi, Y. Iwata, T. Kajiyama, Y. Asao, and K. Sunouchi: “Memory design using a one-transistor gain cell on SOI,” IEEE JSSC, vol.37, No.11, pp1510-1522 (2002).

Non-patent literature 10: T. Shino, N. Kusunoki, T. Higashi, T. Ohsawa, K. Fujita, K. Hatsuda, N. Ikumi, F. Matsuoka, Y. Kajitani, R. Fukuda, Y. Watanabe, Y. Minami, A. Sakamoto, J. Nishimura, H. Nakajima, M. Morikado, K. Inoh, T. Hamamoto, A. Nitayama: “Floating Body RAM Technology and its Scalability to 32nm Node and Beyond,” IEEE IEDM (2006).

In a transistor-type DRAM (gain unit) that has been removed from a memory device using MOS transistors, the capacitance coupling between the word line and the floating body is large. When the potential of the word line oscillates when reading or writing data, there is a problem that it is directly transmitted as noise to the MOS transistor. As a result, it causes the problem of erroneous reading or erroneous rewriting of memory data, making it difficult to achieve practical use of a transistor-type DRAM (gain unit) that has been removed from a capacitor. Furthermore, the above problems must be solved and the memory unit must be made high-performance and high-density.

In order to solve the above problems, the present invention is a memory device using semiconductor elements, which is composed of a plurality of pages arranged in the column direction, wherein the page is composed of a plurality of memory cells arranged in the row direction on a substrate;

Each memory unit contained in the aforementioned pages has:

The first semiconductor layer stands vertically or extends horizontally on the substrate relative to the aforementioned substrate;

The first impurity layer and the second impurity layer are located at two ends of the first semiconductor layer in a first direction parallel to the substrate;

The first gate insulating layer covers the two side surfaces of the first semiconductor layer near the first impurity layer in a second direction parallel to the substrate and perpendicular to the first direction;

The first gate conductive layer and the second gate conductive layer cover both side surfaces of the first gate insulating layer when viewed from above, and are separated from each other;

The second gate insulating layer covers the first semiconductor layer near the second impurity layer; and

The third gate conductor layer covers the aforementioned second gate insulating layer;

The aforementioned memory device controls the voltage applied to the aforementioned first gate conductor layer, the aforementioned second gate conductor layer, the aforementioned third gate conductor layer, the aforementioned first impurity layer, and the aforementioned second impurity layer, and maintains a hole group formed by impact ionization phenomenon inside the aforementioned first semiconductor layer, and the hole group is;

During a page write operation, the memory device sets the voltage of the first semiconductor layer to a first data retention voltage that is higher than the voltage of one or both of the first impurity layer and the second impurity layer;

During the page erase operation, the memory device controls the voltage applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the first impurity layer, and the second impurity layer, thereby removing the hole group from one or both of the first impurity layer and the second impurity layer, and setting the voltage of the first semiconductor layer to a second data retention voltage lower than the first data retention voltage;

The first impurity layer of the memory cell is connected to the source line, the second impurity layer is connected to the bit line, the first gate conductor layer is connected to the first plate line, the second gate conductor layer is connected to the second plate line, and the third gate conductor layer is connected to the word line;

The aforementioned bit line is connected to the sense amplifier circuit;

During the page read operation, the memory device controls the voltage applied to the word line, the first plate line, the second plate line, the source line and the bit line, and reads the page data of the memory cell group selected by the word line into the sense amplifier circuit;

In one or both of the aforementioned page write operation and the aforementioned page read operation, a pulse voltage of a positive bias voltage lower than the voltage of the aforementioned first plate line is input to the aforementioned second plate line (first invention).

The second invention is the same as the first invention, and during the page erase operation, the same pulse voltage or a fixed voltage lower than the first plate line is input to the first plate line and the second plate line (the second invention).

The third invention is the same as the first invention, but during the page reading operation, a fixed voltage higher than the pulse voltage of the aforementioned forward bias voltage of the aforementioned second plate line is input to the aforementioned first plate line (the third invention).

The fourth invention is the first invention as described above, wherein, in one or both of the aforementioned page write operation and the aforementioned page read operation, the pulse voltage amplitude of the aforementioned forward bias voltage of the aforementioned second plate line is shorter than the pulse voltage amplitude of the aforementioned word line (the fourth invention).

The fifth invention is the first invention as described above, wherein the third gate conductor layer is composed of at least two gate conductor layers, and they are operated in a synchronous or asynchronous manner respectively (the fifth invention).

The sixth invention is the first invention as described above, wherein the gate capacitance obtained by adding one or both of the first gate capacitance between the first gate conductive layer and the first semiconductor layer and the second gate capacitance between the second gate conductive layer and the first semiconductor layer is greater than the third gate capacitance between the third gate conductive layer and the first semiconductor layer (the sixth invention).

1: Insulating substrate

2,22a,22b,22A,22B,22ab,22bb:P layer

3a,3b,23a,23b,23c,23d,23B,23D:N ⁺ layer

4a,24a: First gate insulating layer

4b, 24b: Second gate insulation layer

5a, 25a, 25b: First gate conductor layer

5b,26: Second gate conductor layer

5c,27: The third gate conductor layer

6,30,32: Insulating layer

11: Hole group

12a: Inversion layer

13: Clamping point

22a,22aa:P ⁺ layer

31a,31b,31c,31d,32a,32b,33a: contact holes

35: First wiring conductor layer

36: Second wiring conductor layer

37: Third wiring conductor layer

38a: Fourth wiring conductor layer

38b: Fifth wiring conductor layer

BL0 to BL2: bit lines

C00 to C22: memory unit

CSL0 to CSL2: Column selection lines

FB: Floating body

IO,/IO: input and output lines

PL1, PL10 to PL12: First plate line

PL2, PL20 to PL22: Second plate line

SA0 to SA2: Sense amplifier circuit

SL: Source line

SL1: First source line

T0 to T12: time

T0A to T2D: MOS transistor

Vb: built-in voltage

V _FB ,V _BLH ,V _PL1H ,V _PL2H ,V _PL1L : Voltage

V _PLL : First voltage

V _PLH : Second voltage

Vss: third voltage

V _WLH : Fourth voltage

V _FB “1”: First data retention voltage

V _FB “0”: Second data retention voltage

WL0 to WL2: word line

Figure 1 is a structural diagram of the memory device of the first embodiment.

FIG2 is a diagram for explaining the erase operation mechanism of the memory device of the first embodiment.

FIG3 is a diagram for explaining the write operation mechanism of the memory device of the first embodiment.

FIG4 is a diagram for explaining the read operation mechanism of the memory device of the first embodiment.

FIG. 5A is a diagram for explaining the mechanism of the hole-pushing erase operation of the first embodiment in which only a positive bias voltage is applied to perform a page erase operation.

FIG. 5B is a diagram for explaining the mechanism of the hole-pushing erase operation of the first embodiment in which only a positive bias voltage is applied to perform a page erase operation.

FIG6 is a diagram for explaining the read operation mechanism of the memory device with SGT in the first embodiment.

FIG. 7A is a circuit block diagram for illustrating the improvement of write and read operations of a memory device having SGT in the first embodiment.

FIG. 7B is a circuit block diagram for illustrating the improvement of write and read operations of a memory device having SGT in the first embodiment.

FIG. 7C is an action waveform diagram for illustrating the improvement of the write operation and the read operation of the memory device with SGT in the first embodiment.

FIG. 7D is a circuit block diagram for illustrating the improvement of write and read operations of a memory device having SGT in the first embodiment.

FIG. 7E is an action waveform diagram for illustrating the improvement of write and read operations of a memory device having SGT in the first embodiment.

FIG. 7F is a circuit block diagram for illustrating the improvement of write and read operations of a memory device having SGT in the first embodiment.

FIG8 is a diagram for explaining the operational problems of a conventional DRAM memory cell without a capacitor.

FIG. 9 is a diagram for explaining the operational problems of a conventional DRAM memory cell without a capacitor.

FIG. 10 is a diagram showing a read operation of a DRAM memory cell without a capacitor according to a conventional example.

The following refers to the drawings to explain the structure, driving method, and manufacturing method of the memory device using semiconductor elements (hereinafter referred to as dynamic flash memory) of the present invention.

(First implementation form)

Figures 1 to 4 are used to illustrate the structure, operation mechanism and manufacturing method of the first dynamic flash memory unit of the first embodiment of the present invention. Figure 1 is used to illustrate the structure of the first dynamic flash memory unit. Furthermore, Figure 2 is used to illustrate the data erasing mechanism, Figure 3 is used to illustrate the data writing mechanism, and Figure 4 is used to illustrate the data reading mechanism.

FIG1 shows the structure of the first dynamic flash memory unit of the first embodiment of the present invention. (a) is a horizontal cross-sectional view along the Z-Z’ line of (b), (b) is a vertical cross-sectional view along the X-X’ line of (a), (c) is a vertical cross-sectional view along the Y1-Y1’ line of (a), and (d) is a vertical cross-sectional view along the Y2-Y2’ line of (a).

A strip-shaped P layer 2 (an example of a "first semiconductor layer" in the scope of the patent application) is provided on a substrate 1 (an example of a "substrate" in the scope of the patent application). Furthermore, an N ⁺ layer 3a (a "first impurity layer" in the scope of the patent application) and an N ⁺ layer 3b (an example of a "second impurity layer" in the scope of the patent application) are provided on both sides of the P layer 2 in the XX' direction. It has a first gate insulating layer 4a (an example of the "first gate insulating layer" in the scope of the patent application) surrounding the P layer 2 connected to the N ⁺ layer 3a, and a second gate insulating layer 4b (an example of the "second gate insulating layer" in the scope of the patent application) surrounding the P ^layer 2 connected to the N+ layer 3b. Furthermore, there is a first gate conductor layer 5a (an example of the "first gate conductor layer" in the scope of the patent application) and a second gate conductor layer 5b (an example of the "second gate conductor layer" in the scope of the patent application) which cover each of the two side surfaces in the Y1-Y1' direction of the first gate insulating layer 4a and are separated from each other. Furthermore, there is a third gate conductor layer 5c (an example of the "third gate conductor layer" in the scope of the patent application) surrounding the second gate insulating layer 4b. Furthermore, the first gate conductor layer 5a, the second gate conductor layer 5b and the third gate conductor layer 5c are separated by the insulating layer 6. Thus, a dynamic flash memory cell is formed, which is composed of the N ⁺ layers 3a, 3b, the P layer 2, the first gate insulating layer 4a, the second gate insulating layer 4b, the first gate conductor layer 5a, the second gate conductor layer 5b and the third gate conductor layer 5c.

Furthermore, as shown in Figure 1, the N ⁺ layer 3a is connected to the source line SL (an example of the “source line” in the scope of the patent application), the N ⁺ layer 3b is connected to the bit line BL (an example of the “bit line” in the scope of the patent application), the first gate conductor layer 5a is connected to the first plate line PL1 (an example of the “first plate line” in the scope of the patent application), the second gate conductor layer 5b is connected to the second plate line PL2 (an example of the “second plate line” in the scope of the patent application), and the third gate conductor layer 5c is connected to the word line WL (an example of the “word line” in the scope of the patent application).

Figure 2 is used to illustrate the erase operation mechanism. Figure 2(a) shows the state in which the hole group 11 generated by impact ionization in the previous cycle is accumulated in the channel region 8 of the P layer 2 before the erase operation. The channel region 8 between the N ⁺ layers 3a and 3b is electrically separated from the insulating substrate 1 and becomes a floating body. Furthermore, a lower voltage than the first plate line PL1 is applied to the second plate line PL2. Thereby, the hole group 11 is mainly concentrated in the P layer 2 close to the second gate conductor layer 5b connected to the second plate line PL2. A part of the hole group 11 is also concentrated in the channel region 8 surrounded by the third gate conductor layer 5c. Furthermore, as shown in FIG. 2( b ), during the erase operation, the voltage of the source line SL is set to a negative voltage V _ERA . Here, V _ERA is, for example, -3V. As a result, regardless of the value of the initial potential of the channel region 8, the N ⁺ layer 3a that becomes the source and the PN junction of the channel region 8 connected to the source line SL become forward biased. As a result, the hole group 11 accumulated in the channel region 8 generated by impact ionization in the previous cycle is absorbed into the N ⁺ layer 3a of the source part, and the potential V _FB of the channel region 8 becomes V _FB = V _ERA + Vb. Here, Vb is the built-in voltage of the PN junction, which is about 0.7V. Therefore, when V _ERA = -3V, the potential of the channel region 8 becomes -2.3V. This value becomes the potential state of the channel region 8 in the erased state. Therefore, when the potential of the channel region 8 of the floating body becomes a negative voltage, the threshold voltage of the N-channel MOS transistor of the dynamic flash memory unit becomes higher due to the substrate bias effect. Thereby, as shown in FIG2(c), the threshold voltage of the third gate conductor layer 5c connected to the word line WL becomes higher. The erased state of the channel region 8 becomes the logical memory data "0". In data reading, by setting the voltage applied to the first gate conductor layer 5a connected to the first plate line PL1 to be higher than the threshold voltage when the logical data is "1" and lower than the threshold voltage when the logical data is "0", and setting the voltage applied to the second gate conductor layer 5b connected to the second plate line PL2 to, for example, 0V, the characteristic that the current does not flow even if the voltage of the word line WL is increased can be obtained as shown in Figure 2(c). In addition, the above-mentioned voltage conditions applied to the bit line BL, the source line SL, the word line WL, the first plate line PL1 and the second plate line PL2 and the potential of the floating body are an example for performing an erase operation, and can also be other operating conditions that can perform an erase operation.

FIG3 shows a page write operation of a dynamic flash memory cell (an example of a "page write operation" in the scope of the patent application). As shown in FIG3(a), 0V is input to the N ⁺ layer 3a connected to the active pole line SL, 3V is input to the N ⁺ layer 3b connected to the bit line BL, 2V is input to the first gate conductor layer 5a connected to the first plate line PL1, 0V is input to the second gate conductor layer 5b connected to the second plate line PL2, and 5V is input to the third gate conductor layer 5c connected to the word line WL. As a result, as shown in FIG. 3(a), an inversion layer 12a is formed in the channel region 8 on the inner side of the first gate conductor layer 5a connected to the first plate line PL1, and the first N-channel MOS transistor region having the first gate conductor layer 5a operates in the saturation region. As a result, a clamping point 13 exists in the inversion layer 12a on the inner side of the first gate conductor layer 5a connected to the first plate line PL1. On the other hand, the second N-channel MOS transistor region having the third gate conductor layer 5c connected to the word line WL operates in the linear region. As a result, in the channel region 8 on the inner side of the third gate conductor layer 5c connected to the word line WL, there is no clamping point and an inversion layer 12b is formed on the entire surface. The inversion layer 12b formed on the entire inner surface of the third gate conductor layer 5c connected to the word line WL acts as a substantial drain of the first N-channel MOS transistor region having the first gate conductor layer 5a. As a result, the electric field becomes maximum in the first boundary region of the channel region 8 between the first N-channel MOS transistor region having the first gate conductor layer 5a connected in series and the second N-channel MOS transistor region having the third gate conductor layer 5c, and the punch ionization phenomenon occurs in this region. Since this region is the region on the source side when viewed from the second N-channel MOS transistor region having the third gate conductor layer 5c connected to the word line WL, this phenomenon is called the source side impact ionization phenomenon. Through this source side impact ionization phenomenon, electrons flow from the N ⁺ layer 3a connected to the source line SL toward the N ⁺ layer 3b connected to the bit line BL. The accelerated electrons will collide with the lattice Si atoms, and the energy of the movement will generate electron-hole pairs. Although a part of the generated electrons will flow in the first gate conductor layer 5a and the third gate conductor layer 5c, most of them will flow in the N ⁺ layer 3b connected to the bit line BL.

In the write operation of this dynamic flash memory cell, 0V is input to the second gate conductor layer 5b connected to the second plate line PL2, for example. Therefore, the inversion layer 12a is not formed in the channel region 8 inside the second gate conductor layer 5b connected to the second plate line PL2. As a result, the hole group 11 formed by the impact ionization phenomenon is mainly concentrated in the P layer 2 close to the second gate conductor layer 5b connected to the second plate line PL2.

In addition, when writing "1", the gate induced drain leakage (GIDL) current can also be used to generate electron-hole pairs, and the generated hole group 11 can be used to fill the floating body FB (for example, refer to non-patent document 5).

Furthermore, as shown in FIG3(b), the generated hole group 11 is the majority carrier of the channel region 8, charging the channel region 8 to a forward bias. Since the N ⁺ layer 3a connected to the active electrode line SL is 0V, the channel region 8 is charged to the built-in voltage Vb (about 0.7V) of the PN junction between the N ⁺ layer 3a connected to the active electrode line SL and the channel region 8. When the channel region 8 is charged to a forward bias, the threshold voltage of the first N-channel MOS transistor region and the second N-channel MOS transistor region becomes lower due to the substrate bias effect. Thereby, as shown in FIG3(c), the threshold voltage of the second N-channel MOS transistor region connected to the word line WL becomes lower. The first data retention voltage (an example of the "first data retention voltage" in the scope of the patent application) belonging to the write state of this channel region 8 is allocated to the logical memory data "1". The generated hole group 11 is mainly concentrated in the P layer 2 close to the second gate conductor layer 5b. In this way, a stable substrate bias effect can be obtained.

In addition, during the write operation, the first boundary region may be replaced by the second boundary region between the N ⁺ layer 3a and the channel region 8, or the third boundary region between the N ⁺ layer 3b and the channel region 8, to generate electron-hole pairs by impact ionization or GIDL current, and the channel region 8 may be charged with the generated hole group 11. In addition, the voltage conditions applied to the bit line BL, the source line SL, the word line WL, the first plate line PL1, and the second plate line PL2 are examples for performing the write operation, and may also be other operation conditions for performing the write operation.

Figures 4(a) to 4(c) are used to illustrate the read operation of the dynamic flash memory cell. As shown in Figure 4(a), when the channel area 8 is charged to the built-in voltage Vb (about 0.7V), the threshold voltage of the N-channel MOS transistor area will be reduced due to the substrate bias effect. This state is assigned to the logical memory data "1". As shown in Figure 4(b), when the memory block selected before writing is in the erase state "0", the floating voltage V _FB of the channel area 8 becomes V _ERA +Vb. The write state "1" is randomly stored by the write operation. As a result, logical memory data of logical "0" and "1" are created.

When the memory data is logic "0", the threshold voltage of the N-channel MOS transistor region is, for example, 1.3V, and when the memory data is logic "1", it is, for example, 0.3V. Therefore, for example, 0V is input to the N ⁺ layer 3a connected to the active line SL, for example, 0.5V is input to the N ⁺ layer 3b connected to the bit line BL, for example, 0.8V, which is the middle voltage between logic "0" and logic "1" of the N-channel MOS transistor region, is input to the first gate conductor layer 5a connected to the first plate line PL1, and for example, 0V is input to the second gate conductor layer 5b connected to the second plate line PL2. As a result, in the memory cell whose memory data is logical "1", the first N-channel MOS transistor region having the first gate conductor layer 5a operates in the linear region, and the second N-channel MOS transistor region having the third gate conductor layer 5c connected to the word line WL operates in the saturation region. On the other hand, in the memory cell whose memory data is logical "0", the threshold voltage of the first N-channel MOS transistor region having the first gate conductor layer 5a becomes high, for example, to 1.3V, so even if a voltage of 0.8V is applied to the first gate conductor layer 5a connected to the first plate line PL1, it will not be turned on. Therefore, as shown in FIG4(c), the difference between the two threshold voltages relative to the first plate line PL1 and the word line WL is used to read with a sense amplifier circuit. In data reading, by setting the voltage applied to the first gate conductor layer 5a connected to the first plate line PL1 to be higher than the threshold voltage when the logical data is "1" and lower than the threshold voltage when the logical data is "0", and setting the voltage applied to the second gate conductor layer 5b connected to the second plate line PL2 to, for example, 0V, the characteristic that the current does not flow even if the voltage of the word line WL is increased as shown in FIG4(c) can be obtained.

Furthermore, during the read operation, in the memory cell whose memory data is logical "1", electrons flow from the N ⁺ layer 3a connected to the active line SL toward the N ⁺ layer 3b connected to the bit line BL. As a result, the source side impact ionization phenomenon is caused in the same manner as the write operation. Therefore, in parallel with the read operation, the formation of the hole group 11 caused by the impact ionization phenomenon is carried out inside the channel region 8 of the P layer 2 of the memory cell. By performing this first refresh operation in parallel with the read operation, the data retention characteristics of the memory data being logical "1" are significantly improved.

During the read operation, by setting the capacitance of one of the first gate capacitance between the first gate conductive layer 5a and the P layer 2 and the second gate capacitance between the second gate conductive layer 5b and the P layer 2 or the capacitance of the sum of the two to be larger than the third gate capacitance between the third gate conductive layer 5c and the P layer 2, the change of the floating voltage of the channel region 8 during driving can be greatly suppressed. In this way, the read operation of the dynamic flash memory cell with a wider operating margin is performed. In addition, the voltage conditions applied to the bit line BL, source line SL, word line WL, first plate line PL1, second plate line PL2 and the potential of the floating body are an example for performing a read operation, and may also be other operating conditions for performing a read operation.

Figures 5A(a) to (d), Figure 5B and Figure 6 are used to illustrate the mechanism of the hole push erase operation in which a page erase operation (an example of a "page erase operation" within the scope of the patent application) is performed by applying only a positive bias voltage without applying a negative bias voltage to one or both of the source line SL and the bit line BL. Here, the channel region 8 between the N ⁺ layers 3a and 3b is electrically separated from the substrate and becomes a floating body. Figure 5A(a) is a timing operation waveform diagram showing the main nodes of the erase operation. In Figure 5A(a), T0 to T12 represent the moments from the start to the end of the erase operation. Figure 5A(b) shows the state of the hole group 11 generated by impact ionization in the previous cycle accumulated in the channel region 8 at the moment T0 before the erase operation. Furthermore, at time T1 to T2, the bit line BL and the source line SL change from Vss to high voltage states of V _BLH and V _SLH , respectively. Here, Vss is, for example, 0V. This operation is performed during the next period T3 to T4, when the first plate line PL1, the second plate line PL2 and the word line WL selected in the page erase operation are changed from the first voltage V _PLL to the second voltage V _PLH , and from the third voltage Vss to the fourth voltage V _WLH high voltage state, respectively, and an inversion layer 12a on the inner side of the first gate conductor layer 5a connected to the first plate line PL1, an inversion layer 12c (not shown) on the inner side of the third gate conductor layer 5c connected to the second plate line PL2, and an inversion layer 12b on the inner side of the second gate conductor layer 5b connected to the word line WL are not formed in the channel region 8. Therefore, the voltages of V _BLH and V _SLH are preferably V BLH > V WLH + V tWL , V SLH > V _PLH + V _tPL , when the threshold voltages of the second N-channel MOS transistor region on the word line WL side and the first N-channel MOS transistor region on the first plate line PL1 side and the threshold voltage of the third N-channel MOS transistor region on the _second plate line PL2 side are set to V _tWL and V _{tPL , respectively. For example, when V tWL and V tPL are 0.5V, V WLH and V PLH are set to 3V} , _and V _BLH and V _SLH are set to _3.5V or more.

Next, the page erase operation mechanism of FIG. 5A(a) is described. At time T3 to T4, as the first plate line PL1, the second plate line PL2, and the word line WL become the high voltage state of the second voltage V _PLH and the fourth voltage V _WLH , the voltage of the channel region 8 in the floating state is pushed up due to the first plate line PL1 and the second plate line PL2 coupling with the first capacitance of the channel region 8, and the word line WL coupling with the second capacitance of the channel region 8. The voltage of the channel region 8 changes from V _FB "1" of the "1" write state to a high voltage. This is because the voltages of the bit line BL and the source line SL are high voltages of V _BLH and V _SLH , respectively, so that the PN junction between the source N ⁺ layer 3a and the channel region 8 and the PN junction between the drain N ⁺ layer 3b and the channel region 8 are in a reverse bias state, thereby enabling boosting.

Next, the page erase operation mechanism of FIG. 5A(a) is described. In the next period of time T5 to T6, the voltage of the bit line BL and the source line SL is reduced from the high voltage V _BLH and V _SLH to Vss. As a result, the PN junction between the source N ⁺ layer 3a and the channel region 8 and the PN junction between the drain N ⁺ layer 3b and the channel region 8 become forward biased as shown in FIG. 5A(c), and the residual hole group in the hole group 11 of the channel region 8 is discharged to the source N ⁺ layer 3a and the drain N ⁺ layer 3b. As a result, the voltage V _FB of the channel region 8 becomes a built-in voltage Vb of the PN junction formed by the source N ⁺ layer 3 a and the P layer channel region 8 and the PN junction formed by the drain N ⁺ layer 3 b and the P layer channel region 8 .

Next, the page erase operation mechanism of FIG5A(a) is described. Next, at time T7 to T8, the voltages of the bit line BL and the source line SL rise from Vss to high voltages V _BLH and V _SLH . By this measure, as shown in FIG. 5A(d), at time T9 to T10, when the plate line _PL2 and the word line _WL2 are respectively reduced from the second voltage _VPLH and the fourth voltage _VWLH to the first voltage _VPLL and the third voltage Vss, the inversion layer 12a on the first plate line PL1 side, the inversion layer 12c on the second plate line PL2 side, and the inversion layer 12b on the word line WL side are not formed in the channel region 8, and the voltage _VFB of the channel region 8 can be efficiently coupled with the first capacitance of the first plate line PL1 and the second plate line PL2 and the channel region 8, and the word line WL and the second capacitance of the channel region 8 to change from Vb to _VFB "0". Therefore, the potential difference △ _VFB of the channel region 8 in the "1" write state and the "0" erase state is expressed by the following formula.

V _FB “1”=Vb-β _WL ×Vt _WL “1”-β _BL ×V _BLH (4)

V _FB “0” = Vb-β _WL × V _WLH -β _PL × (V _PLH - V _PLL ) (5)

△V _FB =V _FB “1”-V _FB “0”=β _WL ×V _WLH +β _PL ×(V _PLH -V _PLL )-β _WL ×Vt _WL “1”-β _BL ×V _BLH (6)

Here, the sum of β _WL and β _PL is greater than 0.8, ΔV _FB becomes larger, and a sufficient margin can be obtained.

Next, the page erase operation mechanism of FIG. 5A(a) is described. Then, at time T11 to T12, the voltage of the bit line BL and the source line SL drops from V _BLH to Vss and from V _SLH to Vss, respectively, and the erase operation is completed. At this time, although the voltage of the channel region 8 is slightly lowered by the bit line BL and the source line SL due to capacitive coupling, the voltage of the channel region 8 is pulled up by the bit line BL and the source line SL through capacitive coupling at time T7 to T8. Therefore, the rise and fall of the voltage of the bit line BL and the source line SL offset each other, resulting in no effect on the voltage of the channel region 8. The voltage V _FB “0” of the “0” erase state of the channel region 8 is set as a second data retention voltage (an example of the “second data retention voltage” in the scope of the patent application) to perform a page erase operation and is allocated to the logical memory data “0”.

FIG. 5B shows an example of applying a fixed voltage V _PL2 lower than the first plate line PL1 to the second plate line PL2 when performing a hole-push erase operation of a page erase operation with only a forward bias applied voltage. V _PL2 may be, for example, 0V belonging to the ground potential Vss. Thus, by applying a fixed voltage V _PL2 to the second plate line PL2 during the page erase operation and applying a fixed voltage in all operation modes other than the page erase operation, it is no longer necessary to connect the second plate line PL2 to the row decoder circuit RDEC for decoding.

As a result, as shown in FIG6, a large margin can be obtained in the "1" write state and the "0" erase state. Here, in the "0" erase state, the threshold voltage on the first plate line PL1 and the second plate line PL2 side becomes high due to the substrate bias effect. Therefore, when the applied voltage of the first plate line PL1 and the second plate line PL2 is set to below their threshold voltage, for example, the first N-channel MOS transistor region on the first plate line PL1 side and the third N-channel MOS transistor region on the second plate line PL2 side become non-conductive and do not cause the memory cell current to flow. "PL: Non-conductive" on the right side of FIG6 shows this situation.

Figures 7A to 7F are used to illustrate the situation in which a pulse voltage of a positive bias voltage below the voltage of the first plate line PL1 is input to the second plate line PL2 during the page write operation and page read operation of the dynamic flash memory cell of the first embodiment of the present invention, so that the page write operation and page read operation are enhanced.

FIG7A shows that 3 rows × 3 columns of memory cells C00 to C22 constitute a part of a memory cell block. Each of the memory cells C00 to C22 corresponds to the memory cell shown in FIG1 . Although 3 rows × 3 columns of memory cells C00 to C22 are shown here, in an actual memory cell block, memory cells constitute rows and columns larger than 3 rows × 3 columns. Furthermore, in each memory cell, word lines WL0 to WL2, first plate lines PL10 to PL12, second plate lines PL20 to PL22, source lines SL, and bit lines BL0 to BL2 are connected. Transistors T0C to T2C to which transfer signals FT are input to their gates constitute a switch circuit. In addition, the drain of transistors T0D to T2D whose gates are connected to the bit line precharge signal FS is connected to the bit line power VB, and the source is connected to each bit line BL0 to BL2. Furthermore, each bit line BL0 to BL2 is connected to the sense amplifier circuit SA0 to SA2 (an example of the "sense amplifier circuit" in the scope of the patent application) through a switch circuit. The word lines WL0 to WL2, the first plate lines PL10 to PL12, and the second plate lines PL20 to PL22 are connected to the column decoder circuit RDEC. The sense amplifier circuits SA0 to SA2 are connected to a pair of complementary input and output lines IO and /IO through transistors T0A to T2B whose gates are connected to the column selection lines CSL0 to CSL2.

In addition, FIG. 7A shows the state of the memory cell block as a whole undergoing the erase operation of FIG. 2(b) or FIG. 5A or FIG. 5B, and shows the situation where no hole group 11 is accumulated in the channel semiconductor layer 8.

FIG7B is a circuit block diagram showing a page write operation by selecting the word line WL1, and FIG7C is a waveform diagram showing the operation thereof. For the sense amplifier circuits SA0 to SA2, page data is written (loaded) from the input/output lines IO and /IO through the column select lines CSL0 to CSL2. At time T0, the dynamic flash memory cell is in the "0" erase state, and the voltage of the channel region 8 becomes V _FB "0". In addition, Vss is applied to the bit lines BL0 to BL2, the source line SL, and the word line WL1, V _PL1L is applied to the first plate line PL11, and Vss is applied to the second plate line PL21. Here, for example, Vss is 0V and V _PL1L is 0.8V. Next, at time T1 to T2, when the bit lines BL0 and BL2 rise from Vss to V _BLH , for example, when Vss is 0V, the voltage of the channel region 8 of the memory cells C01 and C21 is coupled through the capacitance of the bit lines BL0 and BL2 and the channel region 8 to become V _FB “0” + B _BL × V _BLH .

Next, at time T3 to T4, the word line WL1 rises from Vss to V _WLH . Thus, if the threshold voltage for erasing "0" of the second N-channel MOS transistor region of the third gate conductor layer 5c connected to the word line WL1 and surrounding the channel region 8 is set to Vt _WL "0", then along with the voltage rise of the word line WL1 from Vss to Vt _WL "0", the voltage of the channel region 8 of the memory cells C01 and C21 becomes V _FB "0" + β _BL × V _BLH + β _WL × Vt _WL "0" due to the second capacitance coupling between the word line WL1 and the channel region 8. Here, Vt _WL "0" is, for example, 1.3V. When the voltage of the word line WL1 rises above Vt _WL “0”, an inversion layer 12 b is formed in the channel region 8 inside the third gate conductor layer 5 c to shield the second capacitive coupling between the word line WL1 and the channel region 8 .

Next, at time T3 to T4, the voltage of the first gate conductor layer 5a connected to the first plate line PL11 is increased, for example, from V _PL1L to a high voltage V _PL1H . V _PL1H is, for example, 1.6V. This is to set it to be above 1.3V of the threshold voltage Vt _WL “0” belonging to “0” erasure. In addition, the voltage of the second gate conductor layer 5b connected to the second plate line PL21 is increased, for example, from Vss to V _PL2H , to apply a forward bias pulse voltage (an example of a “forward bias pulse voltage” in the scope of the patent application). Here, V _PL2H is, for example, 0.3V. Since the critical voltage after "1" is written is, for example, 0.3V, when V _PL2H is increased to above 0.3V, an inversion layer is also formed in the channel region 8 of the second gate conductor layer 5b, and the hole group 11 generated by the impact ionization phenomenon is not easy to gather in the channel region 8. In addition, the third gate conductor layer 5c connected to the word line WL1 is increased to, for example, V _WLH = 1.6V. As a result, an inversion layer 12a is formed in the channel region 8 on the inner side of the first gate conductor layer 5a connected to the first plate line PL11, and a clamping point 13 exists in the inversion layer 12a. Therefore, the first N-channel MOS transistor region having the first gate conductor layer 5a operates in the linear region. On the other hand, the second N-channel MOS transistor region having the third gate conductor layer 5c connected to the word line WL1 operates in the saturation region. As a result, there is no clamping point in the channel region 8 inside the third gate conductor layer 5c connected to the word line WL1, and an inversion layer 12b is formed inside the gate conductor layer 5c. The inversion layer 12b formed inside the third gate conductor layer 5c connected to the word line WL1 functions as a substantial drain of the first N-channel MOS transistor region having the first gate conductor layer 5a. As a result, the electric field becomes maximum in the first boundary region of the channel region 8 between the first N-channel MOS transistor region having the first gate conductor layer 5a connected in series and the second N-channel MOS transistor region having the third gate conductor layer 5c, and the impact ionization phenomenon occurs in this region. Since this region is the region on the source side when viewed from the second N-channel MOS transistor region having the third gate conductor layer 5c connected to the word line WL1, this phenomenon is called the source side impact ionization phenomenon. Due to this source side impact ionization phenomenon, electrons flow from the N ⁺ layer 3a connected to the source line SL toward the N ⁺ layer 3b connected to the bit line. The accelerated electrons collide with lattice Si atoms and generate electron-hole pairs by the motion energy. Some of the generated electrons flow through the first gate conductor layer 5a and the third gate conductor layer 5c, but most of them flow through the N ⁺ layer 3b (not shown) connected to the bit line BL.

Next, at time T5, the second plate line PL21 is reduced from V _PL2H to Vss. At time T5, the first plate line PL11 is in a high voltage state of V _PL1H , and the word line WL1 is in a high voltage state of V _WLH , and the hole group 11 is continuously generated by the source side impact ionization phenomenon. Here, at time T5, even if the second plate line PL21 is reduced from V _PL2H to Vss, the hole group 11 is accumulated in the channel region 8 until T5. As a result, the threshold voltage of the first N-channel MOS transistor region and the second N-channel MOS transistor region is reduced from, for example, 1.3V after "0" erasure, so that the page write operation can be fully performed even without the assistance of the second plate line PL21.

Furthermore, at time T6 to T7, the voltage of the word line WL1 decreases from V _WLH to Vss. At this time, the word line WL1 and the channel region 8 will have a second capacitive coupling, but before the voltage V _WLH of the word line WL1 becomes lower than the threshold voltage Vt _WL “1” of the second N-channel MOS transistor region when the voltage of the channel region 8 is Vb, the inversion layer 12b will shield the second capacitive coupling. Therefore, the actual capacitive coupling between the word line WL1 and the channel region 8 occurs only when the word line WL is lower than Vt _WL “1” and decreases to Vss. As a result, the voltage of the channel region 8 becomes Vb-β _WL ×Vt _WL “1”. Here, Vt _WL “1” is lower than the aforementioned Vt _WL “0”, and β _WL ×Vt _WL “1” is smaller.

Next, at time T8 to T9, the bit lines BL0 and BL2 are reduced from V _BLH to Vss. Since the bit lines BL0 and BL2 are capacitively coupled with the channel region 8, the final "1" write voltage V _FB "1" of the channel region 8 will become as follows.

V _FB “1”=Vb-β _WL ×Vt _WL “1”-β _BL ×V _BLH (7)

Here, the coupling ratio β _BL between the bit lines BL0 and BL2 and the channel region 8 is also smaller. A memory write operation is performed to set the "1" write state of the channel region 8 as the first data retention voltage, and the logic memory data "1" is allocated.

In addition, the voltage conditions and the potential of the floating body applied to the bit line BL, the source line SL, the word line WL, the first plate line PL1 and the second plate line PL2 are examples for performing a write operation, and can also be other action conditions for performing a write operation.

FIG. 7D shows that at any time point, "1" is randomly written into the memory cells C10, C01, C21, C02, and C12 in the memory cells C00 to C22, and a hole group 11 is accumulated in the channel semiconductor layer 8.

FIG. 7E shows a page read operation (an example of a “page read operation” in the scope of the application). At time Y1 to Y3, page data (an example of “page data” in the scope of the application) stored in the memory cell group (an example of a “memory cell group” in the scope of the application) C01, C11, C21 belonging to the first page is read to the sense amplifier circuits SA0 to SA2. At time Y1, the word line WL1 connected to the first memory cell group C01, C11, C21 rises from the low voltage Vss to the high voltage V _WLY for reading, and the bit lines BL0 to BL2 rise from the low voltage Vss to the high voltage V _BLY for reading at time Y2. Here, Vss can be, for example, the ground voltage Vss=0V. In addition, the second plate line PL21 rises from the low voltage Vss to the high voltage V _PL2H at the time Y1, and drops from the high voltage V _PL2H to the low voltage Vss at the time Y2. By applying a positive bias pulse voltage to the second plate line PL21 at the start of page reading, the memory cell current of "1" reading is increased. Furthermore, the refresh operation performed in parallel with the "1" reading operation is enhanced. Furthermore, at the time Y3, the word line WL1 drops from the high voltage V _WLY for reading to the low voltage Vss.

Here, as shown in FIG. 7F, the memory cells C01 and C21 in the page data stored in the first memory cell group C01, C11, and C21 are written with "1" in parallel with the "1" read operation. Therefore, the memory cell current flows in the memory cells C01 and C21, and as a result, the source side impact ionization phenomenon is caused to generate the hole group 11. That is, the memory cells C01 and C21 are re-operated in parallel with the "1" read.

In this page read operation, the first plate lines PL10 to PL12 are at a low voltage V _PL1L , and the second plate lines PL20 and PL22 are at a lower voltage Vss than the first plate lines PL10 to PL12. Only the second plate line PL21 becomes a high voltage V _PL2H . However, V _PL2H is lower than the low voltage V _PL1L of the first plate lines PL10 to PL12. For example, V _PL1L is 0.8V, and V _PL2H can be 0.3V.

In addition, at the time R1 of FIG. 7E , the transfer signal FT decreases from the high voltage V _FTH to the low voltage Vss. At the time R2, all word lines WL0 to WL2 are selected and increase from the low voltage Vss to the high voltage V _WLR for reuse. Here, for example, the low voltage Vss may be 0V and the high voltage V _WLR may be 1.3V. Furthermore, at the time R3, when the bit line precharge signal FS increases from the low voltage Vss to the high voltage V _FSH , the bit lines BL0 to BL2 increase from the low voltage Vss to the high voltage V _BLR for reuse. As a result, even if the hole group 11 inside the channel semiconductor layer 8 of the memory cells C10, C01, C21, C02, and C12 written with "1" decreases, it will rise to the built-in voltage Vb due to the refresh operation. Afterwards, at the moment R4, all the word lines WL0 to WL2 are reset, and when the bit lines BL0 to BL2 are reset at the moment R5, the voltage of the channel semiconductor layer 8 is slightly reduced from Vb due to the capacitive coupling between the word lines WL0 to WL2 and the bit lines BL0 to BL2 and the channel semiconductor layer 8, and becomes the first data retention voltage _VFB "1".

In addition, the circuit blocks shown in FIG. 7A, FIG. 7B, FIG. 7D and FIG. 7F can output the page data of the first memory cell group C01, C11, and C21 that have been read to the sense amplifier circuits SA0 to SA2 to the complementary input and output lines IO and /IO during the refresh operation during the page read operation.

The memory data of the memory cells C01, C11, and C21 shown in FIG7D are read to the bit lines BL0 to BL2 respectively when the word line WL1 is selected at time Y1 and the bit line precharge signal FS rises from Vss to the high voltage V _FSH at time Y2. In this page read operation, the transfer signal FT is V _FTH , the transistors T0C to T2C belonging to the switch circuit are in the on state, and the memory data of the memory cells C01, C11, and C21 are read to the sense amplifier circuits SA0 to SA2, where the logic judgment of "0" and "1" is performed. Afterwards, when a new operation starts, the transfer signal FT decreases from V _FTH to Vss, and the transistors T0C to T2C belonging to the switch circuit become non-conductive. As a result, the bit lines BL0 to BL2 and the sense amplifier circuits SA0 to SA2 are electrically separated. In the sense amplifier circuits SA0 to SA2, the read page data from the memory cells C01, C11, and C21 are stored. Then, the column selection lines CSL0 to CSL2 are sequentially input to the transistors T0A to T2B, thereby outputting the page data stored in the sense amplifier circuits SA0 to SA2 to the complementary input and output lines IO and /IO.

In addition, FIG. 7D is also used to illustrate the writing operation of the page data to the sense amplifier circuits SA0 to SA2 in the refresh operation. When the refresh operation starts, the transfer signal FT is reduced from V _FTH to Vss, and the transistors T0C to T2C belonging to the switch circuit become non-conductive. As a result, the bit lines BL0 to BL2 and the sense amplifier circuits SA0 to SA2 are electrically separated. Here, the page data can also be written to the sense amplifier circuits SA0 to SA2 from the input and output lines IO and /IO through the column selection lines CSL0 to CSL2.

In this way, by electrically separating the bit line and the sense amplifier circuit through the switch circuits T0C to T2C, the page data stored in the sense amplifier circuit can be freely read or written into the sense amplifier circuit during the refresh operation. Therefore, the refresh operation can be performed as a background operation behind the page read operation or the page write operation. As a result, a memory device corresponding to a high-speed system can be provided.

In addition, in the circuit blocks shown in FIG. 7A, FIG. 7B, FIG. 7D, and FIG. 7F, although the word lines WL0 to WL2 are connected to the left and right at the memory block ends, they can also be connected to the row decoder circuit RDEC in a separate state and controlled in a synchronous or asynchronous manner.

In addition, in FIG1, even in the structure where the polarity of the conductivity of the N ⁺ layer 3a, 3b and the P layer 2 is opposite, dynamic flash memory operation can be performed. At this time, the "P layer 2" becomes the "N layer 2", and the majority of carriers in the N layer 2 become electrons. Therefore, the electron group generated by impact ionization is accumulated in the channel semiconductor layer 8, and the "1" state is set.

1 , the first gate conductor layer 5a and the third gate conductor layer 5c are separated, and the second gate conductor layer 5b and the third gate conductor layer 5c are separated by the insulating layer 6. Alternatively, the second gate insulating layer 4b may be extended to cover the exposed P layer 2 and the first gate conductor layer 5a, thereby performing insulating separation between the first gate conductor layer 5a, the second gate conductor layer 5b, and the third gate conductor layer 5c. Similarly, the first gate insulating layer 4a can be extended to cover the exposed P layer 2 and the third gate conductive layer 5c, and the first gate conductive layer 5a, the second gate conductive layer 5b, and the third gate conductive layer 5c can be isolated from each other. In addition, the isolation can also be performed by other methods.

In addition, in FIG. 1 , the first gate insulating layer 4a is formed in a manner that covers both side surfaces and the upper surface of the P layer 2. In contrast, the first gate insulating layer 4a may be formed in a manner that covers at least both side surfaces of the P layer 2.

In addition, in FIG. 1, although the dynamic flash memory unit is formed on a first semiconductor layer in a strip shape standing vertically relative to the insulating substrate on the insulating substrate 1, it can also be formed on a planar semiconductor layer. In addition, it can also be formed on a semiconductor layer standing vertically relative to the substrate on the substrate (refer to non-patent document 6) or extending horizontally (refer to non-patent document 7).

1, a P layer having an acceptor impurity concentration lower than that of the P layer 2 may be provided on one or both sides between the N ⁺ layers 3a, 3b and the P layer 2. Also, an N layer having a donor impurity concentration lower than that of the N ⁺ layers 3a, 3b may be provided on one or both sides between the N ⁺ layers 3a, 3b and the P layer 2.

In addition, an SOI substrate can also be used as the insulating substrate 1 of FIG. 1. In addition, a semiconductor substrate can also be used, and after forming the P layer 2, the bottom of the P layer 2 and the upper surface of the semiconductor substrate outside the P layer 2 are oxidized to form the insulating substrate 1.

In addition, equations (1) to (7) in this manual and the figures are used to qualitatively describe the phenomenon, and the phenomenon is not limited by the equations.

Although the refresh operation of a one-bit dynamic flash memory cell composed of a semiconductor substrate has been described in FIGS. 7A to 7F, the present invention is also effective in the refresh operation of a one-bit high-speed dynamic flash memory cell composed of two semiconductor substrates storing complementary data of "1" and "0".

Although FIG. 7A to FIG. 7F illustrate a single-layer memory array in which a one-bit dynamic flash memory cell formed by a semiconductor substrate performs a refresh operation, the present invention is also effective in a multi-layer memory array formed by stacking multiple segments of a one-bit dynamic flash memory cell formed by a semiconductor substrate.

In addition, in FIG. 1 , a word line WL can be set on the side of the source line SL, and a first plate line PL1 and a second plate line PL2 can be set on the side of the bit line BL. In this way, the above-mentioned dynamic flash memory operation can also be performed.

This implementation has the following features.

(Feature 1)

In the known example shown in Figures 8 to 10, "1" is written by gathering the hole group 106 in the floating body 102 of the P layer. This floating body 102 varies greatly due to the read pulse voltage applied to the word line. Due to this voltage variation, there is a problem that the gathered hole group 106 leaks from the floating body 102. Therefore, there is a problem that the potential difference margin between the "1" potential and the "0" potential of the floating body during writing cannot be fully obtained. In contrast, as shown in the present embodiment, different from the third gate conductor layer 5c connected to the first word line WL1, a first gate conductor layer 5a and a second gate conductor layer 5b are provided for controlling the voltage of the floating body of the P layer 2 belonging to the channel region. This can suppress the change of the floating voltage of the P layer 2 when the driving pulse voltage is applied to the first word line. As a result, the potential difference margin between the floating "1" potential and the "0" potential during writing is increased.

(Feature 2)

As shown in FIG1 , a first gate conductor layer 5a connected to the first plate line and a second gate conductor layer 5b connected to the second plate line are provided on both sides of the P layer 2. By setting the second plate line voltage lower than the first plate line voltage, the hole group 11 generated when writing "1" shown in FIG3 can be gathered in the P layer 2 close to the second gate conductor layer Sb. Furthermore, when reading "1", as shown in FIG4 , by setting the second plate line voltage lower than the read conduction voltage of the first plate line, the hole group can be stably maintained in the P layer 2 close to the second gate conductor layer 5b during the read operation. In this way, a high potential difference margin can be stably obtained.

(Feature 3)

In the page write operation and page read operation of the dynamic flash memory cell of the first embodiment of the present invention, a pulse voltage of a positive bias voltage below the voltage of the first plate line PL1 is input to the second plate line PL2. As a result, in the page write operation, the "1" write operation for the memory cell whose threshold voltage becomes high after "0" erase can be accelerated. In addition, in the page read operation, the memory cell current for "1" read can be increased, and a significant improvement in the refresh operation can be sought.

(Other implementation forms)

In addition, in FIG. 1 , the first to third gate conductor layers 5a, 5b, and 5c can also be used in combination with a single layer or multiple layers of conductor material layers including polycrystalline Si, wherein the polycrystalline Si is rich in donor or acceptor impurities. In addition, the outer sides of the first to third gate conductor layers 5a, 5b, and 5c can also be connected to a wiring metal layer such as W. This is also the same in other embodiments.

In addition, in the first embodiment, it has been explained that by setting the capacitance of one of the first gate capacitance between the first gate conductive layer 5a and the P layer 2 and the second gate capacitance between the second gate conductive layer 5b and the P layer 2, or the capacitance after the sum of the two, to be larger than the third gate capacitance between the third gate conductive layer 5c and the P layer 2, a dynamic flash memory with a wider operating margin can be obtained. In this regard, it is also possible to combine the gate lengths of the first to third gate conductive layers 5a, 5b, 5c and the film thickness and dielectric constant of the first to second gate insulating layers 4a, 4b so that one or the sum of the first to second gate capacitances of the first to second gate conductive layers 5a, 5b is larger than the third gate capacitance of the third gate conductive layer 5c. This is also the same in other embodiments. Furthermore, in data reading, by setting the voltage applied to the first gate conductor layer 5a connected to the first plate line PL1 to be higher than the threshold voltage when the logical data is stored "1" and lower than the threshold voltage when the logical data is stored "0", and setting the voltage applied to the second gate conductor layer 5b connected to the second plate line PL2 to, for example, 0V, a characteristic that the current does not flow even if the voltage of the word line WL is increased can be obtained. This is conducive to further expansion of the action margin of the dynamic flash memory cell.

In addition, the first dynamic flash memory unit shown in FIG. 1 can also be stacked in multiple segments in the vertical direction to form a memory device. This is also the same in other implementation forms.

In addition, although the cross-sectional shape of the P layer 2 in FIG. 1 is a rectangle, it may also be a trapezoid. In addition, the cross-sectional shape of the P layer covered by the first gate insulating layer 4a and the part covered by the second gate insulating layer 4b may also be different. This is also the same in other embodiments.

In addition, in the description of the first embodiment, although the source line SL is set to a negative bias during the erase operation to remove the hole group in the channel region 8 belonging to the floating body FB, the source line SL can be replaced by setting the bit line BL to a negative bias, or both the source line SL and the bit line BL can be set to a negative bias to perform the erase operation. Alternatively, the erase operation can also be performed by other voltage conditions.

In addition, the N ⁺ layers 3a and 3b in FIG. 1 may also be formed by Si or other semiconductor material layers containing donor impurities. In addition, the N ⁺ layer 3a and the N ⁺ layer 3b may also be formed by different semiconductor material layers. This is also the same in other embodiments.

In addition, the present invention can be implemented in various forms and variations without departing from the broad spirit and scope of the present invention. In addition, the above-mentioned implementation is used to illustrate one embodiment of the present invention, and does not limit the scope of the present invention. The above-mentioned embodiments and variations can be combined arbitrarily. Furthermore, even if part of the constituent elements of the above-mentioned implementation are removed as needed, they are still within the scope of the technical idea of the present invention.

[Industrial availability]

According to the memory device using semiconductor elements of the present invention, a high-density and high-performance dynamic flash memory can be obtained.

BL0 to BL2: bit lines

FB: Floating body

PL11: First board line

PL21: Second board line

SL: Source line

T0 to T9: time

Vb: built-in voltage

V _FB ,V _BLH ,V _PL1H ,V _PL2H ,V _PL1L : Voltage

Vss: third voltage

V _WLH : Fourth voltage

WL1: First word line

V _FB “1”: First data retention voltage

V _FB “0”: Second data retention voltage

Claims (6)

A memory device using semiconductor elements is formed by arranging a plurality of pages in a row direction, wherein the pages are formed by arranging a plurality of memory cells in a row direction on a substrate, and each memory cell in each page has: a first semiconductor layer standing vertically or extending horizontally relative to the substrate on the substrate; a first impurity layer and a second impurity layer located at both ends of the first semiconductor layer in a first direction parallel to the substrate; a first gate insulating layer covering both sides of the first semiconductor layer in a second direction parallel to the substrate and perpendicular to the first direction near the first impurity layer; and a first gate insulating layer. The first semiconductor layer and the second gate conductive layer cover both sides of the first gate insulating layer when viewed from above and are separated from each other; the second gate insulating layer covers the first semiconductor layer near the second impurity layer; and the third gate conductive layer covers the second gate insulating layer; the memory device is controlled to be applied to the front The voltage of the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the first impurity layer and the second impurity layer is set, and the hole group formed by the impact ionization phenomenon is maintained inside the first semiconductor layer; during the page write operation, the memory device sets the voltage of the first semiconductor layer to The first data retention voltage is higher than the voltage of one or both of the first impurity layer and the second impurity layer; during the page erase operation, the memory device controls the voltage applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the first impurity layer and the second impurity layer, thereby removing the hole group from one or both of the first impurity layer and the second impurity layer, and setting the voltage of the first semiconductor layer to a second data retention voltage lower than the first data retention voltage; the first impurity layer of the memory cell is connected to a source line, and the second impurity layer is connected to a bit line. The first gate conductor layer is connected to the first plate line, the second gate conductor layer is connected to the second plate line, and the third gate conductor layer is connected to the word line; the bit line is connected to the sense amplifier circuit; during the page read operation, the memory device controls the voltage applied to the word line, the first plate line, the second plate line, the source line and the bit line, and reads the page data of the memory cell group selected by the word line to the sense amplifier circuit; in one or both of the page write operation and the page read operation, a pulse voltage of a positive bias voltage below the voltage of the first plate line is input to the second plate line. A memory device using a semiconductor element as described in claim 1, wherein during the page erase operation, the same pulse voltage is input to the first plate line and the second plate line, or a fixed voltage lower than the voltage of the first plate line is input to the second plate line. A memory device using a semiconductor element as described in claim 1, wherein during the aforementioned page read operation, a fixed voltage higher than the aforementioned forward bias pulse voltage of the aforementioned second plate line is input to the aforementioned first plate line. A memory device using a semiconductor element as described in claim 1, wherein, in one or both of the aforementioned page write operation and the aforementioned page read operation, the pulse voltage amplitude of the aforementioned forward bias voltage of the aforementioned second plate line is shorter than the pulse voltage amplitude of the aforementioned word line. A memory device using a semiconductor element as described in claim 1, wherein the third gate conductor layer is composed of at least two gate conductor layers, and they are operated in a synchronous or asynchronous manner. A memory device using a semiconductor element as described in claim 1, wherein the gate capacitance of one or both of the first gate capacitance between the first gate conductive layer and the first semiconductor layer and the second gate capacitance between the second gate conductive layer and the first semiconductor layer is greater than the third gate capacitance between the third gate conductive layer and the first semiconductor layer.

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