TWI835369B - Circuit for switching power supply chip - Google Patents

Abstract

The invention provides a circuit for a switching power supply chip. The circuit of the switching power supply chip includes a first control unit configured to generate a second control signal according to the first control signal of the switching power supply chip; a second control unit configured to turn on or off according to the second control signal. Open the connection between the predetermined pin of the switching power supply chip and the predetermined function module of the switching power supply chip; and a third control unit configured to connect to the predetermined pin or disconnect according to the second control signal. Open the connection with the predetermined pin, wherein when the second control unit disconnects the connection between the predetermined pin and the predetermined function module, the third control unit is connected to the predetermined pin , so that the information sampling signal at the predetermined pin is stable.

Description

Circuit for switching power supply chip

The present invention relates to the field of circuits, and in particular, to a circuit for a switching power supply chip.

Switching power supply chips are widely used in various electronic systems because of their high efficiency, and are used as switching power supplies for loads to control the power supply to the loads.

Usually, a switching power supply chip has a switch for connecting a load to or disconnecting a load from the switching power supply chip, and the switching on and off of the switch is controlled by a corresponding control signal. The control signal controls the on and off of the switch in a specific cycle, which causes a rapid switching of the voltage between the connection terminal of the switch and the load, and there is a parasitic capacitance between the connection terminal and other pins of the chip. The energy coupled by this parasitic capacitance will affect the voltage (or current) at the pin, causing the voltage at the pin to be unstable or even a voltage spike. Voltage instability or voltage spikes will cause errors in the sampling at this pin, which may lead to errors in the measurement of relevant parameters of the functional unit associated with this pin, resulting in corresponding functional errors and excessive voltage. Spikes can cause the reliability and stability of switching power supply chips to deteriorate.

Therefore, there is a need for a method that can improve the stable sampling and reliability of the pins of the switching power supply chip.

An exemplary embodiment according to the present invention provides a circuit for a switching power supply chip, including: a first control unit configured to generate a second control signal according to a first control signal of the switching power supply chip; a second control unit A unit configured to connect or disconnect the predetermined pin of the switching power supply chip and the switch according to the second control signal. connections between predetermined functional modules of the power chip; and a third control unit configured to connect to the predetermined pin or disconnect from the predetermined pin according to the second control signal, wherein in the When the second control unit disconnects the connection between the predetermined pin and the predetermined function module, the third control unit is connected to the predetermined pin to stabilize the information sampling signal at the predetermined pin. .

The circuit for the switching power supply chip according to the exemplary embodiment of the present invention can disconnect the connection with the corresponding functional module by controlling the pin of the switching power supply chip and connect the pin to the switching power supply chip according to the exemplary embodiment of the present invention. The relevant control unit of the circuit of the example makes the information sampling of the pin more stable, avoids the influence of the energy coupled by the parasitic capacitance in the switching power supply chip on the pin voltage, and improves the stability of the switching power supply chip.

100:Switching power supply chip

110,Pin1: pin

120:Function module

130:Circuit

131: First control unit

132: Second control unit

133:Third control unit

a, b, c: nodes

D: Diode

D1: first inverter

D2: Second inverter

D3: The third inverter

Drain: drain

G:Ground

G1: first gate

G2: The second gate

G3: first or gate

HV: high voltage

L:Inductor

LED: constant current load

M, SW: switch

M1: first switch

M2: Second switch

PWM: control signal

R1: Resistor

S1: first control signal

S2: second control signal

S2_N: Inverted second control signal

S910, S920, S930: steps

SG1, SG2: signal

t1: the first time period

t2: The second time period

V0, H0: lower voltage

V1: Positive voltage spike

V1’, V2’: fluctuation

V2: Negative voltage spike

Vin: input voltage

Vpin: voltage

The present invention can be better understood from the following description of specific embodiments of the present invention in conjunction with the drawings, in which: Figure 1 shows a schematic circuit diagram of a switching power supply chip according to an exemplary embodiment.

FIG. 2 shows a timing diagram of signals in a switching power supply die according to an exemplary embodiment.

Figure 3 shows a block diagram of a circuit connected to a switching power supply die according to an exemplary embodiment of the present invention.

FIG. 4 shows a circuit diagram of a circuit for a switching power supply chip according to an exemplary embodiment of the present invention.

FIG. 5 shows a timing diagram of signals in the circuit of FIG. 4 according to an exemplary embodiment of the present invention.

FIG. 6 shows a circuit diagram of a circuit for a switching power supply chip according to another exemplary embodiment of the present invention.

7 shows a circuit diagram of a first control unit in a circuit for a switching power supply chip according to an exemplary embodiment of the present invention.

FIG. 8 shows a timing diagram of signals in the first control unit of FIG. 7 according to an exemplary embodiment of the present invention.

9 illustrates a flowchart of the operation of a circuit connected to a switching power supply die according to an exemplary embodiment of the present invention.

Features and exemplary embodiments of various aspects of the invention are described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the invention by illustrating examples of the invention. The present invention is in no way limited to any specific configurations and algorithms set forth below, but covers any modifications, substitutions and improvements of elements, components and algorithms without departing from the spirit of the invention. In the drawings and the following description, well-known structures and techniques are not shown in order to avoid unnecessarily obscuring the present invention.

FIG. 1 shows a schematic circuit diagram of a switching power supply chip according to an exemplary embodiment.

FIG. 1 shows a schematic circuit diagram of only the portion of the switching power supply chip 100 related to the circuit of the present invention. It should be understood that the switching power supply chip 100 may include more components than those shown in FIG. 1 and include functional modules.

As shown in Figure 1, the switching power supply chip has a switch M, which is turned on or off under the driving of a driver according to a control signal, such as a pulse width modulation (PWM) signal, thereby switching the constant current load Or the constant voltage load is connected to or disconnected from the switching power supply chip 100 . FIG. 1 only shows a constant current load light emitting diode (LED). It should be understood that the switching power supply chip 100 of FIG. 1 can also be applied to a constant voltage load. The switch M shown in Figure 1 can be a power MOS tube or power transistor (Bipolar Junction Transistor, BJT). Figure 1 shows that the switch M is a power MOS tube. The gate of the power MOS tube receives the switching control signal gate generated by the driver according to the control signal PWM, thereby turning it on or off. The drain of the power MOS transistor is connected to the constant current load LED through the drain pin Drain via the diode D and the inductor L to power the constant current load LED when the power MOS is turned on. It should be understood that the number of constant current load LEDs can be set according to actual needs.

In addition, the switching power supply chip 100 also has at least one pin 110 connected to each functional module (not shown in FIG. 1 ). For clarity, Figure 1 shows only one pin, Pin1, as an example. Pin 110 has a corresponding resistance value, for example, a resistance value corresponding to the resistance value of resistor R1 shown in FIG. 1 . It should be understood that the resistor R1 in FIG. 1 is shown to facilitate understanding of the resistance value of the pin Pin. In actual applications, there may or may not be an actual resistor at the pin 110 .

Generally, each pin 110 is connected to its corresponding functional module, and the voltage or current at the pin 110 corresponds to the corresponding functional parameter of the connected functional module. When the switching power supply chip 100 is in the working mode, under ideal conditions, the voltage or current at the pin 110 remains stable.

However, in the power chip 100 shown in Figure 1, in the working mode, the switch M is frequently turned on and off under the control of the control signal PWM, and the drain of the power MOS tube M (or the collector of the power BJT The voltage at the electrode) frequently switches between higher voltage and lower voltage, and the rate of voltage change is extremely high, that is, the voltage rise time and voltage fall time are extremely short, for example, only a few microseconds. There is a parasitic capacitance between the drain (or collector) pin Drain of the power MOS transistor M and other pins 110. Such voltage changes will cause the parasitic capacitance to couple higher energy. Especially when the resistance value of pin 110 is high (for example, greater than a certain value), the energy coupled by the parasitic capacitance between pin 110 and pin Drain will cause the voltage at pin 110 to fluctuate. There are even spikes. This voltage fluctuation affects the sampling at pin 110, thus This may cause functional errors in the functional module, affecting the stability and reliability of the switching power supply chip 100 .

FIG. 2 shows a timing diagram of signals in the switching power supply die 100 according to an exemplary embodiment.

As shown in FIG. 2 , when the switching power supply chip 100 is in the sleep mode, the control signal PWM is in a low potential state, the voltage at the pin Drain is a higher voltage HV, and the voltage at the pin Pin1 is stable at the voltage Vpin.

When the switching power supply chip 100 is in the working mode, the control signal PWM periodically switches between high potential and low potential. When the control signal PWM changes from a low level to a high level, the switch M in Figure 1 is turned on, and the drain voltage of the switch M, that is, the voltage at the pin Drain changes from a higher voltage HV to a lower voltage V0.

For example, for the input voltage Vin in Figure 1 is a 200V AC system composed of the switching power supply chip 100 and a constant current load, the voltage value of the higher voltage HV at the pin Drain can usually reach 311V, and the voltage of the lower voltage V0 Values may typically be below 10V. Such a large voltage change will cause the parasitic capacitance between the pin Drain and other pins 110 to couple a large amount of energy. When the resistance value of pin 110 is greater than a certain value (for example, greater than 10K ohms for the above system), the switching power supply chip 100 will not be able to release the coupled energy in time, thus causing a negative voltage spike to appear at pin 110, such as V2 shown in Figure 2.

When the control signal PWM changes from a high level to a low level, the switch M in Figure 1 is turned off, and the drain voltage of the switch M, that is, the voltage at the pin Drain changes from a lower voltage H0 (for example, less than 10V) to a higher voltage. High voltage HV (for example, 311V). At this time, due to the energy coupled by the parasitic capacitance between pin Drain and pin 110, a positive voltage spike V1 will appear on pin 110, as shown in Figure 2.

When the voltage spike V1 or V2 shown in Figure 2 is too high or too low, that is, when the energy coupled in the parasitic capacitance is too much, it will also cause damping vibration on pin 110, causing the voltage of pin 110 to be unstable for a long time. status, thus affecting the pin 110 The sampling of voltage or current causes the switching power supply chip 100 to operate in an unstable state for a long time, or even cause functional errors. At the same time, excessively high or low voltage spikes will also affect the reliability and life of the switching power supply chip 100 .

In order to stabilize the signal sampling at the pin 110 and thereby stabilize the switching power supply chip 100, the energy coupled in the parasitic capacitance needs to be released.

FIG. 3 shows a block diagram of circuit 130 connected to switching power supply die 100 according to an exemplary embodiment of the present invention.

As shown in FIG. 3 , the circuit 130 for the switching power supply chip 100 according to the embodiment of the present invention includes: a first control unit 131 , a second control unit 132 and a third control unit 133 .

The first control unit 131 is configured to generate a second control signal according to the first control signal of the switching power supply chip 100 .

In one embodiment, the first control signal may be a signal used to control the switch M of the switching power supply chip 100 to be turned on or off, for example, the control signal PWM in FIGS. 1 and 2 . The switch (eg, switch M in FIG. 1 ) may be used to connect or disconnect a constant current load (eg, an LED in FIG. 1 ) or a constant voltage load to or from the switching power supply die 100 .

The second control unit 132 is configured to connect or disconnect the connection between the predetermined pin 110 of the switching power supply chip 100 and the predetermined function module 120 of the switching power supply chip 100 according to the second control signal.

In one embodiment, the predetermined pin 110 may be a pin of the switching power supply chip 100 having a resistance value greater than the first predetermined resistance value. For example, in the case of the above example system of 220V AC, the first predetermined resistance value may be 10K ohms.

The predetermined function module 120 may be a function module corresponding to (for example, connected to) the predetermined pin 110 . The voltage or current at the predetermined pin 110 corresponds to the predetermined function parameter of the predetermined function module 120 . For example, this function parameter can be adjusted by It is adjusted by the resistance value of the corresponding pin to ground, so the functional parameter can be adjusted by detecting the voltage or current at the pin.

In addition, in one embodiment, the second control unit 132 may be configured to invert the second control signal, and connect or disconnect the predetermined pin 110 and the functional module 120 according to the inverted second control signal. connections between.

The third control unit 133 is configured to connect to the predetermined pin 110 or disconnect from the predetermined pin 100 according to the second control signal.

Here, when the second control unit 132 disconnects the connection between the predetermined pin 110 and the predetermined function module 120, the third control unit 133 is connected to the predetermined pin 110 to stabilize the voltage of the predetermined pin 110.

In one embodiment, when the potential of the first control signal PWM changes from the first potential to the second potential, the second control unit 132 may disconnect the predetermined voltage according to the second control signal (or an inverted second control signal). The connection between the pin 110 and the predetermined function module 120 reaches the first time period t1, and the third control unit 133 can be connected to the predetermined pin 110 according to the second control signal for the first time period t1.

Here, the first potential may be one of the high potential and the low potential, and the second potential may be the other of the high potential and the low potential. For example, the first potential may be a low potential of the control signal PWM, and the second potential may be a high potential of the control signal PWM.

In one embodiment, when the potential of the first control signal PWM changes from the second potential to the first potential, the second control unit 132 may turn off the predetermined value according to the second control signal (or an inverted second control signal). The connection between the pin 110 and the predetermined function module 120 reaches the second time period t2, and the third control unit 133 can be connected to the predetermined pin 110 according to the second control signal for the second time period t2.

In other words, when the potential of the first control signal PWM changes, the second control unit 132 can disconnect the pin 110 and the corresponding functional module 120, and the third control unit 133 can be connected to the pin 110 to communicate The impedance becomes lower, that is, the energy coupled by the parasitic capacitor is released. After a period of time (e.g., first period or second After a period of time), the second control unit 132 can connect the pin 110 to the corresponding functional module 120 again, and the third control unit 133 disconnects the pin 110 so that the switching power supply chip 100 can operate normally.

That is to say, in a time period other than the first time period t1 and the second time period t2, the second control unit 132 can turn on the predetermined pin 110 according to the second control signal (or the inverted second control signal). To connect with the predetermined function module 120, the third control unit 133 can disconnect from the predetermined pin 110 according to the second control signal.

In one embodiment, the first time period t1 and the second time period t2 may be greater than the voltage rise time and voltage fall time of the switch M Drain terminal (of FIG. 1 ), and less than the minimum on time and minimum off time of the switching power supply chip 100 . Open time. Furthermore, the first time period t1 may be equal to or different from the second time period t2.

For example, in the above example, the voltage rise time and voltage fall time of the switch M Drain terminal can be hundreds of nanoseconds or even one microsecond, and the minimum on time and minimum off time of the switch power chip 100 can be around a dozen seconds. In this case, the first time period t1 and the second time period t2 can be set between one microsecond and a dozen microseconds. The first time period t1 and the second time period t2 set in this way can make the disconnection time between the pin 110 and the corresponding functional module 120 much shorter than the duration of the high or low potential of the control signal PWM when the potential of the control signal PWM (first control signal) changes, that is, the influence of the disconnection time on the switch power chip 100 can be ignored, so as not to affect the normal operation of the switch power chip 100.

FIG. 4 shows a circuit diagram of a circuit 130 for a switching power supply chip 100 according to an exemplary embodiment of the present invention.

As shown in FIG. 4 , the second control unit 132 may include a first switch M1. The first connection terminal and the second connection terminal of the first switch M1 may be connected between the predetermined pin 110 and the predetermined function module 120, and the control terminal of the first switch M1 may receive the second control signal S2. For example, the first switch M1 may be a P-type MOS transistor.

In another embodiment, the second control unit 132 may include: a first inverter D1 and a first switch M1. The first connection terminal of the first inverter D1 may receive the second control signal S2. The first connection terminal and the second connection terminal of the first switch M1 may be connected between the predetermined pin 110 and the predetermined function module 120, and the control terminal of the first switch M1 may be connected to the output terminal of the first inverter D1, To receive the inverted second control signal S2_N. For example, the first switch M1 may be an N-type MOS transistor.

In the above case, the third control unit 133 may include the second switch M2. The first connection terminal and the second connection terminal of the second switch M2 may be connected between the predetermined pin 110 and the voltage stabilizing element, and the control terminal of the second switch M2 may receive the second control signal S2. The voltage stabilizing element may be an element with a ground potential (grounded as shown in FIG. 4 ), a resistive element having a resistance value smaller than the second predetermined value, or a capacitive element having a capacitance value greater than the predetermined value. For example, in the case of the above example system, the second predetermined resistance value may be 100 ohms. The predetermined capacitance value may be several orders of magnitude larger than the capacitance value of the parasitic capacitor.

In the above situation, the first control unit 131 may be a pulse generator 131, which may generate the second control signal S2 according to the first control signal S1 (PWM).

Generally, for ease of implementation, the first switch M1 and the second switch M2 of the second control unit 132 and the third control unit 133 can both be set as N-type MOS transistors. At this time, the first switch M1 switches according to the inverted second The second switch M2 is turned on or off according to the second control signal S2_N, as shown in FIG. 4 .

FIG. 5 shows a timing diagram of signals in the circuit of FIG. 4 according to an exemplary embodiment of the present invention.

As shown in FIG. 5 , the second control unit 132 can disconnect the pin 110 (Pin1) according to the inverted second control signal S2_N when the potential of the first control signal S1 (PWM) changes from a low potential to a high potential. The connection between the functional modules 120 reaches the first time period t1. At this time, the third control unit 133 is connected to the pin 110 so that the pin communicates Low impedance allows coupling energy to be dissipated. As a result, the voltage at pin Pin1 has smaller fluctuations V2’ and no voltage spikes.

When the potential of the first control signal S1 (PWM) changes from high potential to low potential, the second control unit 132 can disconnect the pin 110 (Pin1) and the functional module 120 according to the inverted second control signal S2_N. The connection reaches the second period of time t2. At this time, the third control unit 133 is connected to the pin 110, so that the AC impedance of the pin is low, so that the coupling energy can be discharged. As a result, the voltage at pin Pin1 has smaller fluctuations V1’ and no voltage spikes.

It should be understood that the voltage fluctuations V1’ and V2’ at the pin Pin1 shown in Figure 5 are only examples, and the voltage fluctuations V1’ and V2’ may have different waveforms depending on the actual voltage stabilizing components. For example, one or both V1' and V2' can fluctuate above voltage Vpin without voltage spikes.

In addition, the settings of the second control unit 132 and the third control unit 133 shown in FIG. 4 are only examples, and the second control unit 132 and the third control unit 133 may have other settings according to actual needs. For example, the first switch and the second switch of the second control unit 132 and the third control unit 133 may be integrated into one switch.

FIG. 6 shows a circuit diagram of a circuit 130 for a switching power supply chip 100 according to another exemplary embodiment of the present invention.

As shown in FIG. 6 , the second control unit 132 and the third control unit 133 can be implemented as a switch SW. The switch SW can connect the node a and the node b, or connect the node a under the control of the second control signal S2. and node c to connect or disconnect the pin 110 from the functional module 120, connect the pin 110 to the diode D, or disconnect the pin 110 from the ground G.

It should be understood that ground D in Figure 6 can be replaced by other voltage stabilizing components as described above.

In the example of FIG. 4 or FIG. 6 , the pulse generator as the first control unit 131 may be any pulse generator 131 capable of generating the second control signal S2 as shown in FIG. 5 .

FIG. 7 shows a circuit diagram of the first control unit 131 in the circuit 130 of the switching power supply chip 100 according to an exemplary embodiment of the present invention.

As shown in FIG. 7 , the first control unit 131 may include: a first delay unit (Delayer 1), a second delay unit (Delayer 2), a second inverter D2, a first AND gate G1, a third inverter phase device D3, the second AND gate G2 and the first OR gate G3.

The input terminal of the first delay unit (delayer 1) may receive the first control signal S1 (PWM) and delay the first control signal S1 for the first time period t1 to be output through the output terminal of the first delay unit.

The input terminal of the second delay unit (delayer 2) may receive the first control signal S1, and delay the first control signal S1 for a second period of time t2 to be output through the output terminal of the second delay unit; The input terminal of the second inverter D2 may be connected to the output terminal of the first delay unit.

The first input terminal of the first AND gate G1 may receive the first control signal S1, and the second input terminal of the first AND gate G1 may be connected to the output terminal of the second inverter D2.

The input terminal of the third inverter D3 may receive the first control signal S1.

The first input terminal of the second AND gate G2 may be connected to the output terminal of the second delay unit, and the second input terminal of the second AND gate G2 may be connected to the output terminal of the third inverter D3.

The first input terminal of the first OR gate G3 may be connected to the output terminal of the first AND gate G1, and the second input terminal of the first OR gate G3 may be connected to the output terminal of the second AND gate G2. The first OR gate G3 The signal output by the output terminal may be the second control signal S2.

FIG. 8 shows a timing diagram of signals in the first control unit 131 of FIG. 7 according to an exemplary embodiment of the present invention.

As shown in FIG. 8 , when the first control signal S1 (PWM) changes from a low level to a high level, the first AND gate G1 outputs a high-level signal S _G1 having a time length of the first period t1 . When the first control signal S1 changes from a high level to a low level, the second AND gate G2 outputs a high level signal _SG2 having a time length of the second period t2. As a result, the third OR gate outputs the second control signal S2 as shown in FIG. 8 .

9 illustrates a flowchart of the operation of a circuit connected to a switching power supply die according to an exemplary embodiment of the present invention.

Referring to FIG. 9 , in step S910 , the control signal PWM of the switching power supply chip 100 is received. That is, at this time, the switching power supply chip 100 begins to enter the working mode.

In step S920, according to the control signal, the connection between the predetermined pin (for example, Pin1) of the switching power supply chip 100 and the predetermined function module 120 of the switching power supply chip 100 is disconnected. For example, when the switching power supply chip 100 turns the switch M on or off according to the control signal PWM, the connection between the pin Pin1 and the functional module 120 is disconnected for a predetermined period of time (for example, the above-mentioned time t1 or t2), and Connect the pin Pin1 to the ground, or an energy storage port or a low-impedance port (ie, the above-mentioned third control unit 133) to mask the sampling at the pin and release the parasitic capacitance associated with the pin. Coupled energy.

In step S930, after disconnecting the connection for a predetermined period of time (for example, the above-mentioned time t1 or t2), the connection between the predetermined pin Pin1 of the switching power supply chip 100 and the predetermined function module 120 of the switching power supply chip 100 is connected. That is, the sampling function of this pin is restored at this time.

It should be understood that the voltage values, resistance values, capacitance values, time values and other values in the above embodiments are examples, and different voltage values, resistance values, capacitance values, time values and other values can be set according to actual needs. wait.

According to the circuit for the switching power supply chip according to the exemplary embodiment of the present invention, the connection with the corresponding functional module can be disconnected by controlling the pin of the switching power supply chip, and the This pin is connected to the relevant control unit of the circuit according to the exemplary embodiment of the present invention, thereby stabilizing the voltage of the pin, avoiding the influence of the energy coupled by the parasitic capacitance in the switching power supply chip on the pin voltage, and improving the switching efficiency. The stability of the power chip.

The present invention may be implemented in other specific forms without departing from its spirit and essential characteristics. For example, algorithms described in specific embodiments may be modified without departing from the basic spirit of the invention. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being defined by the appended claims rather than the foregoing description, and the meanings and equivalents falling within the claims. All changes within the scope are therefore included in the scope of the invention.

100:Switching power supply chip

110,Pin1: pin

120:Function module

130:Circuit

131: First control unit

132: Second control unit

133:Third control unit

Drain: drain

R1: Resistor

Claims (11)

A circuit for a switching power supply chip, including: a first control unit, a signal for controlling the on or off of a switch of the switching power supply chip, configured to be based on the first control signal of the switching power supply chip, Generate a second control signal; a second control unit configured to connect or disconnect the connection between the predetermined pin of the switching power supply chip and the predetermined functional module of the switching power supply chip according to the second control signal, And through the first control signal under the interaction between high potential and low potential, the connection or disconnection between the predetermined pin and the predetermined function module is controlled, and the predetermined function module is connected to the predetermined function module. The functional module corresponding to the predetermined pin; and a third control unit configured to connect to the predetermined pin or disconnect from the predetermined pin according to the second control signal, wherein in the second control unit When the connection between the predetermined pin and the predetermined function module is disconnected, the third control unit is connected to the predetermined pin to stabilize the information sampling signal at the predetermined pin. The circuit of claim 1, wherein the switch of the switching power supply chip is used to connect or disconnect a constant current load or a constant voltage load to or from the switching power supply chip. The circuit of claim 2, wherein when the potential of the first control signal changes from the first potential to the second potential, the second control unit disconnects the predetermined pin according to the second control signal The connection with the predetermined function module reaches a first time period, and the third control unit is connected to the predetermined pin according to the second control signal for the first time period, wherein the first potential is one of high potential and low potential, and the second potential is the other of high potential and low potential. The circuit of claim 3, wherein in the first control signal When the potential of the signal changes from the second potential to the first potential, the second control unit disconnects the connection between the predetermined pin and the predetermined function module for a second time according to the second control signal. period, the third control unit is connected to the predetermined pin according to the second control signal for the second period of time. The circuit of claim 4, wherein in a time period other than the first time period and the second time period, the second control unit switches on the predetermined time period according to the second control signal. The connection between the pin and the predetermined function module, the third control unit disconnects the connection with the predetermined pin according to the second control signal. The circuit of claim 1, wherein the second control unit is configured to invert the second control signal, and connect or disconnect the predetermined pin and the predetermined pin according to the inverted second control signal. The connection between the functional modules. The circuit of claim 4, wherein the second control unit includes: a first switch, the first connection terminal and the second connection terminal of the first switch are connected between the predetermined pin and the predetermined function. Between modules, the control terminal of the first switch receives the second control signal. The circuit of claim 4, wherein the second control unit includes: a first inverter, a first connection terminal of the first inverter receives the second control signal; and a first switch, The first connection terminal and the second connection terminal of the first switch are connected between the predetermined pin and the predetermined function module, and the control terminal of the first switch is connected to the first inverter. output terminal. The circuit of claim 7 or 8, wherein the third control unit includes: a second switch, the first connection terminal and the second connection terminal of the second switch are connected between the predetermined pin and the voltage stabilizing pin. between components, the control terminal of the second switch receives the Two control signals, wherein the voltage stabilizing element is an element with ground potential, a resistive element with a resistance value less than the second predetermined value, or a capacitive element with a capacitance value greater than the predetermined value. The circuit of claim 9, wherein the first control unit includes: a first delay unit, an input terminal of the first delay unit receives the first control signal and delays the first control signal The first time period is output through the output terminal of the first delay unit; the second delay unit, the input terminal of the second delay unit receives the first control signal and delays the first control signal The second time period is output through the output terminal of the second delay unit; a second inverter, the input terminal of the second inverter is connected to the output terminal of the first delay unit; first and a gate, a first input terminal of the first AND gate receives the first control signal, a second input terminal of the first AND gate is connected to the output terminal of the second inverter; a third inverter , the input terminal of the third inverter receives the first control signal; a second AND gate, the first input terminal of the second AND gate is connected to the output terminal of the second delay unit, the third a second input terminal of a second AND gate connected to the output terminal of the third inverter; and a first OR gate, a first input terminal of the first OR gate connected to the output terminal of the first AND gate, The second input terminal of the first OR gate is connected to the output terminal of the second AND gate, and the signal output by the output terminal of the first OR gate is the second control signal. The circuit of claim 10, wherein the predetermined pin is a pin of the switching power supply chip with a resistance value greater than the first predetermined resistance value, and the voltage or current at the predetermined pin is equal to Correspond to the predetermined function parameters of the predetermined function module.

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