TWI835103B - Nitride semiconductor epitaxial stack structure and power device thereof - Google Patents

Nitride semiconductor epitaxial stack structure and power device thereof Download PDF

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TWI835103B
TWI835103B TW111111980A TW111111980A TWI835103B TW I835103 B TWI835103 B TW I835103B TW 111111980 A TW111111980 A TW 111111980A TW 111111980 A TW111111980 A TW 111111980A TW I835103 B TWI835103 B TW I835103B
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aluminum
gallium nitride
superlattice
composition ratio
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TW202229670A (en
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杜尚儒
楊亞諭
劉家呈
張宗正
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晶元光電股份有限公司
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A nitride semiconductor epitaxial stack structure includes a silicon substrate; an aluminum-included nucleation layer disposed on the silicon substrate; a buffer structure disposed on the aluminum-included nucleation layer, including: a first superlattice structure, a first GaN based layer disposed on the first superlattice structure, and a second superlattice structure disposed on the first GaN based layer; a channel layer disposed on the buffer structure; and a barrier layer disposed on the channel layer; wherein the first superlattice structure has a first average aluminum composition ratio, the first GaN based layer has a first aluminum composition ratio, and the second superlattice structure has a second average aluminum composition ratio; wherein an aluminum composition ratio of the aluminum-included nucleation layer≧the first average aluminum composition ratio>the first aluminum composition ratio>the second average aluminum composition ratio.

Description

氮化物半導體磊晶疊層結構及其功率元件Nitride semiconductor epitaxial stack structure and its power components

本揭露是關於一種氮化物半導體磊晶疊層結構及其功率元件,更具體而言,係關於一種應用於半導體功率元件的氮化鎵系半導體磊晶疊層結構及其功率元件。 The present disclosure relates to a nitride semiconductor epitaxial stack structure and power components thereof, and more specifically, to a gallium nitride semiconductor epitaxial stack structure and power components used in semiconductor power components.

近幾年來,由於高頻及高功率元件產品的需求與日俱增,三五族半導體材料氮化鎵(GaN)的能隙約為3.4eV,熱傳導性>1.5W/cm,其寬能隙及高熱傳導性(易於散熱)適合操作在高溫以及耐化學腐蝕的環境。此外,氮化鎵材料的崩潰電場為(3×106V/cm),載子傳輸速度可以達到3×107cm/s,使得氮化鎵材料適合作為微波高功率元件,可施加高電壓於其上而不致崩壞。因此,以氮化鎵材料為主的氮化物半導體功率元件,如氮化鋁鎵/氮化鎵(AlGaN/GaN)半導體功率元件等因具高速電子遷移率、可達到非常快速的切換速度、可於高頻、高功率及高溫工作環境下操作的元件特性,廣泛地於工業運用,包含電子產品、不斷電系統、汽車、馬達、風力發電等領域,特別被應用在電源供應器(power supply)、DC/DC轉換器(DC/DC converter)、DC/AC逆變器(AC/DC inverter)。 In recent years, due to the increasing demand for high-frequency and high-power component products, the energy gap of the III-V semiconductor material gallium nitride (GaN) is about 3.4eV and the thermal conductivity is >1.5W/cm. Its wide energy gap and high thermal conductivity (Easy to dissipate heat) Suitable for operation in high temperature and chemically resistant environments. In addition, the collapse electric field of gallium nitride material is (3×10 6 V/cm), and the carrier transmission speed can reach 3×10 7 cm/s, making gallium nitride material suitable as a microwave high-power component that can apply high voltage on it without breaking down. Therefore, nitride semiconductor power components based on gallium nitride materials, such as aluminum gallium nitride/gallium nitride (AlGaN/GaN) semiconductor power components, can achieve very fast switching speeds due to their high electron mobility. The characteristics of components operating in high-frequency, high-power and high-temperature working environments are widely used in industrial applications, including electronic products, uninterruptible power systems, automobiles, motors, wind power and other fields. They are especially used in power supplies. ), DC/DC converter (DC/DC converter), DC/AC inverter (AC/DC inverter).

然而,現有的產品基於效率、價格等競爭力的考量,在價格考量下,選用較便宜但與氮化物半導體材料晶格常數及熱膨脹係數不同的基板材料。 因之,在基板材料與氮化物半導體材料間晶格常數及熱膨脹係數的差異下,在基板上形成磊晶層時,便容易於磊晶層間產生磊晶缺陷。當磊晶缺陷密度較高時,則容易使磊晶層的表面平整度降低,而若磊晶缺陷延伸成長至磊晶層的表面時,則會成為使磊晶層表面產生裂紋(crack)的成因之一。因此,要在基板上形成磊晶缺陷密度低、表面平整、表面裂紋較少及/或較小之高品質氮化物半導體磊晶疊層結構並不容易。在各種不同基板材料中,矽基板以合理的成本結構被廣泛地應用於氮化物半導體磊晶疊層結構成長之中。然而,直到目前為止在矽基板上生長高品質的氮化物半導體磊晶疊層結構仍然是本技術領域待解決之一課題。此外,經由此氮化物半導體磊晶疊層結構所製造之元件,如功率元件、蕭特基二極體元件,也會因氮化物半導體磊晶疊層結構之品質優劣影響元件之性能。 However, based on competitive considerations such as efficiency and price, existing products use cheaper substrate materials that have different lattice constants and thermal expansion coefficients from nitride semiconductor materials. Therefore, due to differences in lattice constants and thermal expansion coefficients between the substrate material and the nitride semiconductor material, epitaxial defects are easily generated between the epitaxial layers when the epitaxial layer is formed on the substrate. When the density of epitaxial defects is high, the surface flatness of the epitaxial layer is likely to be reduced. If the epitaxial defects extend to the surface of the epitaxial layer, they will cause cracks on the surface of the epitaxial layer. One of the causes. Therefore, it is not easy to form a high-quality nitride semiconductor epitaxial stack structure with low epitaxial defect density, smooth surface, fewer and/or smaller surface cracks on a substrate. Among various substrate materials, silicon substrates are widely used in the growth of nitride semiconductor epitaxial stack structures with a reasonable cost structure. However, growing high-quality nitride semiconductor epitaxial stack structures on silicon substrates is still a problem to be solved in this technical field until now. In addition, the performance of components manufactured through this nitride semiconductor epitaxial stack structure, such as power components and Schottky diode components, will also be affected by the quality of the nitride semiconductor epitaxial stack structure.

請參閱第1圖,第1圖顯示為一種習知可應用於功率元件製作之氮化物半導體磊晶疊層結構100的穿透式電子顯微鏡(Transmission Electron Microscope,TEM)影像。此氮化物半導體磊晶疊層結構100係於矽基板110的(111)表面上沿著[0001]方向先以金屬有機化學氣相沉積法(metal-organic chemical vapor deposition,MOCVD)直接形成一層氮化鋁成核層120,繼而再於氮化鋁成核層120上以相同的MOCVD法形成由複數氮化鋁超晶格層131(18奈米厚)及氮化鎵超晶格層132(5奈米厚)交錯堆疊之超晶格疊層130。接著,在超晶格疊層130上再以MOCVD法形成一層厚度大於1000奈米的氮化鎵厚層140。接著於其上以MOCVD法形成一障壁層152,並在臨近氮化鎵厚層140及障壁層152的接面處產生二維電子氣(two-dimensional electron gas,2DEG,圖未示)。 Please refer to Figure 1. Figure 1 shows a transmission electron microscope (TEM) image of a conventional nitride semiconductor epitaxial stack structure 100 that can be used in power device manufacturing. The nitride semiconductor epitaxial stacked structure 100 is first directly formed with a layer of nitrogen on the (111) surface of the silicon substrate 110 along the [0001] direction by metal-organic chemical vapor deposition (MOCVD). aluminum nitride nucleation layer 120, and then use the same MOCVD method to form a plurality of aluminum nitride superlattice layers 131 (18 nm thick) and gallium nitride superlattice layers 132 ( 5 nm thick) staggered superlattice stack 130. Next, a thick gallium nitride layer 140 with a thickness greater than 1000 nanometers is formed on the superlattice stack 130 by MOCVD. Then, a barrier layer 152 is formed on it by MOCVD method, and a two-dimensional electron gas (2DEG, not shown) is generated near the interface between the gallium nitride thick layer 140 and the barrier layer 152 .

由第1圖中可以發現,此種構造的氮化物半導體磊晶疊層結構100即便下方具有超晶格疊層130的結構,許多磊晶缺陷145仍然形成於氮化鎵厚層140內,並向上延伸至氮化鎵厚層140的上半部,甚至是障壁層152內。 It can be found from Figure 1 that even if the nitride semiconductor epitaxial stack structure 100 has a superlattice stack 130 underneath, many epitaxial defects 145 are still formed in the gallium nitride thick layer 140, and Extend upward to the upper half of the gallium nitride thick layer 140 and even into the barrier layer 152 .

本揭露係關於一種氮化物半導體磊晶疊層結構,包含一矽基板;一含鋁成核層,配置於矽基板上;一緩衝結構,配置於含鋁成核層上,依序包含:一第一超晶格堆疊結構;一第一氮化鎵系層,配置於第一超晶格堆疊結構上;以及一第二超晶格堆疊結構,配置於第一氮化鎵系層上;一通道層,配置於緩衝結構上;以及一障壁層,配置於於通道層上;其中,第一超晶格磊晶結構包含一第一平均鋁組成比例,第一氮化鎵系層包含一第一鋁組成比例,第二超晶格磊晶結構包含一第二平均鋁組成比例;其中,含鋁成核層的鋁組成比例≧第一平均鋁組成比例>第一鋁組成比例>第二平均鋁組成比例。 The present disclosure relates to a nitride semiconductor epitaxial stack structure, which includes a silicon substrate; an aluminum-containing nucleation layer disposed on the silicon substrate; and a buffer structure disposed on the aluminum-containing nucleation layer, which in sequence includes: an aluminum-containing nucleation layer a first superlattice stack structure; a first gallium nitride layer, disposed on the first superlattice stack structure; and a second superlattice stack structure, disposed on the first gallium nitride layer; A channel layer is disposed on the buffer structure; and a barrier layer is disposed on the channel layer; wherein the first superlattice epitaxial structure includes a first average aluminum composition ratio, and the first gallium nitride layer includes a first An aluminum composition ratio, the second superlattice epitaxial structure includes a second average aluminum composition ratio; wherein, the aluminum composition ratio of the aluminum-containing nucleation layer ≧ the first average aluminum composition ratio > the first aluminum composition ratio > the second average Aluminum composition ratio.

一種半導體功率元件,包含前述氮化物半導體磊晶疊層結構;及一源極電極、一閘極電極、及一汲極電極,或一陰極及一陽極分別配置於前述氮化物半導體磊晶疊層結構上;其中,閘極電極位於源極電極及汲極電極之間。 A semiconductor power element, including the aforementioned nitride semiconductor epitaxial stack structure; and a source electrode, a gate electrode, and a drain electrode, or a cathode and an anode respectively disposed on the aforementioned nitride semiconductor epitaxial stack Structurally, the gate electrode is located between the source electrode and the drain electrode.

為讓本揭露之上述和其他目的、特徵和優點能更明顯易懂,下文特舉較佳實施例,並配合所附圖式,作詳細說明如下。 In order to make the above and other objects, features and advantages of the present disclosure more obvious and understandable, preferred embodiments are described in detail below along with the accompanying drawings.

60、60’:介電層 60, 60’: dielectric layer

70:源極電極 70: Source electrode

80:汲極電極 80: Drain electrode

90:閘極電極 90: Gate electrode

100、200、500:氮化物半導體磊晶疊層結構 100, 200, 500: Nitride semiconductor epitaxial stack structure

100’、200’:局部磊晶疊層 100’, 200’: local epitaxial layering

110、210:基板 110, 210: Substrate

120、220:氮化鋁成核層 120, 220: Aluminum nitride nucleation layer

130:超晶格疊層 130:Superlattice stack

131:氮化鋁超晶格層 131:Aluminum nitride superlattice layer

132:氮化鎵超晶格層 132:GaN superlattice layer

140:氮化鎵厚層 140:Thick layer of gallium nitride

145、245:磊晶缺陷 145, 245: Epitaxial defects

400:元件功能結構 400: Component functional structure

300、430、460、490:緩衝結構 300, 430, 460, 490: buffer structure

410:通道層 410: Channel layer

152、420:障壁層 152, 420: Barrier layer

310、432、461、492:第一超晶格磊晶結構 310, 432, 461, 492: The first superlattice epitaxial structure

320、320’、431、462、491:第一氮化鎵系厚層 320, 320’, 431, 462, 491: The first gallium nitride series thick layer

330、434、463、494:第二超晶格磊晶結構 330, 434, 463, 494: Second superlattice epitaxial structure

340、340’、433、464、493:第二氮化鎵系厚層 340, 340’, 433, 464, 493: Second gallium nitride series thick layer

465、496:第三超晶格磊晶結構 465, 496: The third superlattice epitaxial structure

466、495:第三氮化鎵系厚層 466, 495: The third gallium nitride series thick layer

510:帽層 510: Cap layer

550:後障壁層 550:Rear barrier layer

A:陽極 A:Anode

C:陰極 C: cathode

E0、E1:功率元件單元 E0, E1: power component unit

E2:蕭特基二極體元件單元 E2: Schottky diode element unit

E3、E4:功率元件測試單元 E3, E4: Power component test unit

O1~O4:歐姆電極 O1~O4: Ohmic electrode

S:功率元件 S: power component

S70:源極墊 S70: Source pad

S80:汲極墊 S80: drain pad

S90:閘極墊 S90: Gate pad

FF’:剖線 FF’: section line

第1圖係習知之氮化物半導體磊晶疊層結構的TEM影像。 Figure 1 is a TEM image of a conventional nitride semiconductor epitaxial stack structure.

第2圖係本揭露第一實施例之氮化物半導體磊晶疊層結構側視示意圖。 Figure 2 is a schematic side view of the nitride semiconductor epitaxial stack structure according to the first embodiment of the present disclosure.

第3A圖係習知之氮化物半導體磊晶疊層結構包含緩衝結構部分之局部之TEM影像。 Figure 3A is a partial TEM image of a conventional nitride semiconductor epitaxial stack structure including a buffer structure portion.

第3B圖係本揭露第二實施例之氮化物半導體磊晶疊層結構包含緩衝結構部分之局部之TEM影像。 Figure 3B is a partial TEM image of the buffer structure portion of the nitride semiconductor epitaxial stack structure according to the second embodiment of the present disclosure.

第4A圖至第4C圖係顯示本揭露第三至五實施例之氮化物半導體磊晶疊層結構包含緩衝結構部分之局部磊晶疊層結構之側視示意圖。 Figures 4A to 4C are schematic side views showing partial epitaxial stack structures of the nitride semiconductor epitaxial stack structure including the buffer structure portion according to the third to fifth embodiments of the present disclosure.

第5圖係採用本揭露第六實施例之氮化物半導體磊晶疊層結構之功率元件的上視圖。 Figure 5 is a top view of a power device using a nitride semiconductor epitaxial stack structure according to the sixth embodiment of the present disclosure.

第6A圖係採用本揭露第六實施例之氮化物半導體磊晶疊層結構之氮化物半導體功率元件單元的局部放大上視示意圖。 Figure 6A is a partially enlarged top view of a nitride semiconductor power device unit using a nitride semiconductor epitaxial stack structure according to the sixth embodiment of the present disclosure.

第6B圖係第6A圖沿剖線FF’之剖面示意圖。 Figure 6B is a schematic cross-sectional view along section line FF' of Figure 6A.

第7圖係本揭露第六實施例之氮化物半導體磊晶疊層結構細部側視示意圖。 FIG. 7 is a detailed side view of the nitride semiconductor epitaxial stack structure according to the sixth embodiment of the present disclosure.

第8圖係本揭露第七實施例之蕭特基二極體元件單元側視示意圖。 Figure 8 is a schematic side view of a Schottky diode device unit according to the seventh embodiment of the present disclosure.

第9A圖係採用習知氮化物半導體磊晶疊層結構之功率元件測試單元之電性測試結果圖。 Figure 9A shows the electrical test results of a power device test unit using a conventional nitride semiconductor epitaxial stack structure.

第9B圖係採用本揭露第一實施例之氮化物半導體磊晶疊層結構之功率元件測試單元之電性測試結果圖。 Figure 9B is a diagram of electrical test results of a power device test unit using the nitride semiconductor epitaxial stack structure of the first embodiment of the present disclosure.

第10A圖係採用習知氮化物半導體磊晶疊層結構之功率元件測試單元之側視示意圖。 Figure 10A is a schematic side view of a power device test unit using a conventional nitride semiconductor epitaxial stack structure.

第10B圖係採用本揭露第一實施例之氮化物半導體磊晶疊層結構之功率元件測試單元之側視示意圖。 Figure 10B is a schematic side view of a power device testing unit using the nitride semiconductor epitaxial stack structure according to the first embodiment of the present disclosure.

以下實施例將伴隨著圖式說明本揭露之概念,在圖式或說明中,相似或相同之部分係使用相同之標號,並且在圖式中,元件之形狀或厚度可擴大或縮小。需特別注意的是,圖中未繪示或描述之元件,可以是熟習此技藝之人士所知之形式。 The following embodiments will be accompanied by drawings to illustrate the concepts of the present disclosure. In the drawings or descriptions, similar or identical parts use the same reference numerals, and in the drawings, the shape or thickness of elements may be enlarged or reduced. It should be noted that components not shown or described in the drawings may be in forms known to those skilled in the art.

請參閱第2圖,第2圖顯示為本揭露第一實施例顯示之一種氮化物半導體磊晶疊層結構200側視圖。氮化物半導體磊晶疊層結構200包含一矽基板210,矽基板210上形成有一層氮化鋁成核層220,氮化鋁成核層220上形成有一緩衝結構300。其中,緩衝結構300由下至上依序包含由第一氮化鋁鎵超晶格層(Alx1Ga1-x1N,厚度d1)及第二氮化鋁鎵超晶格層(Aly1Ga1-y1N,厚度d2)兩種超晶格層交錯堆疊組合之第一超晶格磊晶結構310、一厚度大於1000奈米的第一氮化鎵系厚層(Alz1Ga1-z1N)320、由第三氮化鋁鎵超晶格層(Alx2Ga1-x2N,厚度d3)及第四氮化鋁鎵超晶格層(Aly2Ga1-y2N,厚度d4)兩種超晶格層交錯堆疊組合之第二超晶格磊晶結構330、一厚度大於1000奈米的第二氮化鎵系厚層(Alz2Ga1-z2N)340。接著,在緩衝結構300之上形成一元件功能結構400。其中,元件功能結構400包含由氮化鋁鎵(AlaGa1-aN),0≦a<1所構成的通道層410以及由氮化鋁鎵(AlbGa1-bN)所形成的障壁層420,0<b<1,且a<b。最終,更包含形成於障壁層420上方由未摻雜之氮化鎵(u-GaN)構成的一帽層510。 Please refer to Figure 2. Figure 2 shows a side view of a nitride semiconductor epitaxial stack structure 200 according to the first embodiment of the present disclosure. The nitride semiconductor epitaxial stack structure 200 includes a silicon substrate 210. An aluminum nitride nucleation layer 220 is formed on the silicon substrate 210. A buffer structure 300 is formed on the aluminum nitride nucleation layer 220. Among them, the buffer structure 300 sequentially includes a first aluminum gallium nitride superlattice layer (Al x1 Ga 1-x1 N, thickness d 1 ) and a second aluminum gallium nitride superlattice layer (Al y1 Ga 1-y1 N, thickness d 2 ) The first superlattice epitaxial structure 310, a staggered stack combination of two superlattice layers, and a first gallium nitride series thick layer (Al z1 Ga 1- z1 N) 320, consisting of the third aluminum gallium nitride superlattice layer (Al x2 Ga 1-x2 N, thickness d 3 ) and the fourth aluminum gallium nitride superlattice layer (Al y2 Ga 1-y2 N, thickness d4) The second superlattice epitaxial structure 330 of a staggered stacking combination of two superlattice layers, and a second gallium nitride series thick layer (Al z2 Ga 1-z2 N) 340 with a thickness greater than 1000 nanometers. Then, a component functional structure 400 is formed on the buffer structure 300 . Among them, the element functional structure 400 includes a channel layer 410 composed of aluminum gallium nitride (Al a Ga 1-a N), 0≦a<1, and a channel layer 410 formed of aluminum gallium nitride (Al b Ga 1-b N). For the barrier layer 420, 0<b<1, and a<b. Finally, a cap layer 510 composed of undoped gallium nitride (u-GaN) is formed above the barrier layer 420 .

於本實施例之中,元件功能結構400例如為功率元件的氮化鎵通道層410及氮化鋁鎵障壁層420,可於其接面鄰近處產生2DEG。當然,於另一實施例中,元件功能結構又或者也可以是發光二極體元件的活性層(圖未示),當發光二極體元件在電流注入後,電子電洞於活性層中復合產生光。 In this embodiment, the device functional structure 400 is, for example, the gallium nitride channel layer 410 and the aluminum gallium nitride barrier layer 420 of the power device, which can generate 2DEG near the junction thereof. Of course, in another embodiment, the functional structure of the device may also be the active layer (not shown) of the light-emitting diode device. When the light-emitting diode device is injected with current, electron holes recombine in the active layer. Produce light.

於本實施例中,氮化物半導體磊晶疊層結構200係於基板210的(111)表面上沿著[0001]方向形成氮化鋁成核層220。值得注意的是,基板210的材料並不以矽基板為限,可以是半導體材料或是氧化物材料,上述的半導體材料例如可以包含矽(Si)、氮化鎵(GaN)、碳化矽(SiC)、砷化鎵(GaAs)、氮化鋁(AlN)等,而上述的氧化物材料例如可以包含藍寶石(sapphire)。另外,當以導電性來區分時,基板210本身可為導電基板或者是絕緣基板,上述的導電基板包含矽(Si)基板、氮化鎵(GaN)基板、砷化鎵(GaAs)等基板,而上述的絕緣基板則包含藍寶石(sapphire)基板、絕緣矽(Silicon on insulator,SOI)基板、氮化鋁(AlN)等基板。此外,基板210可選擇性的摻雜物質於其中,以改變其導電性,以形成導電基板或不導電基板,以矽(Si)基板而言,可藉由摻雜硼(B)、砷(As)、或磷(P)使其具有導電性。於本實施例中,基板210為摻雜硼(B)之p型導電半導體矽基板(Si),厚度約為175~1500μm。 In this embodiment, the aluminum nitride nucleation layer 220 is formed along the [0001] direction on the (111) surface of the substrate 210 in the nitride semiconductor epitaxial stack structure 200 . It is worth noting that the material of the substrate 210 is not limited to a silicon substrate, and can be a semiconductor material or an oxide material. The above-mentioned semiconductor material can include, for example, silicon (Si), gallium nitride (GaN), silicon carbide (SiC). ), gallium arsenide (GaAs), aluminum nitride (AlN), etc., and the above-mentioned oxide material may include, for example, sapphire. In addition, when distinguished by conductivity, the substrate 210 itself can be a conductive substrate or an insulating substrate. The above-mentioned conductive substrate includes a silicon (Si) substrate, a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, and other substrates. The above-mentioned insulating substrates include sapphire (sapphire) substrates, silicon on insulator (SOI) substrates, aluminum nitride (AlN) and other substrates. In addition, the substrate 210 can be selectively doped with substances to change its conductivity to form a conductive substrate or a non-conductive substrate. For a silicon (Si) substrate, it can be doped with boron (B), arsenic ( As), or phosphorus (P) makes it conductive. In this embodiment, the substrate 210 is a p-type conductive semiconductor silicon substrate (Si) doped with boron (B) and has a thickness of approximately 175~1500 μm.

接著,將前述的氮化鋁成核層220以磊晶方式成長於矽基板210的(111)面上,其中氮化鋁成核層220係沿[0001]方向成長,厚度約可為數十奈米或數百奈米,可用以減少基板10和上方半導體層之間的晶格差異。磊晶成長的方式例如為物理氣相沉積法(physical vapor deposition,PVD)、原子層沉積法(atomic layer deposition,ALD)、金屬有機物化學氣相沉積法(metal-organic chemical vapor deposition,MOCVD)、或分子束磊晶法(molecular-beam epitaxy,MBE)。藉由氮化鋁成核層220可讓後續形成於其上的緩衝結構、通道層...等半導體磊晶疊層的磊晶品質較佳。氮化鋁成核層220的材料例如是三五族半導體材料,包括氮化鋁(AlN)、氮化鎵(GaN)、氮化鋁鎵(AlGaN)、或其混和組成的疊層等,而氮化鋁成核層220的結構例如可以是非晶、多晶、單晶或是晶質漸變的 混和層。於本實施例中,氮化鋁成核層220為氮化鋁(AlN),厚度約為20~50nm,是藉由MOCVD法而形成。 Next, the aforementioned aluminum nitride nucleation layer 220 is epitaxially grown on the (111) surface of the silicon substrate 210, where the aluminum nitride nucleation layer 220 grows along the [0001] direction, and the thickness can be about tens of tens. Nanometers or hundreds of nanometers can be used to reduce the lattice difference between the substrate 10 and the upper semiconductor layer. Epitaxial growth methods include physical vapor deposition (PVD), atomic layer deposition (ALD), metal-organic chemical vapor deposition (MOCVD), Or molecular-beam epitaxy (MBE). The aluminum nitride nucleation layer 220 can improve the epitaxial quality of semiconductor epitaxial stacks such as buffer structures and channel layers that are subsequently formed thereon. The material of the aluminum nitride nucleation layer 220 is, for example, a Group III or V semiconductor material, including aluminum nitride (AlN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), or a stack of mixed compositions thereof, etc., and The structure of the aluminum nitride nucleation layer 220 may be, for example, amorphous, polycrystalline, single crystal or crystalline graded. Blending layer. In this embodiment, the aluminum nitride nucleation layer 220 is aluminum nitride (AlN), has a thickness of about 20~50 nm, and is formed by the MOCVD method.

形成氮化鋁成核層220之後,再於氮化鋁成核層220的上方成長一緩衝結構300,如前所述,可透過此緩衝結構300來減少成核層220和上方通道層410之間的晶格差異與降低磊晶缺陷密度。而緩衝結構300製備方式則類似於前述,例如為物理氣相沉積法(physical vapor deposition,PVD)、原子層沉積法(atomic layer deposition,ALD)、金屬有機物化學氣相沉積法(metal-organic chemical vapor deposition,MOCVD)、或分子束磊晶法(molecular-beam epitaxy,MBE)等其中一種可能的磊晶方式。藉由緩衝結構300,可於其上方形成磊晶缺陷密度低、表面平整、表面裂紋較少及/或較小的高品質元件功能結構400。於本實施例中,緩衝結構300由以下四個部分所組成,且以MOCVD法形成,成長步驟說明如下。 After the aluminum nitride nucleation layer 220 is formed, a buffer structure 300 is grown above the aluminum nitride nucleation layer 220. As mentioned above, the buffer structure 300 can be used to reduce the friction between the nucleation layer 220 and the upper channel layer 410. The lattice difference between them and the reduction of epitaxial defect density. The preparation method of the buffer structure 300 is similar to the above, such as physical vapor deposition (PVD), atomic layer deposition (ALD), metal-organic chemical vapor deposition (metal-organic chemical). One of the possible epitaxy methods is vapor deposition (MOCVD) or molecular-beam epitaxy (MBE). Through the buffer structure 300, a high-quality device functional structure 400 with low epitaxial defect density, smooth surface, fewer surface cracks, and/or smaller size can be formed above it. In this embodiment, the buffer structure 300 consists of the following four parts and is formed by the MOCVD method. The growth steps are described below.

首先,於氮化鋁成核層220上以MOCVD法形成由第一氮化鋁鎵超晶格層(Alx1Ga1-x1N,厚度d1)及第二氮化鋁鎵超晶格層(Aly1Ga1-y1N,厚度d2)兩種超晶格層交錯堆疊組合之第一超晶格磊晶結構310。其中,為避免第一超晶格磊晶結構310與下方的氮化鋁成核層220間因晶格常數差異過大而產生多餘的應力,第一超晶格磊晶結構310中兩種氮化鋁鎵超晶格層的平均鋁含量較佳的範圍為0.3≦(x1×d1+y1×d2)/(d1+d2)≦1,x1≠y1。此外,第一超晶格磊晶結構310中每一層超晶格層的厚度d1、d2以不超過50奈米為佳。透過第一超晶格磊晶結構310的結構特性,可以釋放整體氮化物半導體磊晶疊層結構200內的應力累積,並可以阻斷源自於矽基板210與氮化鋁成核層220之間例如因晶格不匹配或應力而產生的磊晶缺陷沿著準垂直於矽基板210表面方向延伸而持續至氮化 物半導體磊晶疊層結構200的上部,繼而影響上方通道層410之品質,若缺陷繼續延伸至表面則產生裂紋。在這邊,適當的平均鋁組成比例,0.3≦(x1×d1+y1×d2)/(d1+d2)≦1,可以減少氮化鋁成核層220與第一超晶格磊晶結構310間晶格常數的差異、減少磊晶時的應力生成、亦可減少磊晶疊層表面產生裂紋。本實施例中,透過MOCVD法形成具有組成層數為100層(50對)的第一超晶格磊晶結構310,但實際上的組成層數並不以此數目為限,較佳的超晶格磊晶結構組成層數可以為20層(10對)至300層(150對);於本實施例之實驗得知,當組成層數低於20層時,超晶格磊晶結構對減緩應力累積及阻擋磊晶缺陷的效果極低,無法使後續成長的半導體磊晶疊層在足夠的厚度下不產生過多或過大的裂紋;而當超晶格磊晶結構的組成層數多於300層時,則會使磊晶過程過於耗時,不利於整體氮化物半導體磊晶結構200的製程經濟,而超晶格磊晶結構本身也會因過厚的厚度而使超晶格磊晶結構的表面開始劣化及產生非期待應力等副作用。 First, a first aluminum gallium nitride superlattice layer (Al x1 Ga 1-x 1N, thickness d 1 ) and a second aluminum gallium nitride superlattice layer are formed on the aluminum nitride nucleation layer 220 using the MOCVD method. (Al y1 Ga 1-y1 N, thickness d 2 ) The first superlattice epitaxial structure 310 of a staggered and stacked combination of two superlattice layers. Among them, in order to avoid excessive stress due to excessive differences in lattice constants between the first superlattice epitaxial structure 310 and the underlying aluminum nitride nucleation layer 220, two types of nitride in the first superlattice epitaxial structure 310 are The preferred range of the average aluminum content of the aluminum gallium superlattice layer is 0.3≦(x1×d 1 +y1×d 2 )/(d 1 +d 2 )≦1, x1≠y1. In addition, the thickness d 1 and d 2 of each superlattice layer in the first superlattice epitaxial structure 310 is preferably no more than 50 nanometers. Through the structural characteristics of the first superlattice epitaxial structure 310, the stress accumulation in the overall nitride semiconductor epitaxial stack structure 200 can be released, and the stress originating from the silicon substrate 210 and the aluminum nitride nucleation layer 220 can be blocked. For example, epitaxial defects generated due to lattice mismatch or stress extend along a direction quasi-perpendicular to the surface of the silicon substrate 210 and continue to the upper part of the nitride semiconductor epitaxial stack structure 200, thereby affecting the quality of the upper channel layer 410. If the defect continues to extend to the surface, cracks will occur. Here, the appropriate average aluminum composition ratio, 0.3≦(x1×d 1 +y1×d 2 )/(d 1 +d 2 )≦1, can reduce the relationship between the aluminum nitride nucleation layer 220 and the first superlattice The difference in lattice constants between the epitaxial structures 310 can reduce stress generation during epitaxial crystallization and can also reduce cracks on the surface of the epitaxial laminated layer. In this embodiment, the first superlattice epitaxial structure 310 having a composition layer number of 100 (50 pairs) is formed through the MOCVD method. However, the actual number of composition layers is not limited to this number. A preferred superlattice epitaxial structure 310 The number of layers of the lattice epitaxial structure can range from 20 layers (10 pairs) to 300 layers (150 pairs); in the experiment of this embodiment, it is found that when the number of layers is less than 20 layers, the super lattice epitaxial structure will The effect of slowing down stress accumulation and blocking epitaxial defects is extremely low, and it is impossible to prevent the subsequent growth of semiconductor epitaxial stacks from producing too many or too large cracks at a sufficient thickness; and when the superlattice epitaxial structure consists of more than When there are 300 layers, the epitaxial process will be too time-consuming, which is not conducive to the process economy of the overall nitride semiconductor epitaxial structure 200, and the superlattice epitaxial structure itself will also cause superlattice epitaxy due to excessive thickness. The surface of the structure begins to deteriorate and produces undesirable stresses and other side effects.

此外,於另一實施例中,第一超晶格磊晶結構310中亦可摻雜碳或鐵等元素,以增加第一超晶格磊晶結構310的層內阻值。於本實施例中,透過MOCVD法形成之第一超晶格磊晶結構310為摻雜碳雜質的氮化鋁鎵層。本實施例之摻雜碳雜質包含刻意摻雜或非刻意摻雜。較佳的碳雜質濃度範圍為透過二次離子質譜儀(Secondary Ion Mass Spectrometer,SIMS)量測時獲得5×1017/cm3~1×1020/cm3的範圍。於本實施例之實驗結果可發現,當碳濃度範圍低於5×1017/cm3時,第一超晶格磊晶結構310的阻值過低,後續當使用阻值過低的氮化物半導體磊晶疊層結構製成功率元件時,元件便無法具有足夠能力抵檔注入之電壓,無法提供較高的崩潰電壓,而當量測獲得之碳濃度範圍高於1×1020/cm3 時,第一超晶格磊晶結構310則會因濃度過高產生磊晶缺陷而使其磊晶品質下降。 In addition, in another embodiment, the first superlattice epitaxial structure 310 may also be doped with elements such as carbon or iron to increase the intra-layer resistance of the first superlattice epitaxial structure 310 . In this embodiment, the first superlattice epitaxial structure 310 formed by the MOCVD method is an aluminum gallium nitride layer doped with carbon impurities. The doped carbon impurities in this embodiment include intentional doping or unintentional doping. The preferred carbon impurity concentration range is the range of 5×10 17 /cm 3 ~1×10 20 /cm 3 when measured with a secondary ion mass spectrometer (SIMS). From the experimental results of this embodiment, it can be found that when the carbon concentration range is lower than 5×10 17 /cm 3 , the resistance of the first superlattice epitaxial structure 310 is too low. Subsequently, when a nitride with too low resistance is used, When a semiconductor epitaxial laminated structure is used to make a power device, the device cannot withstand the injected voltage and cannot provide a higher breakdown voltage. When the measured carbon concentration range is higher than 1×10 20 /cm 3 When the concentration is too high, the first superlattice epitaxial structure 310 will generate epitaxial defects, thereby degrading its epitaxial quality.

接著,在第一超晶格磊晶結構310上再以MOCVD法形成一厚度大於1000奈米的第一氮化鎵系厚層(Alz1Ga1-z1N)320,在這邊,第一氮化鎵系厚層320的組成例如可以是純氮化鎵或者是含有低鋁含量的氮化鋁鎵層。其中,添加適當的鋁元素,例如鋁含量為0≦z1≦0.05,可使該第一氮化鎵系厚層320的能隙寬度變大,若將此氮化物半導體磊晶疊層結構200製成功率元件時,理論上可使元件整體具有較高的垂直耐操作電壓能力,即,具有較高的元件崩潰電壓。同樣的,於第一氮化鎵系厚層320中亦可摻雜碳或鐵等元素,以增加第一氮化鎵系厚層320的層內阻值。於本實施例中,透過MOCVD法形成之第一氮化鎵系厚層320為摻雜碳雜質的氮化鋁鎵層。本實施例之摻雜碳雜質包含刻意摻雜或非刻意摻雜。較佳的碳雜質濃度範圍為透過SIMS量測時獲得5×1017/cm3~1×1020/cm3的範圍。經由本實施例實驗結果可發現,當碳濃度範圍低於5×1017/cm3時,第一氮化鎵系厚層320的阻值過低,後續當使用阻值過低的氮化物半導體磊晶疊層結構製成功率元件時,元件便無法具有足夠的能力抵檔注入之電壓,無法提供較高崩潰電壓,而當量測獲得之碳濃度範圍高於1×1020/cm3時,第一氮化鎵系厚層320則會因濃度過高產生磊晶缺陷而使其磊晶品質下降。 Next, a first gallium nitride series thick layer (Al z1 Ga 1-z1 N) 320 with a thickness greater than 1000 nanometers is formed on the first superlattice epitaxial structure 310 using the MOCVD method. Here, the first The composition of the gallium nitride thick layer 320 may be, for example, pure gallium nitride or an aluminum gallium nitride layer containing low aluminum content. Among them, adding appropriate aluminum elements, for example, the aluminum content is 0≦z1≦0.05, can increase the energy gap width of the first gallium nitride thick layer 320. If the nitride semiconductor epitaxial stacked structure 200 is manufactured, When a high-efficiency component is used, theoretically, the component as a whole can have a higher vertical withstand operating voltage capability, that is, a higher component breakdown voltage. Similarly, elements such as carbon or iron can also be doped into the first gallium nitride thick layer 320 to increase the intra-layer resistance of the first gallium nitride thick layer 320 . In this embodiment, the first gallium nitride thick layer 320 formed by the MOCVD method is an aluminum gallium nitride layer doped with carbon impurities. The doped carbon impurities in this embodiment include intentional doping or unintentional doping. The preferred carbon impurity concentration range is 5×10 17 /cm 3 ~1×10 20 /cm 3 when measured by SIMS. Through the experimental results of this embodiment, it can be found that when the carbon concentration range is lower than 5×10 17 /cm 3 , the resistance of the first gallium nitride thick layer 320 is too low. Subsequently, when a nitride semiconductor with too low resistance is used, When a power device is made of an epitaxial laminated structure, the device cannot withstand the injected voltage and cannot provide a higher breakdown voltage. When the measured carbon concentration range is higher than 1×10 20 /cm 3 , the first gallium nitride thick layer 320 will produce epitaxial defects due to too high concentration, thereby reducing its epitaxial quality.

接著,於第一氮化鎵系厚層320之上繼續藉由MOCVD法形成由第三氮化鋁鎵超晶格層(Alx2Ga1-x2N,厚度d3)及第四氮化鋁鎵超晶格層(Aly2Ga1-y2N,厚度d4)兩種超晶格層交錯堆疊組合之第二超晶格磊晶結構330。其中,為避免第二超晶格磊晶結構330與下方的第一氮化鎵系厚層320間因晶格常數差異過大而產生多餘的應力,第二超晶格磊晶結構330中兩種氮化鋁鎵超晶格層的平均鋁含量較佳的範圍為0≦(x2×d3+y2×d4)/(d3+d4)≦0.05,x2≠y2,而每一層 超晶格層的厚度以不超過50奈米為佳。透過第二超晶格磊晶結構330中釋放整體氮化物半導體磊晶疊層結構200內的應力累積,並可以持續阻斷來自於第一氮化鎵系厚層320側例如晶格不匹配或應力產生的磊晶缺陷再沿著垂直於矽基板210表面的方向隨著後續半導體磊晶疊層的成長而持續向上延伸。在這邊,適當的鋁組成比例,0≦(x2×d3+y2×d4)/(d3+d4)≦0.05,可以減少第一氮化鎵系厚層320與第二超晶格磊晶結構330間晶格常數的差異,減少磊晶時的應力生成、亦可減少磊晶層表面產生裂紋。本實施例中,形成具有組成層數為60層(30對)的第二超晶格磊晶結構330,但實際上組成層數並不以此數目為限。較佳的超晶格磊晶結構組成層數可以為20層(10對)至300層(150對),當組成層數低於20層時,超晶格磊晶結構對減緩應力累積及阻擋磊晶缺陷的效果極低,無法使後續成長的半導體磊晶疊層在足夠的厚度下不產生過多或過大的裂紋;而當超晶格磊晶結構多於300層時,則會使磊晶過程過於耗時,不利於整體氮化物半導體磊晶疊層結構200的製程經濟,而固定堆疊超晶格磊晶結構本身也會因過厚的厚度而使超晶格磊晶結構的表面開始劣化及非期待應力等副作用產生。 Then, a third aluminum gallium nitride superlattice layer (Al x2 Ga 1-x2 N, thickness d 3 ) and a fourth aluminum nitride layer are formed on the first gallium nitride thick layer 320 by the MOCVD method. The second superlattice epitaxial structure 330 is a staggered and stacked combination of two superlattice layers of gallium superlattice layer (Al y2 Ga 1-y2 N, thickness d 4 ). Among them, in order to avoid excessive stress due to excessive differences in lattice constants between the second superlattice epitaxial structure 330 and the underlying first gallium nitride thick layer 320, two types of the second superlattice epitaxial structure 330 are The preferred range of the average aluminum content of the aluminum gallium nitride superlattice layer is 0≦(x2×d 3 +y2×d 4 )/(d 3 +d 4 )≦0.05, x2≠y2, and each layer of supercrystal The thickness of the grid layer is preferably no more than 50 nanometers. The stress accumulation in the overall nitride semiconductor epitaxial stack structure 200 is released through the second superlattice epitaxial structure 330, and can continuously block the stress from the first gallium nitride thick layer 320 side such as lattice mismatch or The epitaxial defects generated by the stress continue to extend upward along the direction perpendicular to the surface of the silicon substrate 210 as the subsequent semiconductor epitaxial stack grows. Here, the appropriate aluminum composition ratio, 0≦(x2×d 3 +y2×d 4 )/(d 3 +d 4 )≦0.05, can reduce the distance between the first gallium nitride series thick layer 320 and the second supercrystal The difference in lattice constants between the lattice epitaxial structures 330 reduces stress generation during epitaxial crystallization and can also reduce cracks on the surface of the epitaxial layer. In this embodiment, the second superlattice epitaxial structure 330 is formed with 60 layers (30 pairs), but in fact, the number of layers is not limited to this number. The preferred number of layers of the superlattice epitaxial structure can be from 20 layers (10 pairs) to 300 layers (150 pairs). When the number of layers is less than 20 layers, the superlattice epitaxial structure can slow down stress accumulation and barrier. The effect of epitaxial defects is extremely low, and it is impossible to prevent the subsequent growth of semiconductor epitaxial stacks from producing too many or too large cracks at a sufficient thickness; and when the superlattice epitaxial structure has more than 300 layers, the epitaxial layer will be The process is too time-consuming and is not conducive to the process economy of the overall nitride semiconductor epitaxial stacked structure 200. The fixed stacked superlattice epitaxial structure itself will also cause the surface of the superlattice epitaxial structure to begin to deteriorate due to its excessive thickness. and unexpected stress and other side effects.

最後,在第二超晶格磊晶結構330上再以MOCVD法形成一厚度大於1000奈米的第二氮化鎵系厚層(Alz2Ga1-z2N)340,在這邊,第二氮化鎵系厚層340的組成例如可以是純氮化鎵或者是含有適當添加低鋁含量的氮化鋁鎵層。其中,添加適當的鋁元素,例如鋁含量為0≦z2≦0.05,可使第二氮化鎵系厚層340的能隙寬度變大,後續將此氮化物半導體磊晶疊層結構200製成功率元件時,理論上可使元件整體具有較高的垂直耐操作電壓能力,即,具有較高的元件崩潰電壓。此外,於第二氮化鎵系厚層340中亦可摻雜碳或鐵等元素,以增加第二氮化鎵系厚層340的層內阻值。於本實施例中,透過MOCVD法形成之第二氮化 鎵系厚層340為摻雜碳雜質的氮化鋁鎵層。本實施例之摻雜碳雜質包含刻意摻雜或非刻意摻雜。本實施例的碳雜質濃度範圍為透過SIMS量測時獲得5×1017/cm3~1×1020/cm3的範圍。經由本實施例的實驗結果可發現,當碳濃度範圍低於5×1017/cm3時,第二氮化鎵系厚層340的阻值過低,後續當使用阻值過低的氮化物半導體磊晶疊層結構製成功率元件時,元件便無法具有足夠的能力抵檔注入之電壓,無法提供較高崩潰電壓,而當量測獲得之碳濃度範圍高於1×1020/cm3時,第二氮化鎵系厚層340則會因碳濃度過高產生磊晶缺陷而使其磊晶品質下降。 Finally, a second gallium nitride series thick layer (Al z2 Ga 1-z2 N) 340 with a thickness greater than 1000 nanometers is formed on the second superlattice epitaxial structure 330 using the MOCVD method. Here, the second The composition of the gallium nitride thick layer 340 may be, for example, pure gallium nitride or an aluminum gallium nitride layer containing appropriately added low aluminum content. Among them, adding appropriate aluminum elements, for example, the aluminum content is 0≦z2≦0.05, can increase the energy gap width of the second gallium nitride series thick layer 340. Subsequently, the nitride semiconductor epitaxial stacked structure 200 is made. When using power components, the overall component can theoretically have a higher vertical withstand operating voltage capability, that is, a higher component breakdown voltage. In addition, elements such as carbon or iron can also be doped into the second gallium nitride thick layer 340 to increase the intra-layer resistance of the second gallium nitride thick layer 340 . In this embodiment, the second gallium nitride thick layer 340 formed by the MOCVD method is an aluminum gallium nitride layer doped with carbon impurities. The doped carbon impurities in this embodiment include intentional doping or unintentional doping. The carbon impurity concentration range in this embodiment is a range of 5×10 17 /cm 3 ~1×10 20 /cm 3 when measured by SIMS. Through the experimental results of this embodiment, it can be found that when the carbon concentration range is lower than 5×10 17 /cm 3 , the resistance of the second gallium nitride thick layer 340 is too low. Subsequently, when a nitride with too low resistance is used, When a semiconductor epitaxial laminated structure is used to make a power device, the device cannot withstand the injected voltage and cannot provide a high breakdown voltage. When the measured carbon concentration range is higher than 1×10 20 /cm 3 When the carbon concentration is too high, epitaxial defects will occur in the second gallium nitride thick layer 340 and its epitaxial quality will be degraded.

同樣的,於第二超晶格磊晶結構330中亦可摻雜碳或鐵等元素,以增加超晶格磊晶結構330的層內阻值。於本實施例中,透過MOCVD法形成之超晶格磊晶結構330為摻雜碳雜質的氮化鋁鎵層。類似的,本實施例之摻雜碳雜質包含刻意摻雜或非刻意摻雜。較佳的碳雜質濃度範圍為透過SIMS量測時獲得5×1017/cm3~1×1020/cm3的範圍。經由相關的實驗結果可發現,當碳濃度範圍低於5×1017/cm3時,第二超晶格磊晶結構330的阻值過低,後續當使用阻值過低的氮化物半導體磊晶疊層結構製成功率元件時,元件便無法具有足夠的能力抵檔注入之電壓,無法提供較高崩潰電壓,而當量測獲得之碳濃度範圍高於1×1020/cm3時,第二超晶格磊晶結構330則會因碳摻雜濃度過高產生磊晶缺陷而使其磊晶品質下降。 Similarly, elements such as carbon or iron can also be doped into the second superlattice epitaxial structure 330 to increase the intra-layer resistance of the superlattice epitaxial structure 330 . In this embodiment, the superlattice epitaxial structure 330 formed by the MOCVD method is an aluminum gallium nitride layer doped with carbon impurities. Similarly, the doping of carbon impurities in this embodiment includes intentional doping or unintentional doping. The preferred carbon impurity concentration range is 5×10 17 /cm 3 ~1×10 20 /cm 3 when measured by SIMS. Through relevant experimental results, it can be found that when the carbon concentration range is lower than 5×10 17 /cm 3 , the resistance value of the second superlattice epitaxial structure 330 is too low. Subsequently, when a nitride semiconductor epitaxial structure with too low resistance value is used, When a power device is made of a crystal laminated structure, the device cannot withstand the injected voltage and cannot provide a higher breakdown voltage. When the measured carbon concentration range is higher than 1×10 20 /cm 3 , In the second superlattice epitaxial structure 330, epitaxial defects may occur due to excessive carbon doping concentration, resulting in reduced epitaxial quality.

完成緩衝結構300後,接著便可於緩衝結構300上磊晶形成元件功能結構400。磊晶成長的方式可參考上述列舉之成長方式,在此不再贅述。於本實施例中,功率元件之元件功能結構400,包含通道層410及障壁層420。通道層410厚度範圍在50~500nm,形成於緩衝結構300上,由三族氮化物材料所構成, 並具有一第一能隙;障壁層420厚度範圍在10~50nm,形成在通道層410上,由三族氮化物材料所構成,並具有一第二能隙。其中,第二能隙較第一能隙大,因此,障壁層420之晶格常數比通道層410小。其中,通道層410可由純氮化鎵或適當添加低鋁含量的氮化鋁鎵組成的氮化鎵系材料(AlaGa1-aN)所構成,0≦a<0.05,而障壁層420則包含氮化鋁鎵(AlbGa1-bN),0<b<1,且a<b。通道層410以及障壁層420自身形成自發性極化(spontaneous polarization),且因其不同晶格常數形成壓電極化(piezoelectric polarization),進而在通道層410及障壁層420間的異質接面產生二維電子氣,請參考第2圖虛線表示處。於本實施例中,藉由MOCVD法形成通道層410及障壁層420,通道層410之材料為氮化鎵,障壁層420之材料為氮化鋁鎵,且為非摻雜之本質半導體。本揭露並不以本實施例為限,障壁層420及通道層410亦可視元件性能需求摻雜施體雜質或受體雜質以其改變其半導體層之特性。而二維電子氣產生的位置亦不侷限於如本實施例中第2圖所示的通道層410中,亦可能依實施例不同而產生於障壁層420中。 After the buffer structure 300 is completed, the device functional structure 400 can be epitaxially formed on the buffer structure 300 . The growth methods of epitaxial crystals can be referred to the growth methods listed above and will not be described again here. In this embodiment, the device functional structure 400 of the power device includes a channel layer 410 and a barrier layer 420. The channel layer 410 has a thickness ranging from 50 to 500 nm and is formed on the buffer structure 300. It is composed of a Group III nitride material and has a first energy gap. The barrier layer 420 has a thickness ranging from 10 to 50 nm and is formed on the channel layer 410. , composed of Group III nitride materials and having a second energy gap. The second energy gap is larger than the first energy gap. Therefore, the lattice constant of the barrier layer 420 is smaller than that of the channel layer 410 . Among them, the channel layer 410 can be composed of pure gallium nitride or a gallium nitride-based material (Al a Ga 1-a N) composed of aluminum gallium nitride with an appropriate addition of low aluminum content, 0≦a<0.05, and the barrier layer 420 It contains aluminum gallium nitride (Al b Ga 1-b N), 0<b<1, and a<b. The channel layer 410 and the barrier layer 420 themselves form spontaneous polarization (spontaneous polarization), and their different lattice constants form piezoelectric polarization (piezoelectric polarization), thereby generating two heterojunctions between the channel layer 410 and the barrier layer 420. For dimensional electron gas, please refer to the dotted line in Figure 2. In this embodiment, the channel layer 410 and the barrier layer 420 are formed by the MOCVD method. The material of the channel layer 410 is gallium nitride, and the material of the barrier layer 420 is aluminum gallium nitride, which is an undoped intrinsic semiconductor. This disclosure is not limited to this embodiment. The barrier layer 420 and the channel layer 410 may also be doped with donor impurities or acceptor impurities according to device performance requirements to change the characteristics of their semiconductor layers. The location where the two-dimensional electron gas is generated is not limited to the channel layer 410 as shown in FIG. 2 in this embodiment, and may also be generated in the barrier layer 420 depending on the embodiment.

於本實施例中,為減少晶格常數差異所造成不必要的應力累積,當氮化鋁成核層220之材料為鋁組成比例較高之材料,如氮化鋁;而上方元件功能結構如通道層410之材料為鋁組成比例較低之材料,如氮化鎵時;緩衝結構300較佳的實施方式為使氮化物半導體磊晶疊層結構中複數層結構的全部或一部分的鋁組成比例位於成核層220材料的鋁組成比例及元件功能層材料的鋁組成比例之間,並且沿磊晶成長方向漸變,其中,鋁組成漸變之方式可以是連續或不連續。即,例如本實施例所示,氮化鋁成核層220之鋁組成比例≧第一超晶格磊晶結構310之平均鋁組成比例≧第一氮化鎵系厚層320之鋁組成比例≧第二超晶格磊晶結構330之平均鋁組成比例≧第二氮化鎵系厚層340之鋁組成比例。 In this embodiment, in order to reduce unnecessary stress accumulation caused by the difference in lattice constants, when the material of the aluminum nitride nucleation layer 220 is a material with a higher aluminum composition ratio, such as aluminum nitride; and the functional structure of the upper device is as follows When the material of the channel layer 410 is a material with a low aluminum composition ratio, such as gallium nitride; a preferred embodiment of the buffer structure 300 is to use an aluminum composition ratio of all or part of the plurality of layers in the nitride semiconductor epitaxial stacked structure. It is located between the aluminum composition ratio of the nucleation layer 220 material and the aluminum composition ratio of the element functional layer material, and gradually changes along the epitaxial growth direction, wherein the aluminum composition gradient may be continuous or discontinuous. That is, for example, as shown in this embodiment, the aluminum composition ratio of the aluminum nitride nucleation layer 220 ≧ the average aluminum composition ratio of the first superlattice epitaxial structure 310 ≧ the aluminum composition ratio of the first gallium nitride series thick layer 320 ≧ The average aluminum composition ratio of the second superlattice epitaxial structure 330 ≧ the aluminum composition ratio of the second gallium nitride series thick layer 340 .

於另一實施例中,氮化物半導體磊晶疊層結構中的通道層410亦可以於形成第二氮化鎵系厚層340時同時形成。也就是說,可以在第二超晶格磊 晶結構330上成長一第二氮化鎵系半導體層(圖未示),其中第二氮化鎵系半導體層的上半部構成通道層410,而第二氮化鎵系半導體層的下半部則構成第二氮化鎵系厚層340。再於其上形成障壁層420,並在鄰近障壁層420及通道層410的接面處產生二維電子氣。 In another embodiment, the channel layer 410 in the nitride semiconductor epitaxial stack structure can also be formed simultaneously when the second gallium nitride thick layer 340 is formed. In other words, in the second superlattice Lei A second gallium nitride-based semiconductor layer (not shown) is grown on the crystal structure 330, in which the upper half of the second gallium nitride-based semiconductor layer constitutes the channel layer 410, and the lower half of the second gallium nitride-based semiconductor layer The second gallium nitride thick layer 340 is formed. A barrier layer 420 is then formed thereon, and a two-dimensional electron gas is generated adjacent to the interface between the barrier layer 420 and the channel layer 410 .

除此之外,於成長障壁層420之後,可以選擇性地利用上述列舉之任一種成長方式將帽層510成長於障壁層420上方,在此不再贅述。於本實施例中,帽層510例如為未摻雜之氮化鎵半導體層,且大致覆蓋障壁層420之表面,可避免障壁層420表面因氧化等反應而產生表面劣化,並可以改善障壁層420表面漏電流現象。值得注意的是,為了使後續製成元件時,於氮化物半導體磊晶疊層結構200表面上需形成的電極結構(圖未示)與障壁層420間維持良好的電性接觸,本實施例帽層510的厚度為0~20奈米之間,以使電子可經由電極結構於帽層510間穿隧通過。 In addition, after the barrier layer 420 is grown, the cap layer 510 can be selectively grown on the barrier layer 420 by any of the above-mentioned growth methods, which will not be described in detail here. In this embodiment, the cap layer 510 is, for example, an undoped gallium nitride semiconductor layer, and substantially covers the surface of the barrier layer 420, which can prevent the surface of the barrier layer 420 from being degraded due to oxidation and other reactions, and can improve the surface leakage current phenomenon of the barrier layer 420. It is worth noting that in order to maintain good electrical contact between the electrode structure (not shown) to be formed on the surface of the nitride semiconductor epitaxial stack structure 200 and the barrier layer 420 when the device is subsequently manufactured, the thickness of the cap layer 510 in this embodiment is between 0 and 20 nanometers, so that electrons can tunnel through the cap layer 510 through the electrode structure.

請參考第3A圖及第3B圖,分別顯示為習知氮化物半導體磊晶疊層結構100及採用本揭露第二實施例之氮化物半導體磊晶疊層結構(圖未示)中包含緩衝結構部分之局部磊晶疊層100’及200’之TEM影像。參考第3A圖及第3B圖,在第3A圖中,局部磊晶疊層100’的緩衝結構由超晶格疊層130及氮化鎵厚層140所組成;在第3B圖中,局部磊晶疊層200’的緩衝結構300則由第一超晶格磊晶結構310、第一氮化鎵系厚層320’、第二超晶格磊晶結構330、第二氮化鎵系厚層340’所組成。從影像中可以發現,局部磊晶疊層100’仍有大部分的磊晶缺陷145自超晶格疊層130中延伸至上層的氮化鎵厚層140中;相對的,如第3B圖所示,在第二實施例中,與第一實施例不同的地方是,第一氮化鎵系厚層320’的厚度為1.3微米,而第二氮化鎵系厚層340’的厚度為0.9微米。由影像中可以發現,在局部磊晶疊層200’中,有一部分的磊晶缺陷 245在第一氮化鎵系厚層320’中轉向或中止外,另一部分的磊晶缺陷245則在第二超晶格磊晶結構330中被中斷,再有,又一部分的磊晶缺陷245又在第二氮化鎵系厚層340’中再度被轉向或中止。由此可知,相較於第3A圖中習知的局部磊晶疊層100’,採用本揭露第二實施例的局部磊晶疊層200’可相對大幅降低磊晶疊層內的磊晶缺陷密度,繼而可減少後續生成的元件功能結構(圖未示)表面裂紋,提高其磊晶品質,並可使後續採用此氮化物半導體磊晶疊層結構200’進行製程的功率元件具有較高的元件性能。從實施例的實驗結果可以發現,第一氮化鎵系厚層320’與第二氮化鎵系厚層340’的整體厚度對於氮化物半導體磊晶疊層結構中的磊晶缺陷245具有轉向或中止的貢獻效果。如第一實施例與第二實施例的結果所示,較佳的情況,兩個氮化鎵系厚層的總厚度應大於兩微米 Please refer to Figures 3A and 3B, which respectively show a conventional nitride semiconductor epitaxial stacked structure 100 and a nitride semiconductor epitaxial stacked structure (not shown) using the second embodiment of the present disclosure including a buffer structure. TEM images of portions of partial epitaxial stacks 100' and 200'. Referring to Figures 3A and 3B, in Figure 3A, the buffer structure of the local epitaxial layer 100' is composed of a superlattice stack 130 and a gallium nitride thick layer 140; in Figure 3B, the local epitaxial layer 100' The buffer structure 300 of the crystal stack 200' is composed of a first superlattice epitaxial structure 310, a first gallium nitride thick layer 320', a second superlattice epitaxial structure 330, and a second gallium nitride thick layer. Composed of 340'. It can be found from the image that the local epitaxial stack 100' still has most of the epitaxial defects 145 extending from the superlattice stack 130 to the upper gallium nitride thick layer 140; in contrast, as shown in Figure 3B shows that in the second embodiment, the difference from the first embodiment is that the thickness of the first gallium nitride thick layer 320' is 1.3 microns, while the thickness of the second gallium nitride thick layer 340' is 0.9 Micron. It can be found from the image that there are some epitaxial defects in the local epitaxial stack 200'. 245 is turned or stopped in the first gallium nitride thick layer 320', another part of the epitaxial defects 245 is interrupted in the second superlattice epitaxial structure 330, and there is another part of the epitaxial defects 245. It is turned or stopped again in the second gallium nitride thick layer 340'. It can be seen from this that, compared with the conventional partial epitaxial stack 100' in Figure 3A, the partial epitaxial stack 200' of the second embodiment of the present disclosure can relatively significantly reduce epitaxy defects in the epitaxial stack. density, thereby reducing surface cracks on the subsequently generated component functional structure (not shown), improving its epitaxial quality, and enabling subsequent power components to be manufactured using this nitride semiconductor epitaxial stack structure 200' to have higher Component performance. From the experimental results of the embodiment, it can be found that the overall thickness of the first gallium nitride-based thick layer 320' and the second gallium nitride-based thick layer 340' has a steering effect on the epitaxial defects 245 in the nitride semiconductor epitaxial stack structure. or the effect of discontinued contributions. As shown in the results of the first embodiment and the second embodiment, in a better case, the total thickness of the two gallium nitride thick layers should be greater than two microns.

請參考第4A~4C圖,所示為依據本揭露第三實施例至第五實施例之氮化物半導體磊晶疊層結構之局部示意圖,分別繪示包含緩衝結構430、460、490部分之局部磊晶疊層結構之側視示意圖。第4A圖所顯示為本揭露第三實施例包含緩衝結構430部分之局部磊晶疊層結構之側視示意圖,本實施例之氮化物半導體磊晶疊層結構與第一實施例不同處在緩衝結構430與緩衝結構300之差異,其他皆與第一實施例相同。於本實施例中,於氮化鋁成核層220之上,緩衝結構430依序包含第一氮化鎵系厚層431、第一超晶格磊晶結構432、第二氮化鎵系厚層433、以及第二超晶格磊晶結構434。即,於本實施例中,緩衝結構430係由兩組依序成長的氮化鎵系厚層及超晶格磊晶結構所組成,與第一實施例中緩衝結構300先成長超晶格磊晶結構,再成長氮化鎵系厚層的順序相反。後續,可再於緩衝結構430上依不同需求形成單層或多層的元件功能結構。 Please refer to Figures 4A to 4C, which are partial schematic diagrams of nitride semiconductor epitaxial stacked structures according to the third to fifth embodiments of the present disclosure, respectively illustrating parts of the buffer structures 430, 460, and 490. Schematic side view of the epitaxial stack structure. Figure 4A shows a schematic side view of a partial epitaxial stack structure including a buffer structure 430 part according to the third embodiment of the present disclosure. The nitride semiconductor epitaxial stack structure of this embodiment is different from the first embodiment in that the buffer structure The other differences between the structure 430 and the buffer structure 300 are the same as those in the first embodiment. In this embodiment, on the aluminum nitride nucleation layer 220, the buffer structure 430 sequentially includes a first gallium nitride series thick layer 431, a first superlattice epitaxial structure 432, and a second gallium nitride series thick layer 431. layer 433, and a second superlattice epitaxial structure 434. That is, in this embodiment, the buffer structure 430 is composed of two groups of sequentially grown thick layers of gallium nitride and a superlattice epitaxial structure. In the first embodiment, the buffer structure 300 first grows a superlattice epitaxial structure. crystal structure, and then the order of growing a thick layer of gallium nitride is reversed. Subsequently, a single-layer or multi-layer component functional structure can be formed on the buffer structure 430 according to different requirements.

其中,為減少晶格常數差異所造成不必要的應力累積,當氮化鋁成核層220之材料為鋁組成比例較高之材料,如氮化鋁;而上方元件功能結構如通道層(圖未示)之材料為鋁組成比例較低之材料,如氮化鎵時;緩衝結構較佳的實施方式為使氮化物半導體磊晶疊層結構中複數層結構的全部或一部的鋁組成比例位於成核層材料的鋁組成比例及元件功能層材料的鋁組成比例之間,並且沿磊晶成長方向漸變,漸變之方式可以是連續或不連續。即,例如本實施例所示,氮化鋁成核層220之鋁組成比例≧第一氮化鎵系厚層431之鋁組成比例≧第一超晶格磊晶結構432之平均鋁組成比例≧第二氮化鎵系厚層433之鋁組成比例≧第二超晶格磊晶結構434之平均鋁組成比例。 Among them, in order to reduce unnecessary stress accumulation caused by the difference in lattice constants, when the material of the aluminum nitride nucleation layer 220 is a material with a high aluminum composition ratio, such as aluminum nitride; and the upper component functional structure such as the channel layer (Fig. When the material (not shown) is a material with a low aluminum composition ratio, such as gallium nitride; a preferred embodiment of the buffer structure is to adjust the aluminum composition ratio of all or part of the plurality of layers in the nitride semiconductor epitaxial stacked structure It is located between the aluminum composition ratio of the nucleation layer material and the aluminum composition ratio of the component functional layer material, and gradually changes along the epitaxial growth direction. The gradient may be continuous or discontinuous. That is, as shown in this embodiment, the aluminum composition ratio of the aluminum nitride nucleation layer 220 ≧ the aluminum composition ratio of the first gallium nitride thick layer 431 ≧ the average aluminum composition ratio of the first superlattice epitaxial structure 432 ≧ The aluminum composition ratio of the second gallium nitride thick layer 433 is ≧ the average aluminum composition ratio of the second superlattice epitaxial structure 434 .

第4B圖所顯示為本揭露第四實施例包含緩衝結構460部分之局部磊晶疊層結構之側視示意圖,與第一實施例不同的是,本實施例中於矽基板210上形成氮化鋁成核層220後,再於其上形成的緩衝結構460依序由第一超晶格磊晶結構461、第一氮化鎵系厚層462、第二超晶格磊晶結構463、第二氮化鎵系厚層464、第三超晶格磊晶結構465、以及第三氮化鎵系厚層466所構成。即,於本實施例中,緩衝結構460係由三組超晶格磊晶結構及氮化鎵系厚層所構成,比第一實施例中的兩組超晶格磊晶結構及氮化鎵系厚層的組成多一組。值得注意的是,包含有兩組以上超晶格磊晶結構及氮化鎵系厚層的組成的緩衝結構應皆可以達成本揭露之精神,本揭露並不以本實施例之組數為限。 Figure 4B shows a schematic side view of a partial epitaxial stack structure including a buffer structure 460 part according to the fourth embodiment of the present disclosure. The difference from the first embodiment is that in this embodiment, nitride is formed on the silicon substrate 210 After the aluminum nucleation layer 220 is formed, the buffer structure 460 formed thereon sequentially consists of a first superlattice epitaxial structure 461, a first gallium nitride thick layer 462, a second superlattice epitaxial structure 463, It is composed of a gallium nitride thick layer 464 , a third superlattice epitaxial structure 465 , and a third gallium nitride thick layer 466 . That is, in this embodiment, the buffer structure 460 is composed of three sets of superlattice epitaxial structures and gallium nitride thick layers, which is smaller than the two sets of superlattice epitaxial structures and gallium nitride thick layers in the first embodiment. The thick layer consists of one more group. It is worth noting that buffer structures including two or more groups of superlattice epitaxial structures and gallium nitride thick layers should be able to achieve the spirit of the disclosure. The disclosure is not limited to the number of groups in this embodiment. .

其中,為減少晶格常數差異所造成不必要的應力累積,當氮化鋁成核層220之材料為鋁組成比例較高之材料,如氮化鋁;而上方元件功能結構如通道層(圖未示)之材料為鋁組成比例較低之材料,如氮化鎵時;緩衝結構較佳的實施方式為使氮化物半導體磊晶疊層結構中複數層結構的全部或一部的鋁組成比例位於成核層材料的鋁組成比例及元件功能層材料的鋁組成比例之間,並且 沿磊晶成長方向漸變,漸變之方式可以是連續或不連續。即,例如本實施例所示,氮化鋁成核層220之鋁組成比例≧第一超晶格磊晶結構461之平均鋁組成比例≧第一氮化鎵系厚層462之鋁組成比例≧第二超晶格磊晶結構463之平均鋁組成比例≧第二氮化鎵系厚層464之鋁組成比例≧第三超晶格磊晶結構465之平均鋁組成比例≧第三氮化鎵系厚層466之鋁組成比例。 Among them, in order to reduce unnecessary stress accumulation caused by the difference in lattice constants, when the material of the aluminum nitride nucleation layer 220 is a material with a high aluminum composition ratio, such as aluminum nitride; and the upper component functional structure such as the channel layer (Fig. When the material (not shown) is a material with a low aluminum composition ratio, such as gallium nitride; a preferred embodiment of the buffer structure is to adjust the aluminum composition ratio of all or part of the plurality of layers in the nitride semiconductor epitaxial stacked structure It is between the aluminum composition ratio of the nucleation layer material and the aluminum composition ratio of the component functional layer material, and Gradient along the epitaxial growth direction, the gradient can be continuous or discontinuous. That is, as shown in this embodiment, the aluminum composition ratio of the aluminum nitride nucleation layer 220 ≧ the average aluminum composition ratio of the first superlattice epitaxial structure 461 ≧ the aluminum composition ratio of the first gallium nitride series thick layer 462 ≧ The average aluminum composition ratio of the second superlattice epitaxial structure 463 ≧ the aluminum composition ratio of the second gallium nitride series thick layer 464 ≧ the average aluminum composition ratio of the third superlattice epitaxial structure 465 ≧ the third gallium nitride series Aluminum composition ratio of thick layer 466.

第4C圖所顯示為本揭露第五實施例包含緩衝結構490部分之局部磊晶疊層結構側視示意圖,與第四實施例不同的是,本實施例中的緩衝結構490依序由第一氮化鎵系厚層491、第一超晶格磊晶結構492、第二氮化鎵系厚層493、第二超晶格磊晶結構494、第三氮化鎵系厚層495、以及第三超晶格磊晶結構496所構成。即,於本實施例中,緩衝結構490系由三組氮化鎵系厚層及超晶格磊晶結構所構成,比第一實施例中的兩組氮化鎵系厚層及超晶格磊晶結構多一組,此外並與第四實施例中的緩衝結構460先成長超晶格磊晶結構,再成長氮化鎵系厚層的順序相反。值得注意的是,包含有兩組以上氮化鎵系厚層及超晶格磊晶結構的組成的緩衝結構應皆可以達成本揭露之精神,本揭露並不以實施例之組數為限。 Figure 4C shows a schematic side view of a partial epitaxial laminated structure including a buffer structure 490 part according to the fifth embodiment of the present disclosure. The difference from the fourth embodiment is that the buffer structure 490 in this embodiment sequentially consists of the first Gallium nitride series thick layer 491, first superlattice epitaxial structure 492, second gallium nitride series thick layer 493, second superlattice epitaxial structure 494, third gallium nitride series thick layer 495, and It is composed of three superlattice epitaxial structures 496. That is, in this embodiment, the buffer structure 490 is composed of three groups of gallium nitride thick layers and a superlattice epitaxial structure, which is larger than the two groups of gallium nitride thick layers and superlattice structures in the first embodiment. There is one more set of epitaxial structures. In addition, the order of growing the superlattice epitaxial structure first and then growing the gallium nitride thick layer is opposite to that of the buffer structure 460 in the fourth embodiment. It is worth noting that buffer structures including two or more groups of gallium nitride thick layers and superlattice epitaxial structures should be able to achieve the spirit of this disclosure, and this disclosure is not limited to the number of groups in the embodiment.

其中,為減少晶格常數差異所造成不必要的應力累積,當氮化鋁成核層220之材料為鋁組成比例較高之材料,如氮化鋁;而上方元件功能結構如通道層(圖未示)之材料為鋁組成比例較低之材料,如氮化鎵時;緩衝結構較佳的實施方式為使氮化物半導體磊晶疊層結構中複數層結構的全部或一部的鋁組成比例位於成核層材料的鋁組成比例及元件功能層材料的鋁組成比例之間,並且沿磊晶成長方向漸變,漸變之方式可以是連續或不連續。即,例如本實施例所示,氮化鋁成核層220之鋁組成比例≧第一氮化鎵系厚層491之鋁組成比例≧第一 超晶格磊晶結構492之平均鋁組成比例≧第二氮化鎵系厚層493之鋁組成比例≧第二超晶格磊晶結構494之平均鋁組成比例≧第三氮化鎵系厚層495之鋁組成比例≧第三超晶格磊晶結構496之平均鋁組成比例。 Among them, in order to reduce unnecessary stress accumulation caused by the difference in lattice constants, when the material of the aluminum nitride nucleation layer 220 is a material with a high aluminum composition ratio, such as aluminum nitride; and the upper component functional structure such as the channel layer (Fig. When the material (not shown) is a material with a low aluminum composition ratio, such as gallium nitride; a preferred embodiment of the buffer structure is to adjust the aluminum composition ratio of all or part of the plurality of layers in the nitride semiconductor epitaxial stacked structure It is located between the aluminum composition ratio of the nucleation layer material and the aluminum composition ratio of the component functional layer material, and gradually changes along the epitaxial growth direction. The gradient may be continuous or discontinuous. That is, for example, as shown in this embodiment, the aluminum composition ratio of the aluminum nitride nucleation layer 220 ≧ the aluminum composition ratio of the first gallium nitride thick layer 491 ≧ the first The average aluminum composition ratio of the superlattice epitaxial structure 492 ≧ the aluminum composition ratio of the second gallium nitride series thick layer 493 ≧ the average aluminum composition ratio of the second superlattice epitaxial structure 494 ≧ the third gallium nitride series thick layer The aluminum composition ratio of 495≧the average aluminum composition ratio of the third superlattice epitaxial structure 496.

接著,請參照第5、6、7A-7B圖。第5圖為本揭露第六實施例之一功率元件S的上視圖。半導體功率元件S例如為三端點的元件。於本實施例中,功率元件S包含一源極墊S70、一汲極墊S80、一閘極墊S90和至少一個功率元件單元E1。功率元件單元E1例如是場效電晶體(FET),具體來說可以是高電子遷移率場效應電晶體(HEMT)。 Next, please refer to Figures 5, 6, and 7A-7B. Figure 5 is a top view of a power element S according to the sixth embodiment of the present disclosure. The semiconductor power element S is, for example, a three-terminal element. In this embodiment, the power device S includes a source pad S70, a drain pad S80, a gate pad S90 and at least one power device unit E1. The power element unit E1 is, for example, a field effect transistor (FET), specifically a high electron mobility field effect transistor (HEMT).

第6A圖至第6B圖所示為前述第5圖功率元件S上視圖中功率元件單元E1的結構示意圖。為了清楚說明功率元件單元E1的細部結構,第6A圖繪示了功率元件單元E1之局部放大上視示意圖,而第6B圖繪示了第6A圖沿剖線FF’之剖面示意圖。功率元件單元E1例如為一種高電子遷移率場效應電晶體,包括使用本揭露後述第六實施例的一氮化物半導體磊晶疊層結構500、一源極電極70、一汲極電極80、以及一閘極電極90。如第5圖所示,於功率元件單元E1中,源極墊S70係與源極電極70電性連結、汲極墊S80係與汲極電極80電性連結、而閘極墊S90則與閘極電極90電性連結,氮化物半導體磊晶疊層結構500則相對應位於電極下方,如第6B圖所示。 Figures 6A to 6B show a schematic structural diagram of the power element unit E1 in the top view of the power element S in Figure 5. In order to clearly illustrate the detailed structure of the power device unit E1, Figure 6A shows a partially enlarged top view of the power device unit E1, and Figure 6B shows a cross-sectional view along the section line FF' in Figure 6A. The power element unit E1 is, for example, a high electron mobility field effect transistor, including a nitride semiconductor epitaxial stack structure 500 using the sixth embodiment of the present disclosure, a source electrode 70, a drain electrode 80, and A gate electrode 90. As shown in Figure 5, in the power element unit E1, the source pad S70 is electrically connected to the source electrode 70, the drain pad S80 is electrically connected to the drain electrode 80, and the gate pad S90 is electrically connected to the gate electrode. The electrodes 90 are electrically connected, and the nitride semiconductor epitaxial stack structure 500 is correspondingly located under the electrodes, as shown in Figure 6B.

功率元件單元E1表面還可以進一步形成保護層(圖未示)以覆蓋介電層60、源極電極70、汲極電極80與閘極電極90之表面,以防止功率元件單元E1整體的電性受到影響。保護層可以是氧化物或者氮化物,如氧化矽或氧化鋁等氧化物,也可以是氮化矽或氮化鎵等氮化物。接著再蝕刻保護層,以露出部分源極電極70、汲極電極80與閘極電極90,即源極電極70、汲極電極80與閘極電極80可以有一部份表面未被保護層所覆蓋,以增加與外界電性連接的方 便性。於本揭露中,未被保護層覆蓋位置例如可以是與源極電極70、汲極電極80與閘極電極90直接電性連結的源極墊S70、汲極墊S80、及閘極墊S90。 A protective layer (not shown) may be further formed on the surface of the power element unit E1 to cover the surfaces of the dielectric layer 60, the source electrode 70, the drain electrode 80 and the gate electrode 90 to prevent the overall electrical damage of the power element unit E1. affected. The protective layer can be an oxide or a nitride, such as an oxide such as silicon oxide or aluminum oxide, or a nitride such as silicon nitride or gallium nitride. Then the protective layer is etched to expose part of the source electrode 70 , the drain electrode 80 and the gate electrode 90 . That is, part of the surface of the source electrode 70 , the drain electrode 80 and the gate electrode 80 may not be covered by the protective layer. , to increase the electrical connection with the outside world Convenience. In the present disclosure, the locations not covered by the protective layer may be, for example, the source pad S70 , the drain pad S80 , and the gate pad S90 that are directly electrically connected to the source electrode 70 , the drain electrode 80 , and the gate electrode 90 .

第7圖所顯示為本揭露第六實施例功率元件S中氮化物半導體磊晶疊層結構500之細部側視示意圖。在本實施例中,氮化物半導體磊晶疊層結構500與第一實施例相似的結構採用與第一實施例相同的標號。值得注意的是,在本實施例中,在緩衝結構300與通道層410之間插入了一後障壁層(Back Barrier)550。此層後障壁層550較佳的組成為鋁組成比例較第二氮化鎵系厚層340鋁組成比例高的氮化鋁鎵層。當氮化物半導體磊晶疊層結構500後續製成功率元件時,後障壁層550較第二氮化鎵系厚層340高的鋁組成比例會具有較高的能隙來提供侷限電子能力,避免元件操作時電子進入緩衝結構300中並被緩衝結構300中的磊晶缺陷所捕捉,進而影響後續元件操作時異質介面間的二維電子氣濃度穩定性。即,可以減少元件於反覆操作時產生電流崩塌(current collapse)的程度。 FIG. 7 shows a detailed side view of the nitride semiconductor epitaxial stack structure 500 in the power device S according to the sixth embodiment of the present disclosure. In this embodiment, the nitride semiconductor epitaxial stack structure 500 is similar to the first embodiment and uses the same reference numerals as the first embodiment. It is worth noting that in this embodiment, a back barrier layer (Back Barrier) 550 is inserted between the buffer structure 300 and the channel layer 410. The preferred composition of the rear barrier layer 550 is an aluminum gallium nitride layer with a higher aluminum composition ratio than that of the second gallium nitride thick layer 340 . When the nitride semiconductor epitaxial stacked structure 500 is subsequently fabricated into a power device, the rear barrier layer 550 has a higher aluminum composition ratio than the second gallium nitride thick layer 340 and will have a higher energy gap to provide localized electronic capabilities to avoid When the device is operated, electrons enter the buffer structure 300 and are captured by epitaxial defects in the buffer structure 300 , thereby affecting the stability of the two-dimensional electron gas concentration between the heterogeneous interfaces during subsequent device operation. That is, the degree of current collapse that occurs when the device is repeatedly operated can be reduced.

值得注意的是,於本實施例中,為了避免後障壁層550的高能隙拉升通道層410的能障高度,進一步影響功率元件操作時電流的強度,後障壁層550的厚度以不超過50奈米為佳。 It is worth noting that in this embodiment, in order to prevent the high energy gap of the rear barrier layer 550 from raising the energy barrier height of the channel layer 410 and further affecting the intensity of the current when the power device is operated, the thickness of the rear barrier layer 550 is no more than 50 Nano is better.

除此之外,如第6B圖所示,在本實施例中,在形成源極電極70、汲極電極80與閘極電極90之前,還可形成有一介電層60於帽層510的上表面之上。介電層60亦可選擇性地位於閘極電極90的下方(圖未示)。當介電層60位於閘極電極的下方時,藉由選擇具有不同介電常數的介電層60以及調整介電層60的厚度,可以進一步降低表面漏電流,更可提高閘極電極90操作偏壓範圍,提升元件可靠度。介電層60可以是氧化物或者氮化物,例如是氧化矽或氧化鋁等氧化物,也可以是氮化矽或氮化鋁等氮化物,也可以是氮氧化鋁等氮氧化物。然而本揭露不以此為限,於其他實施例中亦可不形成介電層60。 In addition, as shown in FIG. 6B, in this embodiment, before forming the source electrode 70, the drain electrode 80 and the gate electrode 90, a dielectric layer 60 can also be formed on the cap layer 510. above the surface. The dielectric layer 60 may also be selectively located under the gate electrode 90 (not shown). When the dielectric layer 60 is located under the gate electrode, by selecting the dielectric layer 60 with different dielectric constants and adjusting the thickness of the dielectric layer 60 , the surface leakage current can be further reduced, and the operation of the gate electrode 90 can be improved. Bias voltage range improves component reliability. The dielectric layer 60 may be an oxide or a nitride, such as an oxide such as silicon oxide or aluminum oxide, a nitride such as silicon nitride or aluminum nitride, or an oxynitride such as aluminum oxynitride. However, the present disclosure is not limited thereto, and the dielectric layer 60 may not be formed in other embodiments.

於本實施例中,如前所述,於氮化物半導體磊晶疊層結構500上方分別形成源極電極70、汲極電極80與閘極電極90,後續並以其延伸並與其電性連結的源極墊S70、汲極墊S80、閘極墊S90作為與外部電性連接的端點。其中,如第6B圖所示,在一個功率元件單元E1的側視圖中,源極電極70、汲極電極80分別置於氮化物半導體磊晶疊層結構500表面的兩側,而閘極電極90則位於源極電極70與汲極電極80之間。在本實施例中,可以藉由選擇適當的源極電極70與汲極電極80的材料,以及/或者藉由製程(如,蝕刻、熱退火等...)以使源極電極70與汲極電極80和障壁層420之間形成歐姆接觸。類似地,也可藉由選擇適當的閘極電極90的材料,使得閘極電極90與障壁層(圖未示)之間形成蕭特基接觸。源極電極70、汲極電極80的材料可以選自鈦(Ti)、鋁(Al)或其組合,而閘極電極90的材料可以選自鎳(Ni)、金(Au)、鎢(W)、氮化鈦(TiN)或其組合,但並不以此為限。 In this embodiment, as mentioned above, the source electrode 70 , the drain electrode 80 and the gate electrode 90 are respectively formed above the nitride semiconductor epitaxial stack structure 500 , and are subsequently extended and electrically connected thereto. The source pad S70, the drain pad S80, and the gate pad S90 serve as terminal points for electrical connection with the outside. As shown in Figure 6B, in the side view of a power element unit E1, the source electrode 70 and the drain electrode 80 are respectively placed on both sides of the surface of the nitride semiconductor epitaxial stack structure 500, and the gate electrode 90 is located between the source electrode 70 and the drain electrode 80 . In this embodiment, the source electrode 70 and the drain electrode 80 can be made by selecting appropriate materials for the source electrode 70 and the drain electrode 80 and/or through processes (such as etching, thermal annealing, etc.). Ohmic contact is formed between the pole electrode 80 and the barrier layer 420 . Similarly, a Schottky contact can be formed between the gate electrode 90 and the barrier layer (not shown) by selecting an appropriate material of the gate electrode 90 . The material of the source electrode 70 and the drain electrode 80 can be selected from titanium (Ti), aluminum (Al) or a combination thereof, and the material of the gate electrode 90 can be selected from the group consisting of nickel (Ni), gold (Au), tungsten (W). ), titanium nitride (TiN) or a combination thereof, but is not limited to this.

在其他實施例中,功率元件S的氮化物半導體磊晶疊層結構500,亦可以本揭露其他實施例中的氮化物半導體磊晶疊層結構所取代或部份取代其緩衝結構部分的結構。 In other embodiments, the nitride semiconductor epitaxial stacked structure 500 of the power device S can also be replaced or partially replaced with the buffer structure part by the nitride semiconductor epitaxial stacked structure in other embodiments of the present disclosure.

請參考第8圖所示為本揭露第七實施例之一蕭特基二極體元件單元E2的側視示意圖。蕭特基二極體元件單元E2為採用本揭露第六實施例中的氮化物半導體磊晶疊層500製作而成。本結構於氮化物半導體磊晶疊層500的上表面之上分別形成一陽極A與一陰極C以作為與外部電性連接的端點。其中陽極A與陰極C可分別置於磊晶疊層500上表面之上的兩側,可以藉由選擇適當的陽極A與陰極C的材料,以及/或者藉由製程(如,蝕刻,熱退火)以使陽極A與陰極C和阻障層之間形成歐姆接觸。陽極A與陰極C的材料可以選自鈦(Ti)、鋁(Al)或其組成。 Please refer to FIG. 8 , which is a schematic side view of the Schottky diode unit E2 according to the seventh embodiment of the present disclosure. The Schottky diode element unit E2 is manufactured using the nitride semiconductor epitaxial stack 500 in the sixth embodiment of the present disclosure. In this structure, an anode A and a cathode C are respectively formed on the upper surface of the nitride semiconductor epitaxial layer 500 as terminal points for electrical connection with the outside. The anode A and the cathode C can be placed on both sides of the upper surface of the epitaxial layer 500 respectively, by selecting appropriate materials of the anode A and cathode C, and/or by processing (such as etching, thermal annealing) ) to form ohmic contact between anode A and cathode C and the barrier layer. The materials of anode A and cathode C can be selected from titanium (Ti), aluminum (Al) or their compositions.

相似地,還可以形成如一介電層60’於氮化物半導體磊晶疊層500的上表面之上,其形成步驟可在形成陽極A與陰極C之前或之後。介電層60’能進一步降低表面漏電流,提高元件可靠度。介電層60’可以是氧化物或者氮化物,例如是氧化矽或氧化鋁等氧化物,也可以是氮化矽或氮化鋁等氮化物。然而本發明不以此為限,於其他實施例中亦可不形成介電層。 Similarly, a dielectric layer 60' may also be formed on the upper surface of the nitride semiconductor epitaxial stack 500, and the forming step may be before or after forming the anode A and cathode C. The dielectric layer 60' can further reduce surface leakage current and improve component reliability. The dielectric layer 60' may be an oxide or a nitride, such as an oxide such as silicon oxide or aluminum oxide, or a nitride such as silicon nitride or aluminum nitride. However, the present invention is not limited to this, and the dielectric layer may not be formed in other embodiments.

最後,請參考第9A-9B圖及第10A-10B圖,第9A-9B圖分別表示採用習知氮化物半導體磊晶疊層結構100製成之功率元件測試單元E3及以本揭露第一實施例之氮化物半導體磊晶疊層結構200製成之功率元件測試單元E4之水平漏電能力的電性測試結果圖。 Finally, please refer to Figures 9A-9B and Figures 10A-10B. Figures 9A-9B respectively show the power device test unit E3 made by using the conventional nitride semiconductor epitaxial stack structure 100 and the first implementation of the present disclosure. For example, the electrical test results of the horizontal leakage capability of the power device test unit E4 made of the nitride semiconductor epitaxial stack structure 200 are shown.

功率元件測試單元E3及E4係經由製程,分別在一習知氮化物半導體磊晶片及一本揭露第一實施例之氮化物半導體磊晶片(圖未示)上形成有複數個前述的功率元件測試單元E3,E4,並依半導體磊晶片中心、周圍、外側三個區域畫分該些區域的功率元件測試單元,並分別對該些區域複數個功率元件測試單元E3,E4進行電性測試。如第9A-9B圖所示,在對該些區域的功率元件的電性特性做代表性量測,由其電性測試結果可分別在9A、9B圖中得到三條不同的電性測試結果趨勢線。第10A及10B圖所繪示的分別是功率元件測試單元E3及E4的側視示意圖,其中,功率元件測試單元的製備是在半導體磊晶片中定義出複數個功率元件測試單元,分別將各單元中磊晶完成的氮化物半導體磊晶疊層結構100、200,包含通道層410、障壁層152、420、及帽層510的中央部分去除後,再分別在左右兩側未去除的半導體磊晶疊層結構表面形成歐姆電極O1~O4。 The power device test units E3 and E4 are formed with a plurality of the aforementioned power device test units on a conventional nitride semiconductor epitaxial wafer and a nitride semiconductor epitaxial wafer (not shown) according to the disclosed first embodiment respectively through a manufacturing process. Units E3 and E4 are divided into power component test units in these areas according to the three areas of the center, periphery, and outside of the semiconductor epitaxial wafer, and electrical tests are performed on a plurality of power component test units E3 and E4 in these areas. As shown in Figures 9A-9B, after making representative measurements of the electrical characteristics of the power components in these areas, three different electrical test result trends can be obtained from the electrical test results in Figures 9A and 9B respectively. String. Figures 10A and 10B show schematic side views of the power component test units E3 and E4 respectively. The power component test unit is prepared by defining a plurality of power component test units in the semiconductor epitaxial wafer, and each unit is The nitride semiconductor epitaxial stacked structures 100 and 200 completed by mid-epitaxial epitaxy, including the channel layer 410, the barrier layer 152, 420, and the central part of the cap layer 510 are removed, and then the semiconductor epitaxial layers that have not been removed on the left and right sides are removed. Ohmic electrodes O1~O4 are formed on the surface of the stacked structure.

測試條件為設定左側的歐姆電極O1及O3為接地狀態(Ground,0V),並對另一側的歐姆電極O2及O4施加相對應的逆向偏壓,如第9A-9B圖橫座標所示,逆向偏壓V=0~-1000伏特,以測試功率元件測試單元E3及E4在緩衝結構部分的漏電流(I,單位為毫安培),如第9A-9B圖之縱坐標所示。由第9A-9B圖中可以發現,功率元件測試單元E3之漏電流在施加相對應偏壓-600伏特時大約為1×10-6毫安培,相較於功率元件測試單元E4之漏電流在施加相對應偏壓-600伏特時則大約為5×10-7毫安培來得高,在其它的逆向偏壓下亦可獲得相似的趨勢,功率元件測試單元E4較E3,其漏電流的狀況下降大約0.5~1個級數。 The test conditions are to set the ohmic electrodes O1 and O3 on the left side to the ground state (Ground, 0V), and apply the corresponding reverse bias voltage to the ohmic electrodes O2 and O4 on the other side, as shown on the abscissa in Figure 9A-9B. The reverse bias voltage V=0~-1000 volts is used to test the leakage current (I, in milliamps) of the power component test units E3 and E4 in the buffer structure part, as shown on the ordinate in Figure 9A-9B. It can be found from Figures 9A-9B that the leakage current of the power component test unit E3 is approximately 1×10 -6 mA when the corresponding bias voltage -600 volts is applied. Compared with the leakage current of the power component test unit E4, When the corresponding bias voltage -600 volts is applied, it is about 5×10 -7 milliamps. A similar trend can be obtained under other reverse bias voltages. The leakage current of power component test unit E4 is lower than that of E3. About 0.5~1 series.

藉由本揭露精神的實施方式,可以形成結晶缺陷密度低、磊晶層表面平整、表面裂紋較少及/或較小之高品質氮化物半導體磊晶疊層結構,經由此氮化物半導體磊晶疊層結構所製造之元件,如功率元件、蕭特基二極體元件,也會因半導體磊晶疊層結構之品質改善而使元件之性能獲得改善,具有產業利用性。以上所述之實施例僅係為說明本揭露之技術思想及特點,其目的在使熟習此項技藝之人士能夠瞭解本揭露之內容並據以實施,當不能以之限定本揭露之專利範圍,即大凡依本揭露所揭示之精神所作之均等變化或修飾,仍應涵蓋在本揭露之專利範圍內。 Through the implementation of the spirit of the present disclosure, a high-quality nitride semiconductor epitaxial stack structure with low crystal defect density, smooth epitaxial layer surface, fewer and/or smaller surface cracks can be formed, and through this nitride semiconductor epitaxial stack structure Components manufactured with a layered structure, such as power components and Schottky diode components, will also have improved component performance due to the improvement in the quality of the semiconductor epitaxial laminated structure, and have industrial applicability. The above-described embodiments are only for illustrating the technical ideas and features of the present disclosure. Their purpose is to enable those skilled in the art to understand the contents of the present disclosure and implement them accordingly. They should not be used to limit the patent scope of the present disclosure. That is to say, all equivalent changes or modifications made in accordance with the spirit of the disclosure should still be covered by the patent scope of the disclosure.

200:氮化物半導體磊晶疊層結構 200:Nitride semiconductor epitaxial stack structure

210:基板 210:Substrate

220:氮化鋁成核層 220: Aluminum nitride nucleation layer

300:緩衝結構 300: Buffer structure

310:第一超晶格磊晶結構 310: The first superlattice epitaxial structure

320:第一氮化鎵系厚層 320: The first gallium nitride series thick layer

330:第二超晶格磊晶結構 330: Second superlattice epitaxial structure

340:第二氮化鎵系厚層 340: Second gallium nitride series thick layer

400:元件功能結構 400: Component functional structure

410:通道層 410: Channel layer

420:障壁層 420: Barrier layer

510:帽層 510: Cap layer

Claims (10)

一種氮化物半導體磊晶疊層結構,包含:一矽基板;一含鋁成核層,配置於該矽基板上;一緩衝結構,配置於該含鋁成核層上,依序包含:一第一超晶格磊晶結構;一第一氮化鎵系層,配置於該第一超晶格磊晶結構上;以及一第二超晶格磊晶結構,配置於該第一氮化鎵系層上;一通道層,配置於於該緩衝結構上;以及一障壁層,配置該通道層上;其中,該第一超晶格磊晶結構包含一第一平均鋁組成比例,該第一平均鋁組成比例大於0且小於或等於1,該第一氮化鎵系層包含一第一鋁組成比例,該第一鋁組成比例大於0且小於或等於1,該第二超晶格磊晶結構包含一第二平均鋁組成比例,該第二平均鋁組成比例大於或等於0且小於1,該含鋁成核層的鋁組成比例大於0且小於或等於1;其中,該含鋁成核層的鋁組成比例≧該第一平均鋁組成比例≧該第一鋁組成比例>該第二平均鋁組成比例。 A nitride semiconductor epitaxial stack structure includes: a silicon substrate; an aluminum-containing nucleation layer disposed on the silicon substrate; a buffer structure disposed on the aluminum-containing nucleation layer, including in sequence: a first a superlattice epitaxial structure; a first gallium nitride system layer disposed on the first superlattice epitaxial structure; and a second superlattice epitaxial structure disposed on the first gallium nitride system layer; a channel layer disposed on the buffer structure; and a barrier layer disposed on the channel layer; wherein the first superlattice epitaxial structure includes a first average aluminum composition ratio, the first average The aluminum composition ratio is greater than 0 and less than or equal to 1, the first gallium nitride layer includes a first aluminum composition ratio, the first aluminum composition ratio is greater than 0 and less than or equal to 1, the second superlattice epitaxial structure Contains a second average aluminum composition ratio, the second average aluminum composition ratio is greater than or equal to 0 and less than 1, the aluminum composition ratio of the aluminum-containing nucleation layer is greater than 0 and less than or equal to 1; wherein, the aluminum-containing nucleation layer The aluminum composition ratio≧the first average aluminum composition ratio≧the first aluminum composition ratio>the second average aluminum composition ratio. 如申請專利範圍第1項所述之氮化物半導體磊晶疊層結構,其中,該第一超晶格磊晶結構由複數氮化鋁超晶格層及複數氮化鋁鎵超晶格層交互堆疊;其中,該第二超晶格磊晶結構由複數氮化鋁鎵超晶格層及複數氮化鎵超晶格層交互堆疊。 The nitride semiconductor epitaxial stack structure described in item 1 of the patent application, wherein the first superlattice epitaxial structure consists of a plurality of aluminum nitride superlattice layers and a plurality of aluminum gallium nitride superlattice layers alternately Stacking; wherein, the second superlattice epitaxial structure consists of a plurality of aluminum gallium nitride superlattice layers and a plurality of gallium nitride superlattice layers alternately stacked. 如申請專利範圍第1項所述之氮化物半導體磊晶疊層,其中,該通道層為氮化鎵層,且該障壁層為氮化鋁鎵層。 For the nitride semiconductor epitaxial stack described in claim 1, the channel layer is a gallium nitride layer, and the barrier layer is an aluminum gallium nitride layer. 如申請專利範圍第1項所述之氮化物半導體磊晶疊層結構,其中,更包含一氮化鋁鎵後障壁層位於該通道層與該緩衝結構之間。 The nitride semiconductor epitaxial stack structure described in claim 1 of the patent application further includes an aluminum gallium nitride rear barrier layer located between the channel layer and the buffer structure. 如申請專利範圍第1項所述之氮化物半導體磊晶疊層結構,其中,更包含一第二氮化鎵系層配置於該第二超晶格磊晶結構上,該第二氮化鎵系層包含一第二鋁組成比例,該第二鋁組成比例大於或等於0且小於1,該第一鋁組成比例大於該第二鋁組成比例。 The nitride semiconductor epitaxial stacked structure described in item 1 of the patent application further includes a second gallium nitride series layer disposed on the second superlattice epitaxial structure, and the second gallium nitride The system layer includes a second aluminum composition ratio, the second aluminum composition ratio is greater than or equal to 0 and less than 1, and the first aluminum composition ratio is greater than the second aluminum composition ratio. 如申請專利範圍第5項所述之氮化物半導體磊晶疊層結構,其中,該第一氮化鎵系層及/或該第二氮化鎵系層中分別包含有一摻雜物。 In the nitride semiconductor epitaxial stack structure described in claim 5, the first gallium nitride layer and/or the second gallium nitride layer respectively include a dopant. 如申請專利範圍第1項所述之氮化物半導體磊晶疊層結構,其中,該第一超晶格磊晶結構及/或該第二超晶格磊晶結構中分別包含有一摻雜物。 The nitride semiconductor epitaxial stack structure described in claim 1, wherein the first superlattice epitaxial structure and/or the second superlattice epitaxial structure each contains a dopant. 如申請專利範圍第6項或第7項所述之氮化物半導體磊晶疊層結構,其中,該摻雜物包含鐵或碳至少其中之一。 For the nitride semiconductor epitaxial stack structure described in item 6 or 7 of the patent application, the dopant includes at least one of iron or carbon. 如申請專利範圍第1項所述之氮化物半導體磊晶疊層結構,其中,該第一氮化鎵系層的厚度大於1000奈米。 In the nitride semiconductor epitaxial stack structure described in claim 1, the thickness of the first gallium nitride layer is greater than 1000 nanometers. 一種功率元件,包含:一如申請專利範圍第1~9項中任一項所述的氮化物半導體磊晶疊層結構;及一源極電極、一閘極電極、及一汲極電極,或一陰極及一陽極分別配置於該氮化物半導體磊晶疊層結構上;其中,該閘極電極位於該源極電極及該汲極電極之間。 A power component, including: a nitride semiconductor epitaxial stack structure as described in any one of items 1 to 9 of the patent application; and a source electrode, a gate electrode, and a drain electrode, or A cathode and an anode are respectively disposed on the nitride semiconductor epitaxial stack structure; wherein the gate electrode is located between the source electrode and the drain electrode.
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