TWI832662B - Display driving voltage offset compensation method, driving chip and display - Google Patents

Abstract

A display driving voltage offset compensation method is implemented by a driving circuit, which includes: receiving a set of pixel array structure description data from a timing control unit; and determining multiple output channels in each column according to the set of pixel array structure description data. The offset value of the output voltage during the scan.

Description

Display driving voltage offset compensation method, driving chip and display

The present invention relates to a display, and in particular to a driving voltage offset compensation method for a display.

When a driver chip is used to drive a display panel, since the output amplifier of the driver chip will have an offset voltage, the display panel will show alternating light and dark stripes.

In order to solve the above problem, a common approach is to make the amplifier alternately output positive and negative offset voltages to eliminate the aforementioned bright and dark stripes through the effect of brightness averaging. Please refer to FIGS. 1a and 1b together, wherein FIG. 1a shows an amplifier 11 that outputs a negative offset voltage -V _ABS ; and FIG. 1b shows an amplifier 12 that outputs a positive offset voltage +V _ABS .

In addition, in order to support different panel architectures or a specific polarity change driving mode, a common approach is to burn control code into a driver chip so that the driver chip can generate an amplifier offset voltage modulation mode according to the control code. .

However, since the above method requires a burning operation, it still has inconvenience.

In order to solve the above problems, a novel display driving voltage offset compensation method is urgently needed in this field.

One object of the present invention is to disclose a display driving voltage offset compensation method, which enables a driving circuit to determine the offset of the output voltage of its multiple output channels during each column scanning period based on a set of pixel array structure description data received. value to minimize the average brightness deviation of a pixel array corresponding to the set of pixel array structure description data, thereby preventing the pixel array from producing an abnormal display.

Another object of the present invention is to disclose a driving chip that can minimize the average brightness deviation of a pixel array corresponding to the set of pixel array structure description data according to the received set of pixel array structure description data, thereby avoiding the The pixel array produces an abnormal display.

Another object of the present invention is to disclose a display that can minimize the average brightness deviation of a pixel array based on the aforementioned driving chip, thereby preventing the pixel array from producing abnormal display images.

In order to achieve the above purpose, a display driving voltage offset compensation method is proposed, which is implemented by a driving circuit and includes: Receive a set of pixel array structure description data from a timing control unit; and The offset values of the output voltages of the multiple output channels during the scanning period of each column are determined according to the structural description data of the pixel array.

In one embodiment, the set of pixel array structure description data includes describing a connection type between a plurality of pixel elements and a plurality of column signal lines and a plurality of row signal lines in a basic pixel combination.

In one embodiment, the offset value includes a positive offset value and a negative offset value.

In one embodiment, each of the output channels includes an amplification circuit and an offset switching circuit to generate the positive offset value and the negative offset value of the output voltage, and the positive offset value The nominal size is the same as the nominal size for the negative offset value.

To achieve the above object, the present invention further proposes a driving chip having a control unit to execute a display driving voltage offset compensation program, which includes: Receive a set of pixel array structure description data from a timing control unit; and The offset values of the output voltages of the multiple output channels during the scanning period of each column are determined according to the structural description data of the pixel array.

In one embodiment, the set of pixel array structure description data includes describing a connection type between a plurality of pixel elements and a plurality of column signal lines and a plurality of row signal lines in a basic pixel combination.

In one embodiment, the offset value includes a positive offset value and a negative offset value.

In one embodiment, each of the output channels includes an amplification circuit and an offset switching circuit to generate the positive offset value and the negative offset value of the output voltage, and the positive offset value The nominal size is the same as the nominal size for the negative offset value.

To achieve the above object, the present invention further proposes a display having a driving circuit and a pixel array, wherein the driving circuit is used to drive the pixel array, and the driving circuit has a control unit to perform a display driving voltage bias. The compensation procedure includes: Receive a set of pixel array structure description data from a timing control unit; and The offset values of the output voltages of the multiple output channels during the scanning period of each column are determined according to the structural description data of the pixel array.

In one embodiment, the set of pixel array structure description data includes describing a connection type between a plurality of pixel elements and a plurality of column signal lines and a plurality of row signal lines in a basic pixel combination of the pixel array.

In one embodiment, the offset value includes a positive offset value and a negative offset value.

In one embodiment, each of the output channels includes an amplification circuit and an offset switching circuit to generate the positive offset value and the negative offset value of the output voltage, and the positive offset value The nominal size is the same as the nominal size for the negative offset value.

In order to enable the review committee to further understand the structure, characteristics and purpose of the present invention, drawings and detailed descriptions of preferred embodiments are attached as follows.

The principle of the present invention is: (1) Use a timing control unit to transmit a set of description data representing the pixel array structure of a display panel to a driving circuit, so that the driving circuit can learn the pixel array structure of the display panel it wants to drive; and (2) The driving circuit determines the offset values of the output voltages of its multiple output channels during the scanning period of each column according to the structural description data of the pixel array, so as to bias the brightness of the pixel array in a complementary or mutually canceling manner. The moving average can be minimized to avoid the pixel array from producing abnormal display images, such as a display image with bright and dark stripes (or forehead wrinkles).

In terms of possible embodiments, the timing control unit and the driving circuit may be independent chips or integrated into one chip. In addition, the timing control unit may be located in a display or not belong to a display, that is, the display may include the timing control unit or not include the timing control unit. In addition, the timing control unit can send the set of description data when the computer is turned on, or send the set of description data during a scanning interval, such as a black screen period.

Please refer to Figures 2a to 2c, which illustrate three pixel array structures with a basic pixel combination of 4 columns*4 rows, in which 21 represents red pixels, 22 represents green pixels, 23 represents blue pixels, and 31 to 34 represent column driving lines. , 41 to 44 represent row drive lines. In addition, each set of description data representing the structure of each pixel array may include three parts: data describing the connection relationship of red pixels; making each of the four columns of pixels display bright and dark differently from the pixels in its adjacent columns. The data; and the data that makes each pixel in the four columns of pixels display light and dark differently from its adjacent pixels. Please refer to Tables 1 to 3 together. Table 1 records an example of a set of description data representing the basic pixel combinations of the pixel array structure of Figure 2a; Table 2 records one of the basic pixel combinations representing the pixel array structure of Figure 2b. Example content of a set of description data; and Table 3 records an example content of a set of description data representing the basic pixel combination of the pixel array structure of FIG. 2c. Table 1 Line 1 Line 2 Line 3 Line 4 Red pixel connection relationship Column 1 FF 00 00 FF Column 2 FF 00 00 FF Column 3 FF 00 00 FF Column 4 FF 00 00 FF Column pixels are bright and dark. Column 1 FF 00 00 FF Column 2 FF 00 00 FF Column 3 FF 00 00 FF Column 4 FF 00 00 FF Adjacent pixels light up and darken differently from each other Column 1 FF 00 00 FF Column 2 FF 00 00 FF Column 3 FF 00 00 FF Column 4 FF 00 00 FF Table 2 Line 1 Line 2 Line 3 Line 4 Red pixel connection relationship Column 1 FF 00 00 FF Column 2 00 FF 00 00 Column 3 FF 00 00 FF Column 4 00 FF 00 00 Column pixels are bright and dark. Column 1 FF FF FF FF Column 2 00 00 00 00 Column 3 FF FF FF FF Column 4 00 00 00 00 Adjacent pixels light up and darken differently from each other Column 1 FF 00 FF 00 Column 2 FF 00 FF 00 Column 3 FF 00 FF 00 Column 4 FF 00 FF 00 table 3 Line 1 Line 2 Line 3 Line 4 Red pixel connection relationship Column 1 FF 00 00 FF Column 2 00 FF 00 00 Column 3 FF 00 00 FF Column 4 00 FF 00 00 Column pixels are bright and dark. Column 1 FF FF FF FF Column 2 FF FF FF FF Column 3 00 00 00 00 Column 4 00 00 00 00 Adjacent pixels light up and darken differently from each other Column 1 FF FF FF FF Column 2 00 00 00 00 Column 3 00 00 00 00 Column 4 FF FF FF FF

That is, the set of description data contained in Table 1 includes: {(FF, 00, 00, FF), (FF, 00, 00, FF), (FF, 00, 00, FF), (FF, 00, 00, FF)}, {(FF, FF, FF, FF), (00, 00, 00, 00), (FF, FF, FF, FF), (00, 00, 00, 00)} and {( FF, 00, 00, FF), (00, FF, 00, FF), ( FF, 00, 00, FF), (00, FF, 00, FF)}; the group of description information contained in Table 2 includes : {(FF, 00, 00, FF), (00, FF, 00, 00), (FF, 00, 00, FF), (00, FF, 00, 00)}, {(FF, FF, FF , FF), (00, 00, 00, 00), (FF, FF, FF, FF), (00, 00, 00, 00)} and {( FF, 00, FF, 00), ( FF, 00 , FF, 00), ( FF, 00, FF, 00), ( FF, 00, FF, 00)}; the set of description information contained in Table 3 includes: { (FF, 00, 00, FF), ( 00, FF, 00, 00), (FF, 00, 00, FF), (00, FF, 00, 00)}, {(FF, FF, FF, FF), (FF, FF, FF, FF) , (00, 00, 00, 00), (00, 00, 00, 00)} and {(FF, FF, FF, FF), (00, 00, 00, 00), (00, 00, 00, 00), (FF, FF, FF, FF)}.

After receiving the set of description data listed in Table 1, the driving circuit will sequentially generate positive, negative, positive and negative output offset voltages during the scanning period of columns 1 to 4; after receiving the set of description data listed in Table 2 After receiving the set of description data, positive, negative, negative, and positive output offset voltages will be generated sequentially during the scanning period of columns 1 to 4; and after receiving the set of description data shown in Table 3, it will The scanning period of columns 1 to 4 generates positive, positive, negative, and negative output offset voltages in sequence.

It is worth mentioning that although the present invention uses 00 and FF to represent dark and bright in the above examples, the present invention is not limited to this, and other numbers can also be used to represent dark and bright. In addition, the basic pixel combination of the present invention is not limited to 4 columns*4 rows. In addition, in possible alternative embodiments, the present invention can also assign a code to each of various common pixel array structures, so that when the driver circuit receives a code, it can generate an output voltage correspondingly during each column scanning period. offset value.

Please refer to FIG. 3 , which is a block diagram of an embodiment of the display of the present invention. As shown in Figure 3, a display 100 has a timing control unit 110, a driving circuit 120 and a pixel array 130. The display 100 can be a liquid crystal display, a micro-LED display, a sub-millimeter LED display, Quantum dot light emitting diode displays or organic light emitting diode displays. In addition, although the timing control unit 110 is included in the display 100 in this embodiment, the display 100 may not include the timing control unit 110 .

The timing control unit 110 is used to provide a set of pixel array structure description data D _DES to the driving circuit 120 .

The driving circuit 120 is used to drive the pixel array 130, and the driving circuit 120 has a control unit 121 to execute a display driving voltage offset compensation process. The process includes: (1) receiving a set of pixel array structure descriptions from the timing control unit 110 Data D _DES ; and (2) determining the offset value of the output voltage of the plurality of output channels 122 during each column scanning period according to the group of pixel array structure description data D _DES .

In a possible alternative embodiment, the set of pixel array structure description data D _DES may include describing a connection type between a plurality of pixel elements and a plurality of column signal lines and a plurality of row signal lines in a basic pixel combination of the pixel array 130 state.

In addition, the offset value includes a positive offset value and a negative offset value.

In a possible embodiment, each output channel 122 may include an amplification circuit and an offset switching circuit to generate the positive offset value and the negative offset value of the output voltage, and the positive offset The nominal size of the value is the same as the nominal size of the negative offset value. Please refer to FIG. 4 , which illustrates a circuit diagram of an embodiment of the output stage of the output channel 122 . As shown in Figure 4, the output stage includes an amplification circuit 122a and an offset switching circuit 122b. During operation, the offset switching circuit 122b determines the polarity of the offset voltage according to a switching signal SW to generate the positive offset value and the negative offset value of the output voltage V _OUT .

As can be seen from the above description, the present invention discloses a display driving voltage offset compensation method. Please refer to FIG. 5 , which illustrates a flow chart of an embodiment of a display driving voltage offset compensation method of the present invention. The method is implemented by a driving circuit. As shown in Figure 5, the method includes: receiving a set of pixel array structure description data from a timing control unit (step a); and determining the output voltages of multiple output channels during each column scanning period based on the set of pixel array structure description data. offset value (step b).

In the above steps, the set of pixel array structure description data may include describing a connection type between a plurality of pixel elements and a plurality of column signal lines and a plurality of row signal lines in a basic pixel combination; the offset value includes a positive offset value and a negative offset value; and each of the output channels may include an amplification circuit and an offset switching circuit to generate the positive offset value and the negative offset value of the output voltage, and The nominal size of the positive offset value is the same as the nominal size of the negative offset value.

Through the design disclosed above, the present invention has the following advantages: 1. The display driving voltage offset compensation method of the present invention can enable a driving chip to determine the offset value of the output voltage of its multiple output channels during each column scanning period based on a set of pixel array structure description data received, so as to minimize The average value of the brightness deviation of a pixel array corresponding to the set of pixel array structure description data is used to prevent the pixel array from producing an abnormal display screen. 2. The driver chip of the present invention can minimize the average brightness deviation of a pixel array corresponding to the set of pixel array structure description data received according to the received set of pixel array structure description data, thereby preventing the pixel array from producing abnormal display. That is, the driver chip of the present invention can adaptively generate different output voltage offset value combinations by receiving the set of pixel array structure description data, so that various pixel array structures can present good picture displays. 3. The display of the present invention can use the aforementioned driving chip to minimize the average brightness deviation of a pixel array, thereby preventing the pixel array from producing abnormal display images.

What is disclosed in this case is a preferred embodiment. Any partial changes or modifications derived from the technical ideas of this case and easily inferred by those familiar with the art will not deviate from the scope of the patent rights of this case.

To sum up, regardless of the purpose, means and effects of this case, it shows that it is completely different from the conventional technology, and that the invention is practical first, and indeed meets the patent requirements for inventions. I sincerely ask the review committee to take a clear look and grant the patent as soon as possible for your benefit. Society is a prayer for the Supreme Being.

11:Amplifier 12:Amplifier 21: red pixels 22: Green pixels 23: blue pixels 31: Column driver line 32: Column driver line 33: Column driver line 34: Column driver line 41: Row drive line 42: Row drive line 43: Row drive line 44: Row drive line 100:Display 110: Timing control unit 120:Drive circuit 121:Control unit 122:Output channel 122a: Amplification circuit 122b: Offset switching circuit 130:Pixel array Step a: Receive a set of pixel array structure description data from a timing control unit. Step b: Determine the offset values of the output voltages of the multiple output channels during the scanning period of each column according to the structural description data of the pixel array.

Figure 1a shows an amplifier outputting a negative offset voltage. Figure 1b shows an amplifier outputting a positive offset voltage. Figures 2a to 2c illustrate three pixel array structures with a basic pixel combination of 4 columns*4 rows. FIG. 3 is a block diagram of a display according to an embodiment of the present invention. FIG. 4 is a circuit diagram of an embodiment of an output stage of an output channel of the display driving circuit of FIG. 3 . FIG. 5 is a flowchart of an embodiment of a display driving voltage offset compensation method of the present invention.

Step a: Receive a set of pixel array structure description data from a timing control unit

Step b: Determine the offset values of the output voltages of the multiple output channels during the scanning period of each column based on the pixel array structure description data of the group of pixels

Claims (10)

A display driving voltage offset compensation method is implemented by a driving circuit, which includes: receiving a set of pixel array structure description data from a timing control unit; and determining multiple output channels in each column according to the set of pixel array structure description data. The offset value of the output voltage during scanning; wherein, the set of pixel array structure description data includes a description of a connection type between a plurality of pixel elements and a plurality of column signal lines and a plurality of row signal lines in a basic pixel combination. In the display driving voltage offset compensation method described in item 1 of the patent application, the offset value includes a positive offset value and a negative offset value. The display driving voltage offset compensation method described in item 2 of the patent application, wherein each output channel includes an amplification circuit and an offset switching circuit to generate the positive offset value of the output voltage and the the negative offset value, and the nominal size of the positive offset value is the same as the nominal size of the negative offset value. A driving chip has a control unit to execute a display driving voltage offset compensation program. The program includes: receiving a set of pixel array structure description data from a timing control unit; and determining multiple outputs based on the set of pixel array structure description data. The offset value of the output voltage of the channel during the scanning period of each column; wherein, the set of pixel array structural description data includes a description of the connection between multiple pixel elements in a basic pixel combination and one of multiple column signal lines and multiple row signal lines type. For the driving chip described in claim 4 of the patent application, the offset value includes a positive offset value and a negative offset value. The driving chip as described in item 5 of the patent application, wherein each output channel includes an amplification circuit and an offset switching circuit to generate the positive offset value and the negative offset value of the output voltage. , and the rated size of the positive offset value is the same as the rated size of the negative offset value. A display has a drive circuit and a pixel array, wherein the drive circuit is used to drive the pixel array, and the drive circuit has a control unit to execute a display drive voltage offset compensation process, the process includes: automatically A timing control unit receives a set of pixel array structure description data; and determines the offset values of the output voltages of multiple output channels during each column scanning period according to the set of pixel array structure description data; wherein the set of pixel array structure description data includes Describes a connection type between a plurality of pixel elements and a plurality of column signal lines and a plurality of row signal lines in a basic pixel combination. For the display described in Item 7 of the patent application, the offset value includes a positive offset value and a negative offset value. The display as described in item 8 of the patent application, wherein each output channel includes an amplification circuit and an offset switching circuit to generate the positive offset value and the negative offset value of the output voltage, And the rated size of the positive offset value is the same as the rated size of the negative offset value. The display as described in any one of items 7 to 9 of the patent application scope is composed of a liquid crystal display, a micro-light-emitting diode display, a sub-millimeter light-emitting diode display, a quantum dot light-emitting diode display and an organic light-emitting diode display. A display selected from a group of polar body displays.

Images