TWI832154B - Memory device - Google Patents

Abstract

A memory device includes a memory cell array, a data accessing circuit, a data bus inversion calculator, a multiplexer and an output result judging circuit. The data accessing circuit performs a data write-in operation or a data read-out operation on the memory cell array. Wherein, the data accessing circuit reads a read-out data from the memory cell array. The data bus inversion calculator generates an inversion indication data according to the read-out data. The multiplexer outputs the inversion indication data or a test data according to a mode signal. The output result judging circuit compares the read-out data with the inversion indication data or the test data to generate an output information.

Description

memory device

The present invention relates to a memory device, and in particular to a memory device with a built-in self-test (BIST) function.

In memory devices, a Data Bus Inversion (DBI) mechanism is often set up to reduce the need for data to be transferred in the bus, thereby reducing power consumption and noise on the bus. On the other hand, in memory devices, it is a necessary requirement to set up a built-in self-test function.

Under the above premise, conventional memory devices need to be equipped with hardware circuits for data reversal to cope with the data bus reversal mechanism, and also need to be equipped with built-in self-test function for error bit detection actions. related circuits. As a result, a certain number of circuits are required on the data readout path in the conventional memory device. In addition to consuming circuit layout area, it also consumes excess power and creates an excessive load on the data readout path, reducing the data readout performance of the memory device.

The present invention provides a memory device that can simplify the circuit required in the built-in self-test function.

The memory device of the present invention includes a memory cell array, a data access circuit, a data bus inversion calculator, a multiplexer and an output result judgment circuit. The data access circuit is coupled to the memory cell array and performs a data writing operation or a data reading operation on the memory cell array. Among them, the data reading action is to read data from the memory cell array. The data bus reversal calculator is coupled to the data access circuit for receiving read data and generating reversal indication data based on the read data. The multiplexer receives reversal indication data and test data, and outputs reversal indication data or test data according to the mode signal. The output result judgment circuit is coupled to the multiplexer to perform operations on the read data and the inverted instruction data or test data to generate output information.

Based on the above, the memory device of the present invention outputs reversal instruction data or test data to the output result judgment circuit through the multiplexer in different operating modes. The output result judgment circuit can correspond to different operating modes to generate final read data or error bit information. In this way, the memory device of the present invention does not need to configure redundant test result judgment circuits for the built-in self-test function, effectively reducing the load on the write path in the memory device and reducing the area required for circuit layout.

Referring to FIG. 1 , the memory device 100 includes a data bus inversion calculator 110 , a multiplexer 120 , an output result determination circuit 130 , a data access circuit 140 and a memory cell array 150 . Data access circuit 140 is coupled to memory cell array 150 . The data access circuit 140 is used to perform data writing operations on the memory cell array 150 according to the writing data WDATA. Alternatively, the data access circuit 140 may perform a data read operation on the memory cell array 150 to obtain the read data RDATA.

In detail, when performing the data writing operation, the data access circuit 140 can generate the writing data WDATA based on the test data TDATA or the external input data EID, and write the writing data WDATA into one of the memory cell arrays 150 or multiple selected memory cells. Among them, the data access circuit 140 selects the external input data EID to perform the data writing operation in the normal mode. In the test mode, the data access circuit 140 selects the test data TDATA to perform the data writing operation.

In addition, when performing a data reading operation, the data access circuit 140 can obtain the read data RDATA by sensing signals on the bit lines of one or more selected memory cells in the memory cell array 150 .

Data bus reversal calculator 110 is coupled to data access circuit 140 . In the normal mode, when performing a data read operation, the data bus inversion calculator 110 can receive the read data RDATA, and calculate the number of bits that are the first logical value among the multiple bits of the read data RDATA. quantity. When the number of bits whose multiple bits in the read data RDATA are first logic values is greater than the preset reference value, the data bus inversion calculator 110 generates enabled inversion indication data DBI. The first logical value can be a logical value 0 or also a logical value 1. The preset reference value can be half of the total number of bits of the read data RDATA.

The multiplexer 120 is coupled between the data bus inversion calculator 110 and the output result judgment circuit 130 . The multiplexer 120 can receive the test data TDATA and the reversal indication data DBI generated by the data bus reversal calculator 110 . The multiplexer 120 can output the inversion indication data DBI or the test data TDATA to the output result judgment circuit 130 according to the mode signal MD. When the mode signal MD indicates that the memory device 100 operates in the normal mode, the multiplexer 120 may output the inversion indication data DBI to the output result determination circuit 130 . In contrast, when the mode signal MD indicates that the memory device 100 operates in the test mode, the multiplexer 120 may output the test data TDATA to the output result determination circuit 130 .

The output result judgment circuit 130 is further coupled to the data access circuit 140 . The output result judgment circuit 130 receives the inversion instruction data DBI or the test data TDATA provided by the multiplexer 120, and receives the read data RDATA provided by the data access circuit 140. The output result judgment circuit 130 is used to make the read data RDATA and the inverted instruction data DBI perform operations, or to make the read data RDATA and the test data TDATA perform operations, and thereby generate output information. Among them, in the normal mode, the output result judgment circuit 130 is used to perform an inverse exclusive OR (XNOR) operation on the read data RDATA and the inversion instruction data DBI, and generate output information as the final read data ODATA. In the test mode, the output result judgment circuit 130 is used to perform an inverse OR operation on the read data RDATA and the test data TDATA, and generate output information as the error bit information EBI.

In terms of the overall operation details of the memory device 100, in the normal mode, when performing a data writing operation, the data access circuit 140 can generate write data WDATA according to the received external input data EID, and write data WDATA written into the memory cell array 150 . Please note here that the data access circuit 140 can judge multiple bits of the external input data EID in advance and generate the write data WDATA accordingly. For example, when the external input data EID has more bits with logic value 1 than bits with logic value 0, the data access circuit 140 can invert the external input data EID to generate write data WDATA. When the bits of the external input data EID with a logical value of 1 are no more than the bits with a logical value of 0, the data access circuit 140 can make the external input data EID equal to the write data WDATA. The above action is called the Data Bus Inversion (DBI) mechanism, which is used to improve the data writing efficiency of the memory and reduce power consumption.

In the normal mode data reading operation, the data access circuit 140 reads the read data RDATA from the memory cell array 150 . The read data RDATA is sent to the data bus inversion calculator 110 . The data bus inversion calculator 110 may generate inversion indication data DBI corresponding to the read data RDATA.

Then, in the normal mode, the read data RDATA and the corresponding reversal indication data DBI may be sent to the output result judgment circuit 130 . The output result judgment circuit 130 can generate the final read data ODATA according to the applied anti-mutex OR operation. Continuing the above example, when the inversion indication data DBI is a logic value 0, it means that there are more bits with a logic value 0 in the read data RDATA and needs to be inverted. Therefore, the output result judgment circuit 130 can perform an inverse exclusive OR operation on the inversion indication data DBI and the read data RDATA, and invert the read data RDATA to generate the final read data ODATA.

On the other hand, in the test mode, when performing a data writing operation, the data access circuit 140 can generate write data WDATA based on the received test data TDATA, and write the write data WDATA into the memory cell array 150 . In the data reading operation, the data access circuit 140 reads the data RDATA from the memory cell array 150 . The read data RDATA is sent to the output result judgment circuit 130. At this time, the data flow reversal calculator 110 stops working. The multiplexer 120 transmits the test data TDATA to the output result judgment circuit 130 according to the mode signal MD.

The output result judgment circuit 130 can compare the test data TDATA and the read data RDATA to generate a test result, and judge the error bit information EBI in the read data RDATA. Please note here that the output result judgment circuit 130 can also use an inverse OR operation to compare the test data TDATA and the read data RDATA. Users only need to reversely interpret the error bit information EBI to know which bits in the read data RDATA are error bits.

It can be seen from the above description that the output result judgment circuit 130 applies the same anti-mutex OR operation to generate the final read data ODATA or error bit information EBI whether in the normal mode or the test mode. In other words, the output result judgment circuit 130 does not need to configure different hardware circuits for the normal mode and the test mode, which effectively reduces the hardware requirements on the data readout path in the memory device 100 and can effectively reduce load on the data read path and improve the data access performance of the memory device 100 .

Referring to Figure 2, the memory device 200 includes a data bus inversion calculator 210, a multiplexer 220, an output result judgment circuit 230, a data access circuit 240, a memory cell array 250, a data input block 280, and a data output block. 2100 and test data register 290. The data input block 280 is coupled to the data access circuit 240 through the data writing path 260 and is used to provide external input data EID. The output result judgment circuit 230 is coupled to the data output block 2100 through the data readout path 270 . The data output block 2100 is used to output the final read data ODATA or error bit information EBI. The test data register 290 is coupled to the data writing path 260 and the multiplexer 220 and is used to provide test data TDATA.

In this embodiment, the test data register 290 is used to store relevant test data TDATA for executing the built-in self-test (Built-In Self-Test, BIST) action. When the built-in self-test mode is activated, test data TDATA is provided to the memory cell array 250 to perform test operations on the memory cell array 250 and its peripheral circuits.

The details of the operations of the data bus inversion calculator 210, the multiplexer 220, the output result judgment circuit 230 and the data access circuit 240 have been described in detail in the foregoing embodiments and will not be repeated here.

Regarding the hardware architecture, the memory cell array 250 may be a memory cell array of a dynamic random access memory. The data bus inversion calculator 210 can be implemented by a digital circuit and does not have a specific circuit structure. The data input block 280 and the data output block 270 may include one or more buffers and switches, which may be implemented using input interface circuits and output interface circuits well known to those skilled in the art. The multiplexer 220 can be implemented using a multiplexer circuit that is well known to those skilled in the art, without any specific limitation.

Regarding the hardware architecture of the output result judgment circuit 230 and the data access circuit 240, please refer to the implementation examples of FIG. 3 and FIG. 4 below.

Referring to FIG. 3 , the output result judgment circuit 300 includes a plurality of anti-mutual exclusive OR gates XNOR1 to XNORN. The first end of the anti-mutex OR gates XNOR1~XNORN receives multiple bits RDATA[1]~RDATA[N] of the read data respectively, and the second end of the anti-mutex OR gates Single bits TDATA[1]~TDATA[N] or multiple bits DBI[1]~DBI[N] of the inverted instruction data. Anti-mutex OR gates XNOR1 ~ .

Referring to FIG. 4 , the data access circuit 400 includes a sense amplifier 410 and a write data buffer 420 . The sense amplifier 410 can receive the external input data EID and convert the external input data EID into write data WDATA. The write data WDATA may be temporarily stored in the write data buffer 420 and provided to the memory cell array by the write data buffer 420 for data writing operations.

The sense amplifier 410 can also sense the bit line signal BLS on the memory cell array to obtain the read data RDATA.

In this embodiment, the sense amplifier 410 can be implemented using any form of sense amplification circuit that is well known to those skilled in the art, and there is no fixed limitation. The data buffer 420 can be a page buffer commonly used in memory devices, and is also not subject to specific limitations.

In summary, the output result judgment circuit provided in the memory device of the present invention uses the same hardware circuit to perform data bit inversion operations and test operations in different modes. In this way, the number of circuits on the data output path of the memory device of the present invention can be reduced, and the load on the data output path is also reduced simultaneously, which can improve the efficiency of the data reading operation of the memory device.

100, 200: Memory device 110, 210: Data flow reversal calculator 120, 220: multiplexer 130, 230, 300: Output result judgment circuit 140, 240, 400: Data access circuit 150, 250: Memory cell array 2100: Data output block 280: Data input block 290:Test data register 410: Sense amplifier 420: Write data buffer DBI: reversal instruction information EBI: Error bit information EBI[1]~EBI[N], ODATA[1]~ODATA[N], TDATA[1] ~ TDATA[N], RDATA[1] ~ RDATA[N]: bits EID: external input data MD: mode signal ODATA: final read data RDATA: read data TDATA: test data WDATA: write data XNOR1~XNORN: mutually exclusive or gate

FIG. 1 is a schematic diagram of a memory device according to an embodiment of the present invention. FIG. 2 is a block diagram of a memory device according to another embodiment of the invention. FIG. 3 is a schematic diagram of an implementation of an output result determination circuit in a memory device according to an embodiment of the present invention. FIG. 4 is a schematic diagram of an implementation of a data access circuit in a memory device according to an embodiment of the present invention.

100:Memory device

110: Data Flow Reversal Calculator

120:Multiplexer

130: Output result judgment circuit

140:Data access circuit

150:Memory cell array

DBI: reversal instruction information

EBI: Error bit information

EID: external input data

MD: mode signal

ODATA: final read data

RDATA: read data

TDATA: test data

WDATA: write data

Claims (10)

A memory device includes: a memory cell array; a data access circuit coupled to the memory cell array, performing a data writing operation or a data reading operation on the memory cell array, wherein the data reading operation is performed by The memory cell array reads out a readout data; a data bus reversal calculator is coupled to the data access circuit for receiving the readout data and generating a reversal indication data based on the readout data; a multiplexer that receives the reversal indication data and a test data, and outputs the reversal indication data and the test data respectively in different modes according to a mode signal; and an output result judgment circuit coupled to the multiplexer, The read data, in different modes, are calculated with the inverted instruction data and the test data through the same hardware to generate an output information, wherein the data flow inversion calculator calculates the read data There is a number of first logic values in the plurality of bits, and when the number is greater than a preset reference value, the enabled reversal indication data is generated. The memory device of claim 1, wherein the mode signal is used to indicate that the memory device operates in a normal mode or a test mode. The memory device of claim 2, wherein when the memory device operates in the test mode, the multiplexer selects to output the test data to the output The result judgment circuit, when the memory device operates in the normal mode, the multiplexer selects to output the inversion indication data to the output result judgment circuit. The memory device as claimed in claim 2, wherein in the normal mode, the output result judgment circuit causes the bits of the read data and the bits of the inversion indication data to perform anti-mutual exclusion or mutual exclusion respectively. Operation is performed to generate the output information as a final read data. When in the test mode, the output result judgment circuit causes the bits of the read data to interact with the plurality of bits of the test data respectively. Exclusive OR operation is performed to respectively generate the output information of an error bit information. The memory device of claim 2, wherein in the test mode, the data bus reversal calculator stops working. The memory device of claim 1, wherein the output result judgment circuit includes a plurality of anti-mutex OR gates, and the first input end of each anti-mutex OR gate receives each bit of the read data, each The second input terminal of the anti-mutex OR gate receives each of the bits of the test data or receives each of the bits of the inversion instruction data, and the output terminal of each anti-mutex OR gate generates each of the output information. Bits. The memory device of claim 1 further includes: a test data register coupled to the multiplexer for storing the test data. The memory device of claim 7, further comprising: a data input block coupled to the data access circuit for providing external input data to the data access circuit; and a data output block coupled to the data access circuit. Connected to the output result judgment circuit for outputting the output information. The memory device of claim 8, wherein there is a data writing path between the data input block and the data access circuit, and there is a data reading path between the data output block and the output result judgment circuit. The memory device of claim 8, wherein the data access circuit includes: a sense amplifier for providing a write data to the memory cell array, or sensing the read data from the memory cell array ; and a write data buffer coupled to the sense amplifier for temporarily storing the write data.

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