TWI830548B - Video encoding method and electronic equipment thereof - Google Patents

Abstract

A video encoder receives raw pixel data to be encoded as a current block of a current picture of a video into a bitstream. The video encoder identifies multiple candidate bi-prediction positions for the current block, including a center position, a first set of offset positions, and a second set of offset positions. The first set of offset positions and the second set of offset positions interleave each other. The encoder computes distortion values for each of the candidate bi-prediction positions based on several possible weighting parameter values. The distortion values for the center position are based on each of the several possible weighting parameter values. The distortion values for the first set of offset positions are based on a first subset of the possible weighting parameter values. The distortion values for the second set of offset positions are based on a second subset of the possible weighting parameter values.

Description

Video encoding method and related electronic equipment

This disclosure relates to video codecs. In particular, the present disclosure relates to hardware architectures configured to support multiple different codec modes.

Unless otherwise indicated herein, the methods described in this section are not prior art to the scope of the claims later listed and are not admitted to be prior art by inclusion in this section.

High Efficiency Video Codec (HEVC) is an international video codec standard developed by the Joint Collaboration on Video Codecs (JCT-VC). HEVC is based on a hybrid block-based motion compensated DCT transform-like codec architecture. The basic unit of compression, called a Codec Unit (CU), is a 2Nx2N square block, and each CU can be recursively split into four smaller CUs until a predefined minimum size is reached. Each CU contains one or more prediction units (PU).

In order to achieve the best encoding and decoding efficiency of the hybrid encoding and decoding architecture in HEVC, each PU has two prediction modes, namely intra prediction and inter prediction. For intra prediction mode, spatially adjacent reconstructed primitives can be used to generate directional predictions. There are up to 35 orientations in HEVC. For inter prediction mode, temporally reconstructed reference frames can be used to generate motion compensated predictions. There are three different modes, including Skip, Merge, and Inter Advanced Motion Vector Prediction (AMVP) mode.

When the PU is coded in inter-AMVP mode, motion compensated prediction is performed using the transmitted motion vector difference (MVD), which can be used with the motion vector predictor (MVP) to derive the motion vector (MV) . To determine the MVP in inter-AMVP mode, the advanced motion vector prediction (AMVP) scheme is used to select motion vector predictors in the AMVP candidate set including two spatial MVPs and one temporal MVP. Therefore, in AMVP mode, the MVP index of MVP and the corresponding MVD need to be encoded and transmitted. In addition, the inter prediction direction and the reference frame index of each manifest should be encoded and transmitted to specify bi-prediction and uni-prediction for list 0 (L0) and list 1 (L1) prediction direction.

When a PU is encoded in skip or merge mode, no motion information is transmitted except for the merge index of the selected candidate. This is because skip and merge modes utilize motion inference methods (MV=MVP+MVD, where MVD is zero) from spatially adjacent blocks (spatial candidates) or temporal blocks (temporal candidates) located in co-located pictures. Get motion information, where the co-located picture is the first reference picture in list 0 or list 1, signaled in the slice header. In case PU is skipped, the residual signal is also ignored. To determine the merge index for Skip and Merge modes, the merge scheme is used to select motion vector predictors in a merge candidate set containing four spatial MVPs and one temporal MVP.

In view of this, the present invention provides the following technical solutions:

The present invention provides a video coding method, which includes: receiving the original picture element data of the picture element block so that the current block of the current picture of the video is encoded into the bit stream; identifying the center position, the first group of offset positions and the second group of a plurality of candidate bidirectional prediction positions for the offset position; calculating a distortion value for each of the plurality of candidate bidirectional prediction positions based on a plurality of possible weighting parameter values, wherein: (i) based on each of the plurality of possible weighting parameter values; a distortion value calculated for the center position, (ii) a distortion value calculated for a first set of offset positions based on a first subset of a plurality of possible weighted parameter values, and (iii) for a second set of offset The positionally calculated distortion value is calculated based on a second subset of the plurality of possible weighting parameter values, wherein the first subset of the plurality of possible weighting parameter values is different from the second subset of the plurality of possible weighting parameter values; Selecting a weighting parameter value of the candidate bidirectional prediction position based on the calculated distortion values of the plurality of candidate bidirectional prediction positions of the current block; and encoding the current block using bidirectional prediction based on the selected weighting parameter value.

The present invention also provides an electronic device, including: an encoder circuit configured to perform operations including: receiving original primitive data of the primitive block to encode the current block of the current picture of the video into the bit stream; identifying the center position including , a plurality of candidate bidirectional prediction positions for the first set of offset positions and a second set of offset positions; calculating a distortion value for each of the plurality of candidate bidirectional prediction positions based on a plurality of possible weighted parameter values, where: (i) a distortion value calculated for the center position based on each of a plurality of possible weighting parameter values, (ii) a distortion value calculated for the first set of offset positions based on a first subset of the plurality of possible weighting parameter values , and (iii) the distortion values calculated for the second set of offset positions are calculated based on a second subset of a plurality of possible weighting parameter values, where the first subset of a plurality of possible weighting parameter values is different from the plurality of possible weighting parameter values. a second subset of possible weighting parameter values; selecting weighting parameter values for candidate bidirectional prediction locations based on calculated distortion values for a plurality of candidate bidirectional prediction locations for the current block; and using bidirectional prediction for the current block based on the selected weighting parameter values. Encode.

The video encoding method and corresponding electronic equipment of the present invention can be shared by multiple different encoding and decoding tools.

In the description that follows, many specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification. However, one of ordinary skill in the art will understand that the present invention may be practiced without such specific details. A person with ordinary knowledge in the art given the included description will be able to implement appropriate functionality without undue experimentation.

The following description is of the best contemplated modes of carrying out the invention. This description is intended to illustrate the general principles of the invention and should not be construed as limiting. The scope of the invention can best be determined by reference to the appended claims.

In the detailed description that follows, numerous specific details are set forth by way of examples in order to provide a thorough understanding of the relevant teachings. Any changes, derivatives, and/or extensions based on the teachings described herein are within the scope of this disclosure. In some instances, well-known methods, procedures, components and/or circuits related to one or more example implementations disclosed herein may be described at a relatively general level without being described in detail to avoid unnecessarily obscuring the disclosure aspects of teaching.

In the latest video coding and decoding standard Versatile Video coding (VVC), many new coding and decoding tools are proposed to improve coding and decoding efficiency. Examples of such codec tools include Advanced Motion Vector Prediction (AMVP), Geometric Prediction Mode (GPM), Adaptive Motion Vector Resolution (Adaptive Motion Vector Resolution) AMVR), Merge Mode with Motion Vector Difference (MMVD), Decoder-side Motion Vector Refinement (DMVR), Bidirectional Prediction (Bi) with CU-level weights -prediction with CU-level Weights, abbreviated as BCW), sub-block transform (Sub-Block Transform, abbreviated as SBT), etc. The VVC standard's high-performance video transcoder can achieve high codec gains by supporting as many of these codec tools as possible. However, it is very inefficient to design dedicated hardware circuits for each codec tool.

Some embodiments of the present disclosure provide a video transcoder that includes circuitry configured to be shared by multiple different codec tools. The video transcoder may include a low-complexity (LC) rate-distortion optimization stage (LC-RDO) as the first-stage RDO and a high-complexity (LC-RDO) as the second-stage RDO. Complexity (high-complexity, abbreviated as HC) rate-distortion optimization stage (HC-RDO). The video transcoder tries various codec tools and selects the codec tool with the lowest RD-cost. Since a codec tool may have multiple possible candidates, the LC-RDO stage is used to select the candidate with the lowest RD cost. In some embodiments, the LC-RDO stage performs simpler transformations such as Sum of Absolute Difference (SAD) or Sum of Absolute Transformed Difference (SATD) to simplify distortion. calculate. LC-RDO can select candidates by performing simpler transformations and/or not performing a full search. The HC-RDO stage then uses the candidates provided by LC-RDO to finalize the selection of codec tools to encode the current CU, including by performing standard transforms such as DCT2.

In some embodiments, the LC-RDO includes circuitry configured to be shared by multiple different codec tools. Therefore, to encode CUs, a video transcoder can implement LC-RDO in multiple different configurations for multiple different codec tools. In some embodiments, for each codec tool, LC-RDO identifies a best candidate for HC-RDO.

Figure 1 conceptually illustrates a portion of video transcoder 100 that uses LC-RDO stage 110 and HC-RDO stage 120 to select codec tools and/or prediction candidates for codec of the current block.

As shown, LC-RDO 110 and HC-RDO 120 together perform RDO functions for video transcoder 100 such that the current block is encoded using the lowest cost codec tool and prediction candidate in terms of rate and distortion. The LC-RDO stage 110 checks the codec tools and prediction candidates to provide intermediate results to the HC-RDO stage 120 . Intermediate results produced by LC-RDO 110 may include information such as the identity of the best predicted candidate for a particular codec tool and its associated cost. HC-RDO can use intermediate results to produce final codec tool selections and prediction candidate selections. Video transcoder 100 then encodes the current block using codec tools and prediction candidate selection.

Both LC-RDO 110 and HC-RDO 120 can retrieve data from data cache 130, which can include storage of primitive data for the current picture (reconstructed or original source) and several reference pictures. . Data cache 130 may also include storage for reference motion information, such as motion vectors previously used for other CUs. LC-RDO and HC-RDO can selectively retrieve data from the data cache 130 based on the location of the current block and the codec tool and prediction candidate being examined.

LC-RDO 110 includes circuitry that is common to different codec tools and may be configured to generate intermediate results for different codec tools. Thus, the same LC-RDO 110 may be configured in a first configuration 111 to produce a first intermediate result 121 for a first codec tool, and then configured in a second configuration 112 to produce a second codec for a second encoding. Intermediate results 122 tools etc. HC-RDO 120 uses the intermediate results of different codec tools to finalize the selection of codec tools and/or prediction candidates for encoding the current block. In the figure, codec tool configurations 111-114 are used by LC-RDO 110 to generate intermediate results 121-124 for HC-RDO 120, respectively.

In some embodiments, LC-RDO stage 110 may perform at least some of the following operations: (1) retrieve data from data cache 130, (2) generate candidates, (3) compute distortion using low-complexity transformations, and (4) compare the RD costs of different candidates. The winning candidates identified by the LC-RDO stage 110 are then provided to the HC-RDO stage 120 . The same 4 operations of LC-RDO can be used to identify the best candidates for different codec tools such as AMVP, MMVD, and GPM.

Figure 2 conceptually illustrates the components of the LC-RDO. The circuitry of the LC-RDO is configured by a codec-specific profile 200 to determine the best candidate for the codec tool and provide the cost of using that candidate.

For each of several candidates, LC-RDO 110 retrieves data from data cache 130 , applies interpolation 210 , performs distortion calculations 220 , and performs rate calculations 230 . Based on the distortion and rate calculations, LC-RDO 110 determines a cost value for each candidate. The overall comparator (also called a candidate comparator) 240 compares the cost values of different candidates to determine the best candidate for a specific codec tool.

LC-RDO 110 performs operations 210-230 according to configuration data 200. Configuration profile 200 may also configure LC-RDO to omit one or more of steps 210-230. In some embodiments, the LC-RDO may have circuitry that is configured to check multiple candidates in parallel (eg, there are independent sets of circuits capable of checking different candidates simultaneously). In some embodiments, the LC-RDO may have circuitry shared by different candidates and may be configured to check each candidate continuously.

Figure 3 illustrates an example implementation of the LC-RDO 110 with common circuitry for multiple different codec tools. The LC-RDO 110 includes an L0 unidirectional prediction part 301, an L0 bidirectional prediction part 302, an L1 unidirectional prediction part 303, and an L1 bidirectional prediction part 304. When configured for the programming tool, each section's circuitry calculates the distortion and rate of that section candidate. Each part has one or more local comparators to determine the best candidate with the lowest cost for that part. The overall comparator 240 compares the best candidates of the four parts 301-304 to identify the overall best candidate for a given codec tool based on costs derived from calculated distortion and rate.

As shown, the L0 unidirectional prediction section 301 has an interpolation filter 310, a SATD array 320, rate calculators 331-334, and a local comparator 340. Interpolation filter 310 receives reference samples ("references") and uses horizontal filter array 311, shift register 312, vertical filter array 313, and interpolation buffer 314 to generate filtered reference samples (e.g., for fractional positions ). The reference picture buffer 315 is used to store the primitive data of the reference picture as a reference sample. Interpolation filter 310 may provide outputs from any of elements 311-314, and SATD array 320 may use any of these outputs for its distortion calculations. The SATD array 320 performs distortion calculations based on the source data (from the video source) and the (unidirectional) filtered reference samples from the interpolation filter 310 . SATD array 320 may also perform distortion calculations based on mixed reference samples from L0 bidirectional prediction section 302 . The output of SATD array 320 is provided to quarter, ½, 1, and 4 comparators 341-344.

The outputs of rate calculators 331-334, along with the output of SATD array 320, are fed to comparators 341-344. Comparators 341-344 in turn provide cost values for different candidates at different primitive resolutions. Local comparator 340 compares these different candidates and identifies the best candidate for L0 unidirectional prediction.

The L0 bi-prediction section 302 has a bi-prediction mixing module 319, a bi-prediction SATD array 325, a rate calculator 335, and a bi-prediction comparator 345. The bi-predictive blending module 319 performs a weighted average to blend reference sample primitives from two reference pictures at different temporal locations (eg, two uni-predictors of L0 and L1). The bidirectional prediction SATD array 325 calculates the distortion in the mixed reference sample and provides the distortion value to the bidirectional prediction comparator 345 and the rate calculator 335 . In some embodiments, when performing L0 bidirectional prediction, SATD array 320 may be reused for calculating distortion, and comparators 331-334 may also be reused.

This figure illustrates the components of L0 bidirectional and L0 unidirectional prediction sections 301 and 302. The components of the L1 unidirectional prediction part 303 and the L1 bidirectional prediction part 304 are not illustrated because they are similar to the components of the L0 unidirectional prediction part 301 and the L0 bidirectional prediction part 302 .

Each candidate is associated with a cost value calculated based on the calculated distortion value and rate value. The global comparator 240 compares the best candidates from the L0 uni-prediction part 301, the L0 bi-prediction part 302, the L1 uni-prediction part 303 and the L1 bi-prediction part 304.

Various components/circuitry of LC-RDO 110 can be shared by different codec tools. In some embodiments, at least some components of the LC-RDO may be configured to identify lowest cost candidates for various codec tools.

Merge Mode with Motion Vector Difference (MMVD) is a codec tool used by the Common Video Codec (VVC) standard. Unlike the regular merging mode, where the implicitly derived motion information is directly used for prediction sample generation of the current CU, in MMVD, the derived motion information is further refined through motion vector difference (MVD). MMVD also extends the candidate list of merge modes by adding additional MMVD candidates based on predefined offsets (also called MMVD offsets).

In some embodiments, the circuitry of LC-RDO 110 may be used to identify candidates for MMVD modes. For example, horizontal filter array 311 and vertical filter array 313 are general coefficient filters configurable for MMVD mode. The size of the reference picture buffer 315 is large enough to store the reference samples required for MMVD. The size of shift register 312 and interpolation buffer 314 are also large enough to accommodate the temporary results of vertical and horizontal filtering. The bidirectional prediction mixing module 319 and the bidirectional prediction SATD array 325 of the bidirectional prediction part can be directly used for MMVD calculation distortion. The overall comparator 240 can also be reused for MMVD.

Decoder-side Motion Vector Refinement (DMVR) is a codec tool that can be applied to regular merge candidates. According to DMVR, the decoder refines the MV according to predefined steps: (i) split the current CU into multiple 16x16/8x16/16x8 sub-blocks, (ii) use a bilinear filter around the regular merge candidates Generate 25 integer offset refinement candidates, (iii) calculate the even row SAD cost through mirror matching, and (iv) apply fractional offset refinement if predefined conditions are met. As shown in the picture. Figure 4 conceptually illustrates image matching in DMVR. The figure shows the mirror matching between the 25 refinement candidate positions of the L0 merged MV and the 25 refinement candidate positions of the L1 merged MV.

The process of DMVR MV offset export has many similarities with the LC-RDO stage. Therefore, the circuitry of the LC-RDO 110 stage can be shared or reused with DMVR, with some modules configured differently than other codec tools. For DMVR, LC-RDO can be configured to (i) read from the cache, (ii) generate bilinear candidates, (iii) calculate the even row SAD cost, and (iv) compare the cost of each candidate for scoring Refine and output a refined merged MV. The refined merged MV is provided to HC-RDO 120. For example, the horizontal filter array 311 and the vertical filter array 313 may be configured to perform bilinear filtering. SATD array 320 may be configured to calculate SAD costs for even rows. Bidirectional mixing module 319 may be configured to support image matching. The reference picture buffer 315, shift register 312, interpolation buffer 314 and local comparator 340 can be directly reused for DMVR. Comparators 341-344 may be configured to perform fractional refinement, such as constructing an error surface and then finding the offset with minimum cost on the error surface.

Adaptive Motion Vector Resolution (AMVR) allows encoding of motion vector differences (MVD) with different precisions. There are 4 AMVR precisions in VVC: four-sample (4-pel), integer-sample (1-pel), 1/2-sample (H-pel), and quarter-sample (Q-pel). In some embodiments, the example architecture of LC-RDO 110 in Figure 3 can be directly shared with AMVR, where 4 comparators 331-334 correspond to 4 AMVR precisions. More commonly, the four AMVR precisions are handled by four separate PE calls (e.g., using four separate hardware processing elements.)

In some embodiments, LC-RDO can execute different AMVR precisions with one PE call (using the same processing element), specifically by aligning the center MVs of different AMVR precisions and executing the RDO together. Figure 5 conceptually illustrates the alignment of four AMVR accuracies by aligning their center MVs. Each circle in the diagram represents a primitive position (integer and fractional). The circle labeled "Q" is the quarter primitive position interpolated using an 8-tap filter, while the circle labeled "H" is interpolated using a 6-tap filter. 1/2 primitive position. The circle labeled "HQ" is where the interpolation operation is performed on the 1/2 primitive and the quarter primitive. The circles labeled "1" and "4" are respectively the 1- and 4-prime locations that do not require interpolation.

By aligning the four precisions at their center MV, all four AMVR precisions can be executed by a single PE-call or have a subset of AMVR precisions (e.g., 1 primitive, 1/2 primitive, and quarter one primitive, but not 4 primitives) into a PE call. Experience shows that under certain conditions this does not have much impact on the BD rate. It can be observed that when the current CU size is larger, AMVR side information becomes less important. Partial interpolation results of four different precisions can be shared to further reduce hardware costs.

Sub-block Transform (SBT) is a coding and decoding tool for CUs used for inter-frame prediction, allowing the video encoder to perform transformation only on a part of the residual block or transformation block. The encoded portion of the transform block is encoded using an implicitly determined transform. The non-coded portion is cleared. SBT specifies a number of different candidate modes for dividing the transform block into a coded part and a non-coded part. Figure 6 illustrates various candidate modes of SBT for dividing a transform block into a coding portion and a zero portion. In the figure, for each candidate SBT mode, the coding part of the transform block is marked as "A" and the non-coding part as "0". The width of the transform block is called tbWidth. The width of the encoded part is called trafoWidth.

The various candidate modes of SBT in Figure 6 can be enabled or disabled via cu_sbt_quad_flag, cu_sbt_horizontal_flag and cu_sb_pos_flag. cu_sbt_quad_flag indicates whether trafoWidth:(tbWidth-trafoWidth) can be 2:2 or 1:3 or 3:1. cu_sbt_horizontal_flag indicates whether the transform block is split horizontally or vertically for SBT. cu_sb_pos_flag indicates whether the left/top sub-block has non-zero transform coefficients and the right/bottom is zeroed out, or whether the right/bottom sub-block has non-zero transform coefficients and the left/top is zeroed out.

Instead of trying all possible candidate modes for SBT in the HC-RDO stage, in some embodiments the LC-RDO stage is used to identify the candidate mode with the minimum cost for coding the transform block. In some embodiments, LC-RDO calculates the residual cost of each candidate mode of the SBT by a weighted average of the SSD of the transform coded portion and the SSD of the zeroed portion. Specifically, the cost of each candidate pattern is calculated as follows:

(Eq. 1)

LC-RDO will select the candidate mode with the lowest cost (calculated according to Equation 1) for testing in HC-RDO. This is called SBT-preselection. Therefore, in some embodiments, instead of having the HC-RDO try every possible candidate mode of SBT, the video encoder can perform SBT pre-selection at the LC-RDO. HC-RDO then performs candidate selection based on the results of SBT pre-selection.

LC-RDO 110 may be configured to perform SBT pre-selection. Specifically, the residuals of each candidate mode of the SBT may be provided to the SATD array 320, which may then calculate the cost of each candidate mode according to Equation 1 above.

Bidirectional prediction with CU-level weights (BCW) is a codec tool for enhanced bidirectional prediction. BCW allows applying different weights to L0 predictions and L1 predictions before combining them to generate bidirectional predictions for the CU. For CUs to be encoded by BCW, a weighting parameter w is sent for L0 and L1 prediction so that the bidirectional prediction result P _bi-pred is calculated based on w according to the following formula:

(Eq. 2)

P ₀ represents the primitive value predicted by L0 MV (or L0 prediction). P ₁ represents the primitive value predicted by L1 MV (or L1 prediction). P _bi-pred is the weighted average of P ₀ and P ₁ according to w. For low-latency pictures, that is, pictures using reference frames with a small picture order count (POC), possible values of w include {-2, 3, 4, 5, 10}. For non-low latency images, possible values for w include {3, 4, 5}. In some embodiments, in order to find the best w for encoding and decoding the current CU, instead of searching all possible values of w for all candidate bidirectional prediction MV positions, the LC-RDO stage can use an interleaving search pattern to find the BCW The optimal value of the weighting parameter w.

Figure 7 conceptually illustrates the interleaved search pattern used to find optimal BCW weighting parameter values. In the figure, weight indexes (BCWIdx) 0, 1, 2, 3, and 4 correspond to possible BCW weight parameter values -2, 3, 4, 5, and 10 respectively. Search mode is used for arrays or permutations of candidate bidirectionally predicted MV positions. Candidate bidirectionally predicted MV positions in the alignment include a center position 700 and a plurality of vertical and/or horizontal offset positions (±1, ±2, etc.) based on the center position 700.

For each candidate bidirectionally predicted MV position, LC-RDO computes the distortion value corresponding to each possible w value for that position. As shown in the figure, at the center bidirectional prediction MV position 700, the LC-RDO stage tries to find by trying the weight indices 0, 1, 2, 3, 4 corresponding to the BCW weight values -2, 3, 4, 5, 10 respectively The optimal value of w. For each of the candidate bidirectional prediction MV positions that are offset positions from the center position, the BCW weight is selectively checked. At type 1 offset positions, the LC-RDO stage attempts weight indices (BCWIdx) 0, 2, and 3, which correspond to weight parameter values -2, 4, and 5, respectively. At the second type of offset position, the LC-RDO stage attempts weight indices 1, 2, and 4, which correspond to BCW weight values 3, 4, and 10, respectively.

By using the w value to calculate the bidirectional prediction (Pbi_pred) of the current block, that is, the weighted average of the L0 prediction (P ₀ ) based on L0 MV and the L1 prediction (P ₁ ) based on L1 MV (Equation 2), LC-RDO calculates the candidate Distortion values for possible w values at bidirectional prediction locations. L0 and L1 MVs are identified based on candidate bidirectional prediction positions. The possible distortion of the w value is the difference between the original primitive data of the current block and the bidirectional prediction.

The placement of the two types of offset positions is arranged in a staggered pattern as shown in the figure. Specifically, the first type of offset positions are at the upper right, upper left, lower right and lower left of the center position 700 , while the second type of offset positions are at the upper, right, left and bottom of the center position 700 . The pattern expands so that each offset position of one type has a diagonal neighbor of the same type (top right, top left, bottom right, bottom left), and a horizontal and vertical neighbor of the opposite type (top, right, left, and bottom ).

Typically, LC-RDO tries all possible BCW weighting parameter values at the center location only. For all other candidate bidirectionally predicted MV positions (offset positions), LC-RDO only tries a subset of possible weighting parameter values. Furthermore, the offset positions are divided into different groups (e.g., according to the interleaving pattern), and LC-RDO tries different subsets of possible w values for different groups of offset positions. Furthermore, BCWIdx=2 (or w=4) is tried for all candidate bidirectional prediction MV positions, because BCWIdx=2 corresponds to equally weighted L1 prediction and L0 prediction when calculating the bidirectional prediction results.

By reducing the number of possible w values that are checked based on the interleaving pattern, the video encoder can reduce the number of SATD operations performed when finding the optimal bidirectionally predicted MV position and the optimal BCW weighting parameter value to obtain the optimal bidirectionally predicted MV position.

As mentioned above, the LC-RDO 110 is a hardware circuit that can be shared by several different codec tools, including BCW. Bidirectional blending module 319 may be used to calculate a weighted average of the L0 and L1 predictions of BCW. Bidirectional SATD array 325 may be used to calculate distortion values for different weighting parameter values at various bidirectional predicted MV positions. Bi-prediction comparator 345 may be used to identify optimal weighting parameter values and optimal bi-prediction MV locations by comparing costs associated with different weighting parameter values at different candidate bi-prediction MV locations.

Sample video encoder

Figure 8 illustrates an example video encoder 800 that can use LC-RDO stages and HC-RDO stages to select codec tools and/or prediction candidates for encoding the current block. As shown, video encoder 800 receives an input video signal from a video source 805 and encodes the signal into a bit stream 895. Video encoder 800 has several components or modules for encoding signals from video source 805, including at least some components selected from the following: transform module 810, quantization module 811, inverse quantization module 814, inverse transform module 815, image Intra estimation module (also called intra estimation module) 820, intra prediction module 825, motion compensation module 830, motion estimation module 835, loop filter 845, reconstructed picture buffer 850, MV buffer 865, MV prediction module 875 and entropy encoder 890. Motion compensation module 830 and motion estimation module 835 are part of inter prediction module 840.

In some embodiments, modules 810-890 are modules of software instructions executed by one or more processing units (eg, processors) of a computing device or electronic device. In some embodiments, modules 810-890 are hardware circuit modules implemented by one or more integrated circuits (ICs) of an electronic device. Although modules 810-890 are shown as separate modules, some modules may be combined into a single module.

Video source 805 provides a raw video signal that represents the primitive data of each video frame without compression. Subtractor 808 calculates the difference between original video primitive data of video source 805 and predicted primitive data 813 from motion compensation module 830 or intra prediction module 825 . The transform module 810 converts the differences (or residual primitives or residual signals 808 ) into transform coefficients (eg, by performing a discrete cosine transform or DCT) 816 . The quantization module 811 quantizes the transform coefficients into quantized data (or quantized coefficients) 812 , which is encoded by the entropy encoder 890 into a bit stream 895 .

The inverse quantization module 814 inversely quantizes the quantized data (or quantized coefficients) 812 to obtain transform coefficients, and the inverse transform module 815 performs an inverse transform on the transform coefficients to produce a reconstructed residual 819 . The reconstructed residuals 819 are added together with the predicted primitives 813 to produce reconstructed primitives 817 . In some embodiments, the reconstructed primitive data 817 is temporarily stored in a line buffer (not shown) for intra-picture prediction and spatial MV prediction. The reconstructed primitives are filtered by loop filter 845 and stored in reconstructed picture buffer 850. In some embodiments, the reconstructed picture buffer 850 is a memory external to the video encoder 800 . In some embodiments, the reconstructed picture buffer 850 is an internal memory of the video encoder 800 .

Intra-picture estimation module 820 performs intra prediction based on the reconstructed primitive data 817 to generate intra prediction data. The intra prediction data is provided to an entropy encoder 890 to be encoded into a bitstream 895. The intra prediction data is also used by the intra prediction module 825 to generate predicted primitive data 813 .

Motion estimation module 835 performs inter prediction by generating MVs to reference primitive data of previously decoded frames stored in reconstructed picture buffer 850 . These MVs are provided to the motion compensation module 830 to generate predicted primitive data.

Instead of encoding the complete actual MV in the bitstream, the video encoder 800 uses MV prediction to generate the predicted MV, and the difference between the MV used for motion compensation and the predicted MV is encoded as residual motion data and Stored in bitstream 895.

The MV prediction module 875 generates a predicted MV based on the reference MV generated for encoding the previous video frame, ie, the motion compensation MV used to perform motion compensation. The MV prediction module 875 retrieves reference MVs from previous video frames from the MV buffer 865 . Video encoder 800 stores the MV generated for the current video frame in MV buffer 865 as a reference MV for generating predicted MVs.

The MV prediction module 875 uses the reference MV to create predicted MVs. Predicted MV can be calculated by spatial MV prediction or temporal MV prediction. Entropy encoder 890 encodes the difference (residual motion data) between the predicted MV and the motion compensated MV (MC MV) of the current frame into the bit stream 895.

Entropy encoder 890 encodes various parameters and information into bit stream 895 using entropy coding techniques such as Context Adaptive Binary Arithmetic Coding (CABAC) or Huffman coding. The entropy encoder 890 encodes various header elements, flags together with the quantized transform coefficients 812 and residual motion data as syntax elements into the bit stream 895 . The bit stream 895 is in turn stored in a storage device or transmitted to the decoder via a communication medium such as a network.

Loop filter 845 performs a filtering or smoothing operation on reconstructed primitive data 817 to reduce coding artifacts, particularly at primitive block boundaries. In some embodiments, the filtering operations performed include sample adaptive offset (SAO). In some embodiments, the filtering operation includes an adaptive loop filter (ALF).

Figure 9 illustrates parts of the video encoder 800 that implement LC-RDO and HC-RDO. Specifically, this figure illustrates the components of inter prediction module 840 of video encoder 800. As shown, inter prediction module 840 includes LC-RDO 110 and HC-RDO 120 for performing rate-distortion optimization to identify the most suitable codec tools and/or prediction candidates.

Both RDO stages 110 and 120 receive source primitive data from video source 805 , reference primitive data from reconstructed picture buffer 850 , and reference MV data from MV buffer 865 . LC-RDO 110 uses the received data to identify prediction candidates and calculate the cost of using various codec tools (eg, rate and distortion values). LC-RDO 110 may identify the prediction candidate with the best cost for each codec tool as the intermediate RDO result of HC-RDO 120 . HC-RDO 120 completes the selection of encoding and decoding tools and prediction candidates in sequence. Motion compensation module 830 (which may be part of HC-RDO 120) uses the selected codec tool and prediction candidates to perform motion compensation and generate prediction primitives 813.

Figure 10 conceptually illustrates the process 1000 of finding weighting parameter values when encoding a coding block using BCW. In some embodiments, one or more processing units (eg, processors) of a computing device implement encoder 800 to perform process 1000 by executing instructions stored in a computer-readable medium. In some embodiments, electronics implementing encoder 800, specifically LC-RDO stage 110, performs process 1000.

The encoder (at block 1010) receives raw primitive data for the primitive block as the current block of the current picture of the video is encoded into the bit stream.

The encoder (at block 1020) identifies a plurality of candidate bi-prediction locations, including a center location, a first set of offset locations, and a second set of offset locations. The first set of offset positions and the second set of offset positions are offset positions from the center position. In some embodiments, the first set of offset locations and the second set of offset locations are interleaved with each other.

The encoder (at block 1030) calculates a distortion value for the center position based on each of several possible weighting parameter values. The encoder (at block 1040) calculates distortion values for each of the first set of offset positions based on the first subset of possible weighting parameter values. The encoder (at block 1050) calculates distortion values for each of the second set of offset positions based on a second different subset of possible weighting parameter values.

In some embodiments, the encoder calculates the distortion value based on the weighted parameter values at the candidate bidirectional prediction positions by using the weighted parameter values to calculate the bidirectional prediction based on the first prediction of the first motion vector and the second prediction based on the second motion vector. The weighted average of the second prediction of the motion vector (eg, according to Equation 2). First and second motion vectors are identified based on the candidate bi-prediction positions. The distortion of the possible weighting parameter values at the candidate bi-prediction positions is the difference between the original primitive data of the current block and the bi-prediction calculated based on the possible weighting parameter values at the candidate bi-prediction positions.

In some embodiments, several possible weighting parameter values include first, second, third, fourth and fifth values. For the BCW codec tool, the five possible weighting parameter values correspond to -2, 3, 4, 5, and 10. A first subset of possible weighting parameter values includes second, third, and fifth values (3, 4, and 10). A second subset of the plurality of possible weighting parameter values includes first, third, and fourth values (-2, 4, and 5). In some embodiments, the first and second subsets of possible weighting parameter values share one possible weighting parameter value (a third value, ie, 4). A common possible weighting parameter value corresponds to equally weighting the first and second predictions (according to Equation 2).

The encoder (at block 1060) selects weighting parameter values for the candidate bi-prediction locations based on the calculated distortion values for the plurality of candidate bi-prediction locations for the current block. The encoder (at block 1070) encodes the current block using bi-prediction based on the selected weighting parameter values and the selected candidate bi-prediction positions.

Example electronic system

Many of the features and applications described above are implemented as software processes specified as a set of instructions recorded on a computer-readable storage medium (also referred to as computer-readable media). When these instructions are executed by one or more computing or processing units (e.g., one or more processors, processor cores, or other processing units), they cause the processing unit to perform the actions indicated in the instructions. Examples of computer-readable media include, but are not limited to, CD-ROMs, flash memory drives, random access memory (RAM) chips, hard drives, erasable programmable read-only memory (EPROM), electronic Erase programmable read-only memory (EEPROM)), etc. Computer-readable media does not include carrier waves and electronic signals transmitted wirelessly or over wired connections.

In this specification, the term "software" is meant to include firmware that resides in read-only memory or applications stored in magnetic memory that can be read into memory for processing by a processor. Furthermore, in some embodiments, multiple software inventions may be implemented as subparts of a larger program while retaining distinct software inventions. In some embodiments, multiple software inventions may also be implemented as separate programs. Finally, any combination of separate programs that together implement the software inventions described herein is within the scope of this disclosure. In some embodiments, one or more specific machine implementations are defined that execute and perform the operations of the software program when it is installed to run on one or more electronic systems.

Figure 11 conceptually illustrates an electronic system 1100 implementing some embodiments of the present disclosure. Electronic system 1100 may be a computer (eg, desktop computer, personal computer, tablet computer, etc.), telephone, PDA, or any other kind of electronic device. Such electronic systems include various types of computer-readable media and interfaces for various other types of computer-readable media. Electronic system 1100 includes bus 1105, processing unit 1110, graphics processing unit (GPU) 1115, system memory 1120, network 1125, read-only memory 1130, persistent storage 1135, input device 1140, and output device 1145.

Bus 1105 collectively represents all system, peripheral, and chipset busses that communicatively connect the numerous internal devices of electronic system 1100 . For example, bus 1105 communicatively connects processing unit 1110 with GPU 1115, read-only memory 1130, system memory 1120, and persistent storage 1135.

From these various memory units, processing unit 1110 retrieves instructions to be executed and data to be processed in order to perform the processes of the present disclosure. In different embodiments, the processing unit may be a single processor or a multi-core processor. Some instructions are passed to the GPU 1115 and executed by it. GPU 1115 can offload various computations or supplement image processing provided by processing unit 1110 .

Read-only memory (ROM) 1130 stores static data and instructions used by processing unit 1110 and other modules of the electronic system. On the other hand, the permanent storage device 1135 is a read-write storage device. This device is a non-volatile storage unit that stores instructions and data even when the electronic system 1100 is turned off. Some embodiments of the present disclosure use large storage area devices (such as magnetic disks or optical disks and their corresponding disk drives) as the permanent storage device 1135 .

Other embodiments use removable storage devices (such as floppy disks, flash memory devices, etc., and their corresponding disk drives) as permanent storage devices. Like permanent storage 1135, system memory 1120 is a read-write storage device. However, unlike the storage device 1135, the system memory 1120 is a volatile read-write memory, such as a random access memory. System memory 1120 stores some instructions and data used by the processor during operation. In some embodiments, processes in accordance with the present disclosure are stored in system memory 1120, persistent storage 1135, and/or read-only memory 1130. For example, various memory units include instructions and some embodiments for processing multimedia clips. From these various memory units, processing unit 1110 retrieves instructions to be executed and data to be processed in order to perform the processes of some embodiments.

Bus 1105 also connects to input and output devices 1140 and 1145. Input devices 1140 enable users to transmit information and select commands to electronic systems. Input devices 1140 include alphanumeric keyboards and pointing devices (also known as "cursor control devices"), cameras (e.g., webcams), microphones or similar devices for receiving voice commands, and the like. Output device 1145 displays images or other output material generated by an electronic system. Output devices 1145 include printers and display devices, such as cathode ray tubes (CRT) or liquid crystal displays (LCD), as well as speakers or similar audio output devices. Some embodiments include devices that serve as both input and output devices, such as touch screens.

Finally, as shown in Figure 11, bus 1105 also couples electronic system 1100 to network 1125 through a network interface card (not shown). In this manner, a computer may be part of a computer network, such as a local area network ("LAN"), a wide area network ("WAN"), or an intranet, or a network of networks, such as the Internet. Any or all elements of electronic system 1100 may be used in connection with the present disclosure.

Some embodiments are included on a machine-readable or computer-readable medium (also referred to as a computer-readable storage medium, a machine-readable medium, or a machine-readable storage medium). Some examples of such computer-readable media include RAM, ROM, compact disc-read only (CD-ROM), compact disc-recordable (CD-R), compact disc-rewritable (CD-RW), compact disc-read only (e.g. , DVD-ROM, dual-layer DVD-ROM), various burnable/rewritable DVDs (such as DVD-RAM, DVD-RW, DVD+RW, etc.), flash memory (such as SD card, mini-SD card, micro SD card, etc.), magnetic and/or solid-state hard drives, read-only and recordable Blu-Ray® discs, ultra-density optical discs, any other optical or magnetic media, and floppy disks. The computer-readable medium may store a computer program executable by at least one processing unit and including a set of instructions for performing various operations. Examples of computer programs or computer code include machine code, such as that generated by a compiler, and files that include high-level code executed by a computer, electronic component, or microprocessor using an interpreter.

While the above discussion primarily relates to microprocessors or multi-core processors executing software, many of the above features and applications are performed by one or more integrated circuits, such as an application specific integrated circuit (ASIC) or a field programmable gate array ( FPGA). In some embodiments, such integrated circuits execute instructions stored on the circuit itself. Additionally, some embodiments execute software stored in a programmable logic device (PLD), ROM, or RAM device.

As used in this specification and any claims filed in this application, the terms "computer", "server", "processor" and "memory" refer to electronic or other technical equipment. These terms do not include persons or groups of people. For illustrative purposes, the term display means display on an electronic device. As used in this specification and any claim claimed in this application, the terms "computer-readable medium," "computer-readable medium," and "machine-readable medium" are strictly limited to tangible physical objects that store information in a computer-readable form. These terms do not include any wireless signals, wired download signals and any other temporary signals.

Although the present disclosure has been described with reference to numerous specific details, those of ordinary skill in the art will recognize that the disclosure may be embodied in other specific forms without departing from the spirit of the disclosure. Additionally, many figures (including Figure 10) illustrate the process conceptually. The specific operations of these procedures may not be performed in the exact sequence shown and described. Specific operations may not be performed in a continuous series of operations, and different specific operations may be performed in different embodiments. Additionally, the process can be implemented using multiple sub-processes or as part of a larger macro-process. Accordingly, one of ordinary skill in the art will understand that the present disclosure is not limited by the foregoing illustrative details, but rather by the scope of the appended claims.

The subject matter described herein sometimes shows various components contained within or connected to various other components. It should be understood that the architecture so depicted is exemplary only, and that many other architectures may be implemented that achieve the same functionality. In a conceptual sense, any arrangement of components performing the same function is effectively "related" such that the desired functionality is achieved. Thus, any two components herein combined to achieve a specific functionality can be considered "associated with" each other so as to achieve the desired functionality, regardless of architecture or intervening components. Similarly, any two components so associated may also be considered "operably connected" or "operably coupled" to each other to achieve the desired functionality, and any two components capable of being so associated Components may also be considered "operably coupled" to each other to achieve the desired functionality. Specific examples of "operably coupled" include, but are not limited to: components that are physically coupled and/or physically interact with each other, and/or components that are wirelessly interactable and/or wirelessly interact, and /or logically interacting and/or logically interactable components.

Furthermore, with regard to the use of substantially any plural and/or singular term herein, one of ordinary skill in the art may convert the plural into the singular, and/or the singular into the plural, as appropriate to the context and/or application. For the sake of clarity, various singular/plural permutations may be explicitly stated here.

One of ordinary skill in the art will understand that generally, terms used herein, and particularly in the appended claims (e.g., the subject matter of the appended claims), are generally intended to be used as "open terms." ” terms (for example, the term “comprising” should be interpreted as “including but not limited to”, the term “having” should be interpreted as “at least having”, the term “comprising” should be interpreted as “including but not limited to”, etc. ). One of ordinary skill in the art will also understand that if an introduced patent claim states a specific number of the subject matter, such intention will be expressly stated in the patent claim, and in the absence of such a statement, no such intention will be expressed. There is such an intention. For example, to aid understanding, the appended claims may contain the use of the introductory phrases "at least one" and "one or more" to introduce the claimed subject matter. However, the use of such a phrase should not be construed to mean that the introduction of a claim statement with the indefinite article "a or an" limits the scope of any claim containing the claim statement so introduced to An invention containing only one such recited object, even if the same patent claim contains the introductory phrase "one or more" or "at least one" together with words such as "a (a)" or "an (an)" This is also true in the case of indefinite articles (e.g., "a(a)" and/or "an" should generally be interpreted to mean "at least one" or "one or more"); The same applies to the case where the definite article is used to introduce the object of the patent scope statement. In addition, even if a specific number of recited objects of an introduced patent claim is expressly stated, one of ordinary skill in the art will recognize that such statements generally should be construed to mean at least the recited number (e.g., only A statement "two declarative objects" without other modifiers usually means at least two declarative objects, or two or more declarative objects). Furthermore, in the case where an idiomatic expression similar to "at least one of A, B, and C, etc." is used, generally such a structure is intended to have the meaning of the idiomatic expression understood by a person of ordinary skill in the art (for example, "having "A system with at least one of A, B and C" will include, but is not limited to, A alone, B alone, C alone, A and B together, A and C together, B and C together and/or A, B and C together system, etc.). Where an idiomatic expression similar to "at least one of A, B or C, etc." is used, usually such a construction is intended to have the meaning of the idiomatic expression as understood by a person of ordinary skill in the art (e.g., "having A, A system with at least one of B or C" will include, but is not limited to, A alone, B alone, C alone, A and B together, A and C together, B and C together and/or A, B and C together with the system, etc.). It will be further understood by those of ordinary skill in the art that virtually any disjunctive word and/or phrase denoting two or more alternative terms, whether in the specification, claims, or drawings, should be understood to mean Consider the possibility of including one of the terms, either of the terms, or both of the terms. For example, the phrase "A or B" should be understood to include the possibilities of "A", "B", or "A and B".

It will be understood from the foregoing that various embodiments of the disclosure have been described herein for purposes of illustration, and that various modifications may be made without departing from the scope and spirit of the disclosure. Therefore, the various embodiments disclosed herein are not intended to be limiting, with the true scope and spirit being indicated by the appended claims.

100:Video transcoder 110:LC-RDO 111~114, 200: Configuration 120:HC-RDO 121~124: Intermediate results 130:Data cache 210: Interpolation 220: Distortion calculation 230: Rate calculation 240: Candidate Comparator 301: L0 one-way prediction part 302:L0 bidirectional prediction part 303:L1 one-way prediction part 304:L1 bidirectional prediction part 310: Interpolation filter 320:SATD array 331-334: Rate Calculator 340: Local comparator 311: Horizontal filter array 312:Shift register 313: Vertical filter array 314: Interpolation buffer 315: Reference picture buffer 331-335: Rate Calculator 340: Local comparator 341-344: Comparator 319: Bidirectional prediction hybrid module 325: Bidirectional prediction SATD array 345: Bidirectional prediction comparator 800:Video encoder 805:Video source 810: Transformation module 811: Quantization module 814:Inverse quantization module 815: Inverse transformation module 820: In-picture estimation module 825: Intra prediction module 830: Motion compensation module 835: Motion estimation module 840: Inter prediction module 845: Loop filter 850: Reconstruct image buffer 865:MV buffer 875:MV prediction module 890:Entropy encoder 895:Bit stream 808: Residual signal 812:Quantized coefficient 816: Transformation coefficient 813, 817: Graph element data 1000:Process 1010~1070: block 1100:Electronic systems 1105:Bus 1110: Processing unit 1115: Graphics processing unit 1120:System memory 1125:Internet 1130: Read-only memory 1135:Permanent storage device 1140:Input device 1145:Output device

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention: Figure 1 conceptually illustrates a portion of a video transcoder that uses the LC-RDO stage and the HC-RDO stage to select codec tools and/or prediction candidates for codec of the current block. Figure 2 conceptually illustrates the components of the LC-RDO. Figure 3 illustrates an example implementation of an LC-RDO with common circuitry for multiple different codec tools. Figure 4 Conceptually illustrates image matching in DMVR. Figure 5 conceptually illustrates the alignment of four AMVR accuracies by aligning their center MVs. Figure 6 illustrates various candidate modes of SBT for dividing the transform block into a coded part and a zero part. Figure 7 conceptually illustrates the interleaved search pattern used to find optimal BCW weighting parameter values. Figure 8 illustrates an example video encoder that may use LC-RDO stages and HC-RDO stages to select codec tools and/or prediction candidates for encoding the current block. Figure 9 illustrates the parts of the video encoder that implements LC-RDO and HC-RDO. Figure 10 conceptually illustrates the process of finding weighting parameter values when encoding a coding block using BCW. Figure 11 conceptually illustrates an electronic system implementing some embodiments of the present disclosure.

1000:Process

1010~1070: block

Claims (9)

A video encoding method including: receiving raw primitive data of the primitive block as the current block of the current picture of the video is encoded into the bit stream; identifying a plurality of candidate bidirectional prediction locations including a center location, a first set of offset locations, and a second set of offset locations; The distortion value calculated for each of the plurality of candidate bidirectional prediction positions is calculated based on a plurality of possible weighting parameter values, wherein: (i) the distortion value calculated for the center position is calculated based on each of the plurality of possible weighting parameter values. a distortion value, (ii) calculated for the first set of offset locations based on a first subset of the plurality of possible weighted parameter values, and (iii) calculated for the second set of offset locations The distortion value is calculated based on a second subset of the plurality of possible weighting parameter values, wherein the first subset of the plurality of possible weighting parameter values is different from the second subset of the plurality of possible weighting parameter values. Subset; Selecting weighting parameter values for candidate bi-directional prediction positions based on the calculated distortion values of the plurality of candidate bi-directional prediction positions of the current block; and The current block is encoded using bidirectional prediction based on the selected weighting parameter value. The video encoding method of claim 1, wherein the first set of offset positions and the second set of offset positions are interleaved. The video encoding method as described in claim 1, wherein calculating the distortion value of encoding and decoding the current block according to the weighted parameter value at the candidate bidirectional prediction position includes: using the weighted parameter value to calculate the bidirectional prediction, wherein the bidirectional prediction is based on the first An average of a first prediction of a motion vector and a second prediction based on a second motion vector, wherein the first motion vector and the second motion vector are identified based on the candidate bidirectional prediction location. The video encoding method of claim 3, wherein the first subset and the second subset of the multiple possible weighting parameter values share one possible weighting parameter value. The video encoding method of claim 4, wherein calculating the distortion value for encoding and decoding the current block based on the common possible weighting parameter value includes weighting the first prediction and the second prediction equally. The video encoding method of claim 3, wherein the distortion value of the possible weighting parameter value at the candidate bidirectional prediction position is the original picture element data of the current block and the possible weighting at the candidate bidirectional prediction position. The difference between the two predictions calculated by the parameter. The video encoding method as described in request item 1, wherein: The plurality of possible weighting parameter values include first, second, third, fourth and fifth values, The first subset of the plurality of possible weighting parameter values includes second, third and fifth values, The second subset of the plurality of possible weighting parameter values includes first, third and fourth values. The video encoding method of claim 1, wherein the distortion value is calculated by a circuit shared by multiple different encoding and decoding tools. An electronic device including: Encoder circuitry, configured to perform operations including: receiving raw primitive data of the primitive block as the current block of the current picture of the video is encoded into the bit stream; identifying a plurality of candidate bidirectional prediction locations including a center location, a first set of offset locations, and a second set of offset locations; The distortion value calculated for each of the plurality of candidate bidirectional prediction positions is calculated based on a plurality of possible weighting parameter values, wherein: (i) the distortion value calculated for the center position is calculated based on each of the plurality of possible weighting parameter values. a distortion value, (ii) calculated for the first set of offset locations based on a first subset of the plurality of possible weighted parameter values, and (iii) calculated for the second set of offset locations The distortion value is calculated based on a second subset of the plurality of possible weighting parameter values, wherein the first subset of the plurality of possible weighting parameter values is different from the second subset of the plurality of possible weighting parameter values. Subset; Selecting weighting parameter values for candidate bi-directional prediction positions based on the calculated distortion values of the plurality of candidate bi-directional prediction positions of the current block; and The current block is encoded using bidirectional prediction based on the selected weighting parameter value.