TWI829394B - Electronic device and operation method thereof - Google Patents

Abstract

An electronic device and an operation method thereof are provided. The electronic device includes a first and second decoding circuits. The electronic device is coupled to a storage device and a memory, and the storage device stores compressed data. The operation method includes the following steps: performing a first read operation to read a first sub-block from a first read address of the storage device; performing a first write operation to write the first sub-block to a first write address of the memory; performing a second read operation to read a second sub-block from a second read address of the storage device, the second read address being a sum of the first read address and the data amount of the first sub-block; performing a second write operation to write the second sub-block to a second write address of the memory; the first decoding circuit reading the first sub-block from the memory and decoding the first sub-block; and the second decoding circuit reading the second sub-block from the memory and decoding the second sub-block.

Description

Electronic device and method of operating the same

The present invention relates to electronic devices, and in particular to decompression operations of electronic devices.

Figure 1 shows a conventional electronic device 100. The electronic device 100 includes a computing circuit 110 and a storage device 120 . The storage device 120 stores compressed files (eg, compressed program codes or program instructions). When the computing circuit 110 wants to execute the program codes or program instructions, the computing circuit 110 must first decompress the file. Therefore, the decompression efficiency of the computing circuit 110 greatly affects the performance of the electronic device 100 .

In some cases, the compressed file stored in the storage device 120 is a boot image file. When the electronic device 100 is started, the computing circuit 110 reads the compressed file from the storage device 120, decompresses the compressed file, and then executes the boot code. Therefore, if the decompression performance of the computing circuit 110 is poor, the electronic device 100 will start slowly, resulting in a poor user experience.

In view of the shortcomings of the prior art, one objective of the present invention is to provide an electronic device and an operating method thereof to improve the shortcomings of the prior art.

One embodiment of the present invention provides an electronic device coupled to a storage device and a memory. The storage device stores compressed data. The electronic device includes a memory interface circuit, a decompression module and a computing circuit. The memory interface circuit is coupled to the memory. The decompression module includes a first decoding circuit and a second decoding circuit. The decompression module or the computing circuit performs the following steps: (A) perform a first read operation to read a first sub-block from a first read address of the storage device; (B) perform a a first write operation to write the first sub-block into a first write address of the memory through the memory interface circuit; (C) perform a second read operation to read from the storage device A second read address reads a second sub-block, the second read address is equal to the first read address plus a data amount of the first sub-block; and (D) performs a second write An input operation is performed to write the second sub-block into a second write address of the memory through the memory interface circuit. The decompression module performs the following steps: (E) the first decoding circuit reads the first sub-block from the memory and decodes the first sub-block; and (F) the second decoding circuit reads the first sub-block from the memory. The memory reads the second sub-block and decodes the second sub-block.

Another embodiment of the present invention provides an operating method of an electronic device. The electronic device includes a first decoding circuit and a second decoding circuit. The electronic device is coupled to a storage device and a memory. The storage device stores a compressed material. The method includes: performing a first read operation to read a first sub-block from a first read address of the storage device; performing a first write operation to write the first sub-block Enter a first write address of the memory; perform a second read operation to read a second sub-block from a second read address of the storage device, the second read address is equal to the first A read address plus a data amount of the first sub-block; a second write operation is performed to write the second sub-block into a second write address of the memory; the first decoding The circuit reads the first sub-byte from the memory block and decode the first sub-block; and, the second decoding circuit reads the second sub-block from the memory and decodes the second sub-block.

Another embodiment of the present invention provides an electronic device coupled to a storage device and a memory. The storage device stores compressed data. The electronic device includes a memory interface circuit, a decompression module and a computing circuit. The memory interface circuit is coupled to the memory. The decompression module includes a first decoding circuit and a second decoding circuit. The decompression module or the computing circuit performs the following steps: reading a first sub-block of the compressed data from the storage device; writing the first sub-block into one of the memory through the memory interface circuit a first storage space; reading a second sub-block of the compressed data from the storage device, the second sub-block being adjacent to the first sub-block in the storage device; and, through the memory interface circuit, The second sub-block is written into a second storage space of the memory, and the second storage space is not equal to the first storage space. The decompression module performs the following steps: the first decoding circuit reads the first sub-block from the first storage space and decodes the first sub-block; and the second decoding circuit reads the first sub-block from the second storage space. The space reads the second sub-block and decodes the second sub-block.

The technical means embodied in the embodiments of the present invention can improve at least one of the shortcomings of the prior art. Therefore, the present invention can improve the program execution performance and/or boot speed of the electronic device compared with the prior art.

The features, implementation and effects of the present invention are described in detail below with reference to the drawings and examples.

100,301: Electronic devices

110,320: Calculation circuit

120,303:Storage device

B1_U,B2_U,B3_U,B1_C,B2_C,B3_C,B1_CP,B2_CP,B3_CP: block

300:Embedded systems

302:Memory

310: Memory interface circuit

330: Read-only memory

340: Storage control circuit

350: Decompression module

351:Parser

352,354,356: Decoding circuit

HDR: header

FID: pre-identifier

NB: number of blocks

SSB: sub-block size

SCB1: size of the first block

SUB1: The decompressed size of the first block

SCB2: The size of the second block

SUB2: The decompressed size of the second block

SCB3: The size of the third block

SUB3: The decompressed size of the third block

PD: fill value

FTR: footnote

RID: rear identifier

B1_CP1,B1_CP2,B1_CP3,B1_CP4,B2_CP1,B2_CP2,B2_CP3,B2_CP4,B2_CP5,B3_CP1,B3_CP2,B3_CP3: sub-block

MB1, MB2, MB3, MB4, MB5, MB6: storage space

addr1, addr2: reference address

S810: Data migration procedure

S820: Decoding program

A1,A2,A3,A4: arrows

410,S420,S430,S440,S450,S460,S470,S810,S811,S812,S813,S814,S820,S821,S822,S823,S824,S825: Steps

Figure 1 shows a conventional electronic device; Figure 2 is a schematic diagram of an embodiment of original data, compressed data and aligned compressed data of the present invention; Figure 3 is a functional block diagram of an embodiment of an embedded system of the present invention; Figure 4 is a flow chart of an embodiment of the data segmentation method of the present invention; Figure 5 is a schematic diagram of an embodiment of the compressed data information file of the present invention; Figure 6 shows an embodiment of the data configuration in the memory and storage device Schematic diagram; Figure 7 is a schematic diagram showing an embodiment of the start address and end address of each sub-block in the memory and storage device; and Figure 8 is a flow chart of an embodiment of the operating method of the electronic device of the present invention.

The technical terms used in the following description refer to the idioms in the technical field. If some terms are explained or defined in this specification, the explanation or definition of these terms shall prevail.

The disclosure of the present invention includes electronic devices and operating methods thereof. Since some components included in the electronic device of the present invention may be individually known components, the following description will omit details of the known components without affecting the full disclosure and implementability of the device invention. In addition, part or all of the process of the operating method of the electronic device of the present invention may be in the form of software and/or firmware. Without affecting the full disclosure and implementability of the method invention, the following description of the method invention will focus on on the content of the steps rather than the hardware.

FIG. 2 is a schematic diagram of one embodiment of original data (ie, data before compression), compressed data, and aligned compressed data according to the present invention. The first column contains the raw data (i.e., contains the block B1_U, block B2_U and block B3_U), the second column is the compressed data after the original data is compressed (including block B1_C, block B2_C and block B3_C, corresponding to block B1_U, block B2_U and block respectively B3_U), the third column is the aligned compressed data (including block B1_CP, block B2_CP and block B3_CP, corresponding to block B1_C, block B2_C and block B3_C respectively). "Alignment" is to make the compressed data into an integer multiple of the unit length (for example, 32 bytes), which can be achieved by padding operation. If the compressed data is exactly an integer multiple of the unit length, no padding is required (i.e., the padding size is 0, such as block B2_C).

The "compressed data" referred to in the following discussion is the compressed data after alignment.

Figure 3 is a functional block diagram of an embodiment of the embedded system of the present invention. The embedded system 300 includes an electronic device 301, a memory 302 and a storage device 303. The electronic device 301 is coupled to the memory 302 and the storage device 303, and includes a memory interface circuit 310, a computing circuit 320, a read-only memory 330, a storage control circuit 340 and a decompression module 350.

In some embodiments, the electronic device 301 is a chip, the memory 302 is a dynamic random access memory (DRAM), and the storage device 303 is a flash memory or an embedded multimedia card. (embedded multimedia card, eMMC) or secure digital (secure digital, SD) memory card.

In some embodiments, the computing circuit 320 may be a circuit or electronic component with program execution capabilities, such as a central processing unit, a microprocessor, a microprocessing unit, a digital signal processor, or an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), or its equivalent circuit. The computing circuit 320 implements the functions of the electronic device 301 by executing program codes and/or program instructions.

The memory interface circuit 310 is coupled to the memory 302, and the electronic device 301 accesses the memory 302 through the memory interface circuit 310. Storage control circuit 340 is used to access storage device 303, and And the data is written into the memory 302 through the memory interface circuit 310. The decompression module 350 is coupled to the memory interface circuit 310, the computing circuit 320 and the storage control circuit 340, and is used to decompress compressed data. The computing circuit 320 is coupled to the ROM 330 and is used to execute the ROM boot code in the ROM 330 . Read-only memory booting is well known to those with ordinary knowledge in the art, and therefore will not be described in detail.

The decompression module 350 includes a decoding circuit 352, a decoding circuit 354 and a decoding circuit 356, respectively used to decode the block B1_CP, the block B2_CP and the block B3_CP in FIG. 2 . The decompression module 350 further includes a parser 351. The operation details of the decompression module 350 will be detailed below with reference to Figures 6 to 8. The parser 351 can be implemented with a logic circuit, such as a finite state machine (FSM).

The decoding circuit 352, the decoding circuit 354 and the decoding circuit 356 can perform decoding operations at the same time to shorten the overall decompression time. In an ideal situation, the decoding circuit 352 , the decoding circuit 354 and the decoding circuit 356 start decoding substantially at the same time and end decoding substantially at the same time to improve the decompression efficiency (ie, the overall decompression time required is shorter). However, because the content of the original data has no rules, if the original data is divided equally (i.e., block B1_U, block B2_U, and block B3_U are the same size), there is a high probability that the compression rate of each block is different. (That is, the required decompression time is different), resulting in the decoding circuit 352, the decoding circuit 354 and the decoding circuit 356 being unable to start decoding substantially at the same time and complete decoding substantially at the same time (for example, there is a big gap in the time point of ending the decoding) . This will result in reduced performance of the electronic device 301 because the computing circuit 320 must wait for all decoding circuits of the decompression module 350 to complete decoding. Therefore, the present invention provides a data segmentation method to improve decompression efficiency.

The following description takes the decompression module 350 including three decoding circuits as an example. However, In other embodiments, the decompression module 350 may include two, four, or more than four decoding circuits.

Figure 4 is a flow chart of an embodiment of the data segmentation method of the present invention, including the following steps.

Step S410: Treat the original data as a single block for compression, that is, compress the original data into a single block.

Step S420: Decompress the block to obtain the decompression reference time T_ref.

Step S430: Divide the decompression reference time T_ref by the number of decoding circuits N_dec (for example, 3) to obtain the target decompression time T_tar=T_ref/N_dec.

Step S440: Divide the original data into N_dec blocks (for example, as shown in Figure 2).

Step S450: Compress and decompress each block separately to obtain N_dec decompression times T_dec(k) (k=1,2,...,N_dec).

Step S460: Determine whether the ratio of the decompression time to the target decompression time (T_dec(k)/T_tar) for the N_dec blocks falls within the target range. For example, Lth<T_dec(k)/T_tar<Uth (for all k) (the lower limit Lth and the upper limit Uth are rational numbers). If yes, then end the data segmentation process (meaning that the block size determined in step S440 can ensure that all decoding circuits of the decompression module 350 complete decoding at substantially the same time or within a target time interval); if not, proceed Step S470.

Step S470: Adjust the block size. For example, if the decompression time T_dec(1) of the first block is too large (i.e., T_dec(k)/T_tar>Uth) or too small (i.e., T_dec(k)/T_tar<Lth), then reduce or increase the The amount of data in the first block.

In some embodiments, the developer or manufacturer of the electronic device 301 can control the decompression time of the decompression module 350 during actual operation by adjusting the target range (ie, adjusting the lower limit Lth and/or the upper limit Uth). For example, in actual operation, the decompression times required by the decoding circuit 352, the decoding circuit 354 and the decoding circuit 356 are Tp_dec(1), Tp_dec(2) and Tp_dec(3) respectively, then the three targets can be controlled by adjusting the target range. The decompression times Tp_dec(1), Tp_dec(2) and Tp_dec(3) are similar, so that the ratio of any two decompression times is substantially less than or equal to 1.2 (Embodiment 1) or 1.05 (Embodiment 2). The first embodiment can ensure the decompression efficiency of the decompression module 350, and the second embodiment can make the decompression module 350 have higher decompression efficiency (that is, the electronic device 301 has better performance).

Please refer to both Figure 2 and Figure 3. As mentioned above, the present invention divides the original data into multiple blocks (for example, block B1_U, block B2_U and block B3_U) in advance, and then generates compressed blocks of these blocks (for example, block B1_CP, block B3_U). Block B2_CP and Block B3_CP). When the electronic device 301 is running, multiple decoding circuits (eg, decoding circuit 352, decoding circuit 354, and decoding circuit 356) of the decompression module 350 decode the compressed blocks simultaneously to improve decompression efficiency. In order to enable multiple decoding circuits of the decompression module 350 to perform decoding operations simultaneously, the present invention further divides each compression block into multiple sub-blocks, and stores the sub-blocks in the storage device 303 in a preset configuration. . This will be further explained below through Figures 5 to 7.

FIG. 5 is a schematic diagram of an embodiment of a compressed data information file according to the present invention. The compressed data is arranged between the header HDR and the footer FTR. The header HDR and footer FTR are collectively called the information file of the compressed data. The compressed data and its information files are stored in the storage device 303 . The header HDR contains the pre-identifier FID, the number of blocks NB (in the example of Figure 2, NB=3, that is, block B1_CP, block B2_CP and block B3_CP), the sub-block size SSB (i.e., sub-area Blocky data amount), the size of the first block SCB1 (that is, the size of block B1_CP), the decompressed size of the first block SUB1 (that is, the size of block B1_U), the size of the second block SCB2 (that is, the size of block B1_U) , the size of block B2_CP), the decompressed size of the second block SUB2 (that is, the size of block B2_U), the size of the third block SCB3 (that is, the size of block B3_CP), the size of the third block decompressed The compressed size SUB3 (ie, the size of block B3_U) and padding value PD. The footnote FTR contains the post identifier RID. The electronic device 301 can find the compressed data in the storage device 303 according to the pre-identifier FID, the block number NB and the post-identifier RID.

The electronic device 301 can obtain the number of sub-blocks NSB1 (=SCB1/SSB) of block B1_CP, the number of sub-blocks NSB2 (=SCB2/SSB) of block B2_CP, and the number of sub-blocks of block B3_CP according to the header HDR. Number NSB3 (=SCB3/SSB).

Figure 6 shows a schematic diagram of an embodiment of the data configuration in the memory 302 and the storage device 303. Figure 7 shows a schematic diagram of an embodiment of the start address and end address of each sub-block in the memory 302 and the storage device 303. .

The first column of FIG. 6 shows the arrangement of the compressed data in the storage device 303 , and the second column of FIG. 6 shows the arrangement of the compressed data and the decompressed data in the memory 302 .

The table on the left side of FIG. 7 shows the start address and the end address of each sub-block in the storage device 303 , and the table on the right side of FIG. 7 shows the start address and the end address of each sub-block in the memory 302 . "addr1" and "addr2" are reference addresses in the storage device 303 and the memory 302 respectively. In some embodiments, the reference address addr1 and the reference address addr2 may be determined in advance by the developer or manufacturer of the embedded system 300 .

Please also refer to Figure 2, Figure 6 and Figure 7. In the examples of Figure 2, Figure 6 and Figure 7, block B1_CP includes four sub-blocks (sub-block B1_CP1, sub-block B1_CP2, sub-block B1_CP3 and sub-block B1_CP4, that is, the number of sub-blocks NSB1=4), block B2_CP includes five sub-blocks (sub-block B2_CP1, sub-block B2_CP2, sub-block B2_CP3, sub-block B2_CP4 and sub-area Block B2_CP5, that is, the number of sub-blocks NSB2=5), and block B3_CP includes three sub-blocks (sub-block B3_CP1, sub-block B3_CP2 and sub-block B3_CP3, that is, the number of sub-blocks NSB3=3) .

Please refer to Figure 6 and Figure 7. In the storage device 303, the sub-blocks of block B1_CP, block B2_CP and block B3_CP are arranged in the following order (from header HDR to footer FTR): sub-blocks B1_CP1, block B2_CP of block B1_CP Sub-block B2_CP1, sub-block B3_CP1 of block B3_CP, sub-block B1_CP2 of block B1_CP, sub-block B2_CP2 of block B2_CP, sub-block B3_CP2 of block B3_CP, . . .

Please refer to Figure 6 and Figure 7. In memory 302, sub-blocks of the same block are arranged together. For example, the sub-blocks of block B1_CP are arranged in storage space MB1, the sub-blocks of block B2_CP are arranged in storage space MB2, and the sub-blocks of block B3_CP are arranged in storage space MB3.

Please refer to Figure 6 and Figure 7. In the storage device 303, the sub-block B1_CP1 and the sub-block B2_CP1 are adjacent (ie, arranged consecutively, that is, the sub-block B2_CP1 immediately follows the sub-block B1_CP1); however, in the memory 302, the sub-block B1_CP1 and sub-block B2_CP1 are not arranged adjacently. In the storage device 303, the sub-block B1_CP1 and the sub-block B1_CP2 are not adjacent; however, in the memory 302, the sub-block B1_CP1 and the sub-block B1_CP2 are adjacent.

The decompression module 350 (more specifically, the parser 351) or the computing circuit 320 controls the storage control circuit 340 (eg, by changing the temporary value of the register) to sequentially read the sub-blocks from the storage device 303, and The storage control circuit 340 writes the sub-block to the memory 302 according to the header HDR control. corresponding storage space. The decoding circuit 352, the decoding circuit 354 and the decoding circuit 356 respectively read the sub-blocks and decode sub-blocks of the corresponding blocks from the storage space MB1, the storage space MB2 and the storage space MB3 through the memory interface circuit 310, and decode the sub-blocks. The resulting data is stored in the storage space MB4, storage space MB5 and storage space MB6 of the memory 302 respectively through the memory interface circuit 310. In other words, block B1_U is arranged in storage space MB4, block B2_U is arranged in storage space MB5, and block B3_U is arranged in storage space MB6. All data in storage space MB4, storage space MB5 and storage space MB6 are original data.

FIG. 8 is a flowchart of an embodiment of the operating method of the electronic device of the present invention, including a data moving process S810 and a decoding process S820. The data moving process S810 is executed by the parser 351 (by controlling the storage control circuit 340), and the decoding process S820 is executed by the decompression module 350. More specifically, while the parser 351 is executing the data moving procedure S810, the decoding circuit 352, the decoding circuit 354 and the decoding circuit 356 are respectively executing the decoding procedure S820 at the same time.

In some embodiments, if the decompression module 350 does not include the parser 351, the data moving procedure S810 is executed by the computing circuit 320.

Please refer to Figures 6~8 for the following instructions.

The data migration procedure S810 includes the following steps.

Step S811: The parser 351 or the calculation circuit 320 performs a read operation to read the target sub-block from the storage device 303 through the storage control circuit 340. When step S811 is executed for the first time, the target sub-block is the sub-block immediately following the header HDR, that is, sub-block B1_CP1 (as shown in Figure 6). In other words, the parser 351 or the calculation circuit 320 first determines the starting address of the sub-block B1_CP1 based on the header HDR (for example, first derives the size of the header HDR from the block number NB, and then adds the address of the previous identifier FID The size of the header HDR to get the starting address of sub-block B1_CP1), Then, the starting address (addr1) of the sub-block B1_CP1 is used as the read address to read the data amount of the sub-block size SSB from the storage device 303 through the storage control circuit 340 (ie, the read target sub-block).

Step S812: The parser 351 or the calculation circuit 320 performs a write operation to store the target sub-block to the target storage space in the memory 302 through the memory interface circuit 310, and the target storage space corresponds to the target sub-block to which it belongs. block.

Continuing from the previous paragraph, the parser 351 or the calculation circuit 320 first determines the block to which the target sub-block belongs based on the header HDR. As mentioned above, the parser 351 or the calculation circuit 320 first obtains the number of sub-blocks (NSB1, NSB2, NSB3) of each block according to the header HDR, and then the parser 351 or the calculation circuit 320 obtains the number of sub-blocks NB according to the header HDR. and the number of sub-blocks (NSB1, NSB2, NSB3) to obtain the distribution of sub-blocks in the storage device 303. Therefore, the parser 351 or the calculation circuit 320 can determine the block to which the target sub-block belongs according to the header HDR.

Continuing from the previous paragraph, after knowing the block to which the target sub-block belongs, the parser 351 or the calculation circuit 320 then obtains the size of the block to which the target sub-block belongs (ie, SCB1, SCB2 or SCB3) according to the header HDR, and stores it in the memory. The storage space corresponding to the block (ie, storage space MB1, storage space MB2, or storage space MB3) is determined or found in the body 302. Therefore, the parser 351 or the calculation circuit 320 can determine the write address (addr2, ie, the starting address of the storage space MB1) of the sub-block B1_CP1 in the memory 302, and then write the sub-block B1_CP1 into the write address. address. In other words, when the target sub-block is sub-block B1_CP1, step S811 and step S812 correspond to arrow A1 in FIG. 6 and FIG. 7 .

Step S813: The parser 351 or the calculation circuit 320 determines whether there are still sub-blocks to be processed according to the header HDR. If yes, the process proceeds to step S814; if no (that is, for the examples of FIGS. 6 and 7 , the parser 351 or the calculation circuit 320 has finished processing the last file in the storage device 303 A sub-block B2_CP5), the process ends.

Step S814: The parser 351 or the calculation circuit 320 uses the subblock immediately below the target subblock as the target subblock, and then returns to step S811. Specifically, step S814 updates the target sub-block to determine the read address of the next round of read operation (ie, step S811) and the write address of the write operation (ie, step S812). Following the above example, because the current target sub-block is sub-block B1_CP1, the next target sub-block is sub-block B2_CP1; therefore, the new read address is the starting address of sub-block B2_CP1 (addr1+SSB ), and the new write address is the starting address of storage space MB2 (addr2+4*SSB). The starting address of sub-block B2_CP1 (addr1+SSB) is equal to the starting address of sub-block B1_CP1 (addr1) plus the sub-block size SSB.

The parser 351 or the calculation circuit 320 repeats the steps of the data moving procedure S810 to move more sub-blocks (ie, perform data movement corresponding to arrow A2, arrow A3, arrow A4, ... in sequence). It should be noted that sub-block B1_CP1 and sub-block B2_CP1 are adjacent in the storage device 303, but not adjacent in the memory 302; in other words, in the memory 302, the starting address of the sub-block B2_CP1 (addr2 +4*SSB) is not equal to the starting address (addr2) of sub-block B1_CP1 plus the sub-block size SSB.

When the sub-block B1_CP1, the sub-block B2_CP1 and the sub-block B3_CP1 start to be stored in the memory 302, the decoding circuit 352, the decoding circuit 354 and the decoding circuit 356 can start to store data from the storage space MB1, the storage space MB2 and the storage space respectively. MB3 reads the sub-block and decodes the sub-block, that is, executes the decoding procedure S820. The decoding circuit 352 , the decoding circuit 354 and the decoding circuit 356 obtain the starting addresses of the storage space MB1 , the storage space MB2 and the storage space MB3 from the parser 351 or the calculation circuit 320 . The decoding procedure S820 includes the following steps.

X

NB)。以圖6為例，解碼電路352(解碼電路354或解碼電路356)從儲存空間MB1(儲存空間MB2或儲存空間MB3)讀取目標子區塊。 Step S821: The X decoding circuit reads the target sub-block from the X storage space of the memory 302 (1

X

NB). Taking FIG. 6 as an example, the decoding circuit 352 (decoding circuit 354 or decoding circuit 356) reads the target sub-block from the storage space MB1 (storage space MB2 or storage space MB3).

Step S822: The X decoding circuit decodes the target sub-block to obtain decoded data. More specifically, decoding circuit 352 (decoding circuit 354 or decoding circuit 356) decodes the target sub-block and generates decoded data (ie, partial data of block B1_U, block B2_U, and block B3_U).

Step S823: The X decoding circuit stores the decoded data into a storage space of the memory. Taking FIG. 6 as an example, the decoding circuit 352 (the decoding circuit 354 or the decoding circuit 356) stores the decoded data into the storage space MB4 (the storage space MB5 or the storage space MB6). In some embodiments, the parser 351 or the calculation circuit 320 performs the processing according to the contents of the header HDR (i.e., the first block decompressed size SUB1, the second block decompressed size SUB2, and the third block decompressed size SUB2). The last size SUB3) configures the storage space MB4, the storage space MB5 and the storage space MB6 in the memory 302 (that is, determines the addresses of the storage space MB4, the storage space MB5 and the storage space MB6 in the memory 302), and sets the storage space The starting addresses of MB4, storage space MB5 and storage space MB6 are sent to the decoding circuit 352, the decoding circuit 354 and the decoding circuit 356.

Step S824: The X decoding circuit determines whether there are still sub-blocks to be processed. In detail, the decoding circuit 352, the decoding circuit 354 and the decoding circuit 356 respectively check whether the sub-blocks in the storage space MB1, the storage space MB2 and the storage space MB3 have been processed. If yes, the process proceeds to step S825; if no (that is, for the example of FIG. 6, the decoding circuit 352 (decoding circuit 354 or decoding circuit 356) has finished processing the storage space MB1 (storage space MB2 or storage space MB3) all sub-blocks), the process ends.

Step S825: The X-th decoding circuit uses the sub-block immediately below the target sub-block as the target sub-block. In other words, as shown in FIG. 6 and FIG. 7 , the decoding circuit 352 (the decoding circuit 354 or the decoding circuit 356) continuously reads the sub-blocks in the storage space MB1 (the storage space MB2 or the storage space MB3). That is to say, in step S825, the X-th decoding circuit adds the current read address (used in step S821) to the sub-block size SSB as a new read address, and then executes step S821.

As mentioned above, since the size of the block has been appropriately designed in advance (i.e., the process of FIG. 4 ), the time points at which the decoding circuit 352 , the decoding circuit 354 and the decoding circuit 356 complete the decoding process S820 are similar (i.e., the block B1_CP , the time points at which block B2_CP and block B3_CP are decoded are similar, which is equivalent to the time points at which storage space MB4, storage space MB5 and storage space MB6 are filled up.)

To sum up, the block in this case is divided into multiple sub-blocks, which is conducive to simultaneous decoding by multiple decoding circuits and can improve the performance of the electronic device 301. Furthermore, by carefully arranging the positions of the sub-blocks in the storage device 303 and the memory 302, this project can read from consecutive addresses in the storage device 303 and the memory 302 respectively when executing the data moving procedure S810 and the decoding procedure S820. Get information. Compared with reading data in jumps, reading data from consecutive addresses can increase the data reading speed.

The compressed data discussed above may be data generated based on the xz compression method. The xz compression method is well known to those with ordinary knowledge in the technical field, and therefore will not be described in detail.

The compressed data discussed above may be data required for the operation of the electronic device 301 (eg, program code or program instructions). In some embodiments, the compressed data is part of the startup process code of the electronic device 301 (executed by the computing circuit 320). For example, the boot process code includes Miniboot, U-boot and Kernel, and the compressed data is U-boot and Kernel. After execution After the read-only memory activation code, the computing circuit 320 first executes Miniboot to activate the memory interface circuit 310, the storage control circuit 340 and the decompression module 350, and then executes the process of FIG. 8 to decode U-boot and Kernel. Miniboot, U-boot and Kernel are well known to those with ordinary knowledge in the technical field, so they will not be described in detail.

Although the embodiments of the present invention are described above, these embodiments are not intended to limit the present invention. Those skilled in the art may make changes to the technical features of the present invention based on the explicit or implicit contents of the present invention. All these changes may fall within the scope of patent protection sought by the present invention. In other words, the patent protection scope of the present invention must be determined by the patent application scope of this specification.

S810,S811,S812,S813,S814,S820,S821,S822,S823,S824,S825: Steps

Claims (19)

An electronic device is coupled to a storage device and a memory. The storage device stores compressed data. The electronic device includes: a memory interface circuit coupled to the memory; a decompression module including a first decoding circuit and a second decoding circuit; and a calculation circuit; wherein the decompression module or the calculation circuit performs the following steps: (A) performing a first read operation to read a first read from the storage device The address reads a first sub-block; (B) performs a first write operation to write the first sub-block into a first write address of the memory through the memory interface circuit; (C) ) performs a second read operation to read a second sub-block from a second read address of the storage device, the second read address being equal to the first read address plus the first sub-area A data amount of the block; and (D) performing a second write operation to write the second sub-block into a second write address of the memory through the memory interface circuit; wherein, the decompression The module performs the following steps: (E) the first decoding circuit reads the first sub-block from the memory and decodes the first sub-block; and (F) the second decoding circuit reads the first sub-block from the memory. Get the second sub-block and decode the second sub-block; Wherein, the compressed data includes a first block and a second block, the first sub-block is a part of the first block, the second sub-block is a part of the second block, and the third sub-block is a part of the second block. A decoding circuit requires a first decompression time to decode the first block, the second decoding circuit requires a second decompression time to decode the second block, and the first decompression time and the second decompression time are The ratio is essentially less than or equal to 1.2. An electronic device is coupled to a storage device and a memory. The storage device stores compressed data. The compressed data includes a first block and a second block. The electronic device includes: a memory interface circuit, coupled to Connect the memory; a decompression module, including a first decoding circuit and a second decoding circuit; and a calculation circuit; wherein, the decompression module or the calculation circuit performs the following steps: (A) execute a first a read operation to read a first sub-block of the first block from a first read address of the storage device; (B) perform a first write operation to read through the memory interface circuit Write the first sub-block to a first write address of the memory; (C) perform a second read operation to read the second block from a second read address of the storage device a second sub-block, the second read address is equal to the first read address plus a data amount of the first sub-block; and (D) perform a second write operation to pass the memory The body interface circuit writes the second sub-block to a second write address of the memory, wherein the first sub-block is part of the first block and the second sub-block is the second part of the block, the second write address is not equal to the first write address plus the data amount of the first sub-block, so that Other sub-blocks of the first block are written between the first address and the second address so that all sub-blocks of the first block are continuously written into the memory from the first write address. ; wherein, the decompression module performs the following steps: (E) the first decoding circuit reads the first sub-block from the memory and decodes the first sub-block; and (F) the second decoding The circuit reads the second sub-block from the memory and decodes the second sub-block. If the electronic device of claim 2 is used, the storage device further stores an information file of the compressed data, and the decompression module or the computing circuit obtains the first reading address and the second reading address based on the information file. address. For example, the electronic device of claim 3, wherein the information file records the data amount of the first sub-block, and the decompression module or the calculation circuit determines the data amount based on the first reading address and the data amount. Second read address. The electronic device of claim 3, wherein the decompression module or the computing circuit further performs the following steps: performing a third read operation to read a third sub-code from a third read address of the storage device. block, the third sub-block is part of the first block, and the second read address is between the first read address and the third read address; and performing a third write The operation is to write the third sub-block into a third write address of the memory through the memory interface circuit. The electronic device of claim 5, wherein the third writing address is equal to the first writing address plus the data amount of the first sub-block. The electronic device of claim 2, wherein the first decoding circuit requires a first decompression time to decode the first block, the second decoding circuit requires a second decompression time to decode the second block, and the second decoding circuit requires a second decompression time to decode the second block. The ratio of a decompression time to the second decompression time is substantially less than or equal to 1.2. The electronic device of claim 2, wherein the computing circuit executes a startup process code of the electronic device, and the compressed data is part of the startup process code. The electronic device of claim 8, wherein the part is a first part of the startup process code, and the computing circuit executes a second part of the startup process code to activate the memory interface circuit, the decompression module or the The computing circuit performs the steps (A) to (F) after the memory interface circuit is activated. An operating method of an electronic device. The electronic device includes a first decoding circuit and a second decoding circuit. The electronic device is coupled to a storage device and a memory. The storage device stores compressed data. The method includes: executing a a first read operation to read a first sub-block from a first read address of the storage device; a first write operation to write the first sub-block into a memory a first write address; performing a second read operation to read a second sub-block from a second read address of the storage device, the second read address being equal to the first read address plus An amount of data of the first sub-block; performing a second write operation to write the second sub-block to a second write address of the memory; The first decoding circuit reads the first sub-block from the memory and decodes the first sub-block; and the second decoding circuit reads the second sub-block from the memory and decodes the second sub-block. Block; wherein, the compressed data includes a first block and a second block, the first sub-block is a part of the first block, and the second sub-block is a part of the second block , the first decoding circuit needs a first decompression time to decode the first block, and the second decoding circuit needs a second decompression time to decode the second block. The first decompression time is the same as the second decompression time. The compression time ratio is substantially less than or equal to 1.2. An operating method of an electronic device. The electronic device includes a first decoding circuit and a second decoding circuit. The electronic device is coupled to a storage device and a memory. The storage device stores compressed data. The compressed data includes a first decoding circuit. A block and a second block, the method includes: performing a first read operation to read a first sub-block of the first block from a first read address of the storage device; executing a first write operation to write the first sub-block to a first write address of the memory; a second read operation to read from a second read address of the storage device A second sub-block of the second block, the second read address is equal to the first read address plus a data amount of the first sub-block; a second write operation is performed to write the A second sub-block is written to a second write address of the memory, wherein the first sub-block is part of the first block and the second sub-block is part of the second block, The second write address is not equal to the first write address plus the data amount of the first sub-block, so as to write other sub-blocks of the first block to the first Between the address and the second address, all sub-blocks of the first block are continuously written into the memory from the first write address; the first decoding circuit reads the first sub-block from the memory. block and decode the first sub-block; and the second decoding circuit reads the second sub-block from the memory and decodes the second sub-block. For example, the method of claim 11, wherein the storage device further stores an information file of the compressed data, the method further includes: reading the information file, and obtaining the first read address and the second read address based on the information file. Get the address. For example, the method of claim 12, wherein the information file records the data amount of the first sub-block, the method further includes: determining the second reading address based on the first reading address and the data amount. The method of claim 12, wherein the method further includes: performing a third read operation to read a third sub-block from a third read address of the storage device, the third sub-block is A portion of the first block, and the second read address is between the first read address and the third read address; and performing a third write operation to write the third sub-block Write to one of the third write addresses in this memory. The method of claim 14, wherein the third writing address is equal to the first writing address plus the data amount of the first sub-block. The method of claim 11, wherein the first decoding circuit requires a first decompression time to decode the first block, the second decoding circuit requires a second decompression time to decode the second block, and the first decoding circuit requires a second decompression time to decode the second block. The ratio of the decompression time to the second decompression time is substantially less than or equal to 1.2. An electronic device is coupled to a storage device and a memory. The storage device stores compressed data. The compressed data includes a first block and a second block. The electronic device includes: a memory interface circuit, coupled to Connect to the memory; a decompression module, including a first decoding circuit and a second decoding circuit; and a calculation circuit; wherein, the decompression module or the calculation circuit performs the following steps: reading from the storage device A first sub-block of the first block of compressed data; writing the first sub-block into a first storage space of the memory through the memory interface circuit; reading the compressed data from the storage device a second sub-block of the second block of data, the second sub-block being immediately adjacent to the first sub-block in the storage device; and writing the second sub-block through the memory interface circuit A second storage space of the memory, wherein the second storage space is not equal to the first storage space, the first sub-block is part of the first block, and the second sub-block is the second part of the block, the second sub-block is not immediately adjacent to the first sub-block in the memory, so that other sub-blocks of the first block are written to the first sub-block and the second sub-block. Between sub-blocks, all sub-blocks of the first block are continuously written into the memory from the first sub-block; wherein, the decompression module performs the following steps: The first decoding circuit reads the first sub-block from the first storage space and decodes the first sub-block; and the second decoding circuit reads the second sub-block from the second storage space, and decode the second sub-block. If the electronic device of claim 17 is used, the storage device further stores an information file of the compressed data, and the decompression module or the computing circuit obtains the first sub-block and the second sub-area based on the information file. The address of the block in the storage device; the decompression module obtains the size of the first sub-block based on the information file, and the decompression module or the calculation circuit obtains the size of the first sub-block based on the address of the first sub-block and The size determines the address of this second sub-block. The electronic device of claim 18, wherein the decompression module further performs the following steps: reading a third sub-block of the compressed data from the storage device, the third sub-block being a portion of the first block a portion, and the third sub-block is not immediately adjacent to the first sub-block in the storage device; and writing the third sub-block into the first storage space of the memory through the memory interface circuit.