TWI829353B - Package substrate and fabrication method thereof - Google Patents

Abstract

A packaging substrate is provided, in which first and second circuit structures are respectively disposed on two opposite surfaces of a core layer, and first and second conductive through holes is formed on the second circuit structure via penetrating the core layer, so as to conductive vias in the second circuit structure are replaced, the first conductive through holes are electrically connected to the second circuit structure, and the second conductive through holes are electrically connected to the first and second circuit structure. Therefore, a transmission path of signal can be effectively shortened to improve the efficiency of the signal transmission through the first and second conductive through holes.

Description

Packaging substrate and manufacturing method thereof

The present invention relates to a semiconductor packaging technology, and in particular to an asymmetric packaging substrate and a manufacturing method thereof.

With the development of industrial applications, in recent years it has gradually moved towards 5G high-frequency communications, augmented reality (AR), virtual reality (VR), etc. Therefore, there is a greater need to develop packaging technology for high-end semiconductors. , to be used in semiconductor flip-chip packaging or multi-chip packaging such as artificial intelligence (AI) chips, high-end chips, multi-chip, etc. Under this packaging demand, the packaging size is bound to become larger and larger, and the number of stacks is also increasing. The higher the number, the more circuit designs are designed in the direction of high density, fine line spacing, and high number of electrical connection points to meet the packaging requirements of the upper chip.

FIG. 1 is a schematic cross-sectional view of a conventional packaging substrate 1 . As shown in FIG. 1 , the packaging substrate 1 forms a circuit build-up structure 12 on the opposite first surface 10 a and the second surface 10 b of the core layer 10 , wherein the core layer 10 has a structure connecting the first and second surfaces. The conductive vias 11 on the surfaces 10a and 10b, and the circuit build-up structure 12 has at least one dielectric layer 120, a circuit layer 121 disposed on the dielectric layer 120, and a circuit layer 121 disposed in the dielectric layer 120 and electrically The conductive blind hole 122 connects the circuit layer 121 and the conductive through hole 11 . Also, the line A solder mask layer 13 can be formed on the circuit layer structure 12, and a plurality of openings 130 exposing the circuit layer 121 are formed on the solder mask layer 13, and a surface treatment layer 14 is formed for subsequent external connection of other electronic components.

However, in the conventional package substrate 1, when transmitting signals, the conductive through holes 11 and the conductive blind holes 122 need to be used as the upper and lower conductive paths. Therefore, when the number of circuit layers 121 increases, the conductive blind holes between the layers increase. The greater the number of connections in the holes 122, the longer the signal transmission path will be, resulting in poorer signal transmission efficiency.

Furthermore, the conductive via 11 is an electrical connection pad (land) 110 on the core layer 10, which occupies a large area of the first surface 10a and the second surface 10b of the core layer 10, so it is difficult to fabricate the circuit layer. 121, it is necessary to match the specifications of the electrical connection pads 110 of the conductive vias 11 (such as line width/line spacing), so it is difficult to manufacture the circuit layer 121 that meets the specifications of fine pitch/fine lines, etc., making the packaging substrate 1 impossible to configure. Ultra-Fine Pitch wiring specifications make it impossible to externally connect miniaturized semiconductor chips with multiple contacts, and if miniaturized semiconductor chips with multiple contacts are externally connected, the yield of the end product will be poor.

Therefore, how to overcome the various problems of the above-mentioned conventional technologies has become an urgent problem that the industry needs to overcome.

In view of the deficiencies of the above-mentioned conventional technologies, the present invention provides a packaging substrate, which includes: a core layer having opposite first and second surfaces, and the first and second surfaces of the core layer respectively have The first inner circuit layer and the second inner circuit layer; the insulating layer is combined on the first surface of the core layer to cover the first inner circuit layer; the first circuit structure is provided on the insulating layer; the second The circuit structure is provided on the second surface of the core layer; the first conductive through hole is provided in the second circuit structure and the core layer to electrically connect the first inner circuit layer and the second inner circuit layer. The circuit layer and the second circuit junction structure; and a second conductive through hole is provided in the second circuit structure, the core layer and the insulating layer to electrically connect the first circuit structure, the first inner circuit layer and the second inner circuit layer. and the second circuit structure.

The invention further provides a method for manufacturing a packaging substrate, which includes: sequentially forming a first circuit structure, an insulating layer and a core layer on a carrier, wherein the core layer has opposite first and second surfaces, and There are first and second inner circuit layers on the first surface and the second surface respectively, so that the core layer is bonded to the insulating layer on its first surface; and on the second surface of the core layer, different depths are formed. The first through hole and the second through hole, so that the first inner circuit layer is exposed to the first through hole, and the first circuit structure is exposed to the second through hole; forming a second circuit structure on the second surface of the core layer , and form a first conductive through hole in the first through hole, so that the first conductive through hole electrically connects the first inner circuit layer, the second inner circuit layer and the second circuit structure, and form a second conductive through hole in the first through hole. In the second through hole, the second conductive through hole is electrically connected to the first circuit structure, the first inner circuit layer, the second inner circuit layer and the second circuit structure; and the carrier is removed.

In the aforementioned packaging substrate and its manufacturing method, the first circuit structure includes at least a first dielectric layer, a first circuit layer disposed on the first dielectric layer and electrically connected to the second conductive through hole, and A plurality of conductive blind holes located in the first dielectric layer and electrically connected to the first circuit layer. Further, a pattern circuit layer is formed on the carrier, and the first circuit structure is electrically connected to the pattern circuit layer through the conductive blind hole. Therefore, the packaging substrate may include a circuit layer disposed on the first circuit structure and electrically connected to the conductive blind hole. The pattern circuit layer that is electrically connected to the conductive blind hole.

In the aforementioned packaging substrate and its manufacturing method, the second circuit structure includes a second dielectric layer and a second circuit layer disposed on the second dielectric layer and electrically connected to the first and second conductive through holes. . For example, the second circuit layer is integrally formed with the first and second conductive through holes.

It can be seen from the above that in the packaging substrate and its manufacturing method of the present invention, inter-layer electrical connection is mainly performed through first and second conductive vias of different depths, so that the second conductive vias replace the insulating layer and the second dielectric Therefore, compared with the conventional technology, the packaging substrate of the present invention can reduce the number of conductive blind holes between layers, greatly shortening the signal transmission path, thereby improving the efficiency of signal transmission.

Furthermore, by directly manufacturing the first and second inner circuit layers on the core layer, when manufacturing the first circuit layer and the second circuit layer, smaller copper thicknesses and processes of different metal layers can be produced. lines, so compared with the conventional technology, the packaging substrate of the present invention is conducive to forming the first circuit layer and the second circuit layer with extremely small line width/line spacing, so that the packaging substrate has ultra-fine pitch wiring specifications for effective external connection. Miniaturized semiconductor chips with multiple contacts can significantly improve the yield of end products.

1,2:Package substrate

10,20:Core layer

10a,20a: first surface

10b,20b: Second surface

11: Conductive vias

110: Electrical connection pad

12:Line layer structure

120:Dielectric layer

121: Line layer

122,214:Conductive blind via

13: Solder mask

130:Opening

14:Surface treatment layer

2a:Substrate structure

201: First inner line layer

202: Second inner line layer

21: First line structure

210: First dielectric layer

211: First line layer

212:Insulation layer

213:Pattern line layer

22: Second line structure

22a: Metal layer

220: Second dielectric layer

221: Second line layer

231: First through hole

232: Second through hole

24a: First conductive hole

24b: Second conductive hole

241:First piercing

242: Second piercing

25: First solder mask

250:First opening

26: Second solder mask layer

260: Second opening

27,28:Surface treatment layer

9: Bearing piece

9a: first side

9b: Second side

91:Plate body

d1,d2: depth

FIG. 1 is a schematic cross-sectional view of a conventional packaging substrate.

2A to 2H are schematic cross-sectional views of the manufacturing method of the packaging substrate of the present invention.

3A to 3B are schematic cross-sectional views of another method of the manufacturing process of FIGS. 2C to 2D.

The following describes the implementation of the present invention through specific embodiments. Those familiar with the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

It should be noted that the structures, proportions, sizes, etc. shown in the drawings attached to this specification are only used to coordinate with the content disclosed in the specification for the understanding and reading of those familiar with the art, and are not used to limit the implementation of the present invention. limiting conditions, so it has no technical substantive significance, any structural modification, proportion Changes in the relationship or adjustments in size should still fall within the scope of the technical content disclosed in the present invention without affecting the effects that can be produced and the purposes that can be achieved by the present invention. At the same time, terms such as "above", "first", "second", and "a" cited in this specification are only for convenience of description and are not used to limit the scope of the present invention. , changes or adjustments in their relative relationships, provided there is no substantial change in the technical content, shall also be deemed to be within the scope of the present invention.

2A to 2G are schematic cross-sectional views of the manufacturing method of the packaging substrate 2 of the present invention.

As shown in Figure 2A, a bearing member 9 is provided, which has opposite first sides 9a and second sides 9b. Next, a pattern circuit layer 213 is formed on the first side 9a and the second side 9b of the carrier 9 .

In this embodiment, the carrier 9 is a temporary carrier plate, and its plate body 91 can be an organic polymer plate such as Bismaleimide triazine (BT) or the like. Copper foil substrate. For example, the carrier 9 is a copper foil substrate, and a patterning process is performed on the copper foil to form the pattern circuit layer 213 . It should be understood that there are many types of temporary carrier plates, such as metal plates of aluminum, copper or stainless steel, and plates made of prepregs with metal surfaces.

As shown in FIG. 2B , a first circuit structure 21 is formed on the first side 9a and the second side 9b of the carrier 9 respectively, wherein the first circuit structure 21 includes at least a first dielectric layer 210 , the first circuit layer 211 provided on the first dielectric layer 210, and a plurality of conductive blind holes 214 located in the first dielectric layer 210 and electrically connecting the first circuit layer 211 and the pattern circuit layer 213. .

In this embodiment, the material of the first dielectric layer 210 includes, for example, polybenzoxazole (PBO), polyimide (PI), prepreg (PP) , epoxy, benzocyclobutene (BCB) or other suitable materials, and the first circuit layer 211 and the conductive blind hole 214 are made of copper or other metals.

Furthermore, the number of layers of the first circuit layer 211 of the first circuit structure 21 can be increased as required and is not limited to a single layer in the figure.

As shown in FIGS. 2C to 2D , a plurality of core layers 20 , a plurality of insulating layers 212 and a plurality of second dielectric layers 220 having metal layers 22 a are provided, and the plurality of core layers 20 , the plurality of insulating layers 212 and the plurality of second dielectric layers 22 a having metal layers are provided. The second dielectric layer 220 of 22a is symmetrically formed on the first circuit structure 21 in a lamination manner, so that the plurality of insulating layers 212 are combined with the first circuit structure 21, wherein the core layer 20 has an opposite first circuit structure 21. The surface 20a and the second surface 20b enable the core layer 20 to combine the insulating layer 212 with the first surface 20a and the second dielectric layer 220 with the second surface 20b, and the metal layer 22a is located on the outermost side.

In this embodiment, the core layer 20 has a single core layer specification, and a first inner circuit layer 201 and a second inner circuit layer 202 are respectively arranged on the first surface 20a and the second surface 20b of the core layer 20 , and the core layer 20 has a first through hole 231 and a second through hole 232 that connect the first surface 20a and the second surface 20b and have different depths. For example, machine drilling or other methods are used to form the first through hole 231 and the second through hole 232, and the first through hole 231 penetrates the second inner circuit layer 202 but does not penetrate the first inner circuit layer 201, and The second through hole 232 penetrates the first inner circuit layer 201 and the second inner circuit layer 202 .

Furthermore, the insulating layer 212 is a dielectric layer, such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), epoxy resin (Epoxy), benzocyclobutene (BCB) or other dielectric materials.

In addition, the materials of the second dielectric layer 220 include, for example, polybenzoxazole (PBO), polyimide (PI), prepreg (PP), epoxy resin (Epoxy), benzocyclobutene (BCB for short) or other suitable materials, and the material of the metal layer 22a is copper or other metal materials.

As shown in FIG. 2E , first through holes 241 and second through holes 242 with different depths are formed on the metal layer 22 a corresponding to the first through holes 231 and the second through holes 232 , so that the first inner circuit layer 201 is exposed at the first through hole 241 , and the first circuit layer 211 is exposed at the second through hole 242 .

In this embodiment, laser drilling is used to form the first through hole 241 and the second through hole 242, and the depth d1 of the first through hole 241 is smaller than the depth d2 of the second through hole 242. It should be understood that the depths d1 and d2 of the first through hole 241 and the second through hole 242 can be adjusted as required.

Furthermore, by first making the first through hole 231 and the second through hole 232, it is easier to align the first through hole 241 and the second through hole 242 when making the first through hole 241 and the second through hole 242. It should be understood that the production of the first through holes 231 and the second through holes 232 of the core layer 20 can also be omitted, as shown in FIG. 3A to FIG. 3B , in order to laminate the plurality of core layers 20 and the plurality of insulating layers 212 After forming the first through hole 241 and the second through hole 242 after forming the second dielectric layer 220 with the metal layer 22a, the process steps and time can be saved, thereby reducing the production cost.

As shown in FIG. 2F, the metal layer 22a is used as a seed layer to perform a patterning process to form a second circuit layer 221 on the second dielectric layer 220, so that the second dielectric layer 220 is connected to the second dielectric layer 220. The circuit layer 221 serves as the second circuit structure 22, and a first conductive through hole 24a is formed in the first through hole 241 to electrically connect the first inner circuit layer 201, the second inner circuit layer 202 and the second circuit layer 221. , and a second conductive through hole 24b electrically connecting the first circuit layer 211, the first inner circuit layer 201, the second inner circuit layer 202 and the second circuit layer 221 is formed in the second through hole 242.

In this embodiment, the second circuit layer 221 is integrally formed with the first and second conductive through holes 24a and 24b. For example, the metal layer 22a is used as a seed layer, and a metal material is electroplated on the metal layer 22a and in the first and second through holes 241, 242, so that the metal material serves as the second circuit layer 221, the first and second circuit layers 221, and the first and second through holes 241, 242. Two conductive holes 24a, 24b.

Furthermore, the number of wiring layers on the first surface 20a and the second surface 20b of the core layer 20 is different to form an asymmetric substrate structure 2a. For example, the number of wiring layers on the first surface 20a of the core layer 20 is three (including the first inner circuit layer 201, the first circuit layer 211 and the pattern circuit layer 213), which is more than the second wiring layer of the core layer 20. The number of two wiring layers on the surface 20b (ie, the second inner circuit layer 202 and the second circuit layer 221).

In addition, the first conductive through hole 24a and the second conductive through hole 24b are both disposed in the second circuit structure 22, so the second circuit structure 22 can be made with multiple second circuit layers 221 as required, and then use the first circuit structure 22 The conductive through holes 24a and the second conductive through holes 24b are connected between the second circuit layers 221.

In addition, the length of the signal transmission path formed by the first conductive through hole 24a is smaller than the length of the signal transmission path formed by the second conductive through hole 24b. It should be understood that the length of the signal transmission path formed by the first conductive through hole 24a and the second conductive through hole 24b can be adjusted arbitrarily according to the depths d1 and d2 of the first through hole 241 and the second through hole 242.

As shown in FIG. 2G , the carrier 9 is removed to obtain a plurality of substrate structures 2 a.

As shown in FIG. 2H , a first solder mask layer 25 and a second solder mask layer 26 are formed on the surfaces of the first dielectric layer 210 and the second dielectric layer 220 respectively, and on the first solder mask layer 25 and A plurality of first openings 250 and second openings 260 are respectively formed on the second solder resist layer 26 so that the pattern circuit layer 213 exposes the first openings 250 and the second circuit layer 221 exposes the third opening. Two openings 260 are provided to obtain the packaging substrate 2 with an asymmetric wiring configuration.

In this embodiment, surface treatment layers 27 and 28 can be formed on the pattern circuit layer 213 in the first opening 250 and the second circuit layer 221 in the second opening 260 for subsequent processes. Electronic components such as semiconductor chips are connected to the pattern circuit layer 213 of the first opening 250, and the second opening 250 is connected to an electronic component such as a semiconductor chip. Solder balls (not shown) are combined with the second circuit layer 221 of the hole 260 to be disposed on a circuit board (not shown). For example, the material forming the surface treatment layers 27 and 28 is nickel, palladium, gold, tin or one of the groups thereof.

Furthermore, the number of wiring layers on the first surface 20a and the second surface 20b of the core layer 20 can be adjusted according to needs to present the package substrate 2 with different forms of asymmetric wiring configurations.

Therefore, the manufacturing method of the present invention performs inter-layer electrical connection through the first and second conductive vias 24a and 24b of different depths, so that the second conductive via 24b replaces the insulating layer 212 and the second dielectric layer 220 Therefore, compared with the conventional technology, the packaging substrate 2 of the present invention does not need to make conductive blind holes in the insulating layer 212 to reduce the number of conductive blind holes 214 between layers and improve the signal transmission path. Significantly shortened, thus improving the efficiency of signal transmission.

Furthermore, the first and second inner circuit layers 201 and 202 are directly formed on the core layer 20, so that when the first circuit layer 211 and the second circuit layer 221 are produced, the copper thickness and process of the metal layer 22a can be different. To produce finer circuits, compared with the conventional technology, the packaging substrate 2 of the present invention is conducive to forming the first circuit layer 211 and the second circuit layer 221 with extremely small line width/line spacing, so that the packaging substrate 2 has ultra-fine features. Ultra-Fine Pitch wiring specifications can effectively connect miniaturized semiconductor chips with multiple contacts, and can greatly improve the yield of end products.

The present invention also provides a packaging substrate 2, which includes: a core layer 20, an insulating layer 212, a first circuit structure 21, a second circuit structure 22, a plurality of first conductive through holes 24a and a plurality of second conductive through holes 24b.

The core layer 20 has an opposite first surface 20a and a second surface 20b, and the first surface 20a and the second surface 20b of the core layer 20 have a first inner circuit layer 201 and a second inner circuit layer respectively. 202.

The insulating layer 212 is combined on the first surface 20a of the core layer 20 to cover the first inner circuit layer 201.

The first circuit structure 21 is provided on the insulating layer 212 .

The second circuit structure 22 is disposed on the second surface 20b of the core layer 20 .

The first conductive vias 24a are disposed in the second circuit structure 22 and the core layer 20 to electrically connect the first inner circuit layer 201, the second inner circuit layer 202 and the second circuit structure. 22 but is not electrically connected to the first circuit structure 21 .

The second conductive through holes 24b are disposed in the second circuit structure 22, the core layer 20 and the insulating layer 212 to electrically connect the first circuit structure 21, the first inner circuit layer 201, and the insulating layer 212. The second inner circuit layer 202 and the second circuit structure 22 .

In one embodiment, the first circuit structure 21 includes at least a first dielectric layer 210, is disposed on the first dielectric layer 210 but is embedded in the insulating layer 212, and is electrically connected to the first dielectric layer 210. The first circuit layer 211 of the two conductive vias 24b and a plurality of conductive blind holes 214 located in the first dielectric layer 210 and electrically connected to the first circuit layer 211. Furthermore, a pattern circuit layer 213 disposed on the first circuit structure 21 but embedded in the first dielectric layer 210 and electrically connected to the conductive blind hole 214 may be included.

In one embodiment, the second circuit structure 22 includes a second dielectric layer 220 and a third conductive hole disposed on the second dielectric layer 220 and electrically connected to the first and second conductive through holes 24a, 24b. Second line layer 221. For example, the second circuit layer 221 is integrally formed with the first and second conductive through holes 24a and 24b.

To sum up, the electronic package and its manufacturing method of the present invention are electrically connected between layers through first and second conductive vias of different depths, so that the second conductive via replaces the insulating layer and the second intermediary. Because of the conductive blind holes in the electrical layer, the packaging substrate of the present invention can reduce the number of conductive blind holes between layers, greatly shortening the signal transmission path, thereby improving the signal transmission efficiency.

Furthermore, by directly manufacturing the first and second inner circuit layers on the core layer, when manufacturing the first circuit layer and the second circuit layer, smaller copper thicknesses and processes of different metal layers can be produced. circuits, so the packaging substrate of the present invention is conducive to forming the first circuit layer and the second circuit layer with extremely small line width/line spacing, so that the packaging substrate has ultra-fine pitch wiring specifications to effectively externally connect miniaturized devices with multiple contacts. Semiconductor chips can significantly improve the yield of end products.

The above embodiments are used to illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can make modifications to the above embodiments without departing from the spirit and scope of the invention. Therefore, the scope of rights protection of the present invention should be as listed in the patent application scope described below.

2:Packaging substrate

20:Core layer

20a: First surface

20b: Second surface

201: First inner line layer

202: Second inner line layer

21: First line structure

210: first dielectric layer

211: First line layer

212:Insulation layer

213:Pattern line layer

214:Conductive blind hole

22: Second line structure

220: Second dielectric layer

221: Second line layer

24a: First conductive hole

24b: Second conductive hole

25: First solder mask

250:First opening

26: Second solder mask layer

260: Second opening

27,28:Surface treatment layer

Claims (10)

A packaging substrate includes: a core layer, which has a first surface and a second surface opposite each other, and the first surface and the second surface of the core layer respectively have a first inner circuit layer and a second inner circuit layer; insulation layer is combined on the first surface of the core layer to cover the first inner circuit layer; the first circuit structure is provided on the insulating layer; the second circuit structure is provided on the second surface of the core layer Above; the first conductive through hole is provided in the second circuit structure and the core layer to electrically connect the first inner circuit layer, the second inner circuit layer and the second circuit structure; and the second conductive via Through holes are provided in the second circuit structure, the core layer and the insulating layer to electrically connect the first circuit structure, the first inner circuit layer, the second inner circuit layer and the second circuit structure. ; Wherein, the first conductive through hole and the second conductive through hole have different depths. The packaging substrate of claim 1, wherein the first circuit structure includes at least a first dielectric layer, a first circuit disposed on the first dielectric layer and electrically connected to the second conductive through hole layer, and a plurality of conductive blind holes located in the first dielectric layer and electrically connected to the first circuit layer. The packaging substrate according to claim 2 further includes a pattern circuit layer disposed on the first circuit structure and electrically connected to the conductive blind hole. The packaging substrate as claimed in claim 1, wherein the second circuit structure includes a second dielectric layer, and a third conductive hole disposed on the second dielectric layer and electrically connected to the first and second conductive through holes. Second line layer. The packaging substrate of claim 4, wherein the second circuit layer is integrally formed with the first and second conductive through holes. A method for manufacturing a packaging substrate includes: sequentially forming a first circuit structure, an insulating layer and a core layer on a carrier, wherein the core layer has opposite first and second surfaces, and on the first There are first and second inner circuit layers on the surface and the second surface respectively, so that the core layer is bonded to the insulating layer with its first surface; first through holes and holes with different depths are formed on the second surface of the core layer. a second through hole, so that the first inner circuit layer is exposed to the first through hole, and the first circuit structure is exposed to the second through hole; a second circuit structure is formed on the second surface of the core layer, and a third circuit structure is formed on the second surface of the core layer. A conductive through hole is formed in the first through hole, so that the first conductive through hole is electrically connected to the first inner circuit layer, the second inner circuit layer and the second circuit structure, and a second conductive through hole is formed in the second through hole. , so that the second conductive through hole is electrically connected to the first circuit structure, the first inner circuit layer, the second inner circuit layer and the second circuit structure, wherein the first conductive through hole and the second conductive through hole depth; and remove the carrier. The method of manufacturing a packaging substrate as claimed in claim 6, wherein the first circuit structure includes at least a first dielectric layer, a third layer disposed on the first dielectric layer and electrically connected to the second conductive through hole. A circuit layer, and a plurality of conductive blind holes located in the first dielectric layer and electrically connected to the first circuit layer. The manufacturing method of a packaging substrate as claimed in claim 7, wherein a pattern circuit layer is formed on the carrier, and the first circuit structure is electrically connected to the pattern circuit layer through the conductive blind hole. The method of manufacturing a packaging substrate as claimed in claim 6, wherein the second circuit structure includes a second dielectric layer, and is disposed on the second dielectric layer and electrically connected to the first and second conductive vias. The second line layer. The method of manufacturing a packaging substrate as claimed in claim 9, wherein the second circuit layer is integrally formed with the first and second conductive through holes.

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