TWI828138B - Matrix multiplication circuit module and martrix mulitplication method - Google Patents

Abstract

A matrix multiplication circuit module and a matrix multiplication method are provided by the embodiments of the present disclosure. The circuit module includes one or more row-column calculation units for realizing row-column multiplication calculation. Each of the row-column calculation units comprises one or more multiplying units and an adding unit. Each of the one or more multiplying unit has an output end connected to an input end of the adding unit. Each of the multiplying units comprises an electrical signal regulating subunit and a load. The electrical signal regulating subunit is configured to regulate a magnitude of an input electrical signal. A multiplication operation is performed by the electrical signal regulating subunit and the load in response to an electrical signal inputted to the multiplying unit. The load has a fixed load value. By using a load with a fixed load value, regulating the duty cycle of the electrical signal to regulate the magnitude of the electrical signal, and applying the regulated electric signal to the load, the effect of multiplying the matrix elements can be realized, which is convenient to adapt to the change of the matrix elements. The structure of the circuit module for realizing matrix multiplication is simplified, and the complexity of the circuit module is reduced.

Description

A matrix multiplication circuit module and method

The present invention relates to the field of neural network technology, and in particular, to a matrix multiplication circuit module and method that uses hardware to implement matrix multiplication.

As technology develops, a large number of computing operations are required. The above calculations will include matrix multiplication.

The above matrix multiplication can be implemented using software programs. To increase calculation speed, matrix multiplication can be implemented in hardware.

This Summary is provided to introduce in a simplified form concepts that are further described in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed technical solution, nor is it intended to be used to limit the scope of the claimed technical solution.

Embodiments of the present invention provide a matrix multiplication circuit module and a matrix implementation method.

In a first aspect, an embodiment of the present invention provides a matrix multiplication circuit module, including: at least one row-row calculation unit that implements row-row multiplication calculation; the row-row calculation unit includes at least one multiplication unit and an addition unit; the at least one multiplication unit The output end is connected to the input end of the adder unit; the multiplication unit includes an electrical signal conditioning subunit and a load, wherein the electrical signal conditioning subunit is used to adjust the size of the input electrical signal; wherein the electrical signal is adjusted The subunit and the load respond to the electrical signal input to the multiplication unit to implement the multiplication operation; wherein the load value of the load is fixed.

In a second aspect, embodiments of the present invention provide a matrix multiplication implementation method, which is applied to the circuit module of the first aspect, including: obtaining a column matrix element of a column of the first matrix, and obtaining a column matrix element of a row corresponding to the column in the second matrix. Row matrix elements, wherein the column matrix elements are represented by electrical signals; the electrical signals corresponding to the column matrix elements are input to the row and column calculation unit, and the electrical signal is processed based on the size of the row matrix element by the electrical signal adjustment subunit. Adjustment, wherein the row and column calculation unit includes at least one multiplication unit and an addition unit, and the multiplication unit includes an electrical signal conditioning subunit and a load; the accumulated sum of the response signals of each multiplication unit is used as the corresponding calculation result of the row and column calculation unit , wherein the response signal of the multiplication unit is obtained based on the electrical signal adjusted by the electrical signal conditioning sub-unit of the multiplication unit acting on the load of the multiplication unit.

In a third aspect, an embodiment of the present invention provides an integrated circuit, which includes the matrix multiplication circuit module described in the first aspect.

The matrix multiplication circuit module and matrix multiplication implementation method provided by the embodiments of the present invention use a load with a fixed load value, and the electrical signal conditioning sub-unit of the multiplication unit regulates the electrical signal, and the row matrix is realized by the adjustment ratio and the load. Element, the adjusted electrical signal is applied to the load to achieve the effect of multiplying the electrical signal used to represent the column matrix element and the corresponding row matrix element. The above method is convenient for adapting to changes in the row matrix element. The structure of the circuit module that implements matrix multiplication is simplified and the complexity of the circuit module is reduced.

Embodiments of the invention will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present invention are shown in the drawings, it should be understood that the present invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided for A more thorough and complete understanding of the present invention. It should be understood that the drawings and embodiments of the present invention are for illustrative purposes only and are not intended to limit the scope of the present invention.

It should be understood that the various steps described in the method embodiments of the present invention can be executed in different orders and/or in parallel. Furthermore, method embodiments may include additional steps and/or omit performance of illustrated steps. The scope of the invention is not limited in this respect.

As used herein, the term "include" and its variations are open-ended, meaning "including but not limited to." The term "based on" means "based at least in part on." The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; and the term "some embodiments" means "at least some embodiments". Relevant definitions of other terms will be given in the description below.

It should be noted that concepts such as "first" and "second" mentioned in the present invention are only used to distinguish different devices, modules or units, and are not used to limit the functions performed by these devices, modules or units. sequence or interdependence.

It should be noted that the modifications of "one" and "multiple" mentioned in the present invention are illustrative and not restrictive. Those skilled in the art will understand that unless the context clearly indicates otherwise, it should be understood as "one or Multiple".

The names of messages or information exchanged between multiple devices in the embodiment of the present invention are only for illustrative purposes and are not used to limit the scope of these messages or information.

Please refer to FIG. 1 , which shows a schematic structural diagram of some embodiments of a matrix multiplication circuit module according to the present invention. As shown in Figure 1, the matrix multiplication circuit module includes: At least one row and column calculation unit 11 that implements row and column multiplication calculations. The row and column calculation unit 11 includes at least one multiplication unit 110 and an addition unit 111. As shown in FIG. 1 , the multiplication unit 110 includes an electrical signal conditioning subunit 1101 and a load 1102 . The electrical signal adjustment subunit 1101 is used to adjust the size of the input electrical signal. The electrical signal conditioning subunit 1101 and the load 1102 respond to the electrical signal input to the multiplication unit 110 to implement a multiplication operation.

The output of at least one multiplication unit 110 is connected to the input of the addition unit 111 .

The load value of the load 1102 is fixed. That is, the load value of load 1102 cannot be adjusted.

In this embodiment, the electrical signals input to the row and column calculation units 11 in one row and column calculation unit may be different.

In some application scenarios, the above matrix multiplication realizes the multiplication of the eigenvalue matrix and the weight matrix output by the neurons in the neural network. The above electrical signal can represent the matrix elements in the eigenvalue matrix output by the neurons. Different electrical signals in the same row and column calculation unit can represent different matrix elements in the eigenvalue matrix. The above eigenvalue matrix can be expressed as an electrical signal matrix.

The above electrical signal adjustment unit can adjust the size of the electrical signal. Taking the voltage signal as an example, the above-mentioned electrical signal adjustment unit can adjust the size of the voltage signal input to the row and column calculation unit.

In some optional implementations, the electrical signal is a voltage signal or a current signal. The present invention is explained by taking the electrical signal as a voltage signal as an example. The above electrical signal adjustment unit may include a voltage signal duty cycle adjustment unit.

In these optional implementations, the electrical signal may be a pulse signal. The period of the above pulse signal may be T. By adjusting the duration of the effective operating level (such as the high level) in the pulse signal within the period T, the duty cycle of the pulse signal is adjusted. In this example, the size of the voltage signal can be adjusted by adjusting the duty cycle of the pulse signal.

In the present invention, the electrical signal conditioning subunit and the load are used to jointly implement the weights in the above matrix multiplication. While keeping the parameters of the load unchanged, the electrical signal adjustment subunit adjusts the duty cycle of the electrical signal according to the change in weight. The response signal obtained by applying the adjusted electrical signal to the load has the same effect as the response signal obtained by adjusting the load value of the load according to the weight. That is, the duty cycle of the electrical signal is adjusted according to the weight, and the effect of changing the weight is achieved by applying the electrical signal with the adjusted duty cycle to the load.

In the related art, in order to realize the multiplication of the feature matrix output by the neuron and the weight matrix, a load with an adjustable load value (such as a resistor) is used to realize the weights in the weight matrix. For different weight sizes, adjust the load to the corresponding load value. For each row and column calculation unit, in order to adjust the load value of the load of the row and row calculation unit, it is necessary to set up multiple loads with fixed load values, connect these loads according to the preset connection method, and then use the method used to control the load. Load value logic circuits, switching circuits, etc. In this kind of circuit implementation that realizes different weights by adjusting the load value, the structure is relatively complicated.

The matrix multiplication circuit module provided in this embodiment uses a load with a fixed load value to adjust the size of the electrical signal by adjusting the duty cycle of the electrical signal according to the matrix elements (weights) in the weight matrix, and the adjusted size When the electrical signal is applied to the load, the corresponding weight can be multiplied by the electrical signal. The above method is easy to adapt to changes in the weight. The structure of the circuit module that implements matrix multiplication is simplified, and the complexity of the matrix multiplication circuit module that implements matrix multiplication is reduced.

As an implementation method, pulse width modulation (PWM) technology can be used to adjust the duty cycle of the voltage signal.

The above pulse width modulation technology can use a phase locked loop based phase interposer (PLL based phase interposer) to generate control signals. The control signal is applied to the switch circuit, and the control signal controls the on or off of the switch circuit to adjust the duty cycle of the electrical signal.

Optionally, please refer to FIG. 2 , which shows a schematic structural diagram of the electrical signal conditioning subunit in the matrix multiplication circuit module shown in FIG. 1 . As shown in Figure 2, the electrical signal adjustment subunit 1101 (voltage signal duty cycle adjustment unit) includes a control signal generation circuit 1103 and a switch circuit 1104. The control signal generation circuit 1103 may include a phase interpolator based on a phase locked loop. The above-mentioned switching circuit 1104 may include various switching devices. Switching devices include three-pole transistors, field-effect transistors, gate-insulated bipolar transistors, etc. that implement switching functions. The control signal generated by the control signal generating circuit controls the duty cycle of the voltage signal by controlling the on or off of the switch circuit.

The above control signal generating circuit can adjust the duration of the effective operating signal of the control signal within the period T1 of the control signal according to the change in the value of a matrix element in the weight matrix. The effective working signal here can make the switching device conductive. When the switching device conducts the device, the electrical signal acts on the load. During the duration of the inactive working signal in period T1, the above-mentioned switching device is turned off, and the electrical signal cannot act on the above-mentioned load. For example, when the control signal is at a high level, the switch circuit is turned on; when the control signal is at a low level, the switch circuit is turned off. The conduction time of the above-mentioned switch circuit is positively related to the duty cycle of the above-mentioned control signal. In this way, the duty cycle of the electrical signal applied to the load is adjusted, thereby adjusting the size of the electrical signal.

As a schematic illustration, taking the amplitude of the electrical signal as 12V as an example, when the duty cycle is 1, the electrical signal acting on the load is 12V. The above control signal can be used to make the duty cycle of the electrical signal acting on the load be 1/2, so that the electrical signal acting on the above load is 6V.

Furthermore, the same control signal generating circuit 1103 (for example, a phase interpolator based on a phase locked loop) can be used to generate control signals Cin corresponding to multiple row and column calculation units. Multiple control signals generated by the same phase interpolator based on phase locked loop can be respectively input to corresponding row and column calculation units through multiplexers. The input end of the switch circuit in the row and column calculation unit inputs the electrical signal output by the multiplexer, and the output end of the switch circuit is connected to the load. After the electrical signal conditioning subunit outputs the control signal Cin of the preset duty cycle through the multiplexer, the switch circuit is turned on or off under the action of the pulse signal.

Using the same control signal generating circuit 1103 to generate control signals Cin corresponding to multiple row and column calculation units can further simplify the structure of the circuit module that implements matrix multiplication.

In some optional implementations, at least one multiplication unit 110 included in the same row and column calculation unit 11 uses the load 1102 of the same parameters. Each multiplication unit uses a load with the same parameters, which means that the load used by each multiplication unit has the same parameter value. Taking the load as a resistor as an example, the resistance values (or conductance values) of the resistors used by each row and row calculation unit are the same.

In these alternative implementations, each multiplication unit of the row and column calculation unit may use the load 1102 with the same parameters. The weight corresponding to each multiplication unit of the row and column calculation unit can be realized by the electrical signal conditioning subunit of each multiplication unit and the load.

In these optional implementations, since the same load is used in the same row and column computing unit, the process of making the load can be simplified compared to the method of making different loads in a single channel of the row and column computing unit, thereby reducing the time required to implement matrix multiplication. The complexity of the manufacturing process of the circuit module simplifies the structure of the circuit that implements matrix multiplication.

Further optionally, for at least one row-row calculation unit that implements row-row multiplication calculation, the multiplication units corresponding to each row-row calculation unit may use the same load with the same parameters. Each row and row calculation unit uses the load with the same parameters, which means that the load used by each row and row calculation unit has the same load value. Taking the load as a resistor as an example, the resistance values (or conductance values) of the resistors used by each row and row calculation unit are the same. The load manufacturing process can be further simplified, thereby further reducing the complexity of the manufacturing process of the circuit module that implements matrix multiplication,

In some application scenarios, please refer to Figure 3, which shows a circuit structure diagram of an implementation of the row and column calculation unit. As shown in Figure 3, the load in the row and column calculation unit is a resistor. Electrical signals are voltage signals. The resistance values in each multiplication unit are equal and are all R.

In the row-column calculation unit shown in Figure 3, one column of the electrical signal matrix includes two matrix elements Vin1 and Vin2. One row in the weight matrix includes two matrix elements D11×(1/R) and D21×(1/R). D11 here is the voltage signal size adjustment ratio achieved by the duty cycle of the voltage signal Vin1 adjusted by the electrical signal adjustment subunit 1101. D12 here is the voltage signal size adjustment ratio achieved by the duty cycle of the voltage signal Vin2 adjusted by the electrical signal adjustment subunit 1101'. For the input signal Vin1, after passing through the multiplication unit 110, the resistor 1102 (R) responds to the input Vin1, and the response signal output by the resistor 1102 is the current signal I1: (1); For the input signal Vin2, after passing through the multiplication unit 110', the resistor 1102' (R) responds to the input Vin2, and the response signal output by the resistor 1102' is the current signal I2: (2);

The above addition unit 111 is implemented by connecting the multiplication unit 110 and the multiplication unit 110' in parallel. The multiplication unit 110 and the multiplication unit 110' are connected in parallel, and the output out of the row-column calculation unit is the accumulated sum of the current signal I1 and the current signal I2. That is: (3);

The row and column calculation unit shown in Figure 3 fixes the load value of the load, adjusts the duty cycle of the input voltage signal through the electrical signal adjustment subunit, and adjusts the size of the electrical signal acting on the load according to the change in weight. Adjust. Matrix multiplication operations can be implemented through multiple row and column calculation units. The circuit module that implements matrix multiplication composed of the above row and column calculation units has a low structural complexity.

Please refer to Figure 4, which shows a circuit structure diagram of another implementation manner of the row and column calculation unit. As shown in Figure 4, the load in the row and column calculation unit is a capacitor. Electrical signals are voltage signals. The capacitance values of each multiplication unit are equal, both are C.

One column of the above electrical signal matrix includes two matrix elements Vin1 and Vin2. One row in the above weight matrix includes two matrix elements D11×C and D21×C. D11 here is the voltage signal size adjustment ratio achieved by the duty cycle of the voltage signal Vin1 adjusted by the electrical signal adjustment subunit 1101. D12 here is the voltage signal size adjustment ratio achieved by the duty cycle of the voltage signal Vin2 adjusted by the electrical signal adjustment sub-unit 1101'. For the input signal Vin1, after passing through the multiplication unit 110, the capacitor 1102 (C) responds to the input Vin1, and the response signal output by the capacitor 1102 is the charge signal Q1: (4); For the input signal Vin2, after passing through the multiplication unit 110', the capacitor 1102' (R) responds to the input Vin2, and the response signal output by the resistor 1102' is the charge signal Q2: (5);

The above addition unit 111 is implemented by connecting the multiplication unit 110 and the multiplication unit 110' in parallel. The multiplication unit 110 and the multiplication unit 110' are connected in parallel, and the output out of the row-column calculation unit is the accumulated sum of the charge signal Q1 and the charge signal Q2. That is: (6);

The row and column calculation unit shown in Figure 4 fixes the load value of the load, adjusts the duty cycle of the input voltage signal through the electrical signal adjustment subunit, and adjusts the size of the electrical signal acting on the load according to the change in weight. Adjust. Matrix multiplication operations can be implemented through multiple row and column calculation units. The matrix multiplication module composed of the above row and column calculation units has a low structural complexity.

An embodiment of the present invention also provides an integrated circuit. The integrated circuit includes the matrix multiplication circuit module of the embodiment shown in FIGS. 1 to 4 . The integrated circuit may be an integrated circuit that implements various functions.

Referring now to FIG. 5 , a schematic flowchart of some embodiments of a matrix multiplication implementation method according to the present invention is shown. This matrix multiplication implementation method is used in the matrix multiplication circuit module shown in Figure 1.

As shown in Figure 5, the matrix multiplication implementation method includes the following steps: Step 501: Obtain the column matrix element of a column of the first matrix and the row matrix element of the row corresponding to the column in the second matrix, where the column matrix element is represented by an electrical signal.

Matrix multiplication includes performing row and column multiplication calculations on each column matrix element of the first matrix and the corresponding row matrix element of the second matrix. This embodiment takes the implementation of a row-row multiplication as an example to illustrate the implementation of matrix multiplication.

The first matrix here may include n×m matrix elements. That is, it includes n columns and m rows of matrix elements. n and m are integers greater than or equal to 1 respectively.

The second matrix may include m×p matrix elements, that is, include m columns and p rows of matrix elements. m and p are integers greater than or equal to 1 respectively.

The matrix elements in the first matrix can be represented as electrical signals. That is, the size of the above electrical signal can be used to represent the size of the matrix element. The electrical signal here may include a voltage signal or a current signal. The present invention is explained by taking the electrical signal as a voltage signal as an example.

In some application scenarios, the above-mentioned first matrix is a feature matrix output by neurons of the neural network. In these application scenarios, a matrix element in the first matrix can be regarded as the eigenvalue of the neuron output. The above-mentioned second matrix may be a weight matrix. The weights in the above weight matrix correspond to the eigenvalues one-to-one.

Step 502: Input the electrical signal corresponding to the column matrix element into the row and column calculation unit, and use the electrical signal adjustment sub-unit to adjust the electrical signal based on the size of the row matrix element, wherein the row and column calculation unit includes at least one A multiplication unit and an addition unit, the multiplication unit includes an electrical signal conditioning subunit and a load, the load value of the load is fixed.

The number of multiplication units included in the row and column calculation units may match the number of matrix elements included in one column of the first matrix.

The above-mentioned multiplication unit is used to realize the product of a column matrix element in a column in the first matrix and a row matrix element in a row of the second matrix corresponding to the column.

In this embodiment, the load value of the above load is fixed.

The above load can be a resistor or a capacitor.

The above electrical signal includes a voltage signal, and the electrical signal adjustment subunit includes a voltage signal duty cycle adjustment unit. The voltage signal duty cycle adjustment unit includes: a control signal generating circuit and a switching circuit; the above step 502 includes: First, the control signal generating circuit is used to generate a control signal matching the size of the row matrix element.

Secondly, the control signal is applied to the switch circuit, and by controlling the on or off of the switch circuit, the magnitude of the voltage signal acting on the load is adjusted to match the row matrix element. For specific description, please refer to the description of the electrical signal conditioning subunit shown in FIG. 2 , which will not be described again this time.

For each multiplication unit implemented by the multiplication of a column matrix element and a row matrix element, the electrical signal adjustment subunit can be used to adjust the size of the electrical signal used to represent the column matrix element according to the size of the row matrix element. The scaling of the electrical signal in combination with the load can be matched to the size of the row matrix elements.

For neural networks, for the same neural network unit, the neural network unit can correspond to multiple matrix multiplications. The matrix elements in the weight matrix corresponding to each matrix multiplication can be different. In order to adapt to the problem that the weights corresponding to multiple matrix multiplications will change, the matrix multiplication circuit module for realizing matrix multiplication provided by the present invention and the matrix method implementation method provided by this embodiment can be used to complete the matrix multiplication. By adjusting the input electrical signal, the complexity of the circuit structure for implementing matrix multiplication can be reduced.

Step 503: The accumulated sum of the response signals of each multiplication unit is used as the corresponding calculation result of the row and column calculation unit, wherein the response signal of the multiplication unit is based on the electrical signal adjusted by the electrical signal conditioning sub-unit of the multiplication unit. The load acting on the multiplication unit is obtained.

If the above load is a resistor, the response signal output by the multiplication unit is a current signal. If the load is a capacitor, the response signal output by the multiplication unit is a charge signal.

The above description is only an illustration of the preferred embodiments of the present invention and the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present invention is not limited to technical solutions formed by specific combinations of the above technical features. At the same time, it should also cover the above technical features without departing from the above inventive concept. or other technical solutions formed by any combination of equivalent features. For example, a technical solution is formed by replacing the above features with technical features with similar functions disclosed in the present invention (but not limited to).

Furthermore, although operations are depicted in a specific order, this should not be understood as requiring that these operations be performed in the specific order shown or performed in a sequential order. Under certain circumstances, multitasking and parallel processing may be advantageous. Likewise, although several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the invention. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination.

Although the present subject matter has been described in language specific to structural features and/or methodological logical acts, it is to be understood that the subject matter defined in the scope of the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are merely example forms of implementing the claimed scope.

11: Row and column calculation unit 110, 110’: Multiplication unit 111: Addition unit 501, 502, 503: Steps 1101, 1101’: Electrical signal conditioning subunit 1102, 1102’: load 1103: Control signal generation circuit 1104: Switch circuit Cin: control signal I1, I2: current signal out: output Q1, Q2: charge signal R: Resistor Vin1, Vin2: input signal

Figure 1 is a schematic structural diagram of some embodiments of a matrix multiplication circuit module according to the present invention. FIG. 2 is a schematic structural diagram of the electrical signal conditioning subunit in the example shown in FIG. 1 . FIG. 3 is a schematic structural diagram of the row and column calculation units in the circuit module shown in FIG. 1 . FIG. 4 is another schematic structural diagram of the row and column calculation units in the circuit module shown in FIG. 1 . Figure 5 is a schematic flowchart of some embodiments of a matrix multiplication implementation method according to the present invention. The above and other features, advantages and aspects of various embodiments of the invention will become more apparent with reference to the following detailed description taken in conjunction with the accompanying drawings. Throughout the drawings, the same or similar reference numbers refer to the same or similar elements. It should be understood that the drawings are schematic and that elements and elements are not necessarily drawn to scale.

11: Row and column calculation unit 110: Multiplication unit 111: Addition unit 1101: Electrical signal conditioning subunit 1102: Load

Claims (13)

A matrix multiplication circuit module, including: at least one row-row calculation unit that implements row-row multiplication calculation, The row and column calculation unit includes at least one multiplication unit and an addition unit, the output end of the at least one multiplication unit is connected to the input end of the addition unit, The multiplication unit includes an electrical signal conditioning subunit and a load, wherein the electrical signal conditioning subunit is used to adjust the size of the input electrical signal, wherein the pair of the electrical signal conditioning subunit and the load is input to the multiplication unit to respond to the electrical signal to implement the multiplication operation, The load values of the above loads are fixed. The circuit module according to claim 1, wherein at least one multiplication unit included in the same row and column calculation unit uses a load with the same parameters. The circuit module according to claim 1, wherein the corresponding multiplication units of the at least one row-column calculation unit that implements row-row multiplication calculation use loads with the same parameters. The circuit module according to claim 1, wherein the load includes a resistor or a capacitor. The circuit module of claim 1, wherein the electrical signal includes a voltage signal, and the electrical signal adjustment subunit includes a voltage signal duty cycle adjustment unit. The circuit module according to claim 5, wherein the voltage signal duty cycle adjustment unit includes: a control signal generating circuit and a switching circuit, and the control signal generated by the control signal generating circuit is controlled by controlling the conduction of the switching circuit. Or disconnected to control the duty cycle of the voltage signal. The circuit module of claim 1, wherein the electrical signal is a voltage signal, and the load is a resistor, The addition unit of the row-column calculation unit is used to sum the current signals output by each multiplication unit. The circuit module of claim 1, wherein the electrical signal is a voltage signal, and the load is a capacitor, The addition unit of the row-column calculation unit is used to sum the charge signals output by each multiplication unit. The circuit module according to claim 1, wherein the circuit module is used to realize the convolution calculation of the weight matrix in the neural network and the feature matrix output by the neuron. A matrix multiplication implementation method for the matrix multiplication circuit module described in any one of claims 1 to 9, including: Obtaining a column matrix element of a column of the first matrix and a row matrix element of a row corresponding to the column in the second matrix, wherein the column matrix element is represented by an electrical signal; The electrical signal corresponding to the column matrix element is input to the row and column calculation unit, and the electrical signal is adjusted based on the size of the row matrix element using the electrical signal adjustment sub-unit, wherein the row and column calculation unit includes at least one multiplication unit and an addition unit. unit, the multiplication unit includes an electrical signal conditioning subunit and a load; and The accumulated sum of the response signals of each multiplication unit is used as the corresponding calculation result of the row and column calculation unit, wherein the response signal of the multiplication unit is based on the electrical signal adjusted by the electrical signal conditioning sub-unit of the multiplication unit. The load of the unit is obtained. The method of claim 10, wherein the electrical signal includes a voltage signal, the electrical signal adjustment subunit includes a voltage signal duty cycle adjustment unit, and the voltage signal duty cycle adjustment unit includes: a control signal generating circuit and switching circuit, The step of inputting the electrical signals corresponding to the column matrix elements into the row and column calculation unit, and using the electrical signal adjustment subunit to adjust the electrical signals based on the size of the row matrix elements further includes: utilizing the control signal generation circuit to generate a control signal matching the size of the row matrix element; and The control signal is applied to the switch circuit, and by controlling the on or off of the switch circuit, the magnitude of the voltage signal acting on the load is adjusted to match the row matrix element. The method of claim 10 or 11, wherein the first matrix is a feature matrix output by neurons of the neural network, and the second matrix is a weight matrix. An integrated circuit includes at least one matrix multiplication circuit module as described in any one of claims 1 to 9.

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