TWI827561B - Radio frequency front end devices with masked write and the method thereof - Google Patents

Abstract

Methods and apparatuses are described that facilitate data communication between a first slave device and a second slave device across a serial bus interface. In one configuration, a master device receives, from a first slave device, a request to send a masked-write datagram to a second slave device via a bus, wherein the masked-write datagram is addressed to a radio frequency front end (RFFE) register of the second slave device. The masked-write datagram includes a mask field identifying at least one bit to be changed in the RFFE register and a data field providing a value of the at least one bit to be changed in the RFFE register. The master device detects whether the first slave device is authorized to send the masked-write datagram to the second slave device and permits the first slave device to send the masked-write datagram to the second slave device if authorization is detected.

Description

Radio frequency front-end device with mask writing and method thereof

The present invention relates generally to data transfer, and more particularly to radio frequency front-end (RFFE) devices with mask write operations.

As the mobile device market has grown rapidly with the development of multifunctional smart phones, the complexity of cellular communications has increased. It is now common practice for mobile device radio front ends to cover as many as ten or more frequency bands. The radio front-end therefore requires multiple power amplifiers, duplexers, low-noise amplifiers, antenna switches, filters and other radio frequency (RF) front-end devices to accommodate the complexity of radio signaling. These various RF front-end devices are in turn controlled by a host or master device such as a radio frequency integrated circuit (RFIC). As the complexity of RF front-ends increases, the need for standardized protocols to control many different devices led to the development of the Mobile Industry Processor Interface (MIPI) RF Front-End Control Interface (RFFE) standard.

The RFFE standard specifies a serial bus that includes a clock line and a bidirectional data line. Through the RFFE bus, the RFFE master device can read from and write registers in a plurality of RFFE slave devices to registers in a plurality of RFFE slave devices in order to control the RF front-end device. Read and write commands are organized into protocol messages in the RFFE standard, which may each include an initial sequence start condition (SSC), a command frame, a data payload, and a final bus park cycle (BPC). . The protocol messages include register commands, extended register commands and extended register length commands. Information on these agreements The information may further include broadcast commands. Register, extended register and extended register long commands (three types of commands) can all be read or write commands. For the three types of commands, the registers in each of the RFFE slave devices are organized into a 16-bit wide address space (0x0000-0xFFFF in hexadecimal). Each of the three types of commands includes a command frame that addresses a specific RFFE slave device and register address. The command frame in the register command (register command frame) targets the register in the first five bits (0x00-0x1F) of the address space, so that only five register address bits are needed. . The register command frame is followed by an 8-bit data payload frame. In contrast, the extended register command frame includes eight register address bits and can be followed by up to 16 bytes of data. Finally, the extended register length command frame includes a full 16-bit register address, so it uniquely identifies any register in the addressed RFFE slave device. The extended register length command frame can be followed by up to eight bytes of data.

Each of the commands begins with a unique sequence start condition (SSC), followed by a corresponding command frame, some number of data frames, and finally a bus park cycle (BPC) to signal the command. The end. The latency involved in transmitting any of these commands therefore depends on the number of bits in its various frames, and the timing speed for the RFFE clock line. Under the RFFE protocol, each bit of the transmitted frame corresponds to one cycle of the clock. This is because the transmission is Single Data Rate (SDR), which corresponds to one bit per clock cycle. For example, SDR is generated by transmitting a bit in response to each rising edge of the clock (or in response to only falling edges). In the RFFE v2 specification, the maximum timing speed is 52MHz. This timing rate has been increased relative to previous versions of the RFFE protocol and is associated with increased power consumption.

Each of the three types of RFFE commands (extended register, extended register length, and register) can be a read or write command. In general, each write command writes a full set of bytes to each designated register. However, it may be the case that the RFFE master device does not need to change all eight bits in the RFFE slave device register. Additionally, in many devices, more than one master or radio access technology (RAT) component may share control bits in the same RFFE slave device register. to avoid contamination A "partial write" operation may be desired corresponding to bits written to "other" sources in the same register. During this portion of the write operation, the RFFE master device must first perform a read operation on the selected slave device register using the appropriate one of three command types. The RFFE master device then knows the current state of all bits in the corresponding RFFE slave device register. The RFFE master device can then issue an RFFE write command using the appropriate one of three command types, where the data payload for the corresponding slave device register has its positive changes while all remaining bits remain as before A bit in its current state as determined by a previous read operation. The increased need for read operations to precede partial write operations may violate the latency requirements of certain radio access technologies implemented in corresponding RF front-ends.

Therefore, there is a need in this technology for RFFE messaging with reduced latency for partial write operations.

Embodiments disclosed herein provide systems, methods, and apparatus that facilitate data communication between slave devices across a serial bus interface. A radio frequency front-end (RFFE) network is provided in which a slave device can generate a mask write command and request a master device for permission to issue a mask write command to other slave devices, and the other slave devices The device does not require any read operations to determine the value of the immutable bit in the addressed slave device register. Each mask write command may include a mask field or a bit index field that identifies the bit position of the bit to be changed in the addressed slave device register.

In one aspect of the invention, a method performed at a master device for facilitating data communication over a bus includes receiving from a first slave device a mask write data packet transmitted over the bus to A request from the second slave device, wherein the mask write datagram is addressed to the radio frequency front end (RFFE) register of the second slave device, and the mask write datagram includes the identification of the remaining RFFE register. A mask field of at least one bit changed in the RFFE register and a data field providing the value of at least one bit to be changed in the RFFE register; detecting whether the first slave device is authorized to send a mask write Input information report a second slave device; if authorization is detected, permitting the first slave device to send a mask write data report to the second slave device; and if authorization is not detected, preventing the first slave device from sending The controller device sends a mask write data report to the second slave device.

In one aspect, the permission includes notifying the first slave device that the first slave device is authorized to send the mask write datagram. In another aspect, the preventing includes notifying the first slave device of unauthorized sending of a mask write datagram and/or issuing a bus park cycle on the bus to prevent masking. Cover the sending of written data report.

In one aspect, the mask field further identifies a remaining set of bits that remain unchanged in the RFFE register of the second slave device. In another aspect, the mask field is a bit index field that identifies the bit location to be changed in the RFFE register of the second slave device and the data field is a provided bit index field. The bit value field of the bit value for the bit position identified in .

In another aspect of the invention, a host device for facilitating data communication on a bus includes a bus interface and processing circuitry. The processing circuit is configured to receive a request from the first slave device via the bus interface to send a mask write data report to the second slave device via the bus, wherein the mask write data report is Addressed to the radio frequency front end (RFFE) register of the second slave device, the mask write datagram includes a mask field identifying at least one bit to be changed in the RFFE register and provided in the RFFE register. A data field containing the value of at least one bit in the register to be changed; detecting whether the first slave device is authorized to send a mask write data report to the second slave device; if authorization is detected, then permit the first slave device to send a mask write data report to the second slave device; and if authorization is not detected, prevent the first slave device from sending a mask write data report to the second slave device controller device.

In another aspect of the invention, a master device for facilitating data communication over a bus includes: receiving from a first slave device a mask write data packet transmitted over the bus to a second slave device. A component of a request from a slave device in which a mask write datagram is addressed to a radio frequency front-end (RFFE) register of a second slave device, the mask write datagram including an identification pending in the RFFE register mid-term reform Change the mask field of at least one bit and provide the data field of the value of at least one bit to be changed in the RFFE register; used to detect whether the first slave device is authorized to send the mask means for writing a data report to a second slave device; means for allowing the first slave device to send a masked write data report to the second slave device if authorization is detected; and Component that prevents the first slave device from sending a mask write data report to the second slave device if authorization is not detected.

In one aspect of the invention, a method performed at a first slave device for communicating data to a second slave device via a bus includes generating, at the first slave device, data to be transmitted via the bus. A mask write datagram sent to the second slave device, wherein the mask write datagram is addressed to a radio frequency front end (RFFE) register of the second slave device, the mask write datagram includes A mask field identifying at least one bit to be changed in the (RFFE) register and a data field providing a value of at least one bit to be changed in the RFFE register; sending a request to the master device Mask write data to the permission of the second slave device; detect whether permission is granted; if granted by the master device, send a mask write data report to the second slave device; and if not Allowed by the master device, prohibits sending mask write data reports to the second slave device.

In one aspect, the detecting includes receiving a notification from the master device that the first slave device is authorized to send the mask write datagram. In another aspect, the detecting includes receiving from the master device a notification that the first slave device is sending a mask write datagram without permission and/or observing that the first slave device sends a user message on the bus by the master device. Bus park loop to prevent mask write datagram from being sent.

In one aspect, the mask field further identifies a remaining set of bits that remain unchanged in the RFFE register of the second slave device. In another aspect, the mask field is a bit index field that identifies the bit location to be changed in the RFFE register of the second slave device and the data field is a provided bit index field. The bit value field of the bit value for the bit position identified in .

In another aspect of the invention, a slave device for communicating data to a second slave device via a bus includes a bus interface and processing circuitry. The processing circuit is configured to perform the following operations Action: Generate a mask write datagram at the slave device to be sent to a second slave device via the bus, where the mask write datagram is addressed to the radio frequency front end of the second slave device ( RFFE) register, the mask write datagram includes a mask field identifying at least one bit to be changed in the (RFFE) register and a mask field providing at least one bit to be changed in the RFFE register Value data field; requests permission from the master device to send mask write data reports to the second slave device; detects whether the permission is granted; if granted by the master device, via the bus interface sending a mask write data report to the second slave device; and inhibiting sending of the mask write data report to the second slave device if not permitted by the master device.

In yet another aspect of the invention, a first slave device for communicating data over a bus to a second slave device includes generating, at the slave device, data to be sent to the second slave device via the bus. Components for a mask write datagram of a slave device, wherein the mask write datagram is addressed to a radio frequency front end (RFFE) register of a second slave device, the mask write datagram including an identification to be A mask field of at least one bit changed in the (RFFE) register and a data field providing the value of at least one bit to be changed in the RFFE register; used to request transmission to the master device means for masking the permission to write a data report to the second slave device; means for detecting whether the permission is granted; means for sending a mask write data report to the second slave device if granted by the master device Means for a slave device; and means for inhibiting sending of a mask write data report to a second slave device if not permitted by the master device.

100:Equipment

102: Processing circuit

104: Integrated circuit (IC) device/Application special integrated circuit (ASIC) device

106: Integrated circuit (IC) device/radio frequency (RF) front-end device

108:Antenna

110: Modem

112: Processing device

114:Memory device

120:Display

122: Integrated or external keypad

124:Button

200:Block diagram

202:Device

204: Modem

206: Baseband processor

208: Radio Frequency Front End (RFFE) Bus

210: Radio frequency front end (RFFE) interface

212: Front-End Devices/Radio Frequency (RF) Integrated Circuits (RFIC)

213: Front-end device/switch

214: Front End Unit/Radio Frequency (RF) Tuner

215: Front-end device/power amplifier (PA)

216: Front-end device/low noise amplifier (LNA)

217: Front-end device/power management module

220: Communication link

300:Device

302: First controlled device

306: Radio frequency front-end (RFFE) register

310:Transceiver

310a:Receiver

310b: Common circuit

310c:Transmitter

312: Processing circuit and/or control logic

314a: Line driver/receiver circuit

314b: Line driver/receiver circuit

316: Serial clock line (SCLK)

318: Serial data line (SDATA)

3201:Bus master controller device

320N: Bus master controller device

3221: Controller device

322N: Controlled device

324:Storage device

328: Transmission clock (TXCLK) signal

330: Radio Frequency Front End (RFFE) Bus

400:Command message box

500: Mask Write Radio Frequency Front End (RFFE) Command/Mask Write Command

502: Extended register mask write command/Extended register mask write command (WR)

504: Extended register long mask write command/Extended register mask write command (WR) long

506: Temporary register mask write command/temporary register mask write command (WR)

508: Extended temporary register short mask write command/Extended temporary register mask write command (WR) short

510: Mask N-bit field

512: Data N-bit field

600: Universal mask writing command

602: General extended temporary register mask write command/Extended temporary register mask write command (WR)

604: General extended temporary register mask write command/Extended temporary register mask write command (WR) long

606: General register mask write command/scratch register mask write command (WR)

608: General register short mask write command/extended register mask write command (WR) short

610: Mask N-bit field

612: Data N-bit field

614: 2-bit mode field

702: Extended register index mask write command/Extended register mask write command (WR)

704: Extended register long index mask write command/Extended register mask write command (WR) long

706: Temporary register index mask write command/temporary register mask write command (WR)

708: Extended register short index mask write command/Extended register mask write command (WR) short

710:Bit index

712:Bit value field

800: Universal index mask writing command

802: General extended register index mask write command/extended register mask write command (WR)

804: General extended register long index mask write command/Extended register mask write command (WR) long

806: General scratchpad index mask write command/register mask write command (WR)

808: General extended register short index mask write command/Extended register mask write command (WR) short

810:Field

812:Field

814: 2-bit mode field

900:Instance packet structure

902: Data report header

904: 16-bit address

906:1 byte most significant byte (MSB)

908:1 byte least significant byte (LSB)

910: Mask and data on clump length

1000:Information report

1004: 16-bit address

1006:1 byte most significant byte (MSB)

1008:1 byte least significant byte (LSB)

1010: Mask and data on clump length

1012:Master controller device

1014: Shadow register

1016: Shadow register

1022: Controller device

1024:1 byte base address register

1026:1 byte mask written to burst length register

1100:Information report

1104: 16-bit address

1106:1 byte most significant byte (MSB)

1108:1 byte least significant byte (LSB)

1110: Mask and data on clump length

1112:Master controller device

1114: Shadow register

1116: Shadow register

1122: Controller device

1124:1 byte base address register

1126:1 byte mask written to burst length register

1130:Compare

1136: Register write access command

1140:Compare

1146: Register write access command

1200:Instance packet structure

1202: Extended register write command

1204: Payload

1300:Instance packet structure

1302: Extended register long write command

1304: Payload

1400:Instance bit structure

1402: Configuration register

1404: Third register bit D5

1406: Fourth register bit D4

1500: Radio Frequency Front End (RFFE) register space

1600: Radio Frequency Front End (RFFE) register space

1700: Chart

1750: Schema

1800: Schema

1802: Page address register

1804: 8-bit address

1900:Equipment

1902: Processing circuit

1904: Processor

1906:Storage

1908:Bus interface

1910:Bus

1912: Line interface circuit

1914:Execution image

1916:Software module

1918:User interface

1920: time-sharing program

1922: Logic circuits

2000:Flowchart

2002: steps

2004: steps

2006: Steps

2008: Steps

2100:Flowchart

2102: Steps

2104: Steps

2106: Steps

2108: Steps

2110: Steps

2200:Flowchart

2202: Steps

2204:Step

2206: Steps

2208: Steps

2300:Flowchart

2302:Step

2304:Step

2306:Step

2308: Steps

2310: Steps

2312: Steps

2400:Transmission equipment

2402: Processing circuit

2404: Data report generation/sending module/circuit

2406: Address comparison module/circuit

2408: Burst length comparison module/circuit

2410: Register setting module/circuit

2412:Bus interface module/circuit

2414: Connector/Wire

2416: Processor

2418: Computer readable storage media

2420:Bus

2500:Flowchart

2502:Step

2504:Step

2506:Step

2508:Step

2510:Step

2512:Step

2600:Flowchart

2602:Step

2604:Step

2606:Step

2608:Step

2610:Step

2700:Flowchart

2702:Step

2704:Step

2706:Step

2708:Step

2710:Step

2712: Steps

2714:Step

2716: Steps

2800: Receiving device

2802: Processing circuit

2804: Data report receiving module/circuit

2806: Field reading module/circuit

2808:Bit changing module/circuit

2810: Register reading module/circuit

2812:Bus interface module/circuit

2814: Connector/Wire

2816: Processor

2818: Computer readable storage media

2900:Device

2902: Radio Frequency Front End (RFFE) Bus

2904:Bus master controller device

2906(1):Controller device

2906(2): Controller device

2906(3):Controller device

2906(N-1): Controller device

2906(N): Controller device

2916: Identification circuit/module

3000:Flowchart

3002:Step

3004:Step

3006:Step

3008: Steps

3010: Steps

3100:Flowchart

3102: Steps

3104: Steps

3106: Steps

3108: Steps

3200:Master controller device

3202: Processing circuit

3204: Request to receive module/circuit

3206: Data report authorization module/circuit

3208: Datagram transmission permission module/circuit

3210: Datagram transmission prevention module/circuit

3212:Bus interface circuit

3214: Connector/Wire

3216: Processor

3218: Computer readable storage media

3220:Bus

3300:Flowchart

3302: Steps

3304: Steps

3306: Steps

3308: Steps

3310: Steps

3400: Controller device

3402: Processing circuit

3404: Data report generation module/circuit

3406: Permission request module/circuit

3408:Permission detection module/circuit

3410: Data report sending module/circuit

3412:Bus interface circuit

3414: Connector/Wire

3416: Processor

3418: Computer readable storage media

3420:Bus

Figure 1 illustrates a device including an RF front end (RFFE) that may be adapted in accordance with certain aspects disclosed herein.

Figure 2 is a block diagram illustrating a device using an RFFE bus to couple various front-end devices.

3 illustrates an example of a system architecture for a device employing data links between IC devices in accordance with certain aspects disclosed herein.

Figure 4 is a diagram illustrating reserved command fields in the RFFE protocol.

Figure 5 is a diagram illustrating four mask write commands including N-bit mask fields according to an aspect of the present invention.

Figure 6 is a diagram illustrating a modification of the mask write command of Figure 5 using a single reserved command field in accordance with an aspect of the invention.

7 is a diagram illustrating four mask write commands that include a bit index identifying the bit position of the bit to be changed according to an aspect of the invention.

Figure 8 is a diagram illustrating a modification of the mask write command of Figure 7 using a single reserved command field in accordance with an aspect of the invention.

Figure 9 is a diagram illustrating an example packet structure supporting a 16-bit address space and N pairs of mask and data bytes.

Figure 10 is a diagram illustrating an example datagram in a transmission buffer.

Figure 11 is a diagram illustrating example operations for transmitting datagrams in a buffer.

FIG. 12 is a diagram illustrating an example packet structure of an extended register write command that supports mask write operations.

Figure 13 is a diagram illustrating an example packet structure of an extended register write long command that supports mask write operations.

Figure 14 is a diagram illustrating the bit structure of the configuration register.

Figure 15 is a diagram of an RFFE register space.

Figure 16 is a diagram of an RFFE register space with a configuration register and a page address register.

Figure 17 illustrates a diagram defining another example bit structure of a configuration register and a diagram depicting the functions of the configuration register bits.

Figure 18 is a diagram illustrating page segmented access.

19 is a block diagram illustrating an example of an apparatus employing processing circuitry adaptable in accordance with certain aspects disclosed herein.

20 is a flow diagram of a method of sending data to a receiver according to certain aspects disclosed herein.

21 is a flow diagram of another method of sending data to a receiver according to certain aspects disclosed herein.

Figure 22 is a flow diagram of another method of sending data to a receiver according to certain aspects disclosed herein.

Figure 23 is a flow diagram of another method of sending data to a receiver according to certain aspects disclosed herein.

24 is a diagram illustrating an example of a hardware implementation for a transmission device employing processing circuitry adapted in accordance with certain aspects disclosed herein.

25 is a flow diagram of a method of receiving data from a transmitter in accordance with certain aspects disclosed herein.

26 is a flow diagram of another method of receiving data from a transmitter in accordance with certain aspects disclosed herein.

27 is a flow diagram of another method of receiving data from a transmitter in accordance with certain aspects disclosed herein.

28 is a diagram illustrating an example of a hardware implementation for a receiving device employing processing circuitry adapted in accordance with certain aspects disclosed herein.

29 is a block schematic diagram illustrating an example of the architecture of a device that may employ an RFFE bus to connect a bus master device and a slave device.

30 is a flowchart of a method for communicating mask write packets between slave devices over an RFFE bus.

Figure 31 is a flow diagram of a method for facilitating data communication on a bus.

32 is a diagram illustrating a simplified example of a hardware implementation for a host device employing processing circuitry adapted in accordance with certain aspects disclosed herein.

33 is a flow diagram of a method for communicating data between slave devices on a bus.

34 is a diagram illustrating a simplified example of a hardware implementation for a slave device employing processing circuitry adapted in accordance with certain aspects disclosed herein.

Cross-references to related applications

This application claims priority to non-provisional application No. 15/803,639 titled "RADIO FREQUENCY FRONT END DEVICES WITHMASKED WRITE" filed on November 3, 2017, the entire content of which is incorporated herein by reference. .

Now refer to the diagram to describe the various styles. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more aspects. Obviously, however, this aspect(s) may be practiced without these specific details.

As used in this application, the terms "component," "module," "system" and the like are intended to include computer-related entities such as (but not limited to) hardware, firmware, combinations of hardware and software, Software or software in execution. For example, a component may be, but is not limited to, a program, a processor, an object, an executable, a thread, a program, and/or a computer that executes on a processor. With instructions, on a computing device Both the executing application and the computing device may be components. One or more components may reside within a program and/or thread, and a component may be localized on one computing device and/or distributed between two or more computing devices. Additionally, such components can execute from a variety of computer-readable media having various data structures stored thereon. Such components may interact with the local system, another component in a distributed system, and/or with other systems across a network such as the Internet, such as from a signal having one or more data packets, such as from interacting with the local system, another component in a distributed system, and/or across a network such as the Internet. Information about a component of the interaction) is communicated by means of local and/or remote programs.

Furthermore, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clear from the context, the phrase "X assumes A or B" is intended to mean either of the natural inclusive permutations. That is, the phrase "X adopts A or B" is satisfied by any of the following cases: X adopts A; X adopts B; or X adopts both A and B. Additionally, as used in this application and the appended claims, the article "a" shall generally be understood to mean "one or more" unless otherwise specified or it is clear from the context that a singular form is intended. Exemplary device with multiple IC device subassemblies

Certain aspects of the invention may be applicable to communication links deployed between electronic devices, which may include sub-assemblies of equipment such as phones, mobile computing devices, appliances, automotive electronics, avionics systems, etc. . Figure 1 depicts an apparatus 100 that may employ communication links between IC devices. In one example, device 100 may be a mobile communications device. The device 100 may include a processing circuit with two or more IC devices 104, 106 that may be coupled using a first communication link. An IC device may be an RF front-end device 106 that enables a device to communicate with a radio access network, a core access network, the Internet, and/or another network via one or more antennas 108. RF front-end device 106 may include a plurality of devices coupled by a second communication link, which may include an RFFE bus.

Processing circuitry 102 may include one or more application specific IC (ASIC) devices 104 . In one example, ASIC device 104 may include and/or be coupled to one or more processing devices 112, logic circuitry, one or more data machines 110, and processor-readable storage, such as memory device 114, which may Instructions and data executable by a processor on processing circuit 102 are maintained. The processing circuit 102 may be configured by the operating system and application Controlled by one or more of the programming interface (API) layers that support and enable the execution of software modules that reside on storage media. Memory device 114 may include read only memory (ROM) or random access memory (RAM), electrically erasable programmable ROM (EEPROM), flash memory card, or any other memory device that may be used in processing systems and computing platforms. memory device. Processing circuitry 102 may include or have access to a local database or parameter store that may maintain operating parameters and other information used to configure and operate device 100. The native database may be implemented using one or more of database modules, flash memory, magnetic media, EEPROM, optical media, magnetic tape, floppy or hard disk, or the like. The processing circuitry may also be operatively coupled to external devices, such as antenna 108, display 120, operator controls (such as buttons 124 and/or integrated or external keypad 122), and other components.

Overview of RFFE bus

FIG. 2 is a block diagram 200 illustrating an example of a device 202 employing an RFFE bus 208 to couple various front-end devices 212 - 217 . Modem 204 including an RFFE interface 210 may also be coupled to RFFE bus 208. In various examples, device 202 may implement one or more baseband processors 206, one or more other communication links 220, and various other buses, devices, and/or different functionality. In an example, modem 204 can communicate with baseband processor 206, and device 202 can be embodied in one or more of: a mobile computing device, a cellular phone, a smart phone, a session initiation protocol ( SIP) phones, laptops, notebooks, mini-laptops, smart laptops, personal digital assistants (PDAs), satellite radios, global positioning system (GPS) devices, smart home devices, smart lighting , multimedia devices, video devices, digital audio players (e.g., MP3 players), video cameras, game consoles, entertainment devices, vehicle components, avionics systems, wearable computing devices (e.g., smart watches, health or fitness trackers devices, goggles, etc.), electrical appliances, sensors, safety devices, vending machines, smart meters, drones, multi-rotor aircraft or any other similar functional devices.

RFFE bus 208 may be coupled to an RF integrated circuit (RFIC) 212, which may include one or more controllers and/or processors that configure and control some aspects of the RF front end. RFFE bus 208 The RFIC 212 may be coupled to the switch 213, the RF tuner 214, the power amplifier (PA) 215, the low noise amplifier (LNA) 216, and the power management module 217.

In one example, baseband processor 206 may be a master controller device. The master device/baseband processor 206 can drive the RFFE bus 208 to control the various front-end devices 212-217. During transmission, the baseband processor 206 can control the RFFE interface 210 to select the power amplifier 215 for the corresponding transmission band. Additionally, baseband processor 206 can control switch 213 so that the resulting transmission can be propagated from an appropriate antenna. During reception, the baseband processor 206 may control the RFFE interface 210 to receive from the low-noise amplifier 216 depending on the corresponding transmission frequency band. It should be understood that numerous other components may be controlled via RFFE bus 208 in this manner, so that device 202 is representative only and not limiting. Additionally, in alternative embodiments, other devices such as RFIC 212 may act as an RFFE master device.

3 is a block diagram illustrating an example of an architecture for a device 300 that may employ an RFFE bus 330 to connect bus master devices 3201 - 320N to slave devices 302 and 3221 - 322N. RFFE bus 330 may be configured according to application requirements and may provide access to multiple buses 330 to some of devices 3201-320N, 302, and 3221-322N. In operation, one of bus master devices 3201 to 320N may gain control of the bus and transmit a slave identifier (slave address) to identify slave devices 302 and 3221 to 322N One of them can participate in a communication change. Bus master devices 3201-320N can read data and/or status from slave devices 302 and 3221-322N, and can write data to memory or configure slave devices 302 and 3221-322N. . Configuration may involve writing to one or more registers or other storage on slave device 302 and 3221 through 322N.

In the example illustrated in FIG. 3 , first slave device 302 coupled to RFFE bus 330 may respond that data can be read from or written to the first slave device 302 One or more bus master devices 3201-320N of device 302. In one example, the first slave device 302 may include or control a power amplifier (see PA 215 in Figure 2), and one or more Bus master devices 3201 through 320N may configure a gain setting at first slave device 302 from time to time.

The first slave device 302 may include RFFE registers 306 and/or other storage devices 324, processing circuitry and/or control logic 312, a transceiver 310, and an interface including a plurality of line driver/receiver circuits 314a, 314b. The interface couples the first slave device 302 to the RFFE bus 330 as needed, such as via the serial clock line (SCLK) 316 and the serial data line (SDATA) 318. Processing circuitry and/or control logic 312 may include a processor such as a state machine, sequencer, signal processor, or general purpose processor. Interfaces can be implemented using state machines. Alternatively, the interface may be implemented in software on a suitable processor (if included in the first controller device 302). Transceiver 310 may include one or more receivers 310a, one or more transmitters 310c, and certain common circuitry 310b, including timing, logic, and storage circuits and/or devices. In some examples, transceiver 310 may include encoders and decoders, clock and data recovery circuitry, and the like. A transmission clock (TXCLK) signal 328 may be provided to the transmitter 310c, where the TXCLK signal 328 may be used to determine the data transmission rate.

RFFE bus 330 is typically implemented as a serial bus in which data is converted from parallel to serial form by a transmitter that transmits the encoded data as a serial bit stream. A receiver processes the received serial bit stream using a serial-to-parallel converter to deserialize the data. A serial bus may include two or more wires and may carry a clock signal on one wire with serialized data carried on one or more other wires. In some cases, the data may be encoded in symbols, where each bit of the symbol controls the signaling state of the wires of RFFE bus 330.

To control slave devices 302 and 3221-322N, a master device (eg, one of master devices 3201-320N) writes to an RFFE register within the slave device (eg, the first RFFE register 306 in the slave device 302) or read the RFFE register in the slave device. The RFFE register 306 can be arranged according to one of the RFFE register address spaces ranging from the zero (0)th address to the 65535th address. In other words, each slave device may include up to 65,536 registers. for Addressing this number of registers requires 16 register address bits for each of slave device 302 and 3221 through 322N. The master device can use one of the three types of commands discussed above (register commands, extended register commands, or extended register length commands) from the buffers in each slave device. Register 306 reads or writes to register 306 in each slave device. For example, the register command addresses only the first 32 registers 306 in the address space for slave device 302 and each of 3221 through 322N. In this manner, the register command requires only five register address bits. In contrast, an extended register command may initially access up to the first 256 registers in slave device 302 and each of 3221 through 322N. A corresponding 8-bit register address for an extended register command serves as a pointer, where the data payload for the extended register command may include up to 16 bytes. A corresponding read or write operation for an extended register command may thus begin across 16 register extensions from the register identified by the 8-bit register address. The extended register length command includes a 16-bit register address that serves as a pointer to any of the possible 65,536 registers in each slave device. The data payload for an extended register length command may include up to eight bytes, so that the corresponding read or write operation for the extended register length command may start with 16 bits The address-identified registers extend across eight registers. In one aspect of the invention, up to 15 slave devices can be coupled to one RFFE bus. If a front-end includes more than 15 slave devices, additional RFFE busses may be provided. Exemplary mask writing operating environment for radio frequency front-end (RFFE) devices

In one aspect of the invention, it is not uncommon for registers to be shared by two slave devices or components. For example, a pair of LNAs can each be configured by sharing four of the eight bits in the slave register. Sharing registers by two constrained slave devices can be referred to as a "highly integrated" register map. Configuring only one of the slave devices requires a partial write operation in which only four bits of the 8-bit slave register are written instead of all eight bits. The remaining bits for the other slave device that share the register must remain unchanged. The master device may include a "shadow register" that may be loaded with the contents of the corresponding slave device via a read operation. The master device can be configured using shadow registers Only the corresponding bits used for a specific slave device are changed and the remaining bits used in the shared register are written to the slave device unaffected. This part of the write operation may be referred to as a "read-modify-write" operation, where it involves reading the slave device register, modifying only selected bits, and using data from the corresponding shadow register. A write operation of modified bits and unmodified bits to an entire eight-bit register in the slave device. The use of shadow registers not only necessitates previous reads in the case of multi-master configurations but also increases the silicon area due to the additional register space requirements.

Figure 4 is a diagram illustrating reserved command fields in the RFFE protocol. To reduce the latency of conventional RFFE commands for partial write operations (read-modify-write operations) over the RFFE bus 208, a new command frame that invokes the mask write mode of the transfer is provided herein. To provide these new command frames, reserved command frames created through the RFFE protocol are utilized. In that regard, the RFFE protocol reserves at least 12 command frames 400 ranging from the reserved command frame at hex 10 to the reserved command frame at hex 1B as shown in FIG. 4 . Each reserved command frame begins with a sequence start condition (SSC) followed by a four-bit slave device address (SA(4)) as shown in Figure 4. Each reserved command is eight bits long. For example, a reserved command at hexadecimal position 10 contains eight bits 00010000. All reserved commands are followed by a parity bit P, which is followed by the address (Reg-Adrs) and data frame used for the purpose of the reservation.

Figure 5 is a diagram illustrating four mask write commands including N-bit mask fields according to an aspect of the present invention. For use in signaling mask write operations, four of the reserved command frames (indicated as command frames CF1 through CF4) may be used to identify the mask write RFFE command 500 as shown in Figure 5. In these mask write commands 500, the mask N bit field 510 identifies the mask bits that will remain unchanged by the mask write operation and the unmask bits that will change by the mask write operation. Bits. N is the number of bits in the corresponding register. The following discussion will assume N=8, but it should be understood that other register widths may be used in alternative implementations. Data N-bit field 512 provides the binary value of the unmask bit. For example, the extended register mask write command (extended register WR) 502 begins with a 4-bit slave SSC of the device address (controller address (4 bits)). The 8-bit command frame CF1 obtained from one of the reserved command frames 400 discussed with respect to FIG. 4 identifies the command 502 to receive the slave device interface. The 8-bit Reg-Adrs (8-bit )) identifies the address of the register in the corresponding slave device for the extended register mask write operation. The idle symbol (bus park cycle) completes command 502.

The extended register long mask write command (extended register WR length) 504 also starts with the SSC and the four-bit slave address (slave address (4 bits)), but continues With only reserved command frame CF2. Command frame CF2 is followed by a sixteen-bit register address (Reg-Adrs (16 bits)), a mask N-bit field 510, a data N-bit field 512, and an idle symbol. The register mask write command (register WR) 506 also starts at SSC and is followed by the slave address field (controller address (4 bits)) of the only reserved command frame CF3. The reserved command frame CF3 is followed by a 5-bit register address (Reg-Adrs (5 bits)), a mask N-bit field 510, a data N-bit field 512, and an idle symbol. Finally, the extended register short mask write command (extended register WR short) 508 uses the only reserved command code CF4 and 6-bit, 7-bit or 9 to 15-bit register bits The address (Reg-Adrs (9 to 15 bits)) is similar to the extended register long mask write command 502. The number of register bits can be established during the device initialization phase.

Figure 6 is a diagram illustrating a modification of the mask write command of Figure 5 using a single reserved command field in accordance with an aspect of the invention. Figure 6 depicts the use of a single reserved command frame for the universal mask write command 600, rather than the use of four reserved command frames as in Figure 5. All commands 600 start with the SSC and slave address (slave address (4 bits)) and end with an idle symbol. The general extended register mask write command (extended register WR) 602 is used followed by a value such as (0,0) intended to represent the extended register mask write operation. Reserved command frame CF1 of 2-bit mode field 614. Similar to command 502, command 602 includes an 8-bit register address, a mask N-bit field 610, a data N-bit field 612, and an idle symbol. The general extended register length mask write command (extended register WR length) 604 uses the same reserved command field CF1. Order 604 also includes specific There is, for example, a 2-bit mode field 614 that represents a value of (0,1) intended for an extended register long mask write operation. Similar to command 604, command 604 includes a 16-bit register address, a mask N-bit field 610, a data N-bit field 612, and an idle symbol. The general purpose register mask write command (register WR) 606 also includes a reserved command field CF1 and a 2-bit mode field 614 having a value such as (1,0), which is (1,0) The identification register mask write operation is intended to use the mask N-bit field 610 and the data N-bit field 612 at the subsequent 5-bit register address. Finally, the general purpose register short mask write command (extended register WR short) 608 is similar except that it uses a 9 to 15 bit register address (Reg-Adrs (9 to 15 bits)) General extended register long mask command 508.

7 is a diagram illustrating four mask write commands that include a bit index identifying the bit position of the bit to be changed according to an aspect of the invention. If only one bit needs to be changed in the addressed register, the mask N bit field 510 can be replaced by a log2(N) bit index 710 as shown in Figure 7, which bit index 710 uniquely identifies the Write to the bit location corresponding to the N-bit wide slave device register. Bit value field 712 identifies what the bit value should be for the bit position identified by bit index 710 . It should be appreciated that bit index 710 and bit value field 712 may be used in embodiments in which each mask command includes a unique reserved command field as discussed similarly with respect to FIG. 5 . Thus, the extended register index mask write command (extended register WR) 702 is similar to command 502 except that fields 510 and 512 are replaced by fields 710 and 712, respectively. Similarly, extended register length index mask write command (extended register WR length) 704 is similar to command 504, register index except that fields 510 and 512 are replaced by fields 710 and 712 respectively. Mask write command (Extended Register WR) 706 is similar to command 506, and Extended Register Short Index Mask Write command (Extended Register WR short) 708 is similar to command 508.

Figure 8 is a diagram illustrating a modification of the mask write command of Figure 7 using a single reserved command field in accordance with an aspect of the invention. The number of reserved commands can be reduced even further as shown in Figure 8 for the universal index mask write command 800 using a common reserved command field CF1. To identify the type of index mask write operation, the commands 800 each include 2 bits as discussed with respect to FIG. 6 Mode field 814. Therefore, the general extended register index mask write command (extended register WR) 802 is similar to command 602 except that fields 610 and 612 are replaced by fields 810 and 812 respectively. Similarly, general extended register length index mask write command (extended register WR length) 804 is similar to command 604, general extended register length index mask write command 804, except that fields 810 and 812 respectively replace fields 610 and 612. The register index mask write command (register WR) 806 is similar to command 606, and the general extended register short index mask write command (extended register WR short) 808 is similar to command 608. In one aspect of the invention, the master device interface and the slave device interface are configured to perform the mask write operations discussed herein. This is highly advantageous because it eliminates the conventional need for a read-modify-write sequence on the RFFE (ie, reading the contents of the register before a partial write operation). In this manner, the disclosed mask write operation advantageously reduces bus communication latency.

The techniques discussed above utilize multiple command frames (also called command codes) or a single command frame combined with pattern bits. While the above techniques may be preferred in some implementations, additional techniques with the added benefits of address paging and burst writes are described below. Although the technology is rooted in RFFE enhancement, its application is not particularly limited to RFFE bus, but can also be applied to other bus architectures.

As described above, the RFFE mask write command provides an N-bit mask field and an N-bit control data field per datagram. Each datagram has a fixed overhead of 15 clock cycles (SSC: 1 cycle, USID: 4 cycles, command code: 8 cycles, parity: 1 cycle, BPC: 1 cycle). However, for applications where multiple masks and data bits will be sent, the use of multiple data packets may not be the best way to send the data due to the associated additional overhead. In addition, the number of unused reserved RFFE command codes is limited. Therefore, the use of multiple reserved command codes to indicate a burst transmission may not be appropriate since there may not be enough command codes available to accommodate even eight bursts of, for example, a mask write command.

Therefore, a new technology is needed to enable write access in the entire RFFE UDR space, which provides support for burst mode when using a command code. Accordingly, aspects of the present invention provide page addressing schemes and burst write schemes using masks and data byte pairs.

In the page addressing scheme, the slave device has a 1-byte base address register. For example, the base address register may contain the hexadecimal value 0x00. The master device maintains a copy of the slave device's base address register at the master device in a shadow register. The master device prepares a datagram based on the 16-bit address (i.e., 1 byte Most Significant Byte (MSB) and 1 byte Least Significant Byte (LSB)), but will only send the mask Write the 1-byte LSB in the datagram. Before sending the mask write datagram, the master device will compare the 1-byte MSB of the 16-bit address with the current copy of the slave device's base address register in the shadow register. If the value of the slave device's base address register does not match the 1-byte MSB of the 16-bit address, the master device will first set (or update) the base address on the slave device ( to change the page) to match the 1-byte MSB of the 16-bit address. The master device may use a register write access command or (preferably) any other type of write access command to perform the slave device base address change before sending the mask write datagram. Pages are changed only when a page mismatch is detected before the datagram is transmitted. The master device may further update the shadow register with the updated slave device base address.

In a burst write scheme using mask and data byte pairs, the slave device has a 1-byte mask write burst length register. For example, the burst length register may have a hexadecimal value of 0x01. The master device maintains a copy of the slave device's mask write burst length register at the master device in the shadow register. The master device prepares a datagram based on the specified mask and data pair burst length (eg, the number of mask and data byte pairs), but will not send the burst length that the mask writes in the datagram. Before sending the mask write datagram, the master device will compare the specified burst length to the slave device's current copy of the mask write burst length in the shadow register. If the slave device's mask write burst length does not match the specified burst length, the master device will first set (or update) the slave device. The mask on the controller device writes the burst length to match the specified burst length. The master device may use a register write access command or (preferably) any other type of write access command to perform the slave device mask write burst length before sending the mask write datagram. change. The mask write burst length is changed only when a burst length mismatch is detected before the datagram is transmitted. The master device may further update the shadow register using the updated mask write burst length. Therefore, the master device can send when the 1-byte MSB of the 16-bit address matches the slave device's base address and the specified burst length matches the slave device's mask write burst length. Mask write data is reported to the slave device.

FIG. 9 is a diagram illustrating an example packet structure 900 that supports a 16-bit address space and N pairs of mask and data bytes. Referring to Figure 9, the datagram header 902 may include a four-bit controller address (SA(4)), an eight-bit command frame (CMD(8)), and a parity bit P . The master device may prepare a data report based on a 16-bit address 904 having a 1-byte Most Significant Byte (MSB) 906 and a 1-byte Least Significant Byte (LSB) 908. The master device will only send the 1 byte LSB 908 in the mask write datagram. Therefore, the 1-byte MSB 906 will not be transmitted as part of the mask write datagram. Additionally, the master device may prepare a data report for the burst length 910 based on the specified mask and data. The mask and data pair burst length 910 indicates the number of mask and data byte pairs in the payload (e.g. mask+data pair #0, mask+data pair #1, ..., mask+data pair #N ). The mask and data pair burst length 910 will not be transmitted as part of the mask write datagram.

Figure 10 is a diagram illustrating an example datagram 1000 in a transmission buffer. In the page addressing scheme, the slave device 1022 has a 1-byte base address register 1024. The master device 1012 maintains a copy of the slave device's base address register 1024 in the shadow register 1014 at the master device. Master device 1012 prepares datagram 1000 based on 16-bit address 1004 with 1 byte Most Significant Byte (MSB) 1006 and 1 byte Least Significant Byte (LSB) 1008, but will only send The mask is written to 1 byte LSB 1008 in datagram 1000. Before sending the mask write datagram 1000, the master device 1012 will compare the 1-byte MSB 1006 with the one in the shadow register 1014. The current copy of the slave device's base address register 1024. If the base address register 1024 of the slave device does not match the 1-byte MSB 1006, the master device 1012 will first set (or update) the base address 1024 on the slave device 1022 (to change the page ) to match the 1-byte MSB 1006. The master device 1012 may further update the shadow register 1014 with the updated slave device base address 1024 .

In a burst write scheme using mask and data byte pairs, the slave device 1022 has a 1-byte mask write burst length register 1026. The master device 1012 maintains a copy of the slave device's mask write burst length register 1026 at the master device 1012 in the shadow register 1016 . The master device 1012 prepares the datagram 1000 based on the specified mask and data pair burst length 1010 (eg, the number of mask and data byte pairs), but will not send the mask written in the datagram 1000 . Hair length 1010. Before sending the mask write datagram 1000, the master device will compare the specified burst length 1010 to the slave device's current copy of the mask write burst length 1026 in the shadow register 1016. If the slave device's mask write burst length 1026 does not match the specified burst length 1010, the master device 1012 will first set (or update) the mask write burst length on the slave device 1022 1026 to match the specified burst length of 1010. The master device 1012 may further update the shadow register 1016 using the updated mask write burst length 1026 . Therefore, when the 1-byte MSB 1006 matches the base address 1024 of the slave device 1022 and the specified burst length 1010 matches the mask write burst length 1026 of the slave device 1022, the master device 1012 can Send mask write datagram 1000 to slave device 1022.

Figure 11 is a diagram illustrating example operations for transmitting a datagram 1100 in a buffer. In the page addressing scheme, the slave device 1122 has a 1-byte base address register 1124. The master device 1112 maintains a copy of the slave device's base address register 1124 in the shadow register 1114 at the master device. The master device 1112 prepares a datagram 1100 based on a 16-bit address 1104 with a 1-byte Most Significant Byte (MSB) 1106 and a 1-byte Least Significant Byte (LSB) 1108, but will only send The mask is written to 1 byte LSB 1108 in datagram 1100. When sending mask writing information Before reporting 1100, the master device 1112 will compare 1130 the 1-byte MSB 1106 with the current copy of the slave device's base address register 1124 in the shadow register 1114. If the slave device's base address register 1124 in shadow register 1114 is equal to 1 byte MSB 1006 (see 1132), then there is no need to set (or update) the base address on slave device 1122 1124. If the slave device's base address register 1124 is not equal to 1 byte MSB 1106 (see 1134), then the master device 1112 will set (or update) the base address 1124 on the slave device 1222 (to Change page) to match 1 byte MSB 1106. The master device 1112 may use the register write access command 1136 or (preferably) any other type of write access command to perform the slave device base address change before sending the mask write datagram. Pages are changed only when a page mismatch is detected before the datagram is transmitted. The master device 1112 may further update the shadow register 1114 with the updated slave device base address 1124 .

In a burst write scheme using mask and data byte pairs, the slave device 1122 has a 1-byte mask write burst length register 1126. The master device 1112 maintains a copy of the slave device's mask write burst length register 1126 at the master device 1112 in the shadow register 1116 . The master device 1112 prepares the datagram 1100 based on the specified mask and data pair burst length 1110 (eg, the number of mask and data byte pairs), but will not send the mask written to the burst in the datagram 1100. Hair length 1110. Before sending the mask write datagram 1100, the master device will compare 1140 the specified burst length 1110 to the slave device's current copy of the mask write burst length 1126 in the shadow register 1116. If the mask write burst length 1126 of the slave device in the shadow register 1116 is equal to the specified burst length 1110 (see 1142), then there is no need to set (or update) the mask on the slave device 1122 Write burst length 1126. If the slave device's mask write burst length 1126 is not equal to the specified burst length 1110 (see 1144), the master device 1112 will set (or update) the mask write on the slave device 1122 Burst length 1126 to match the specified burst length 1110. The master device may use the register write access command 1146 or (preferably) any other type of write access command to perform a slave device mask write burst before sending the mask write datagram. Length changes. Mask writes the burst length Only changed if a burst length mismatch is detected before datagram transmission. The master device 1112 may further update the shadow register 1116 using the updated mask write burst length 1126 . Therefore, when the 1-byte MSB 1106 matches the base address 1124 of the slave device 1122 and the specified burst length 1110 matches the mask write burst length 1126 of the slave device 1122, the master device 1112 can Send mask write datagram 1100 to slave device 1122.

In one aspect of the invention, the mask write operation may be performed using an extended register write datagram and/or an extended register long write datagram. The payload of a data packet can be used to transmit several mask and data pairs. This operation may be referred to as a custom mask write operation below. In one aspect, the normal write datagram can be distinguished from the custom mask write datagram by defining two bits in the configuration register, as described below. The use of the write data payload for mask writing purposes is illustrated in FIGS. 12 and 13 .

FIG. 12 is a diagram illustrating an example packet structure 1200 for an extended register write command 1202 that supports mask write operations. 13 is a diagram illustrating an example packet structure 1300 for an extended register length write command 1302 that supports mask write operations.

Referring to Figures 12 and 13, a custom mask write operation can take advantage of the extension when the number of bytes in the payload segment is specified as an even number to allow the transmission of an integer number of mask and data byte pairs. Register write command 1202 and extended register length write command 1302. The first mask byte (ie, mask 0) is located at the first even position (0th byte) after the address byte in the payload. The first mask byte then corresponds to the first data byte (ie, data 0), which is located at the first odd position after the address byte. Therefore, in the payload, after the address bytes, mask bytes (e.g., mask0, mask1, mask2, etc.) can occupy even positions, while data bytes (e.g., data0, mask2, etc.) Data 1, Data 2, etc.) can occupy odd positions.

The maximum number of mask and data byte pairs that can be transferred in a write command depends on the maximum number of bytes allowed in the payload. For example, in the extended register write command 1202, the maximum allowed byte count in the payload 1204 is 16 bytes (128 bytes). Therefore, the extended temporary storage The device write command 1202 can support the transmission of a maximum of 8 mask and data byte pairs in a datagram. As shown in Figure 12, payload 1204 may include 1 to 8 mask and data byte pairs (eg, mask+data pair #0, mask+data pair #1, ..., mask+data pair #7 ). In another example, in the extended register length write command 1302, the maximum allowed byte count in the payload 1304 is 8 bytes (64 bits). Therefore, the extended register long write command 1302 can support the transmission of a maximum of 4 mask and data byte pairs in one datagram. As shown in Figure 13, payload 1304 may include 1 to 4 mask and data byte pairs (eg, mask+data pair #0, mask+data pair #1, ..., mask+data pair #3 ).

In one aspect of the invention, the 8-bit configuration register can be used to provide a control function interface to facilitate activation and deactivation using the extended register write command and/or the extended register long write command. Mask write operation. The configuration register can be located in a user-defined register space: in hexadecimal, 0x01 to 0x1C. For example, register location 0x18 can be used as a configuration register. However, in alternative aspects, it is contemplated that the configuration register may be located anywhere within the overall register space.

FIG. 14 is a diagram illustrating an example bit structure 1400 of the configuration register 1402. As shown, the configuration register 1402 includes eight configuration register bits D7, D6, D5, D4, D3, D2, and D1. In one aspect of the present invention, the third register bit D5 1404 and the fourth register bit D4 1406 can be used to distinguish the extended register write and the extended register length write command to be used. In normal mode, the extended register write and extended register long write commands will be used for custom mask write operations.

For example, when the third register bit D5 1404 is set to a value of 1, a custom mask write operation is enabled, and the extended register write command or the extended register long write command Will be used for mask write operations. However, when third register bit D5 1404 is set to a value of 0, the custom mask write operation is disabled, and both the extended register write command and the extended register long write command will be used in the normal way. In addition, when the fourth register bit D4 1406 is set to the value 1, then if the third register bit D5 1404 is set to the value 1, then the extended register length write command (such as the extended register The scratchpad long write command 1302) will be used specifically for custom mask write operations. When the fourth register bit D4 1406 has When set to a value of 0, then if the third register bit D5 1404 is set to a value of 1, an extended register write command (such as the extended register write command 1202) will be used specifically for custom Mask write operation.

Figure 15 is a diagram of an RFFE register space 1500. The RFFE register space 1500 can be extended in hexadecimal from register 0x0000 to register 0xFFFF.

A correlation of commands in terms of register space accessibility is shown in Figure 15. The range of extended register operations can be limited to the space between the 0x00 register and the 0xFF register. However, a complex RFFE slave can contain multiple pages within the 64K register space (each with 1-byte locations from 0x00 to 0xFF), and thus enable extended register operations to access the entire 64K register space. memory space and reduce bus drain latency. To achieve this, the 64K register space can be segmented into 256 pages (pages 0x00 to 0xFF), each containing 256 register locations. An 8-bit register address in a database combined with a page address allows any register access within the 64K space. The page address can be stored at a known register location and combined with the 8-bit register address (address LSB) provided by the data report to form an address MSB. For an extended register operation, this can be the basis for page segmented accesses.

Figure 16 is a diagram of an RFFE register space 1600 having a configuration register and a page address register. To facilitate the enabling and disabling of various features, an 8-bit configuration register is used. The configuration register and a page address register can use two specific registers in the register space that are accessible for register mode. For example, as shown in Figure 16, the configuration register may be defined at location 0x18 in the register space, and the page address register may be defined at location 0x19. Positions 0x18 and 0x19 are both in a user-defined space.

Figure 17 illustrates a diagram 1700 defining another example bit structure of a configuration register and a diagram 1750 depicting the functions of the configuration register bits. The configuration register containing bit locations D7 to D0 can be defined at register location 0x18. Referring to diagram 1700 and diagram 1750, page segmented access (PSA) may be enabled (eg, set to "1") or disabled (eg, set to "0") by configuring the bit at bit location D2 and enable or disable. Double Data Rate (DDR) mode can be enabled or disabled by enabling or disabling the combination of bit positions D1 status bits to enable or disable. Additionally, Custom Mask Write (CMW) can be enabled or disabled by enabling or disabling the configuration bit at bit location D0. For D0, D1 and D2, configuring a bit value of "1" means enabling the corresponding function and configuring a bit value of "0" means disabling the corresponding function.

Figure 18 is a diagram 1800 illustrating page segmented access. Standard extended register operations are based on an 8-bit register address. This limits the applicability of these modes to register accesses to the first 256 locations of the register space (0x00 to 0xFF). Therefore, Page Segmented Access (PSA) for extended register operations can be used to access the entire 64K register space using only the 8-bit register address in the datagram. A replacement for one of the standard extended register long operations. Because only 8-bit register addresses are used, page segmentation also allows a maximum payload of 16 bytes per data report, compared to using 16-bit addresses and having 8 bytes per data report. Maximum payload conventional extended register operations are more efficient.

64K register space access can be enabled for extended register mode by using the page segmented address register as the register address (MSB location). From a chip-level design perspective, PSA operations can be orthogonal to mask write operations and double data rate (DDR) mode operations. Page Segmented Access (PSA) for extended register mode can be enabled using a 1-byte register with the register address MSB included in the configuration register and a single configuration bit.

The PSA for extended register operations can be applied to both read operations and write operations. The PSA can use the value located at register location 0x19 as the register address MSB and compare the register address MSB with the 8-bit address (register bit) supplied in the extended register operation data report. address LSB) concatenation. A single bit in the configuration register enables/disables PSA.

Page segment access using the contents of register location 0x19 and the address LSB retrieved from the extended register operation data report is shown in Figure 18. Page address register 1802 at register location 0x19 may contain 8-bit MSB values for register addresses in register space 0x0000 to 0xFFFF. The value from register location 0x19 can be used as the address MSB and combined with the self-expanding register operation data. The received 8-bit address 1804 (address LSB) combination is reported. Therefore, the entire 64K register space can be accessed using only one of the 8-bit register addresses 1804 in the extended register operation datagram. If Page Segmented Access (PSA) mode is disabled, the value at register location 0x19 has no effect on extended register operations.

In one aspect of the invention, page segmented access (PSA) for extended register operations allows full access to the entire 16-bit address space of any RFFE device. Enabling this feature provides several advantages over extended register length-based operations. For example, using only the 8-bit address in the datagram, the entire 64K register space becomes available. Additionally, since an extended register command can have a payload of up to 16 bytes compared to an extended register length command, an extended register length command can only have a payload of up to 8 bytes. Therefore PSA provides improved delivery capacity and reduced latency.

The PSA can be configured by enabling (e.g., setting to "1") or disabling (e.g., setting to "0") a single configuration bit in the configuration register located at register location 0x18 (e.g., at bit location 0x18). Configuration bit at D2) to enable or disable. When enabled, the 8-bit page address stored at register location 0x19 serves as the register address MSB and can be attached to the 8-bit address supplied within the extended register datagram (acting as Register address LSB).

Referring back to Figure 12, if page segmented access (PSA) is not enabled, the extended register write command 1202 that supports mask write operations can be limited to the first 256 locations of the register space (register locations 0x00 to 0xFF). However, when PSA is enabled, the extended register write command 1202 that supports mask write operations may have full access to the entire 64K register space. As described above, by using the 8-bit page address stored at register location 0x19 as the register address MSB, and appending the register address MSB to the extended register write The 8-bit address supplied in command 1202 (used as the register address LSB) facilitates full access to the entire 64K register space.

Examples of hardware implementations

19 is a conceptual diagram illustrating a simplified example of a hardware implementation of a device 1900 employing processing circuitry 1902 that can be configured to perform one or more functions disclosed herein. According to various aspects of the invention, an element, or any portion of an element, or any combination of elements as disclosed herein, may be implemented using processing circuitry 1902. Processing circuitry 1902 may include one or more processors 1904 controlled by some combination of hardware and software modules. Examples of processors 1904 include microprocessors, microcontrollers, digital signal processors (DSPs), ASICs, field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, sequencers, Gating logic, discrete hardware circuits, and other suitable hardware configured to perform the various functionality described throughout this disclosure. One or more processors 1904 may include special purpose processors that perform specific functions and may be configured, expanded, or controlled by one of the software modules 1916 . One or more processors 1904 may be configured through a combination of software modules 1916 loaded during initialization and additionally configured by loading or unloading one or more software modules 1916 during operation.

In the illustrated example, processing circuitry 1902 may be implemented with a bus architecture represented generally by bus 1910 . Bus 1910 may include any number of interconnecting busses and bridges depending on the specific application and overall design constraints of processing circuit 1902 . Bus 1910 links together various circuits including one or more processors 1904 and memory 1906 . Storage 1906 may include memory devices and mass storage devices, and may be referred to herein as computer-readable media and/or processor-readable media. Bus 1910 may also connect various other circuits, such as timing sources, timers, peripheral devices, voltage regulators, and power management circuits. Bus interface 1908 may provide an interface between bus 1910 and one or more line interface circuits 1912 . Line interface circuitry 1912 may be provided for each network connection technology supported by the processing circuitry. In some cases, multiple network connection technologies may share some or all of the circuitry or processing modules found in online interface circuitry 1912. Each line interface circuit 1912 provides a means for communicating with various other devices via transmission media. Depending on the nature of the device 1900, a user interface 1918 (e.g., keypad, display, speakers, microphone, joystick) may also be provided, and the user interface may be communicatively coupled to the bus directly or via the bus interface 1908 1910.

Processor 1904 may be responsible for managing bus 1910 and may be responsible for general processing, which may include execution of software stored in computer-readable media, which may include storage 1906 . In this regard, processing circuitry 1902 including processor 1904 may be used to implement any of the methods, functions, and techniques disclosed herein. Storage 1906 may be used to store data manipulated by processor 1904 when executing software, and the software may be configured to perform any of the methods disclosed herein.

One or more processors 1904 in processing circuitry 1902 may execute software. Software shall be construed broadly to mean instructions, sets of instructions, code, code segments, program code, routines, subroutines, software modules, applications, software applications, packages, routines, subroutines, objects, Execution code, thread, program, function, algorithm, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The software may reside in computer-readable form in storage 1906 or on external computer-readable media. External computer-readable media and/or storage 1906 may include non-transitory computer-readable media. By way of example, non-transitory computer-readable media includes magnetic storage devices (e.g., hard disks, floppy disks, magnetic stripes), optical disks (e.g., compact discs (CDs) or digital versatile discs (DVDs)), smart cards , flash memory device (e.g., "pen drive," card, stick, or secure disk), random access memory (RAM), read-only memory (ROM), programmable ROM (PROM), erasable Except for PROM (EPROM), electrically erasable PROM (EEPROM), registers, removable disks, and any other suitable storage medium for storing software and/or instructions that can be accessed and read by a computer. media. By way of example, computer-readable media and/or storage 1906 may also include carrier waves, transmission lines, and any other suitable medium for transmitting software and/or instructions that can be accessed and read by a computer. Computer-readable media and/or storage 1906 may reside within processing circuitry 1902 , within processor 1904 , external to processing circuitry 1902 , or distributed across multiple entities including processing circuitry 1902 . Computer-readable media and/or storage 1906 may be embodied in a computer program product. By way of example, a computer program product may include a computer-readable medium in the packaging material. Those skilled in the art will recognize the manner in which the described functionality presented throughout this disclosure is best implemented depending on the particular application and the overall design constraints imposed on the overall system.

Storage 1906 may maintain software maintained and/or organized in loadable code segments, modules, applications, programs, etc. (which may be referred to herein as software modules 1916). Each of software modules 1916 may include instructions and data that when installed or loaded on processing circuitry 1902 and executed by one or more processors 1904 facilitate a control of the operation of one or more processors 1904 Execution time image 1914. When executed, certain instructions may cause processing circuit 1902 to perform functions in accordance with certain methods, algorithms, and procedures described herein.

Certain software modules 1916 may be loaded during initialization of the processing circuit 1902, and such software modules 1916 may configure the processing circuit 1902 to enable performance of the various functions disclosed herein. For example, some software modules 1916 may configure the internal devices and/or logic circuitry 1922 of the processor 1904 and may manage functions such as line interface circuitry 1912, bus interface 1908, user interface 1918, timers, math commons, etc. Access to external devices such as processors. Software module 1916 may include a control program and/or an operating system that interacts with interrupt handlers and device drivers and controls access to various resources provided by processing circuitry 1902 . Resources may include memory, processing time, access to wire interface circuitry 1912, user interface 1918, etc.

One or more processors 1904 of processing circuit 1902 may be multifunctional, whereby several software modules 1916 are loaded and configured to perform different functions or different instances of the same function. For example, one or more processors 1904 may additionally be adapted to manage background tasks initiated in response to input from user interface 1918, line interface circuitry 1912, and device drivers. To support execution of multiple functions, one or more processors 1904 may be configured to provide a multitasking environment whereby each of the plurality of functions is implemented as needed or desired by one or more processors A set of tasks for the 1904 servo. In one example, a multitasking environment may be implemented using a time-sharing program 1920 through control of the processor 1904 between different tasks, whereby each task completes any outstanding operations and/or in response to input such as an interrupt. Control of one or more processors 1904 is returned to time-sharing routine 1920. When a task has control of one or more processors 1904, the processing circuitry is effectively specified to be solved by the functionality associated with controlling the task. the goal of. Time-sharing program 1920 may include an operating system, a primary loop that delivers control on a round-robin basis, functionality that allocates control to one or more processors 1904 based on priority of functionality, and/or by providing one or more processors 1904 The main interrupt-driven loop controls the processing function and responds to external events. Exemplary methods and apparatus for sending data packets from a transmitter to a receiver

Figure 20 is a flowchart 2000 of a method for sending data to a receiver via a bus interface. The method may be performed at a device operating as a transmitter (eg, bus master).

The device can generate a data report 2002 based on the 16-bit address and the mask and data burst length. The 16-bit address includes the most significant byte (MSB) and the least significant byte (LSB).

The device then compares the MSB to the receiver base address (segment or value) maintained in the shadow register 2004. This comparison includes detecting whether the MSB is equal to the receiver base address maintained in the shadow register. If the MSB is not equal to the receiver base address maintained in the shadow register, the device sets the base address at the receiver equal to the MSB. The device can set the base address at the receiver by sending a write access command to the receiver before sending a datagram. The device further updates the receiver base address maintained in the shadow register to the MSB.

The device may further compare the mask and data pair burst lengths to the receiver mask write burst length (segment or value) maintained in the shadow register 2006. This comparison includes detecting whether the mask and data pair burst length is equal to the receiver mask write burst length maintained in the shadow register. If the mask and data pair burst length is not equal to the receiver mask write burst length maintained in the shadow register, the device sets the mask write burst length at the receiver to be equal to the mask and data On the length of the tufts. A device can set the mask write burst length at the receiver by sending a write access command to the receiver before sending a datagram. The device further updates the receiver mask write burst length maintained in the shadow register to the mask and data pair burst length.

Finally, when the MSB is equal to the receiver base address maintained in the shadow register and the mask and data pair burst length is equal to the receiver mask write burst length maintained in the shadow register, the device The device sends data reports to the receiver 2008 via the bus interface. The datagram sent to the receiver does not include the MSB as well as the mask and data pair burst length.

Figure 21 is a flowchart 2100 of another method for sending data to a receiver via a bus interface. The method may be performed at a device operating as a transmitter (eg, bus master).

The device may generate command fields 2102 in the datagram to be transmitted to the receiver via the bus interface. The command field can indicate the type of mask write command for the data report. For example, the data report is an extended register mask write command, an extended register long mask write command, or a register mask write command. Enter command or extended register short mask write command.

Alternatively, the device may generate the command field and mode field 2104 in the data report. Thus, the command field may indicate that the data report is a mask write command and the mode field may indicate the mask write command type, such as that the data report is an extended register mask write command, an extended register length Mask write command, register mask write command or extended register short mask write command.

The device can generate mask fields 2106 in the data report. The mask field identifies at least one bit to be changed in the radio frequency front end (RFFE) register. The mask field also indicates the remaining set of bits to remain unchanged in the RFFE register. The device may also generate data fields 2108 in the data report. The data field provides the value of at least one bit to be changed in the RFFE register. In one aspect of the invention, the mask field is a bit index field that identifies the bit position to be changed in the RFFE register, and the data field is a bit index field that provides the bit position identified in the bit index field. The bit value field of the bit position value.

Finally, the device can transmit a datagram via the interface, where the datagram is addressed to the receiver's RFFE register 2110.

Figure 22 is a flowchart 2200 of another method for sending data to a receiver via a bus interface. The method may be performed at a device operating as a transmitter (eg, bus master).

The device may set the configuration register to indicate whether mask write operations 2202 are enabled on datagrams to be transmitted to the receiver. The configuration register can include eight register bits. Therefore, the device can The third register bit of the eight register bits (eg, register bit D5 1404) is set to a value of 1 to indicate that the mask write operation is enabled. Alternatively, the device may set a third register bit (eg, register bit D5 1404) to a value of 0 to indicate that the mask write operation is disabled.

In one aspect, the datagram may be an extended register write command or an extended register write command. Therefore, when a mask write operation is enabled, the device can set the fourth register bit (e.g., register bit D4 1406) in the configuration register to a value of 1 to indicate that the extended register The long write command enables mask write operations. When a mask write operation is enabled, the device may also set a fourth register bit (eg, register bit D4 1406) to a value of 0 to indicate that a mask write is enabled for an extended register write command. operate.

The device can generate the command field 2204 in the data report. The command field may indicate whether the data report is an extended register write command or an extended register long write command.

The device may also generate the payload field 2206 in the data report. When mask writing is enabled the payload field can contain several mask and data pairs. Each mask and data pair may include a mask field identifying at least one bit to be changed in the radio frequency front end (RFFE) register and providing a value for at least one bit to be changed in the RFFE register data field.

The device transmits datagrams through the bus interface, where the datagrams are addressed to the receiver's RFFE register 2208.

Figure 23 is a flowchart 2300 of another method for sending data to a receiver via a bus interface. The method may be performed at a device operating as a transmitter (eg, bus master).

The device may enable the mask write operation 2302 by setting a single bit in the configuration register at the receiver to a first value. Additionally and/or alternatively, the device may disable the mask write operation by setting a single bit within the configuration register at the receiver to the second value. For example, a mask write operation can be enabled by performing a write operation to the receiver's configuration register (such as the register at location 0x18) to set bit D0 to the value "1" . In another example, the configuration of the receiver can be performed by A write operation to a register (such as the register at location 0x18) sets bit D0 to the value "0" to disable the mask write operation.

The device may generate a datagram 2304 to be transmitted to the receiver via the bus interface. The datagram includes or provides an address value (eg, register address 1804 in Figure 18). The datagram can be an extended register write datagram or an extended register write long datagram.

The device may also generate the payload field 2306 in the data report. When the mask writing operation is enabled the payload field contains several mask and data pairs. Each mask and data pair includes a mask field identifying at least one bit to be changed in the radio frequency front end (RFFE) register and providing a value of at least one bit to be changed in the RFFE register. Data field.

The device may enable the page segment access operation 2308 by setting another single bit within the configuration register at the receiver to the first value. For example, page segmented access can be enabled by performing a write operation to the receiver's configuration register (such as the register at location 0x18) to set bit D2 to the value "1" operate. When the page segment access operation is enabled, the address of the RFFE register is the address value located in the page address register at the receiver (for example, register location 0x19) and the bit provided by the datagram. A combination of address values.

The device may disable the page segment access operation 2310 by setting another single bit within the configuration register at the receiver to the second value. For example, a page segment access operation may be performed by performing a write operation to the receiver's configuration register (such as the register at location 0x18) to set bit D2 to the value "0" Deactivate. When page segmentation is disabled, the address of the RFFE register is the address value provided by the datagram.

The device may transmit datagrams via the bus interface, where the datagrams are addressed to the receiver's RFFE register 2312.

24 is a diagram illustrating a simplified example of a hardware implementation of a transmission device 2400 employing processing circuitry 2402. Examples of operations performed by transmission device 2400 include those described above with respect to Figures 20 to The operations described in the flowchart of Figure 23. The processing circuitry typically has a processor 2416 that may include one or more of a microprocessor, a microcontroller, a digital signal processor, a sequencer, and a state machine. Processing circuitry 2402 may be implemented with a bus architecture (represented generally by bus 2420). Bus 2420 may include any number of interconnecting busses and bridges depending on the specific application and overall design constraints of processing circuit 2402. Bus 2420 will include one or more processors, represented by processor 2416, and/or hardware modules, modules or circuits 2404, 2406, 2408, 2410 that may be configured to support communications via connectors or wires 2414 Various circuits of the bus interface circuit 2412 and the computer-readable storage medium 2418 are linked together. Bus 2420 may also link together various other circuits such as timing sources, peripherals, voltage regulators, and power management circuits that are well known in the art and therefore will not be described any further.

Processor 2416 is responsible for general processing, including executing software/instructions stored on computer-readable storage media 2418. The software/instructions, when executed by processor 2416, cause processing circuitry 2402 to perform the various functions previously described for any particular device. Computer-readable storage media may also be used to store data manipulated by processor 2416 when executing software, including data decoded using symbols transmitted through connectors or wires 2414, which connectors or wires may be configured It is a data channel and a timing channel. Processing circuitry 2402 further includes at least one of modules/circuits 2404, 2406, 2408, and 2410. Modules/circuits 2404, 2406, 2408, and 2410 may be software modules executing in processor 2416, resident/stored in computer-readable storage media 2418, and coupled to one or more hardware components of processor 2416 module, or some combination thereof. Modules/circuits 2404, 2406, 2408, and/or 2410 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

In one configuration, a device for communications 2400 includes a datagram generation/transmission module/circuitry 2404 configured to generate a burst length based on a 16-bit address and a mask and data pair. Data report, the 16-bit address includes the most significant byte (MSB) and the least significant byte (LSB); and when the MSB is equal to the receiver base address maintained in the shadow register, and the mask and The data pair burst length is equal to the receiver mask write burst length maintained in the shadow register, via the bus interface model. Group/Circuit 2412, sends this data report to the receiver. Device 2400 further includes an address comparison module/circuitry 2406 configured to compare the MSB to the receiver base address maintained in the shadow register. The device 2400 further includes a burst length comparison module/circuitry 2408 configured to compare the mask and data pair burst lengths to the receiver mask write burst length maintained in the shadow register. Device 2400 further includes a register setting module/circuitry 2410 configured to set a configuration register to indicate whether masking is enabled with respect to data packets to be transmitted to the receiver via bus interface module/circuitry 2412. Cover write operation.

In another configuration, datagram generation/transmission module/circuitry 2404 is configured to generate command fields in the datagram to be transmitted to the receiver via bus interface module/circuitry 2412, generating the command fields in the datagram. The mode field generates the payload field in the data report, generates the mask field in the data report, generates the data field in the data report, and transmits the data report via the bus interface module/circuit 2412, where the data report Addressed to the receiver's radio frequency front-end (RFFE) register.

In another configuration, datagram generation/transmission module/circuitry 2404 is configured to enable mask writing by setting a single bit in the configuration register at the receiver to a first value Operation; disables the mask write operation by setting a single bit in the configuration register at the receiver to a second value; generates a data report to be transmitted to the receiver via the bus interface, the data report Provides the address value to generate a payload field in the data report. When the mask write operation is enabled, the payload field includes a number of mask and data pairs, where each mask and data pair includes an identification of the radio to be held. A mask field for at least one bit changed in the frequency front end (RFFE) register and a data field providing the value of at least one bit to be changed in the RFFE register; by placing the Another single bit in the configuration register is set to a first value to enable the page segment access operation, wherein the address of the RFFE register is the page located at the receiver when the page segment access operation is enabled Combination of the address value at the address register and the address value provided by the datagram; deactivated by setting another single bit in the configuration register at the receiver to a second value Page segmentation access operation, in which the address of the RFFE register is provided by the data report when the page segmentation access operation is disabled. The address value provided; and the datagram is transmitted through the bus interface, where the datagram is addressed to the RFFE register of the receiver. Exemplary methods and apparatus for receiving datagrams from a transmitter at a receiver

Figure 25 is a flow diagram 2500 of a method for receiving data from a transmitter via a bus interface. The method may be performed at a device operating as a receiver (eg, a bus slave).

The device may receive data packets 2502 from the transmitter via the bus interface. Datagrams are addressed to the receiver's radio frequency front-end (RFFE) registers.

The device can read command field 2504 in the data report. The command field can indicate the type of mask write command for the data report. For example, the data report is an extended register mask write command, an extended register long mask write command, or a register mask write command. Enter command or extended register short mask write command.

Alternatively, the device may read the command field and mode field 2506 in the data report. Thus, the command field may indicate that the data report is a mask write command and the mode field may indicate the mask write command type, such as that the data report is an extended register mask write command, an extended register length Mask write command, register mask write command or extended register short mask write command.

The device can read the mask field 2508 in the data report. The mask field identifies at least one bit to be changed in the RFFE register. The mask field also indicates the remaining set of bits to remain unchanged in the RFFE register. The device can also read data field 2510 in the data report. The data field provides the value of at least one bit to be changed in the RFFE register. In one aspect of the invention, the mask field is a bit index field that identifies the bit position to be changed in the RFFE register, and the data field is a bit index field that provides the bit position identified in the bit index field. The bit value field of the bit position value.

Ultimately, the device may change at least one bit 2512 of the RFFE register identified in the mask field based on the value provided in the data field.

Figure 26 is a flow diagram 2600 of another method for receiving data from a transmitter via a bus interface. The method may be performed at a device operating as a receiver (eg, a bus slave).

The device may read the configuration register to detect whether mask write operation 2602 is enabled for datagrams to be received from the transmitter. The configuration register consists of eight register bits. Therefore, the device can detect that the mask write operation is enabled when the third register bit of the eight register bits (eg, register bit D5 1404) is set to a value of 1. The device may also detect that the mask write operation is disabled when a third register bit (eg, register bit D5 1404) is set to a value of zero.

In one aspect, the datagram may be an extended register write command or an extended register write command. Therefore, when a mask write operation is enabled, the device can detect an extension when the fourth register bit (e.g., register bit D4 1406) in the configuration register is set to a value of 1. The scratchpad long write command enables mask write operations. When a mask write operation is enabled, the device may also detect that the extended register write command enables the mask when the fourth register bit (eg, register bit D4 1406) is set to a value of 0. Cover write operation.

The device may receive datagrams 2604 from the transmitter via the bus interface, where the datagrams are addressed to the radio frequency front-end (RFFE) registers of the receiver.

The device can read command field 2606 in the data report. The command field indicates whether the data report is an extended register write command or an extended register write command.

The device can also read payload field 2608 in the data report. When the mask writing operation is enabled the payload field contains several mask and data pairs. Each mask and data pair includes a mask field identifying at least one bit to be changed in the RFFE register and a data field providing the value of the at least one bit to be changed in the RFFE register. Bit. Ultimately, the device may change at least one bit 2610 in the RFFE register identified in the mask field based on the value provided in the data field of each mask and data pair.

Figure 27 is a flow diagram 2700 of another method for receiving data from a transmitter via a bus interface. The method may be performed at a device operating as a receiver (eg, a bus slave).

The device may receive a first datagram 2702 from the transmitter for setting a single bit in the configuration register at the receiver. The device can detect when a single bit in the configuration register is set to the first value. Detected that mask write operation is enabled. Alternatively, the device may detect that the mask write operation is disabled 2704 when a single bit within the configuration register at the receiver is set to the second value. For example, a device may detect when bit D0 in the receiver's configuration register (e.g., the register at location 0x18) has the value "1" as set by the transmitter via a write operation. To mask writing operations are enabled. In another example, the device may operate when bit D0 in the receiver's configuration register (e.g., the register at location 0x18) has a value of "0" as set by the transmitter via a write operation. Mask writing disabled was detected.

The device may receive a second datagram 2706 from the transmitter. The second datagram includes or provides an address value (eg, register address 1804 in Figure 18). The second datagram may be an extended register write datagram or an extended register write long datagram.

The device can read the payload field 2708 in the second data report. When the mask writing operation is enabled the payload field contains several mask and data pairs. Each mask and data pair includes a mask field identifying at least one bit to be changed in a radio frequency front end (RFFE) register of the receiver and providing at least one bit to be changed in the RFFE register A data field with a value.

The device may receive a third data report 2710 from the transmitter for setting another single bit in the configuration register at the receiver. The device may detect that the page segmentation access operation is enabled 2712 when another single bit in the configuration register at the receiver is set to the first value. For example, a device may detect when bit D2 in the receiver's configuration register (e.g., the register at location 0x18) has the value "1" as set by the transmitter via a write operation. Staging access to the page is enabled. When the page segment access operation is enabled, the address of the RFFE register is the address value located in the page address register at the receiver (for example, register location 0x19) and the bit provided by the datagram. A combination of address values.

The device may detect that the page segmentation access operation is disabled 2714 when another single bit in the configuration register at the receiver is set to the second value. For example, a device may have bit D2 in the receiver's configuration register (e.g., the register at location 0x18) as configured by the transmitter via a write operation. When setting the value of "0", it is detected that the page segmentation operation is disabled. When page segmentation is disabled, the address of the RFFE register is the address value provided by the datagram.

The device may change at least one bit 2716 in the RFFE register identified in the mask field based on the value provided in the data field of each mask and data pair.

Figure 28 is a diagram illustrating a simplified example of a hardware implementation of a receiving device 2800 employing processing circuitry 2802. Examples of operations performed by receiving device 2800 include the operations described above with respect to the flowcharts of Figures 25 and 27. The processing circuitry typically has a processor 2816 that may include one or more of a microprocessor, a microcontroller, a digital signal processor, a sequencer, and a state machine. Processing circuitry 2802 may be implemented with a bus architecture (represented generally by bus 2820). Bus 2820 may include any number of interconnecting busses and bridges depending on the specific application and overall design constraints of processing circuit 2802. Bus 2820 will include one or more processors, represented by processor 2816, and/or hardware modules, modules or circuits 2804, 2806, 2808, 2810 that may be configured to support communications via connectors or wires 2814 Various circuits of the bus interface circuit 2812 and the computer-readable storage medium 2818 are linked together. Bus 2820 may also link together various other circuits such as timing sources, peripherals, voltage regulators, and power management circuits that are well known in the art and therefore will not be described any further.

Processor 2816 is responsible for general processing, including executing software/instructions stored on computer-readable storage media 2818. The software/instructions, when executed by processor 2816, cause processing circuitry 2802 to perform the various functions previously described for any particular device. Computer-readable storage media may also be used to store data manipulated by processor 2816 when executing software, including data decoded using symbols transmitted through connectors or wires 2814, which connectors or wires may be configured It is a data channel and a pulse channel. Processing circuitry 2802 further includes at least one of modules/circuits 2804, 2806, 2808, and 2810. Modules/circuits 2804, 2806, 2808, and 2810 may be software modules executing in processor 2816, resident/stored in computer-readable storage media 2818, and coupled to one or more hardware components of processor 2816 module, or a certain combination thereof. Modules/circuits 2804, 2806, 2808, and/or 2810 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

In one configuration, a device for communications 2800 includes a datagram receiving module/circuitry 2804 configured to receive datagrams from a transmitter via a bus interface module/circuitry 2812, where the datagrams are addressed to Device 2800 Radio Frequency Front End (RFFE) register. Device 2800 further includes a field reading module/circuitry 2806 configured to read the command field in the data report, read the payload field in the data report, and read the mode field in the data report. , read the mask field in the data report, and read the data field in the data report. Device 2800 further includes a bit change module/circuitry 2808 configured to change at least one bit in the RFFE register identified in the mask field based on the value provided in the data field. Device 2800 also includes a register read module/circuitry 2810 configured to read the configuration register to detect whether a mask write operation is enabled for a datagram to be received from the transmitter.

In another configuration, the datagram receiving module/circuit 2804 is configured to: receive a first datagram from the transmitter that sets a single bit in the configuration register at the receiver; in the configuration A mask write operation is enabled when a single bit in the register is set to a first value; a mask write operation is enabled when a single bit in the configuration register at the receiver is set to a second value. until the mask write operation is disabled; receive a second datagram from the transmitter that provides an address value; receive from the transmitter another value in the configuration register used to set the receiver. A third datagram of a single bit; detecting that the page segmentation access operation is enabled when another single bit in the configuration register at the receiver is set to the first value, wherein when page segmentation is enabled During a segment access operation, the address of the RFFE register is a combination of the address value at the page address register at the receiver and the address value provided by the datagram; and the combination at the receiver When another single bit in the status register is set to the second value, it is detected that the page segmentation access operation is disabled, wherein when the page segmentation access operation is disabled, the address of the RFFE register is the address value provided via the datagram,

In another configuration, the field read module/circuitry 2806 is configured to read a payload field in the second data report that includes a number of masks when a mask write operation is enabled. and data pair, its Each mask and data pair includes a mask field identifying at least one bit to be changed in the radio frequency front end (RFFE) register of the receiver and providing at least one bit to be changed in the RFFE register Data field for dollar value.

In another configuration, the field read module/circuitry 2806 is configured to change the RFFE register identified in the mask field based on the value provided in the data field of each mask and data pair. At least one bit in it.

Another exemplary mask writing operating environment for a radio frequency front-end (RFFE) device

29 is a block diagram illustrating an example architecture for a device 2900 that may employ an RFFE bus 2902 to connect bus master device 2904 to slave devices 2906(1)-2906(N). RFFE bus 2902 can be configured according to application requirements, and access to multiple buses 2902 can be provided to some of devices 2904 and 2906(1)-2906(N). In one aspect, bus master device 2904 and slave devices 2906(1)-2906(N) may be configured to operate with the bus described above (eg, with respect to FIGS. 2 and 3). The master controller device and the slave controller device operate in the same manner.

In another aspect, any of the slave devices 2906(1)-2906(N) (eg, a source slave device) may generate another slave device directed onto the RFFE bus 2902 The mask is written into the data report. The mask write datagram may include a mask field identifying at least one bit to be changed in the RFFE register of the directed slave device and providing at least one bit to be changed in the RFFE register. Value data field. Before the source slave device sends a mask write data packet to the directed slave device, the source slave device may request the bus master device 2904 to perform slave-to-slave communication. Thereafter, if permitted by bus master device 2904, the source slave device may send a mask write data report to the directed slave device.

In one aspect, bus master device 2904 may be configured to perform security functions regarding slave-to-slave communications on RFFE bus 2902 . For example, the bus master controller Setup 2904 may include an authentication circuit/module 2916 configured to determine whether slave-to-controller communication is allowed, for example, based on a graph query of allowed interactions.

Generally speaking, when one of slave devices 2906(1) through 2906(N) indicates a request to send a mask write datagram on RFFE bus 2902 to another slave device, the bus master Controller device 2904 may consider the request (via authentication circuitry/module 2916) and compare the intended controller-to-controller communication to the system definition for which the interaction is allowed. This comparison may include communications with the security entity. If bus master device 2904 approves the requested slave-to-slave communication, bus master device 2904 may not take a particular action or may confirm approval of the requesting slave device. If the bus master device 2904 does not approve the requested slave-to-slave communication, the bus master device 2904 can prevent the sending of the mask write datagram on the RFFE bus 2902 and send the requested slave to the slave. Approved notification requests the controlled device, and/or takes some other action.

Figure 30 is a flow diagram 3000 of a method for communicating mask write packets between slave devices over an RFFE bus.

At 3002, the slave device may generate a mask write datagram directed to another slave device on the RFFE bus. The slave device may further instruct the bus master device a request to send a mask write data packet to another slave device.

At 3004, the bus master device may receive the request and determine whether to authorize the slave device to send a mask write data report to another slave device. For example, the bus master device may compare the requested slave-to-slave communication to the system definition that is allowed to interact.

At 3006, if the bus master device authorizes slave-to-slave communication, the bus master device (at 3008) permits the slave device to send a mask write data packet to another slave. device. For example, the bus master device may permit sending of the mask write datagram by not taking a specific action or by indicating to the requesting slave device that slave slave communication is approved.

Alternatively, at 3006, if the bus master device does not authorize slave-to-slave communication, the bus master device (at 3010) may prevent the slave device from sending a mask write data report. to another controlled device. For example, the bus master device can prevent the mask from writing data by indicating to the requesting slave device that slave-to-slave communication is not approved and/or issuing a bus park cycle on the RFFE bus. The communication of the message prevents the sending of the mask write data message. Exemplary methods and apparatus for facilitating data communication on a bus

Figure 31 is a flow diagram 3100 of a method for facilitating data communication on a bus. Methods can be executed at the master device.

The master device may receive a request 3102 from a first slave device to send a mask write data packet to a second slave device via the bus. The mask write datagram is addressed to the radio frequency front end (RFFE) register of the second slave device. The mask write datagram may include a mask field identifying at least one bit to be changed in the RFFE register and a data field providing a value of at least one bit to be changed in the RFFE register. Bit. The mask field further identifies the remaining set of bits that remain unchanged in the RFFE register of the second slave device. In one aspect, the mask field is a bit index field that identifies a bit location to be changed in the RFFE register of the second slave device and the data field is provided in the bit index field The bit value field of the bit value of the identified bit position.

The master device may detect whether the first slave device is authorized to send a mask write data report to the second slave device 3104. For example, the master device may compare the requested mask write datagram communication to the system definition of allowed interactions between the slave device. In one aspect, the master device may communicate with the security entity to determine whether the mask write datagram communication is allowed.

If authorization is detected, the master device may allow the first slave device to send the mask write data report to the second slave device 3106. In one aspect, the master device may grant permission by notifying the first slave device that the first slave device is authorized to send a mask write datagram. Alternatively, the master device may grant permission by not taking a specific action.

If authorization is not detected, the master device may prevent the first slave device from sending a mask write data report to the second slave device 3108. In one aspect, the master device may prevent the first slave device from notifying the first slave device of unauthorized sending of a mask write datagram. Additionally and/or alternatively, the master device may prevent the sending of the mask write datagram by issuing a bus park cycle on the bus.

32 is a diagram illustrating a simplified example of a hardware implementation of a master device 3200 employing processing circuitry 3202. Examples of operations performed by host device 3200 include the operations described above with respect to the flowcharts of FIGS. 30 and 31 . The processing circuitry typically has a processor 3216 which may include one or more of a microprocessor, microcontroller, digital signal processor, sequencer, and state machine. Processing circuitry 3202 may be implemented with a bus architecture (represented generally by bus 3220). Bus 3220 may include any number of interconnecting busses and bridges depending on the specific application and overall design constraints of processing circuit 3202. Bus 3220 will include one or more processors, represented by processor 3216, and/or hardware modules, modules or circuits 3204, 3206, 3208, 3210 that may be configured to support communications via connectors or wires 3214 The various circuits of the bus interface circuit 3212 and the computer-readable storage medium 3218 are linked together. Bus 3220 may also link together various other circuits such as timing sources, peripherals, voltage regulators, and power management circuits that are well known in the art and therefore will not be described any further.

Processor 3216 is responsible for general processing, including executing software/instructions stored on computer-readable storage media 3218. The software/instructions, when executed by processor 3216, cause processing circuitry 3202 to perform the various functions described above for any particular device. Computer-readable storage media may also be used to store data manipulated by processor 3216 when executing software, including data decoded using symbols transmitted through connectors or wires 3214, which connectors or wires may be configured It is a data channel and a timing channel. Processing circuitry 3202 further includes at least one of modules/circuits 3204, 3206, 3208, and 3210. Modules/circuits 3204, 3206, 3208, and 3210 may be software modules executing in processor 3216, resident/stored in computer-readable storage media 3218, and coupled to one or more hardware components of processor 3216 module, or a certain combination thereof. Modules/circuits 3204, 3206, 3208, and/or 3210 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

In one configuration, the apparatus for communicating 3200 includes a request receive module/circuitry 3204 configured to receive a mask write data packet from a first slave device over the bus to a second slave device. a request from a slave device, wherein the mask write datagram is addressed to a radio frequency front-end (RFFE) register of the second slave device, the mask write datagram including identifying changes to be made in the RFFE register A mask field of at least one bit and a data field providing the value of at least one bit to be changed in the RFFE register. Apparatus 3200 further includes a datagram authorization module/circuitry 3206 configured to detect whether the first slave device is authorized to send the mask write datagram to the second slave device. Apparatus 3200 also includes a datagram transmission permission module/circuitry 3208 configured to permit the first slave device to send a mask write datagram to the second slave device if authorization is detected. Apparatus 3200 further includes a datagram transmission prevention module/circuitry 3210 configured to prevent a first slave device from sending a mask write datagram to a second slave device if authorization is not detected. Exemplary methods and apparatus for communicating data from a first slave device to a second slave device over a bus

Figure 33 is a flow diagram 3300 of a method for communicating data between slave devices over a bus. The method may be performed at the first control device.

The first slave device may generate a mask write datagram 3302 to be sent to the second slave device via the bus. The mask write datagram may be addressed to the radio frequency front end (RFFE) register of the second slave device. The mask write datagram may include a mask field identifying at least one bit to be changed in the (RFFE) register and providing the at least one bit to be changed in the RFFE register. A data field of one value. The mask field further identifies the remaining set of bits that remain unchanged in the RFFE register of the second slave device. In one aspect, the mask field is a bit index field that identifies a bit location to be changed in the RFFE register of the second slave device and the data field is provided in the bit index field The bit value field of the bit value of the identified bit position.

The first slave device may request permission 3304 from the master device to send a mask write data packet to the second slave device. The first slave device may then detect whether permission to send the mask write datagram is granted 3306 by the master device.

For example, the first slave device may detect that permission is granted when the first slave device receives a notification from the master device that the first slave device is permitted to send a mask write datagram. In another example, the first control device may detect that permission is granted if the first control device does not receive a response to the request after a threshold amount of time has elapsed. Therefore, if permitted by the master device, the first slave device may send a mask write data report to the second slave device 3308.

In another example, the first slave device may detect the permission failure when the first slave device receives a notification from the master device that the first slave device is not permitted to send the mask write datagram. be awarded. In yet another example, the first slave device may detect that permission is not granted by observing a bus park cycle issued by the master device on the bus to prevent the sending of a mask write datagram. Therefore, the first slave device may refrain from sending the mask write data report to the second slave device 3310 if not permitted by the master device.

34 is a diagram illustrating a simplified example of a hardware implementation of a slave device 3400 employing processing circuitry 3402. Examples of operations performed by slave device 3400 include the operations described above with respect to the flowcharts of Figures 30 and 33. The processing circuitry typically has a processor 3416 which may include one or more of a microprocessor, microcontroller, digital signal processor, sequencer, and state machine. Processing circuitry 3402 may be implemented with a bus architecture (represented generally by bus 3420). Bus 3420 may include any number of interconnecting busses and bridges depending on the specific application and overall design constraints of processing circuit 3402. Bus 3420 will include one or more processors, represented by processor 3416, and/or hardware modules, modules or circuits 3404, 3406, 3408, 3410 that may be configured to support communications via connectors or wires 3414 Various circuits of the bus interface circuit 3412 and the computer-readable storage medium 3418 are linked together. Confluence Bank 3420 may also link together various other circuits such as timing sources, peripherals, voltage regulators, and power management circuits that are well known in the art and therefore will not be described any further.

Processor 3416 is responsible for general processing, including executing software/instructions stored on computer-readable storage media 3418. The software/instructions, when executed by processor 3416, cause processing circuitry 3402 to perform the various functions described above for any particular device. Computer-readable storage media may also be used to store data manipulated by processor 3416 when executing software, including data decoded using symbols transmitted through connectors or wires 3414, which connectors or wires may be configured It is a data channel and a timing channel. Processing circuitry 3402 further includes at least one of modules/circuits 3404, 3406, 3408, and 3410. Modules/circuits 3404, 3406, 3408, and 3410 may be software modules executing in processor 3416, resident/stored in computer-readable storage media 3418, and coupled to one or more hardware components of processor 3416 module, or some combination thereof. Modules/circuits 3404, 3406, 3408, and/or 3410 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

In one configuration, apparatus for communications 3400 includes a datagram generation module/circuitry 3404 configured to generate a datagram at a first slave device to be sent to a second slave device via the bus. A mask write datagram, wherein the mask write datagram is addressed to a radio frequency front end (RFFE) register of the second slave device, the mask write datagram includes an identification stay (RFFE) temporary A mask field for at least one bit changed in the register and a data field providing the value of at least one bit to be changed in the RFFE register. Apparatus 3400 further includes a permission request module/circuitry 3406 configured to request permission from the master device to send the mask write data report to the second slave device. Apparatus 3400 also includes an permission detection module/circuitry 3408 configured to detect whether the first slave device is authorized to send mask write data reports to the second slave device. Apparatus 3400 further includes a datagram sending module/circuitry 3410 configured to send a mask write datagram to the second slave device if permitted by the master device and if not enabled by the master device. If allowed, it is prohibited to send mask write data reports to the second slave device.

It is understood that the specific order or hierarchy of steps in the disclosed procedures is an illustration of an illustrative approach. The specific order or hierarchy of steps in a process can be rearranged based on design preferences. The accompanying method requests present elements of the various steps in a sample order and are not meant to be limited to the specific order or hierarchy presented.

The preceding description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to such aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Accordingly, the patentable scope is not intended to be limited to the aspects shown herein, but is to be given the full scope consistent with the language claimed, wherein reference to an element in the singular is not intended to mean "one and only one," Unless expressly stated so, it means "one or more". Unless specifically stated otherwise, the term "some" refers to one or more. All structural and functional equivalents to the elements in the various aspects described throughout this invention that are known to or hereafter come to be known to those skilled in the art are expressly incorporated by reference herein and are intended to be patentable by the claims. Covered. Furthermore, nothing disclosed herein is intended to be exclusive to the public, whether or not such disclosure is expressly recited in the patent claims. Unclaimed components will be construed as means plus function unless the component is explicitly recited using the phrase "means for".

1300:Instance packet structure

1302: Extended register long write command

1304: Payload

Claims (28)

A method executed at a master device for facilitating data communication on a bus includes receiving from a first slave device a mask write data packet sent over the bus to a A request from a second slave device, wherein the mask write datagram is addressed to a radio frequency front end (RFFE) register of the second slave device, the mask write datagram including the identification to be a mask field of at least one bit changed in the RFFE register and a data field providing a value of the at least one bit to be changed in the RFFE register; detecting the first Whether the slave device is authorized to send the mask write data report to the second slave device; and if authorization is detected, allowing the first slave device to send the mask write data report to the second controlled device. The method of claim 1, wherein the granting includes notifying the first slave device that the first slave device is authorized to send the mask write datagram. The method of claim 1, further comprising: if no authorization is detected, preventing the first slave device from sending the mask write data report to the second slave device. The method of claim 3, wherein the preventing includes notifying the first slave device that the first slave device is unauthorized to send the mask write data packet. The method of claim 3, wherein the preventing includes issuing a bus park cycle on the bus to prevent the sending of the mask write datagram. The method of claim 1, wherein the mask field further identifies a remaining set of bits to remain unchanged in the RFFE register of the second slave device. The method of claim 1, wherein: the mask field is a bit index field identifying a bit position to be changed in the RFFE register of the second slave device; and the data field Bits is a bit value field that provides the bit value for one of the bit positions identified in the bit index field. A master device for facilitating data communication on a bus, including: a bus interface; and a processing circuit configured to: from a first slave device via the bus interface Receive a request to send a mask write datagram to a second slave device via the bus, wherein the mask write datagram is addressed to a radio frequency front end (RFFE) of the second slave device ) register, the mask write datagram includes a mask field identifying at least one bit to be changed in the RFFE register and providing the at least one bit to be changed in the RFFE register a data field of one value that detects whether the first slave device is authorized to send the mask write data report to the second slave device, and If authorization is detected, the first slave device is allowed to send the mask write data report to the second slave device. The master device of claim 8, wherein the processing circuit configured to allow is configured to notify the first slave device that the first slave device is authorized to send the mask write data packet device. The master controller device of claim 8, wherein the processing circuit is further configured to prevent the first slave device from sending the mask write data report to the second slave device if authorization is not detected. device. The master device of claim 10, wherein the processing circuit configured to prevent is configured to notify the first slave device of unauthorized transmission of the mask write data packet. device. The master device of claim 10, wherein the processing circuit configured to prevent is configured to issue a bus park cycle on the bus to prevent the sending of the mask write datagram. The master device of claim 8, wherein the mask field further identifies a remaining set of bits to remain unchanged in the RFFE register of the second slave device. The master device of claim 8, wherein: the mask field identifies a parameter to be changed in the RFFE register of the second slave device. a bit index field for a bit position; and the data field is a bit value field that provides a bit value for the bit position identified in the bit index field. A method performed at a first slave device for communicating data to a second slave device via a bus, comprising: generating data at the first slave device to be transmitted via the bus. sending a mask write datagram to the second slave device, wherein the mask write datagram is addressed to a radio frequency front end (RFFE) register of the second slave device, the The mask write datagram includes a mask field identifying at least one bit to be changed in the RFFE register and a mask field providing a value of the at least one bit to be changed in the RFFE register. data field; requests permission from a master device to send the mask write data report to the second slave device; detects whether the permission is granted; and if granted by the master device, sends The mask write data is reported to the second slave device. The method of claim 15, wherein the detecting includes receiving a notification from the master device that the first slave device is permitted to send the mask write datagram. The method of claim 15, further comprising inhibiting sending the mask write data report to the second slave device if not permitted by the master device. The method of claim 17, wherein the detecting includes receiving a notification from the master device that the first slave device is not authorized to send the mask write datagram. The method of claim 17, wherein the detecting includes observing a bus park cycle issued by the master device on the bus to prevent the transmission of the mask write datagram. The method of claim 15, wherein the mask field further identifies a remaining set of bits to remain unchanged in the RFFE register of the second slave device. The method of claim 15, wherein: the mask field is a bit index field identifying a bit position to be changed in the RFFE register of the second slave device; and the data field Bits is a bit value field that provides the bit value for one of the bit positions identified in the bit index field. A slave device for communicating data to a second slave device via a bus, including: a bus interface; and a processing circuit configured to: at the slave device Generating a mask write datagram to be sent to the second slave device via the bus, wherein the mask write datagram is addressed to a radio frequency front end (RFFE) of the second slave device register, the mask write datagram includes a mask field identifying at least one bit to be changed in the RFFE register and providing the at least one bit to be changed in the RFFE register a data field of value requesting permission from a master device to send the mask write data report to the second slave device, Detect whether the permission is granted, and if granted by the master device, send the mask write data report to the second slave device via the bus interface. The slave device of claim 22, wherein the processing circuit is further configured to receive a notification from the master device that the slave device is permitted to send the mask write datagram. The slave device of claim 22, wherein the processing circuit is further configured to inhibit sending the mask write data report to the second slave device if not permitted by the master device. The slave device of claim 24, wherein the processing circuit is further configured to receive a notification from the master device that the slave device is not authorized to send the mask write datagram. The slave device of claim 24, wherein the processing circuit is further configured to observe a bus park issued by the master device on the bus to prevent the transmission of the mask write datagram. cycle. The slave device of claim 22, wherein the mask field further identifies a remaining set of bits to remain unchanged in the RFFE register of the second slave device. The slave device of claim 22, wherein: the mask field identifies a parameter to be changed in the RFFE register of the second slave device. a bit index field for a bit position; and the data field is a bit value field that provides a bit value for the bit position identified in the bit index field.