TWI827561B - Radio frequency front end devices with masked write and the method thereof - Google Patents

Radio frequency front end devices with masked write and the method thereof Download PDF

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TWI827561B
TWI827561B TW107139057A TW107139057A TWI827561B TW I827561 B TWI827561 B TW I827561B TW 107139057 A TW107139057 A TW 107139057A TW 107139057 A TW107139057 A TW 107139057A TW I827561 B TWI827561 B TW I827561B
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register
slave device
mask
bit
mask write
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TW107139057A
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TW201923604A (en
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拉藍 米序拉
理查 韋特費爾德
海倫娜 歐夏
陳真棋
瓦夫岡 勒蒂希
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美商高通公司
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol

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  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mobile Radio Communication Systems (AREA)

Abstract

Methods and apparatuses are described that facilitate data communication between a first slave device and a second slave device across a serial bus interface. In one configuration, a master device receives, from a first slave device, a request to send a masked-write datagram to a second slave device via a bus, wherein the masked-write datagram is addressed to a radio frequency front end (RFFE) register of the second slave device. The masked-write datagram includes a mask field identifying at least one bit to be changed in the RFFE register and a data field providing a value of the at least one bit to be changed in the RFFE register. The master device detects whether the first slave device is authorized to send the masked-write datagram to the second slave device and permits the first slave device to send the masked-write datagram to the second slave device if authorization is detected.

Description

具有遮罩寫入之無線電頻率前端裝置及其方法 Radio frequency front-end device with mask writing and method thereof

本發明大體上係關於資料傳送,且更特定言之係關於具有遮罩寫入操作之無線電頻率前端(RFFE)裝置。 The present invention relates generally to data transfer, and more particularly to radio frequency front-end (RFFE) devices with mask write operations.

隨著行動裝置市場隨著多功能智慧型電話之發展迅速成長,蜂巢式通信複雜性已因此增大。現在習知行動裝置之無線電前端覆蓋多達十個或更多頻帶。無線電前端因此需要多個功率放大器、雙工器、低雜訊放大器、天線開關、濾波器及其他無線電頻率(RF)前端裝置以適應無線電傳信複雜性。此等各種RF前端裝置又由諸如無線電頻率積體電路(RFIC)之主機或主控器裝置控制。隨著RF前端複雜性增大,對控制許多不同裝置之標準化協定之需求導致行動行業處理器介面(MIPI)RF前端控制介面(RFFE)標準之發展。 As the mobile device market has grown rapidly with the development of multifunctional smart phones, the complexity of cellular communications has increased. It is now common practice for mobile device radio front ends to cover as many as ten or more frequency bands. The radio front-end therefore requires multiple power amplifiers, duplexers, low-noise amplifiers, antenna switches, filters and other radio frequency (RF) front-end devices to accommodate the complexity of radio signaling. These various RF front-end devices are in turn controlled by a host or master device such as a radio frequency integrated circuit (RFIC). As the complexity of RF front-ends increases, the need for standardized protocols to control many different devices led to the development of the Mobile Industry Processor Interface (MIPI) RF Front-End Control Interface (RFFE) standard.

RFFE標準指定包括一時脈線及一雙向資料線之一串列匯流排。經由RFFE匯流排,RFFE主控器裝置可自複數個RFFE受控器裝置中之暫存器讀取及寫入至複數個RFFE受控器裝置中之暫存器以便控制RF前端裝置。在RFFE標準中將讀取及寫入命令組織成協定訊息,該等訊息可各自包括一初始序列開始條件(SSC)、一命令訊框、一資料酬載及一最終匯流排停放循環(BPC)。該等協定訊息包括暫存器命令、擴展之暫存器命令及擴展之暫存器長命令。該等協定訊 息可進一步包括廣播命令。暫存器、擴展之暫存器及擴展之暫存器長命令(三種類型之命令)可皆為讀取或寫入命令。關於三種類型之命令,RFFE受控器裝置中之每一者中的暫存器經組織成16位元寬位址空間(十六進位中之0x0000-0xFFFF)。三種類型之命令中之每一者包括一命令訊框,其定址一特定RFFE受控器裝置以及暫存器位址。暫存器命令中之命令訊框(暫存器命令訊框)係針對位址空間之前五個位元(0x00-0x1F)中之暫存器,使得僅需要五個暫存器位址位元。暫存器命令訊框後跟著為8位元資料酬載訊框。相比之下,擴展之暫存器命令訊框包括八個暫存器位址位元,且可跟著多達16位元組之資料。最後,擴展之暫存器長命令訊框包括一全16位元暫存器位址,因此其可唯一地識別定址之RFFE受控器裝置中的任一暫存器。擴展之暫存器長命令訊框可跟著為多達八個位元組之資料。 The RFFE standard specifies a serial bus that includes a clock line and a bidirectional data line. Through the RFFE bus, the RFFE master device can read from and write registers in a plurality of RFFE slave devices to registers in a plurality of RFFE slave devices in order to control the RF front-end device. Read and write commands are organized into protocol messages in the RFFE standard, which may each include an initial sequence start condition (SSC), a command frame, a data payload, and a final bus park cycle (BPC). . The protocol messages include register commands, extended register commands and extended register length commands. Information on these agreements The information may further include broadcast commands. Register, extended register and extended register long commands (three types of commands) can all be read or write commands. For the three types of commands, the registers in each of the RFFE slave devices are organized into a 16-bit wide address space (0x0000-0xFFFF in hexadecimal). Each of the three types of commands includes a command frame that addresses a specific RFFE slave device and register address. The command frame in the register command (register command frame) targets the register in the first five bits (0x00-0x1F) of the address space, so that only five register address bits are needed. . The register command frame is followed by an 8-bit data payload frame. In contrast, the extended register command frame includes eight register address bits and can be followed by up to 16 bytes of data. Finally, the extended register length command frame includes a full 16-bit register address, so it uniquely identifies any register in the addressed RFFE slave device. The extended register length command frame can be followed by up to eight bytes of data.

命令中之每一者開始於一唯一序列開始條件(SSC),其後接著跟有一對應命令訊框、一些數目個資料訊框,及最後一匯流排停放循環(BPC)以用信號表示命令之結尾。傳輸該等命令中之任一者所涉及的潛時因此取決於其各種訊框中的位元之數目,以及針對RFFE時脈線之計時速度。在RFFE協定下,傳輸之訊框之每一位元對應於時脈之一週期,此係由於傳輸為單資料速率(SDR),其對應於每時脈循環一個位元。舉例而言,SDR自回應於時脈之每一上升邊緣(或回應於僅下降邊緣)傳輸一位元產生。在RFFE v2規範中,最大計時速度為52MHz。此計時速率已相對於RFFE協定之先前版本增大,且與增大之功率消耗相關聯。 Each of the commands begins with a unique sequence start condition (SSC), followed by a corresponding command frame, some number of data frames, and finally a bus park cycle (BPC) to signal the command. The end. The latency involved in transmitting any of these commands therefore depends on the number of bits in its various frames, and the timing speed for the RFFE clock line. Under the RFFE protocol, each bit of the transmitted frame corresponds to one cycle of the clock. This is because the transmission is Single Data Rate (SDR), which corresponds to one bit per clock cycle. For example, SDR is generated by transmitting a bit in response to each rising edge of the clock (or in response to only falling edges). In the RFFE v2 specification, the maximum timing speed is 52MHz. This timing rate has been increased relative to previous versions of the RFFE protocol and is associated with increased power consumption.

三種類型之RFFE命令(擴展暫存器、擴展之暫存器長及暫存器)中之每一者可為讀取或寫入命令。一般而言,每一寫入命令寫入全位元組至每一指定暫存器。然而,其可係RFFE主控器裝置不需要改變RFFE受控器裝置暫存器中之全部八個位元的情況。此外,在許多裝置中,多於一個主控器或無線電存取技術(RAT)組件可共用同一RFFE受控器裝置暫存器中之控制位元。為避免污染 對應於寫入至同一暫存器的「其他」源之位元,「部分寫入」操作可係所要的。在此部分寫入操作中,RFFE主控器裝置必須首先使用三種命令類型中之一適當者對所選擇受控器裝置暫存器執行讀取操作。RFFE主控器裝置接著知曉對應RFFE受控器裝置暫存器中之全部位元的當前狀態。RFFE主控器裝置接著可使用三種命令類型中之一適當者發出RFFE寫入命令,其中用於對應受控器裝置暫存器之資料酬載具有其正改變同時全部剩餘位元保持在如藉由先前讀取操作所判定之其當前狀態中的位元。對在部分寫入操作之前讀取操作的需求增加可違反實施於對應RF前端中的某些無線電存取技術之潛時需求的潛時。 Each of the three types of RFFE commands (extended register, extended register length, and register) can be a read or write command. In general, each write command writes a full set of bytes to each designated register. However, it may be the case that the RFFE master device does not need to change all eight bits in the RFFE slave device register. Additionally, in many devices, more than one master or radio access technology (RAT) component may share control bits in the same RFFE slave device register. to avoid contamination A "partial write" operation may be desired corresponding to bits written to "other" sources in the same register. During this portion of the write operation, the RFFE master device must first perform a read operation on the selected slave device register using the appropriate one of three command types. The RFFE master device then knows the current state of all bits in the corresponding RFFE slave device register. The RFFE master device can then issue an RFFE write command using the appropriate one of three command types, where the data payload for the corresponding slave device register has its positive changes while all remaining bits remain as before A bit in its current state as determined by a previous read operation. The increased need for read operations to precede partial write operations may violate the latency requirements of certain radio access technologies implemented in corresponding RF front-ends.

因此,在此項技術中需要針對部分寫入操作具有減小潛時的RFFE訊息傳遞。 Therefore, there is a need in this technology for RFFE messaging with reduced latency for partial write operations.

本文所揭示之實施例提供促進跨越串列匯流排介面在受控器裝置之間的資料通信的系統、方法及設備。提供一種無線電頻率前端前端(RFFE)網路,其中受控器裝置可產生遮罩寫入命令並向主控器裝置請求發出遮罩寫入命令至其他受控器裝置的權限,其他受控器裝置不需要任何讀取操作以判定經定址受控器裝置暫存器中的不變位元之值。每一遮罩寫入命令可包括遮罩欄位或位元索引欄位,其識別待在經定址受控器裝置暫存器中改變的位元之位元位置。 Embodiments disclosed herein provide systems, methods, and apparatus that facilitate data communication between slave devices across a serial bus interface. A radio frequency front-end (RFFE) network is provided in which a slave device can generate a mask write command and request a master device for permission to issue a mask write command to other slave devices, and the other slave devices The device does not require any read operations to determine the value of the immutable bit in the addressed slave device register. Each mask write command may include a mask field or a bit index field that identifies the bit position of the bit to be changed in the addressed slave device register.

在本發明之一態樣中,在用於促進在匯流排上之資料通信的主控器裝置處執行之方法包括:自第一受控器裝置接收經由匯流排發送遮罩寫入資料報至第二受控器裝置的請求,其中遮罩寫入資料報經定址至第二受控器裝置之無線電頻率前端(RFFE)暫存器,遮罩寫入資料報包括識別待在RFFE暫存器中改變之至少一個位元的遮罩欄位及提供待在RFFE暫存器中改變的至少一個位元之值的資料欄位;偵測第一受控器裝置是否經授權以發送遮罩寫入資料報至 第二受控器裝置;若偵測到授權,則准許第一受控器裝置發送遮罩寫入資料報至第二受控器裝置;及若未偵測到授權,則防止第一受控器裝置發送遮罩寫入資料報至第二受控器裝置。 In one aspect of the invention, a method performed at a master device for facilitating data communication over a bus includes receiving from a first slave device a mask write data packet transmitted over the bus to A request from the second slave device, wherein the mask write datagram is addressed to the radio frequency front end (RFFE) register of the second slave device, and the mask write datagram includes the identification of the remaining RFFE register. A mask field of at least one bit changed in the RFFE register and a data field providing the value of at least one bit to be changed in the RFFE register; detecting whether the first slave device is authorized to send a mask write Input information report a second slave device; if authorization is detected, permitting the first slave device to send a mask write data report to the second slave device; and if authorization is not detected, preventing the first slave device from sending The controller device sends a mask write data report to the second slave device.

在一態樣中,該准許包括將第一受控器裝置經授權以發送遮罩寫入資料報通知第一受控器裝置。在另一態樣中,該防止包括將第一受控器裝置未經授權以發送遮罩寫入資料報通知第一受控器裝置及/或在匯流排上發出匯流排停放循環以阻止遮罩寫入資料報之發送。 In one aspect, the permission includes notifying the first slave device that the first slave device is authorized to send the mask write datagram. In another aspect, the preventing includes notifying the first slave device of unauthorized sending of a mask write datagram and/or issuing a bus park cycle on the bus to prevent masking. Cover the sending of written data report.

在一態樣中,遮罩欄位進一步識別第二受控器裝置之RFFE暫存器中保持不變的剩餘位元集合。在另一態樣中,遮罩欄位為識別待在第二受控器裝置之RFFE暫存器中改變之位元位置的位元索引欄位且資料欄位為提供在位元索引欄位中識別的位元位置之位元值的位元值欄位。 In one aspect, the mask field further identifies a remaining set of bits that remain unchanged in the RFFE register of the second slave device. In another aspect, the mask field is a bit index field that identifies the bit location to be changed in the RFFE register of the second slave device and the data field is a provided bit index field. The bit value field of the bit value for the bit position identified in .

在本發明之另一態樣中,用於促進在匯流排上資料通信的主控器裝置包括匯流排介面及處理電路。處理電路經組態以執行以下操作:經由匯流排介面自第一受控器裝置接收經由匯流排發送遮罩寫入資料報至第二受控器裝置的請求,其中遮罩寫入資料報經定址至第二受控器裝置之無線電頻率前端(RFFE)暫存器,遮罩寫入資料報包括識別在RFFE暫存器中待改變的至少一個位元之遮罩欄位及提供在RFFE暫存器中待改變的至少一個位元之值的資料欄位;偵測第一受控器裝置是否經授權以發送遮罩寫入資料報至第二受控器裝置;若偵測到授權,則准許第一受控器裝置發送遮罩寫入資料報至第二受控器裝置;及若未偵測到授權,則防止第一受控器裝置發送遮罩寫入資料報至第二受控器裝置。 In another aspect of the invention, a host device for facilitating data communication on a bus includes a bus interface and processing circuitry. The processing circuit is configured to receive a request from the first slave device via the bus interface to send a mask write data report to the second slave device via the bus, wherein the mask write data report is Addressed to the radio frequency front end (RFFE) register of the second slave device, the mask write datagram includes a mask field identifying at least one bit to be changed in the RFFE register and provided in the RFFE register. A data field containing the value of at least one bit in the register to be changed; detecting whether the first slave device is authorized to send a mask write data report to the second slave device; if authorization is detected, then permit the first slave device to send a mask write data report to the second slave device; and if authorization is not detected, prevent the first slave device from sending a mask write data report to the second slave device controller device.

在本發明之另一態樣中,用於促進在匯流排上之資料通信的主控器裝置包括:用於自第一受控器裝置接收經由匯流排發送遮罩寫入資料報至第二受控器裝置的請求的構件,其中遮罩寫入資料報經定址至第二受控器裝置之無線電頻率前端(RFFE)暫存器,遮罩寫入資料報包括識別待在RFFE暫存器中改 變之至少一個位元的遮罩欄位及提供待在RFFE暫存器中改變的至少一個位元之值的資料欄位;用於偵測第一受控器裝置是否經授權以發送遮罩寫入資料報至第二受控器裝置的構件;用於若偵測到授權,則准許第一受控器裝置發送遮罩寫入資料報至第二受控器裝置的構件;及用於若未偵測到授權,則防止第一受控器裝置發送遮罩寫入資料報至第二受控器裝置的構件。 In another aspect of the invention, a master device for facilitating data communication over a bus includes: receiving from a first slave device a mask write data packet transmitted over the bus to a second slave device. A component of a request from a slave device in which a mask write datagram is addressed to a radio frequency front-end (RFFE) register of a second slave device, the mask write datagram including an identification pending in the RFFE register mid-term reform Change the mask field of at least one bit and provide the data field of the value of at least one bit to be changed in the RFFE register; used to detect whether the first slave device is authorized to send the mask means for writing a data report to a second slave device; means for allowing the first slave device to send a masked write data report to the second slave device if authorization is detected; and Component that prevents the first slave device from sending a mask write data report to the second slave device if authorization is not detected.

在本發明之一態樣中,在用於經由匯流排傳達資料至第二受控器裝置的第一受控器裝置處執行之方法包括:在第一受控器裝置處產生待經由匯流排發送至第二受控器裝置的遮罩寫入資料報,其中遮罩寫入資料報經定址至第二受控器裝置之無線電頻率前端(RFFE)暫存器,遮罩寫入資料報包括識別待在(RFFE)暫存器中改變之至少一個位元的遮罩欄位及提供待在RFFE暫存器中改變的至少一個位元之值的資料欄位;向主控器裝置請求發送遮罩寫入資料報至第二受控器裝置的權限;偵測權限是否被授予;若由主控器裝置准許,則發送遮罩寫入資料報至第二受控器裝置;及若未由主控器裝置准許,則制止發送遮罩寫入資料報至第二受控器裝置。 In one aspect of the invention, a method performed at a first slave device for communicating data to a second slave device via a bus includes generating, at the first slave device, data to be transmitted via the bus. A mask write datagram sent to the second slave device, wherein the mask write datagram is addressed to a radio frequency front end (RFFE) register of the second slave device, the mask write datagram includes A mask field identifying at least one bit to be changed in the (RFFE) register and a data field providing a value of at least one bit to be changed in the RFFE register; sending a request to the master device Mask write data to the permission of the second slave device; detect whether permission is granted; if granted by the master device, send a mask write data report to the second slave device; and if not Allowed by the master device, prohibits sending mask write data reports to the second slave device.

在一態樣中,該偵測包括自主控器裝置接收第一受控器裝置經准許以發送遮罩寫入資料報的通知。在另一態樣中,該偵測包括自主控器裝置接收第一受控器裝置未經准許發送遮罩寫入資料報的通知及/或觀測藉由主控器裝置在匯流排上發出用以阻止遮罩寫入資料報之發送的匯流排停放循環。 In one aspect, the detecting includes receiving a notification from the master device that the first slave device is authorized to send the mask write datagram. In another aspect, the detecting includes receiving from the master device a notification that the first slave device is sending a mask write datagram without permission and/or observing that the first slave device sends a user message on the bus by the master device. Bus park loop to prevent mask write datagram from being sent.

在一態樣中,遮罩欄位進一步識別第二受控器裝置之RFFE暫存器中保持不變的剩餘位元集合。在另一態樣中,遮罩欄位為識別待在第二受控器裝置之RFFE暫存器中改變之位元位置的位元索引欄位且資料欄位為提供在位元索引欄位中識別的位元位置之位元值的位元值欄位。 In one aspect, the mask field further identifies a remaining set of bits that remain unchanged in the RFFE register of the second slave device. In another aspect, the mask field is a bit index field that identifies the bit location to be changed in the RFFE register of the second slave device and the data field is a provided bit index field. The bit value field of the bit value for the bit position identified in .

在本發明之另一態樣中,用於經由匯流排傳達資料至第二受控器裝置的受控器裝置包括匯流排介面及處理電路。處理電路經組態以執行以下操 作:在受控器裝置處產生待經由匯流排發送至第二受控器裝置的遮罩寫入資料報,其中遮罩寫入資料報經定址至第二受控器裝置之無線電頻率前端(RFFE)暫存器,遮罩寫入資料報包括識別待在(RFFE)暫存器中改變的至少一個位元之遮罩欄位及提供待在RFFE暫存器中改變的至少一個位元之值的資料欄位;向主控器裝置請求發送遮罩寫入資料報至第二受控器裝置的權限;偵測該權限是否被授予;若由主控器裝置准許,則經由匯流排介面發送遮罩寫入資料報至第二受控器裝置;及若未由主控器裝置准許,則制止發送遮罩寫入資料報至第二受控器裝置。 In another aspect of the invention, a slave device for communicating data to a second slave device via a bus includes a bus interface and processing circuitry. The processing circuit is configured to perform the following operations Action: Generate a mask write datagram at the slave device to be sent to a second slave device via the bus, where the mask write datagram is addressed to the radio frequency front end of the second slave device ( RFFE) register, the mask write datagram includes a mask field identifying at least one bit to be changed in the (RFFE) register and a mask field providing at least one bit to be changed in the RFFE register Value data field; requests permission from the master device to send mask write data reports to the second slave device; detects whether the permission is granted; if granted by the master device, via the bus interface sending a mask write data report to the second slave device; and inhibiting sending of the mask write data report to the second slave device if not permitted by the master device.

在本發明之又一態樣中,用於經由匯流排傳達資料至第二受控器裝置的第一受控器裝置包括:用於在受控器裝置處產生待經由匯流排發送至第二受控器裝置的遮罩寫入資料報的構件,其中遮罩寫入資料報經定址至第二受控器裝置之無線電頻率前端(RFFE)暫存器,遮罩寫入資料報包括識別待在(RFFE)暫存器中改變之至少一個位元的遮罩欄位及提供待在RFFE暫存器中改變的至少一個位元之值的資料欄位;用於向主控器裝置請求發送遮罩寫入資料報至第二受控器裝置的權限的構件;用於偵測權限是否被授予的構件;用於若由主控器裝置准許,則發送遮罩寫入資料報至第二受控器裝置的構件;及用於若未由主控器裝置准許,則制止發送遮罩寫入資料報至第二受控器裝置的構件。 In yet another aspect of the invention, a first slave device for communicating data over a bus to a second slave device includes generating, at the slave device, data to be sent to the second slave device via the bus. Components for a mask write datagram of a slave device, wherein the mask write datagram is addressed to a radio frequency front end (RFFE) register of a second slave device, the mask write datagram including an identification to be A mask field of at least one bit changed in the (RFFE) register and a data field providing the value of at least one bit to be changed in the RFFE register; used to request transmission to the master device means for masking the permission to write a data report to the second slave device; means for detecting whether the permission is granted; means for sending a mask write data report to the second slave device if granted by the master device Means for a slave device; and means for inhibiting sending of a mask write data report to a second slave device if not permitted by the master device.

100:設備 100:Equipment

102:處理電路 102: Processing circuit

104:積體電路(IC)裝置/特殊應用積體電路(ASIC)裝置 104: Integrated circuit (IC) device/Application special integrated circuit (ASIC) device

106:積體電路(IC)裝置/無線電頻率(RF)前端裝置 106: Integrated circuit (IC) device/radio frequency (RF) front-end device

108:天線 108:Antenna

110:數據機 110: Modem

112:處理裝置 112: Processing device

114:記憶體裝置 114:Memory device

120:顯示器 120:Display

122:整合式或外部小鍵盤 122: Integrated or external keypad

124:按鈕 124:Button

200:方塊圖 200:Block diagram

202:裝置 202:Device

204:數據機 204: Modem

206:基頻處理器 206: Baseband processor

208:無線電頻率前端(RFFE)匯流排 208: Radio Frequency Front End (RFFE) Bus

210:無線電頻率前端(RFFE)介面 210: Radio frequency front end (RFFE) interface

212:前端裝置/無線電頻率(RF)積體電路(RFIC) 212: Front-End Devices/Radio Frequency (RF) Integrated Circuits (RFIC)

213:前端裝置/交換器 213: Front-end device/switch

214:前端裝置/無線電頻率(RF)調諧器 214: Front End Unit/Radio Frequency (RF) Tuner

215:前端裝置/功率放大器(PA) 215: Front-end device/power amplifier (PA)

216:前端裝置/低雜訊放大器(LNA) 216: Front-end device/low noise amplifier (LNA)

217:前端裝置/功率管理模組 217: Front-end device/power management module

220:通信鏈路 220: Communication link

300:裝置 300:Device

302:第一受控器裝置 302: First controlled device

306:無線電頻率前端(RFFE)暫存器 306: Radio frequency front-end (RFFE) register

310:收發器 310:Transceiver

310a:接收器 310a:Receiver

310b:共同電路 310b: Common circuit

310c:傳輸器 310c:Transmitter

312:處理電路及/或控制邏輯 312: Processing circuit and/or control logic

314a:線驅動器/接收器電路 314a: Line driver/receiver circuit

314b:線驅動器/接收器電路 314b: Line driver/receiver circuit

316:串列時脈線(SCLK) 316: Serial clock line (SCLK)

318:串列資料線(SDATA) 318: Serial data line (SDATA)

3201:匯流排主控器裝置 3201:Bus master controller device

320N:匯流排主控器裝置 320N: Bus master controller device

3221:受控器裝置 3221: Controller device

322N:受控器裝置 322N: Controlled device

324:儲存裝置 324:Storage device

328:傳輸時脈(TXCLK)信號 328: Transmission clock (TXCLK) signal

330:無線電頻率前端(RFFE)匯流排 330: Radio Frequency Front End (RFFE) Bus

400:命令訊框 400:Command message box

500:遮罩寫入無線電頻率前端(RFFE)命令/遮罩寫入命令 500: Mask Write Radio Frequency Front End (RFFE) Command/Mask Write Command

502:擴展之暫存器遮罩寫入命令/擴展之暫存器遮罩寫入命令(WR) 502: Extended register mask write command/Extended register mask write command (WR)

504:擴展之暫存器長遮罩寫入命令/擴展之暫存器遮罩寫入命令(WR)長 504: Extended register long mask write command/Extended register mask write command (WR) long

506:暫存器遮罩寫入命令/暫存器遮罩寫入命令(WR) 506: Temporary register mask write command/temporary register mask write command (WR)

508:擴展之暫存器短遮罩寫入命令/擴展之暫存器遮罩寫入命令(WR)短 508: Extended temporary register short mask write command/Extended temporary register mask write command (WR) short

510:遮罩N位元欄位 510: Mask N-bit field

512:資料N位元欄位 512: Data N-bit field

600:通用遮罩寫入命令 600: Universal mask writing command

602:通用擴展暫存器遮罩寫入命令/擴展之暫存器遮罩寫入命令(WR) 602: General extended temporary register mask write command/Extended temporary register mask write command (WR)

604:通用擴展之暫存器長遮罩寫入命令/擴展之暫存器遮罩寫入命令(WR)長 604: General extended temporary register mask write command/Extended temporary register mask write command (WR) long

606:通用暫存器遮罩寫入命令/暫存器遮罩寫入命令(WR) 606: General register mask write command/scratch register mask write command (WR)

608:通用暫存器短遮罩寫入命令/擴展之暫存器遮罩寫入命令(WR)短 608: General register short mask write command/extended register mask write command (WR) short

610:遮罩N位元欄位 610: Mask N-bit field

612:資料N位元欄位 612: Data N-bit field

614:2位元模式欄位 614: 2-bit mode field

702:擴展之暫存器索引遮罩寫入命令/擴展之暫存器遮罩寫入命令(WR) 702: Extended register index mask write command/Extended register mask write command (WR)

704:擴展之暫存器長索引遮罩寫入命令/擴展之暫存器遮罩寫入命令(WR)長 704: Extended register long index mask write command/Extended register mask write command (WR) long

706:暫存器索引遮罩寫入命令/暫存器遮罩寫入命令(WR) 706: Temporary register index mask write command/temporary register mask write command (WR)

708:擴展之暫存器短索引遮罩寫入命令/擴展之暫存器遮罩寫入命令(WR)短 708: Extended register short index mask write command/Extended register mask write command (WR) short

710:位元索引 710:Bit index

712:位元值欄位 712:Bit value field

800:通用索引遮罩寫入命令 800: Universal index mask writing command

802:通用擴展之暫存器索引遮罩寫入命令/擴展之暫存器遮罩寫入命令(WR) 802: General extended register index mask write command/extended register mask write command (WR)

804:通用擴展之暫存器長索引遮罩寫入命令/擴展之暫存器遮罩寫入命令(WR)長 804: General extended register long index mask write command/Extended register mask write command (WR) long

806:通用暫存器索引遮罩寫入命令/暫存器遮罩寫入命令(WR) 806: General scratchpad index mask write command/register mask write command (WR)

808:通用擴展之暫存器短索引遮罩寫入命令/擴展之暫存器遮罩寫入命令(WR)短 808: General extended register short index mask write command/Extended register mask write command (WR) short

810:欄位 810:Field

812:欄位 812:Field

814:2位元模式欄位 814: 2-bit mode field

900:實例封包結構 900:Instance packet structure

902:資料報標頭 902: Data report header

904:16位元位址 904: 16-bit address

906:1位元組最高有效位元組(MSB) 906:1 byte most significant byte (MSB)

908:1位元組最低有效位元組(LSB) 908:1 byte least significant byte (LSB)

910:遮罩及資料對叢發長度 910: Mask and data on clump length

1000:資料報 1000:Information report

1004:16位元位址 1004: 16-bit address

1006:1位元組最高有效位元組(MSB) 1006:1 byte most significant byte (MSB)

1008:1位元組最低有效位元組(LSB) 1008:1 byte least significant byte (LSB)

1010:遮罩及資料對叢發長度 1010: Mask and data on clump length

1012:主控器裝置 1012:Master controller device

1014:影子暫存器 1014: Shadow register

1016:影子暫存器 1016: Shadow register

1022:受控器裝置 1022: Controller device

1024:1位元組基礎位址暫存器 1024:1 byte base address register

1026:1位元組遮罩寫入叢發長度暫存器 1026:1 byte mask written to burst length register

1100:資料報 1100:Information report

1104:16位元位址 1104: 16-bit address

1106:1位元組最高有效位元組(MSB) 1106:1 byte most significant byte (MSB)

1108:1位元組最低有效位元組(LSB) 1108:1 byte least significant byte (LSB)

1110:遮罩及資料對叢發長度 1110: Mask and data on clump length

1112:主控器裝置 1112:Master controller device

1114:影子暫存器 1114: Shadow register

1116:影子暫存器 1116: Shadow register

1122:受控器裝置 1122: Controller device

1124:1位元組基礎位址暫存器 1124:1 byte base address register

1126:1位元組遮罩寫入叢發長度暫存器 1126:1 byte mask written to burst length register

1130:比較 1130:Compare

1136:暫存器寫入存取命令 1136: Register write access command

1140:比較 1140:Compare

1146:暫存器寫入存取命令 1146: Register write access command

1200:實例封包結構 1200:Instance packet structure

1202:擴展之暫存器寫入命令 1202: Extended register write command

1204:酬載 1204: Payload

1300:實例封包結構 1300:Instance packet structure

1302:擴展之暫存器長寫入命令 1302: Extended register long write command

1304:酬載 1304: Payload

1400:實例位元結構 1400:Instance bit structure

1402:組態暫存器 1402: Configuration register

1404:第三暫存器位元D5 1404: Third register bit D5

1406:第四暫存器位元D4 1406: Fourth register bit D4

1500:無線電頻率前端(RFFE)暫存器空間 1500: Radio Frequency Front End (RFFE) register space

1600:無線電頻率前端(RFFE)暫存器空間 1600: Radio Frequency Front End (RFFE) register space

1700:圖表 1700: Chart

1750:圖式 1750: Schema

1800:圖式 1800: Schema

1802:頁面位址暫存器 1802: Page address register

1804:8位元位址 1804: 8-bit address

1900:設備 1900:Equipment

1902:處理電路 1902: Processing circuit

1904:處理器 1904: Processor

1906:儲存器 1906:Storage

1908:匯流排介面 1908:Bus interface

1910:匯流排 1910:Bus

1912:線介面電路 1912: Line interface circuit

1914:執行時影像 1914:Execution image

1916:軟體模組 1916:Software module

1918:使用者介面 1918:User interface

1920:分時程式 1920: time-sharing program

1922:邏輯電路 1922: Logic circuits

2000:流程圖 2000:Flowchart

2002:步驟 2002: steps

2004:步驟 2004: steps

2006:步驟 2006: Steps

2008:步驟 2008: Steps

2100:流程圖 2100:Flowchart

2102:步驟 2102: Steps

2104:步驟 2104: Steps

2106:步驟 2106: Steps

2108:步驟 2108: Steps

2110:步驟 2110: Steps

2200:流程圖 2200:Flowchart

2202:步驟 2202: Steps

2204:步驟 2204:Step

2206:步驟 2206: Steps

2208:步驟 2208: Steps

2300:流程圖 2300:Flowchart

2302:步驟 2302:Step

2304:步驟 2304:Step

2306:步驟 2306:Step

2308:步驟 2308: Steps

2310:步驟 2310: Steps

2312:步驟 2312: Steps

2400:傳輸設備 2400:Transmission equipment

2402:處理電路 2402: Processing circuit

2404:資料報產生/發送模組/電路 2404: Data report generation/sending module/circuit

2406:位址比較模組/電路 2406: Address comparison module/circuit

2408:叢發長度比較模組/電路 2408: Burst length comparison module/circuit

2410:暫存器設定模組/電路 2410: Register setting module/circuit

2412:匯流排介面模組/電路 2412:Bus interface module/circuit

2414:連接器/導線 2414: Connector/Wire

2416:處理器 2416: Processor

2418:電腦可讀儲存媒體 2418: Computer readable storage media

2420:匯流排 2420:Bus

2500:流程圖 2500:Flowchart

2502:步驟 2502:Step

2504:步驟 2504:Step

2506:步驟 2506:Step

2508:步驟 2508:Step

2510:步驟 2510:Step

2512:步驟 2512:Step

2600:流程圖 2600:Flowchart

2602:步驟 2602:Step

2604:步驟 2604:Step

2606:步驟 2606:Step

2608:步驟 2608:Step

2610:步驟 2610:Step

2700:流程圖 2700:Flowchart

2702:步驟 2702:Step

2704:步驟 2704:Step

2706:步驟 2706:Step

2708:步驟 2708:Step

2710:步驟 2710:Step

2712:步驟 2712: Steps

2714:步驟 2714:Step

2716:步驟 2716: Steps

2800:接收設備 2800: Receiving device

2802:處理電路 2802: Processing circuit

2804:資料報接收模組/電路 2804: Data report receiving module/circuit

2806:欄位讀取模組/電路 2806: Field reading module/circuit

2808:位元改變模組/電路 2808:Bit changing module/circuit

2810:暫存器讀取模組/電路 2810: Register reading module/circuit

2812:匯流排介面模組/電路 2812:Bus interface module/circuit

2814:連接器/導線 2814: Connector/Wire

2816:處理器 2816: Processor

2818:電腦可讀儲存媒體 2818: Computer readable storage media

2900:裝置 2900:Device

2902:無線電頻率前端(RFFE)匯流排 2902: Radio Frequency Front End (RFFE) Bus

2904:匯流排主控器裝置 2904:Bus master controller device

2906(1):受控器裝置 2906(1):Controller device

2906(2):受控器裝置 2906(2): Controller device

2906(3):受控器裝置 2906(3):Controller device

2906(N-1):受控器裝置 2906(N-1): Controller device

2906(N):受控器裝置 2906(N): Controller device

2916:鑑認電路/模組 2916: Identification circuit/module

3000:流程圖 3000:Flowchart

3002:步驟 3002:Step

3004:步驟 3004:Step

3006:步驟 3006:Step

3008:步驟 3008: Steps

3010:步驟 3010: Steps

3100:流程圖 3100:Flowchart

3102:步驟 3102: Steps

3104:步驟 3104: Steps

3106:步驟 3106: Steps

3108:步驟 3108: Steps

3200:主控器設備 3200:Master controller device

3202:處理電路 3202: Processing circuit

3204:請求接收模組/電路 3204: Request to receive module/circuit

3206:資料報授權模組/電路 3206: Data report authorization module/circuit

3208:資料報發送准許模組/電路 3208: Datagram transmission permission module/circuit

3210:資料報發送防止模組/電路 3210: Datagram transmission prevention module/circuit

3212:匯流排介面電路 3212:Bus interface circuit

3214:連接器/導線 3214: Connector/Wire

3216:處理器 3216: Processor

3218:電腦可讀儲存媒體 3218: Computer readable storage media

3220:匯流排 3220:Bus

3300:流程圖 3300:Flowchart

3302:步驟 3302: Steps

3304:步驟 3304: Steps

3306:步驟 3306: Steps

3308:步驟 3308: Steps

3310:步驟 3310: Steps

3400:受控器設備 3400: Controller device

3402:處理電路 3402: Processing circuit

3404:資料報產生模組/電路 3404: Data report generation module/circuit

3406:權限請求模組/電路 3406: Permission request module/circuit

3408:權限偵測模組/電路 3408:Permission detection module/circuit

3410:資料報發送模組/電路 3410: Data report sending module/circuit

3412:匯流排介面電路 3412:Bus interface circuit

3414:連接器/導線 3414: Connector/Wire

3416:處理器 3416: Processor

3418:電腦可讀儲存媒體 3418: Computer readable storage media

3420:匯流排 3420:Bus

圖1說明包括可根據本文中揭示之某些態樣調適的一RF前端(RFFE)之一設備。 Figure 1 illustrates a device including an RF front end (RFFE) that may be adapted in accordance with certain aspects disclosed herein.

圖2為說明採用一RFFE匯流排耦接各種前端裝置之一裝置之方塊圖。 Figure 2 is a block diagram illustrating a device using an RFFE bus to couple various front-end devices.

圖3說明根據本文中揭示之某些態樣的用於採用IC裝置之間的資料鏈路之設備之系統架構的實例。 3 illustrates an example of a system architecture for a device employing data links between IC devices in accordance with certain aspects disclosed herein.

圖4為說明RFFE協定中之經保留命令欄位的圖式。 Figure 4 is a diagram illustrating reserved command fields in the RFFE protocol.

圖5為說明根據本發明之一態樣的包括N位元遮罩欄位之四個遮罩寫入命令的圖式。 Figure 5 is a diagram illustrating four mask write commands including N-bit mask fields according to an aspect of the present invention.

圖6為說明其中根據本發明之一態樣採用單一經保留命令欄位的圖5之遮罩寫入命令的修改之圖式。 Figure 6 is a diagram illustrating a modification of the mask write command of Figure 5 using a single reserved command field in accordance with an aspect of the invention.

圖7為說明包括識別待根據本發明之一態樣改變的位元之位元位置的位元索引之四個遮罩寫入命令的圖式。 7 is a diagram illustrating four mask write commands that include a bit index identifying the bit position of the bit to be changed according to an aspect of the invention.

圖8為說明其中根據本發明之一態樣採用單一經保留命令欄位的圖7之遮罩寫入命令的修改之圖式。 Figure 8 is a diagram illustrating a modification of the mask write command of Figure 7 using a single reserved command field in accordance with an aspect of the invention.

圖9為說明支援16位元位址空間及N對遮罩及資料位元組之實例封包結構的圖式。 Figure 9 is a diagram illustrating an example packet structure supporting a 16-bit address space and N pairs of mask and data bytes.

圖10為說明傳輸緩衝器中之實例資料報的圖式。 Figure 10 is a diagram illustrating an example datagram in a transmission buffer.

圖11為說明用於傳輸緩衝器中之資料報之實例操作的圖式。 Figure 11 is a diagram illustrating example operations for transmitting datagrams in a buffer.

圖12為說明支援遮罩寫入操作的擴展之暫存器寫入命令之實例封包結構的圖式。 FIG. 12 is a diagram illustrating an example packet structure of an extended register write command that supports mask write operations.

圖13為說明支援遮罩寫入操作之擴展之暫存器寫入長命令之實例封包結構的圖式。 Figure 13 is a diagram illustrating an example packet structure of an extended register write long command that supports mask write operations.

圖14為說明組態暫存器之位元結構的圖式。 Figure 14 is a diagram illustrating the bit structure of the configuration register.

圖15為一RFFE暫存器空間之圖式。 Figure 15 is a diagram of an RFFE register space.

圖16為具有一組態暫存器及一頁面位址暫存器的一RFFE暫存器空間之圖式。 Figure 16 is a diagram of an RFFE register space with a configuration register and a page address register.

圖17說明定義組態暫存器之另一實例位元結構的圖表及描繪組態暫存器位元之功能的圖式。 Figure 17 illustrates a diagram defining another example bit structure of a configuration register and a diagram depicting the functions of the configuration register bits.

圖18為說明頁面分段存取之圖式。 Figure 18 is a diagram illustrating page segmented access.

圖19為說明採用可根據本文所揭示之某些態樣調適的處理電路之設備之實例的方塊圖。 19 is a block diagram illustrating an example of an apparatus employing processing circuitry adaptable in accordance with certain aspects disclosed herein.

圖20為根據本文中揭示之某些態樣的將資料發送至接收器之一方法之流程圖。 20 is a flow diagram of a method of sending data to a receiver according to certain aspects disclosed herein.

圖21為根據本文中揭示之某些態樣的將資料發送至接收器之另一方法之流程圖。 21 is a flow diagram of another method of sending data to a receiver according to certain aspects disclosed herein.

圖22為根據本文中揭示之某些態樣的將資料發送至接收器之另一方法之流程圖。 Figure 22 is a flow diagram of another method of sending data to a receiver according to certain aspects disclosed herein.

圖23為根據本文中揭示之某些態樣的將資料發送至接收器之另一方法之流程圖。 Figure 23 is a flow diagram of another method of sending data to a receiver according to certain aspects disclosed herein.

圖24為說明用於一傳輸設備且採用根據本文所揭示之某些態樣調適的處理電路的硬體實施方案之實例的圖式。 24 is a diagram illustrating an example of a hardware implementation for a transmission device employing processing circuitry adapted in accordance with certain aspects disclosed herein.

圖25為根據本文中揭示之某些態樣的自傳輸器接收資料之一方法之流程圖。 25 is a flow diagram of a method of receiving data from a transmitter in accordance with certain aspects disclosed herein.

圖26為根據本文中揭示之某些態樣的自傳輸器接收資料之另一方法之流程圖。 26 is a flow diagram of another method of receiving data from a transmitter in accordance with certain aspects disclosed herein.

圖27為根據本文中揭示之某些態樣的自傳輸器接收資料之另一方法之流程圖。 27 is a flow diagram of another method of receiving data from a transmitter in accordance with certain aspects disclosed herein.

圖28為說明用於一接收設備且採用根據本文所揭示之某些態樣調適的處理電路的硬體實施方案之實例的圖式。 28 is a diagram illustrating an example of a hardware implementation for a receiving device employing processing circuitry adapted in accordance with certain aspects disclosed herein.

圖29為說明可採用RFFE匯流排以連接匯流排主控器裝置及受控器裝置的裝置之架構之實例的方塊示意圖。 29 is a block schematic diagram illustrating an example of the architecture of a device that may employ an RFFE bus to connect a bus master device and a slave device.

圖30為用於經由RFFE匯流排在受控器裝置之間傳達遮罩寫入資料包之方法的流程圖。 30 is a flowchart of a method for communicating mask write packets between slave devices over an RFFE bus.

圖31為用於促進匯流排上之資料通信之方法的流程圖。 Figure 31 is a flow diagram of a method for facilitating data communication on a bus.

圖32為說明用於一主控器設備且採用根據本文所揭示之某些態樣調適的處理電路的硬體實施方案之簡化實例的圖式。 32 is a diagram illustrating a simplified example of a hardware implementation for a host device employing processing circuitry adapted in accordance with certain aspects disclosed herein.

圖33為用於在匯流排上在受控器裝置之間傳達資料之方法的流程圖。 33 is a flow diagram of a method for communicating data between slave devices on a bus.

圖34為說明用於一受控器設備且採用根據本文所揭示之某些態樣調適的處理電路的硬體實施方案之簡化實例的圖式。 34 is a diagram illustrating a simplified example of a hardware implementation for a slave device employing processing circuitry adapted in accordance with certain aspects disclosed herein.

相關申請案之交互參考 Cross-references to related applications

本申請案主張2017年11月3日申請之名為「RADIO FREQUENCY FRONT END DEVICES WITHMASKED WRITE」之非臨時申請案第15/803,639號的優先權,該案之全部內容以引用的方式併入本文中。 This application claims priority to non-provisional application No. 15/803,639 titled "RADIO FREQUENCY FRONT END DEVICES WITHMASKED WRITE" filed on November 3, 2017, the entire content of which is incorporated herein by reference. .

現參看圖式來描述各種態樣。在以下描述中,為達成解釋之目的,闡述許多特定細節以便提供對一或多個態樣之透徹理解。然而,明顯地,此(此等)態樣可在無此等特定細節之情況下得以實踐。 Now refer to the diagram to describe the various styles. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more aspects. Obviously, however, this aspect(s) may be practiced without these specific details.

如在本申請案中所使用,術語「組件」、「模組」、「系統」及類似者意欲包括電腦相關實體,諸如(但不限於)硬體、韌體、硬體與軟體之組合、軟體或執行中的軟體。舉例而言,組件可為(但不限於)在處理器上執行之程序、處理器、物件、可執行體、執行緒、程式及/或電腦。借助於說明,在計算裝置上 執行之應用程式及計算裝置兩者可為組件。一或多個組件可駐存於程序及/或執行緒內,且組件可位於一個計算裝置上及/或分散於兩個或大於兩個計算裝置之間。另外,此等組件可自其上儲存有各種資料結構的各種電腦可讀媒體執行。該等組件可諸如根據具有一或多個資料封包的信號(諸如來自借助於信號與本端系統、分佈式系統中之另一組件交互及/或跨越諸如網際網路之網路而與其他系統交互的一個組件的資料)借助於本端和/或遠端程序而通信。 As used in this application, the terms "component," "module," "system" and the like are intended to include computer-related entities such as (but not limited to) hardware, firmware, combinations of hardware and software, Software or software in execution. For example, a component may be, but is not limited to, a program, a processor, an object, an executable, a thread, a program, and/or a computer that executes on a processor. With instructions, on a computing device Both the executing application and the computing device may be components. One or more components may reside within a program and/or thread, and a component may be localized on one computing device and/or distributed between two or more computing devices. Additionally, such components can execute from a variety of computer-readable media having various data structures stored thereon. Such components may interact with the local system, another component in a distributed system, and/or with other systems across a network such as the Internet, such as from a signal having one or more data packets, such as from interacting with the local system, another component in a distributed system, and/or across a network such as the Internet. Information about a component of the interaction) is communicated by means of local and/or remote programs.

此外,術語「或」欲意謂包括性「或」而非排他性「或」。亦即,除非另外規定或自上下文清楚可見,否則片語「X採用A或B」欲意謂自然包括性排列中之任一者。亦即,藉由以下個例中的任一者滿足片語「X採用A或B」:X採用A;X採用B;或X採用A與B兩者。另外,如本申請案及所附申請專利範圍中所使用,冠詞「一」一般應理解為意謂「一或多個」,除非另外規定或自上下文清楚可見是針對單數形式。具有多個IC裝置子組件之例示性設備 Furthermore, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clear from the context, the phrase "X assumes A or B" is intended to mean either of the natural inclusive permutations. That is, the phrase "X adopts A or B" is satisfied by any of the following cases: X adopts A; X adopts B; or X adopts both A and B. Additionally, as used in this application and the appended claims, the article "a" shall generally be understood to mean "one or more" unless otherwise specified or it is clear from the context that a singular form is intended. Exemplary device with multiple IC device subassemblies

本發明之某些態樣可適用於在電子裝置之間部署的通信鏈路,該等電子裝置可包括諸如電話、行動計算裝置、器具、汽車電子元件、航空電子設備系統等之設備的子組件。圖1描繪可採用在IC裝置之間的通信鏈路之設備100。在一個實例中,設備100可為行動通信裝置。設備100可包括一處理電路,其具有可使用一第一通信鏈路耦接之兩個或大於兩個IC裝置104、106。一個IC裝置可為使設備能夠經由一或多個天線108與無線電存取網路、核心存取網路、網際網路及/或另一網路通信之RF前端裝置106。RF前端裝置106可包括由可包括RFFE匯流排之第二通信鏈路耦接之複數個裝置。 Certain aspects of the invention may be applicable to communication links deployed between electronic devices, which may include sub-assemblies of equipment such as phones, mobile computing devices, appliances, automotive electronics, avionics systems, etc. . Figure 1 depicts an apparatus 100 that may employ communication links between IC devices. In one example, device 100 may be a mobile communications device. The device 100 may include a processing circuit with two or more IC devices 104, 106 that may be coupled using a first communication link. An IC device may be an RF front-end device 106 that enables a device to communicate with a radio access network, a core access network, the Internet, and/or another network via one or more antennas 108. RF front-end device 106 may include a plurality of devices coupled by a second communication link, which may include an RFFE bus.

處理電路102可包括一或多個特殊應用IC(ASIC)裝置104。在一個實例中,ASIC裝置104可包括及/或耦接至一或多個處理裝置112、邏輯電路、一或多個數據機110及處理器可讀儲存器,諸如記憶體裝置114,其可維持可由處理電路102上之一處理器執行之指令及資料。處理電路102可由作業系統及應 用程式設計介面(API)層中之一或多者控制,該API層支援及實現駐存於儲存媒體中之軟體模組之執行。記憶體裝置114可包括唯讀記憶體(ROM)或隨機存取記憶體(RAM)、電可抹除可程式化ROM(EEPROM)、快閃記憶卡,或可用於處理系統及計算平台之任何記憶體裝置。處理電路102可包括或能夠存取可維持用以組態及操作設備100之操作參數及其他資訊的一本機資料庫或參數儲存器。本機資料庫可使用資料庫模組、快閃記憶體、磁性媒體、EEPROM、光學媒體、磁帶、軟碟或硬碟或類似者中之一或多者實施。處理電路亦可以可操作方式耦接至外部裝置,諸如天線108、顯示器120、操作員控制件(諸如按鈕124及/或整合式或外部小鍵盤122)以及其他組件。 Processing circuitry 102 may include one or more application specific IC (ASIC) devices 104 . In one example, ASIC device 104 may include and/or be coupled to one or more processing devices 112, logic circuitry, one or more data machines 110, and processor-readable storage, such as memory device 114, which may Instructions and data executable by a processor on processing circuit 102 are maintained. The processing circuit 102 may be configured by the operating system and application Controlled by one or more of the programming interface (API) layers that support and enable the execution of software modules that reside on storage media. Memory device 114 may include read only memory (ROM) or random access memory (RAM), electrically erasable programmable ROM (EEPROM), flash memory card, or any other memory device that may be used in processing systems and computing platforms. memory device. Processing circuitry 102 may include or have access to a local database or parameter store that may maintain operating parameters and other information used to configure and operate device 100. The native database may be implemented using one or more of database modules, flash memory, magnetic media, EEPROM, optical media, magnetic tape, floppy or hard disk, or the like. The processing circuitry may also be operatively coupled to external devices, such as antenna 108, display 120, operator controls (such as buttons 124 and/or integrated or external keypad 122), and other components.

RFFE匯流排之概觀 Overview of RFFE bus

圖2為說明採用RFFE匯流排208以耦接各種前端裝置212至217之裝置202的實例之方塊圖200。包括一RFFE介面210之數據機204亦可耦接至RFFE匯流排208。在各種實例中,裝置202可實施有一或多個基頻處理器206、一或多個其他通信鏈路220及各種其他匯流排、裝置及/或不同功能性。在實例中,數據機204可與基頻處理器206通信,且裝置202可體現於以下各者中之一或多者中:行動計算裝置、蜂巢式電話、智慧型電話、會話起始協定(SIP)電話、膝上型電腦、筆記型電腦、迷你筆記型電腦、智慧筆記型電腦、個人數位助理(PDA)、衛星無線電、全球定位系統(GPS)裝置、智慧型家庭裝置、智慧型照明設備、多媒體裝置、視訊裝置、數位音訊播放器(例如,MP3播放器)、攝影機、遊戲控制台、娛樂裝置、車輛組件、航電系統、可穿戴計算裝置(例如,智慧型手錶、健康或健身追蹤器、護目鏡等)、電器、感測器、安全性裝置、自動販賣機、智慧型儀錶、無人駕駛飛機、多旋翼飛行器或任何其他類似功能裝置。 FIG. 2 is a block diagram 200 illustrating an example of a device 202 employing an RFFE bus 208 to couple various front-end devices 212 - 217 . Modem 204 including an RFFE interface 210 may also be coupled to RFFE bus 208. In various examples, device 202 may implement one or more baseband processors 206, one or more other communication links 220, and various other buses, devices, and/or different functionality. In an example, modem 204 can communicate with baseband processor 206, and device 202 can be embodied in one or more of: a mobile computing device, a cellular phone, a smart phone, a session initiation protocol ( SIP) phones, laptops, notebooks, mini-laptops, smart laptops, personal digital assistants (PDAs), satellite radios, global positioning system (GPS) devices, smart home devices, smart lighting , multimedia devices, video devices, digital audio players (e.g., MP3 players), video cameras, game consoles, entertainment devices, vehicle components, avionics systems, wearable computing devices (e.g., smart watches, health or fitness trackers devices, goggles, etc.), electrical appliances, sensors, safety devices, vending machines, smart meters, drones, multi-rotor aircraft or any other similar functional devices.

RFFE匯流排208可耦接至一RF積體電路(RFIC)212,其可包括一或多個控制器,及/或組態並控制RF前端之某些態樣的處理器。RFFE匯流排208 可將RFIC 212耦接至交換器213、RF調諧器214、功率放大器(PA)215、低雜訊放大器(LNA)216及功率管理模組217。 RFFE bus 208 may be coupled to an RF integrated circuit (RFIC) 212, which may include one or more controllers and/or processors that configure and control some aspects of the RF front end. RFFE bus 208 The RFIC 212 may be coupled to the switch 213, the RF tuner 214, the power amplifier (PA) 215, the low noise amplifier (LNA) 216, and the power management module 217.

在一實例中,基頻處理器206可為一主控器裝置。主控器裝置/基頻處理器206可驅動RFFE匯流排208以控制各種前端裝置212至217。在傳輸期間,基頻處理器206可控制RFFE介面210以選擇功率放大器215用於對應傳輸頻帶。另外,基頻處理器206可控制交換器213以使得所得傳輸可自一適當天線傳播。在接收期間,取決於對應的傳輸頻帶,基頻處理器206可控制RFFE介面210自低雜訊放大器216接收。應瞭解,可以此方式經由RFFE匯流排208控制多個其他組件,使得裝置202僅為代表性且非限制性。此外,在替代性實施例中,諸如RFIC 212之其他裝置可充當一RFFE主控器裝置。 In one example, baseband processor 206 may be a master controller device. The master device/baseband processor 206 can drive the RFFE bus 208 to control the various front-end devices 212-217. During transmission, the baseband processor 206 can control the RFFE interface 210 to select the power amplifier 215 for the corresponding transmission band. Additionally, baseband processor 206 can control switch 213 so that the resulting transmission can be propagated from an appropriate antenna. During reception, the baseband processor 206 may control the RFFE interface 210 to receive from the low-noise amplifier 216 depending on the corresponding transmission frequency band. It should be understood that numerous other components may be controlled via RFFE bus 208 in this manner, so that device 202 is representative only and not limiting. Additionally, in alternative embodiments, other devices such as RFIC 212 may act as an RFFE master device.

圖3為說明用於一裝置300的一架構之一實例之方塊示意圖,該裝置可採用一RFFE匯流排330將匯流排主控器裝置3201至320N與受控器裝置302及3221至322N連接。RFFE匯流排330可根據應用需求組態,且可將對多個匯流排330之存取提供至裝置3201至320N、302及3221至322N中之某些。在操作中,匯流排主控器裝置3201至320N中之一者可獲得對匯流排之控制且傳輸一受控器識別符(受控器位址)以識別受控器裝置302及3221至322N中之一者以參與一通信異動。匯流排主控器裝置3201至320N可自受控器裝置302及3221至322N讀取資料及/或狀態,且可將資料寫入至記憶體或可組態受控器裝置302及3221至322N。組態可涉及寫入至受控器裝置302及3221至322N上之一或多個暫存器或其他儲存器。 3 is a block diagram illustrating an example of an architecture for a device 300 that may employ an RFFE bus 330 to connect bus master devices 3201 - 320N to slave devices 302 and 3221 - 322N. RFFE bus 330 may be configured according to application requirements and may provide access to multiple buses 330 to some of devices 3201-320N, 302, and 3221-322N. In operation, one of bus master devices 3201 to 320N may gain control of the bus and transmit a slave identifier (slave address) to identify slave devices 302 and 3221 to 322N One of them can participate in a communication change. Bus master devices 3201-320N can read data and/or status from slave devices 302 and 3221-322N, and can write data to memory or configure slave devices 302 and 3221-322N. . Configuration may involve writing to one or more registers or other storage on slave device 302 and 3221 through 322N.

在圖3中所說明之實例中,耦接至RFFE匯流排330之第一受控器裝置302可回應可自第一受控器裝置302讀取資料或將資料寫入至第一受控器裝置302的一或多個匯流排主控器裝置3201至320N。在一個實例中,第一受控器裝置302可包括或控制一功率放大器(參見圖2中之PA 215),且一或多個 匯流排主控器裝置3201至320N可不時地組態在第一受控器裝置302處之一增益設定。 In the example illustrated in FIG. 3 , first slave device 302 coupled to RFFE bus 330 may respond that data can be read from or written to the first slave device 302 One or more bus master devices 3201-320N of device 302. In one example, the first slave device 302 may include or control a power amplifier (see PA 215 in Figure 2), and one or more Bus master devices 3201 through 320N may configure a gain setting at first slave device 302 from time to time.

第一受控器裝置302可包括RFFE暫存器306及/或其他儲存裝置324、處理電路及/或控制邏輯312、收發器310及包括若干線驅動器/接收器電路314a、314b之介面,該介面根據需要例如,經由串列時脈線(SCLK)316及串列資料線(SDATA)318將第一受控器裝置302耦接至RFFE匯流排330。處理電路及/或控制邏輯312可包括諸如狀態機、定序器、信號處理器或通用處理器之處理器。介面可使用狀態機來實施。替代地,介面可以軟體實施於一合適處理器(若包括於第一受控器裝置302中)上。收發器310可包括一或多個接收器310a、一或多個傳輸器310c及某些共同電路310b,包括時序、邏輯及儲存電路及/或裝置。在一些實例中,收發器310可包括編碼器及解碼器、時脈及資料恢復電路及類似者。可將一傳輸時脈(TXCLK)信號328提供至傳輸器310c,其中TXCLK信號328可用以判定資料傳輸速率。 The first slave device 302 may include RFFE registers 306 and/or other storage devices 324, processing circuitry and/or control logic 312, a transceiver 310, and an interface including a plurality of line driver/receiver circuits 314a, 314b. The interface couples the first slave device 302 to the RFFE bus 330 as needed, such as via the serial clock line (SCLK) 316 and the serial data line (SDATA) 318. Processing circuitry and/or control logic 312 may include a processor such as a state machine, sequencer, signal processor, or general purpose processor. Interfaces can be implemented using state machines. Alternatively, the interface may be implemented in software on a suitable processor (if included in the first controller device 302). Transceiver 310 may include one or more receivers 310a, one or more transmitters 310c, and certain common circuitry 310b, including timing, logic, and storage circuits and/or devices. In some examples, transceiver 310 may include encoders and decoders, clock and data recovery circuitry, and the like. A transmission clock (TXCLK) signal 328 may be provided to the transmitter 310c, where the TXCLK signal 328 may be used to determine the data transmission rate.

RFFE匯流排330通常實施為一串列匯流排,其中資料由一傳輸器自並列轉換至串列形式,該傳輸器將該經編碼資料作為一串列位元串流傳輸。一接收器使用串列至並列轉換器處理接收之串列位元串流以解串列化資料。串列匯流排可包括兩個或大於兩個導線,及可將一時脈信號在一個導線上傳輸,其中在一或多個其他導線上傳輸串列化之資料。在一些情況下,可以符號編碼資料,其中符號之每一位元控制RFFE匯流排330之導線之傳信狀態。 RFFE bus 330 is typically implemented as a serial bus in which data is converted from parallel to serial form by a transmitter that transmits the encoded data as a serial bit stream. A receiver processes the received serial bit stream using a serial-to-parallel converter to deserialize the data. A serial bus may include two or more wires and may carry a clock signal on one wire with serialized data carried on one or more other wires. In some cases, the data may be encoded in symbols, where each bit of the symbol controls the signaling state of the wires of RFFE bus 330.

為了控制受控器裝置302及3221至322N,一主控器裝置(例如,主控器裝置3201至320N中之一者)寫入至受控器裝置內之RFFE暫存器(例如,第一受控器裝置302內之RFFE暫存器306)或讀取受控器裝置內之RFFE暫存器。RFFE暫存器306可根據範圍自第零(0)個位址至65535位址之一RFFE暫存器位址空間佈置。換言之,每一受控器裝置可包括多達65,536個暫存器。為了 定址此數目個暫存器,需要用於受控器裝置302及3221至322N中之每一者的16個暫存器位址位元。主控器裝置可使用以上論述的三種類型之命令中之一者(暫存器命令、擴展之暫存器命令或擴展之暫存器長命令)自每一受控器裝置中之暫存器306讀取或寫入至每一受控器裝置中之暫存器306。舉例而言,暫存器命令僅將前32個暫存器306定址於用於受控器裝置302及3221至322N中之每一者的位址空間中。以此方式,暫存器命令僅需要五個暫存器位址位元。相比之下,擴展之暫存器命令可一開始存取受控器裝置302及3221至322N中之每一者中的多達前256個暫存器。用於擴展之暫存器命令的一對應8位元暫存器位址充當一指標,其中用於該擴展之暫存器命令之資料酬載可包括多達16個位元組。用於一擴展之暫存器命令的一對應讀取或寫入操作可因此開始於由8位元暫存器位址識別之暫存器跨越16個暫存器擴展。擴展之暫存器長命令包括一16位元暫存器位址,其可充當對每一受控器裝置中之可能的65,536個暫存器中之任一者的一指標。用於一擴展之暫存器長命令的資料酬載可包括多達八個位元組,使得用於擴展之暫存器長命令的對應讀取或寫入操作可開始於由16位元位址識別之暫存器跨越八個暫存器擴展。在本發明之一態樣中,多達15個受控器裝置可耦接至一個RFFE匯流排。若一前端包括多於15個受控器裝置,則可提供額外RFFE匯流排。用於無線電頻率前端(RFFE)裝置之例示性遮罩寫入操作環境 To control slave devices 302 and 3221-322N, a master device (eg, one of master devices 3201-320N) writes to an RFFE register within the slave device (eg, the first RFFE register 306 in the slave device 302) or read the RFFE register in the slave device. The RFFE register 306 can be arranged according to one of the RFFE register address spaces ranging from the zero (0)th address to the 65535th address. In other words, each slave device may include up to 65,536 registers. for Addressing this number of registers requires 16 register address bits for each of slave device 302 and 3221 through 322N. The master device can use one of the three types of commands discussed above (register commands, extended register commands, or extended register length commands) from the buffers in each slave device. Register 306 reads or writes to register 306 in each slave device. For example, the register command addresses only the first 32 registers 306 in the address space for slave device 302 and each of 3221 through 322N. In this manner, the register command requires only five register address bits. In contrast, an extended register command may initially access up to the first 256 registers in slave device 302 and each of 3221 through 322N. A corresponding 8-bit register address for an extended register command serves as a pointer, where the data payload for the extended register command may include up to 16 bytes. A corresponding read or write operation for an extended register command may thus begin across 16 register extensions from the register identified by the 8-bit register address. The extended register length command includes a 16-bit register address that serves as a pointer to any of the possible 65,536 registers in each slave device. The data payload for an extended register length command may include up to eight bytes, so that the corresponding read or write operation for the extended register length command may start with 16 bits The address-identified registers extend across eight registers. In one aspect of the invention, up to 15 slave devices can be coupled to one RFFE bus. If a front-end includes more than 15 slave devices, additional RFFE busses may be provided. Exemplary mask writing operating environment for radio frequency front-end (RFFE) devices

在本發明之一態樣中,暫存器藉由兩個受控器裝置或組件共用並非不常見。舉例而言,一對LNA可各自藉由共用受控器暫存器中之八個位元中之四者組態。藉由兩個受限受控器裝置共用暫存器可被稱作「高度整合之」暫存器映射。組態受控器裝置中之僅僅一者需要部分寫入操作,其中8位元受控器暫存器之僅僅四個位元而非全部八個位元被寫入。用於共用暫存器的另一受控器裝置之剩餘位元必須保持不變。主控器裝置可包括「影子暫存器」,其可經由讀取操作裝載有對應受控器裝置之內容。主控器裝置可藉由使用影子暫存器之內 容及僅改變用於特定受控器裝置之對應位元並使用於共用暫存器之剩餘位元不受影響而寫入至受控器裝置。此部分寫入操作可被稱作「讀取-修改-寫入」操作,其中其涉及受控器裝置暫存器之讀取、僅僅所選擇位元之修改,及使用來自對應影子暫存器之經修改位元及未經修改位元至受控器暫存器中之整個八位元的寫入操作。影子暫存器之使用不僅使在多主控器組態之情況下的先前讀取成為必要而且歸因於額外暫存器空間要求增加矽區域。 In one aspect of the invention, it is not uncommon for registers to be shared by two slave devices or components. For example, a pair of LNAs can each be configured by sharing four of the eight bits in the slave register. Sharing registers by two constrained slave devices can be referred to as a "highly integrated" register map. Configuring only one of the slave devices requires a partial write operation in which only four bits of the 8-bit slave register are written instead of all eight bits. The remaining bits for the other slave device that share the register must remain unchanged. The master device may include a "shadow register" that may be loaded with the contents of the corresponding slave device via a read operation. The master device can be configured using shadow registers Only the corresponding bits used for a specific slave device are changed and the remaining bits used in the shared register are written to the slave device unaffected. This part of the write operation may be referred to as a "read-modify-write" operation, where it involves reading the slave device register, modifying only selected bits, and using data from the corresponding shadow register. A write operation of modified bits and unmodified bits to an entire eight-bit register in the slave device. The use of shadow registers not only necessitates previous reads in the case of multi-master configurations but also increases the silicon area due to the additional register space requirements.

圖4為說明RFFE協定中之經保留命令欄位的圖式。為減小經由RFFE匯流排208的用於部分寫入操作(讀取-修改-寫入操作)之習知RFFE命令的潛時,本文提供調用傳輸之遮罩寫入模式的新命令訊框。為提供此等新的命令訊框,利用藉由RFFE協定建立之經保留命令訊框。在彼方面,RFFE協定保留如圖4中所示範圍介於在十六進位10處之經保留命令訊框至在十六進位1B處之經保留命令訊框的至少12個命令訊框400。每一經保留命令訊框開始於如圖4中所示的繼之以四位元受控器裝置位址(SA(4))之序列開始條件(SSC)。每一經保留命令為八位元長。舉例而言,在十六進位10處之經保留命令包含八個位元00010000。所有經保留命令繼之以同位位元P,同位位元P繼之以用於保留目的之位址(Reg-Adrs)及資料訊框。 Figure 4 is a diagram illustrating reserved command fields in the RFFE protocol. To reduce the latency of conventional RFFE commands for partial write operations (read-modify-write operations) over the RFFE bus 208, a new command frame that invokes the mask write mode of the transfer is provided herein. To provide these new command frames, reserved command frames created through the RFFE protocol are utilized. In that regard, the RFFE protocol reserves at least 12 command frames 400 ranging from the reserved command frame at hex 10 to the reserved command frame at hex 1B as shown in FIG. 4 . Each reserved command frame begins with a sequence start condition (SSC) followed by a four-bit slave device address (SA(4)) as shown in Figure 4. Each reserved command is eight bits long. For example, a reserved command at hexadecimal position 10 contains eight bits 00010000. All reserved commands are followed by a parity bit P, which is followed by the address (Reg-Adrs) and data frame used for the purpose of the reservation.

圖5為說明根據本發明之一態樣的包括N位元遮罩欄位之四個遮罩寫入命令的圖式。為傳信遮罩寫入操作之使用,經保留命令訊框中之四個(指示為命令訊框CF1至CF4)可用於識別如圖5中所示之遮罩寫入RFFE命令500。在此等遮罩寫入命令500中,遮罩N位元欄位510識別將藉由遮罩寫入操作保持不變的遮罩位元及將藉由遮罩寫入操作改變的解遮罩位元。N為對應暫存器中之位元的數目。以下論述將假定N=8,但應瞭解,其他暫存器寬度可在替代實施方案中使用。資料N位元欄位512提供解遮罩位元之二進位值。舉例而言,擴展之暫存器遮罩寫入命令(擴展之暫存器WR)502開始於繼之以4位元受控器 裝置位址(受控器位址(4位元))的SSC。獲自關於圖4論述的經保留命令訊框400中之一者的8位元命令訊框CF1識別至接收受控器裝置介面之命令502。8位元位址(Reg-Adrs(8位元))識別用於擴展暫存器遮罩寫入操作的對應受控器裝置中之暫存器之位址。閒置符號(匯流排停放循環)完成命令502。 Figure 5 is a diagram illustrating four mask write commands including N-bit mask fields according to an aspect of the present invention. For use in signaling mask write operations, four of the reserved command frames (indicated as command frames CF1 through CF4) may be used to identify the mask write RFFE command 500 as shown in Figure 5. In these mask write commands 500, the mask N bit field 510 identifies the mask bits that will remain unchanged by the mask write operation and the unmask bits that will change by the mask write operation. Bits. N is the number of bits in the corresponding register. The following discussion will assume N=8, but it should be understood that other register widths may be used in alternative implementations. Data N-bit field 512 provides the binary value of the unmask bit. For example, the extended register mask write command (extended register WR) 502 begins with a 4-bit slave SSC of the device address (controller address (4 bits)). The 8-bit command frame CF1 obtained from one of the reserved command frames 400 discussed with respect to FIG. 4 identifies the command 502 to receive the slave device interface. The 8-bit Reg-Adrs (8-bit )) identifies the address of the register in the corresponding slave device for the extended register mask write operation. The idle symbol (bus park cycle) completes command 502.

擴展之暫存器長遮罩寫入命令(擴展之暫存器WR長)504亦開始於SSC及四位元受控器位址(受控器位址(4位元)),但繼之以唯一經保留命令訊框CF2。命令訊框CF2繼之以十六位元暫存器位址(Reg-Adrs(16位元))、遮罩N位元欄位510、資料N位元欄位512及閒置符號。暫存器遮罩寫入命令(暫存器WR)506亦開始於SSC及繼之以唯一經保留命令訊框CF3的受控器位址欄(受控器位址(4位元))。經保留命令訊框CF3繼之以5位元暫存器位址(Reg-Adrs(5位元))、遮罩N位元欄位510、資料N位元欄位512及閒置符號。最終,擴展之暫存器短遮罩寫入命令(擴展之暫存器WR短)508除其使用唯一經保留命令碼CF4及6位元、7位元或9至15位元暫存器位址(Reg-Adrs(9至15位元))以外類似於擴展之暫存器長遮罩寫入命令502。暫存器位元之數目可在裝置初始化階段期間建立。 The extended register long mask write command (extended register WR length) 504 also starts with the SSC and the four-bit slave address (slave address (4 bits)), but continues With only reserved command frame CF2. Command frame CF2 is followed by a sixteen-bit register address (Reg-Adrs (16 bits)), a mask N-bit field 510, a data N-bit field 512, and an idle symbol. The register mask write command (register WR) 506 also starts at SSC and is followed by the slave address field (controller address (4 bits)) of the only reserved command frame CF3. The reserved command frame CF3 is followed by a 5-bit register address (Reg-Adrs (5 bits)), a mask N-bit field 510, a data N-bit field 512, and an idle symbol. Finally, the extended register short mask write command (extended register WR short) 508 uses the only reserved command code CF4 and 6-bit, 7-bit or 9 to 15-bit register bits The address (Reg-Adrs (9 to 15 bits)) is similar to the extended register long mask write command 502. The number of register bits can be established during the device initialization phase.

圖6為說明其中根據本發明之一態樣採用單一經保留命令欄位的圖5之遮罩寫入命令的修改之圖式。圖6描繪用於通用遮罩寫入命令600之單一經保留命令訊框的使用,而非如圖5中使用經保留命令訊框中之四個。全部命令600以SSC及受控器位址(受控器位址(4位元))開始並以閒置符號結束。通用擴展之暫存器遮罩寫入命令(擴展之暫存器WR)602使用繼之以具有例如用以表示擴展之暫存器遮罩寫入操作係意欲的(0,0)之值的2位元模式欄位614的經保留命令訊框CF1。類似於命令502,命令602包括8位元暫存器位址、遮罩N位元欄位610、資料N位元欄位612及閒置符號。通用擴展之暫存器長遮罩寫入命令(擴展之暫存器WR長)604使用相同經保留命令欄位CF1。命令604亦包括具 有例如表示擴展之暫存器長遮罩寫入操作係意欲的(0,1)之值的2位元模式欄位614。類似於命令604,命令604包括16位元暫存器位址、遮罩N位元欄位610、資料N位元欄位612及閒置符號。通用暫存器遮罩寫入命令(暫存器WR)606亦包括經保留命令欄位CF1及具有例如(1,0)之值的2位元模式欄位614,該值(1,0)識別暫存器遮罩寫入操作係在後續5位元暫存器位址處使用遮罩N位元欄位610及資料N位元欄位612而意欲的。最終,通用暫存器短遮罩寫入命令(擴展之暫存器WR短)608除其使用9至15位元暫存器位址(Reg-Adrs(9至15位元))以外類似於通用擴展之暫存器長遮罩命令508。 Figure 6 is a diagram illustrating a modification of the mask write command of Figure 5 using a single reserved command field in accordance with an aspect of the invention. Figure 6 depicts the use of a single reserved command frame for the universal mask write command 600, rather than the use of four reserved command frames as in Figure 5. All commands 600 start with the SSC and slave address (slave address (4 bits)) and end with an idle symbol. The general extended register mask write command (extended register WR) 602 is used followed by a value such as (0,0) intended to represent the extended register mask write operation. Reserved command frame CF1 of 2-bit mode field 614. Similar to command 502, command 602 includes an 8-bit register address, a mask N-bit field 610, a data N-bit field 612, and an idle symbol. The general extended register length mask write command (extended register WR length) 604 uses the same reserved command field CF1. Order 604 also includes specific There is, for example, a 2-bit mode field 614 that represents a value of (0,1) intended for an extended register long mask write operation. Similar to command 604, command 604 includes a 16-bit register address, a mask N-bit field 610, a data N-bit field 612, and an idle symbol. The general purpose register mask write command (register WR) 606 also includes a reserved command field CF1 and a 2-bit mode field 614 having a value such as (1,0), which is (1,0) The identification register mask write operation is intended to use the mask N-bit field 610 and the data N-bit field 612 at the subsequent 5-bit register address. Finally, the general purpose register short mask write command (extended register WR short) 608 is similar except that it uses a 9 to 15 bit register address (Reg-Adrs (9 to 15 bits)) General extended register long mask command 508.

圖7為說明包括識別待根據本發明之一態樣改變的位元之位元位置的位元索引之四個遮罩寫入命令的圖式。若需要在經定址暫存器中改變僅僅一個位元,遮罩N位元欄位510可由如圖7中所示之log2(N)位元索引710替換,該位元索引710唯一地識別將寫入至對應N位元寬受控器裝置暫存器中的位元位置。位元值欄位712識別針對藉由位元索引710識別之位元位置位元值應為什麼。應瞭解,位元索引710及位元值欄位712可在其中每一遮罩命令包括如關於圖5類似地論述之唯一經保留命令欄位的實施例中使用。因此,擴展之暫存器索引遮罩寫入命令(擴展之暫存器WR)702除欄位510及512分別由欄位710及712替換以外類似於命令502。類似地,除了分別以欄位710及712替代欄位510及512以外,擴展之暫存器長索引遮罩寫入命令(擴展之暫存器WR長)704類似於命令504,暫存器索引遮罩寫入命令(暫存器WR)706類似於命令506,且擴展之暫存器短索引遮罩寫入命令(擴展之暫存器WR短)708類似於命令508。 7 is a diagram illustrating four mask write commands that include a bit index identifying the bit position of the bit to be changed according to an aspect of the invention. If only one bit needs to be changed in the addressed register, the mask N bit field 510 can be replaced by a log2(N) bit index 710 as shown in Figure 7, which bit index 710 uniquely identifies the Write to the bit location corresponding to the N-bit wide slave device register. Bit value field 712 identifies what the bit value should be for the bit position identified by bit index 710 . It should be appreciated that bit index 710 and bit value field 712 may be used in embodiments in which each mask command includes a unique reserved command field as discussed similarly with respect to FIG. 5 . Thus, the extended register index mask write command (extended register WR) 702 is similar to command 502 except that fields 510 and 512 are replaced by fields 710 and 712, respectively. Similarly, extended register length index mask write command (extended register WR length) 704 is similar to command 504, register index except that fields 510 and 512 are replaced by fields 710 and 712 respectively. Mask write command (Extended Register WR) 706 is similar to command 506, and Extended Register Short Index Mask Write command (Extended Register WR short) 708 is similar to command 508.

圖8為說明其中根據本發明之一態樣採用單一經保留命令欄位的圖7之遮罩寫入命令的修改之圖式。經保留命令之數目如圖8中針對使用共同經保留命令欄位CF1之通用索引遮罩寫入命令800所示可甚至進一步減小。為識別索引遮罩寫入操作之類型,命令800各自包括如關於圖6所論述之2位元 模式欄位814。因此,通用擴展之暫存器索引遮罩寫入命令(擴展之暫存器WR)802除欄位610及612分別由欄位810及812替換以外類似於命令602。類似地,除了分別以欄位810及812替代欄位610及612以外,通用擴展之暫存器長索引遮罩寫入命令(擴展之暫存器WR長)804類似於命令604,通用暫存器索引遮罩寫入命令(暫存器WR)806類似於命令606,且通用擴展之暫存器短索引遮罩寫入命令(擴展之暫存器WR短)808類似於命令608。在本發明之一態樣中,主控器裝置介面及受控器裝置介面經組態以實施本文所論述之遮罩寫入操作。此係非常有利的,此係因為消除了對在RFFE上之讀取-修改-寫入序列(亦即,在部分寫入操作之前讀取暫存器之內容)之習知需求。以此方式,所揭示遮罩寫入操作有利地減小匯流排通信潛時。 Figure 8 is a diagram illustrating a modification of the mask write command of Figure 7 using a single reserved command field in accordance with an aspect of the invention. The number of reserved commands can be reduced even further as shown in Figure 8 for the universal index mask write command 800 using a common reserved command field CF1. To identify the type of index mask write operation, the commands 800 each include 2 bits as discussed with respect to FIG. 6 Mode field 814. Therefore, the general extended register index mask write command (extended register WR) 802 is similar to command 602 except that fields 610 and 612 are replaced by fields 810 and 812 respectively. Similarly, general extended register length index mask write command (extended register WR length) 804 is similar to command 604, general extended register length index mask write command 804, except that fields 810 and 812 respectively replace fields 610 and 612. The register index mask write command (register WR) 806 is similar to command 606, and the general extended register short index mask write command (extended register WR short) 808 is similar to command 608. In one aspect of the invention, the master device interface and the slave device interface are configured to perform the mask write operations discussed herein. This is highly advantageous because it eliminates the conventional need for a read-modify-write sequence on the RFFE (ie, reading the contents of the register before a partial write operation). In this manner, the disclosed mask write operation advantageously reduces bus communication latency.

上文所論述之技術利用多個命令訊框(亦稱為命令碼)或結合模式位元之單一命令訊框。雖然上述技術在一些實施方案中可係較佳的,但下文將描述具有位址分頁及叢發寫入之添加益處的額外技術。儘管技術生根於RFFE增強,但其應用不特別限制於RFFE匯流排,而亦可適用於其他匯流排架構。 The techniques discussed above utilize multiple command frames (also called command codes) or a single command frame combined with pattern bits. While the above techniques may be preferred in some implementations, additional techniques with the added benefits of address paging and burst writes are described below. Although the technology is rooted in RFFE enhancement, its application is not particularly limited to RFFE bus, but can also be applied to other bus architectures.

如上文所描述,RFFE遮罩寫入命令可每資料報提供一個N位元遮罩欄位及一個N位元控制資料欄位。每一資料報具有15個時脈循環(SSC:1個循環、USID:4個循環、命令碼:8個循環、同位:1個循環、BPC:1個循環)之固定額外負擔。然而,對於其中多個遮罩及資料位元將被發送的應用,多個資料包之使用可歸因於相關聯額外負擔而並非係傳送資料之最佳方式。此外,未使用之經保留RFFE命令碼的數目受到限制。因此,指示叢發傳送之多個經保留命令碼的使用可並不適當,此係由於可不存在足夠命令碼甚至可用於適應例如遮罩寫入命令之八個叢發。 As described above, the RFFE mask write command provides an N-bit mask field and an N-bit control data field per datagram. Each datagram has a fixed overhead of 15 clock cycles (SSC: 1 cycle, USID: 4 cycles, command code: 8 cycles, parity: 1 cycle, BPC: 1 cycle). However, for applications where multiple masks and data bits will be sent, the use of multiple data packets may not be the best way to send the data due to the associated additional overhead. In addition, the number of unused reserved RFFE command codes is limited. Therefore, the use of multiple reserved command codes to indicate a burst transmission may not be appropriate since there may not be enough command codes available to accommodate even eight bursts of, for example, a mask write command.

因此,需要啟用全部RFFE UDR空間中之寫入存取之新的技術,當使用一個命令碼時該新技術提供對於叢發模式的支援。因此,本發明之態樣提供運用遮罩及資料位元組對的頁面定址方案及叢發寫入方案。 Therefore, a new technology is needed to enable write access in the entire RFFE UDR space, which provides support for burst mode when using a command code. Accordingly, aspects of the present invention provide page addressing schemes and burst write schemes using masks and data byte pairs.

在頁面定址方案中,受控器裝置具有1位元組基礎位址暫存器。舉例而言,基礎位址暫存器可含有十六進位的值0x00。主控器裝置將主控器裝置處之受控器裝置之基礎位址暫存器的複本維持在影子暫存器中。主控器裝置基於16位元位址(亦即,1位元組最高有效位元組(MSB)及1位元組最低有效位元組(LSB))準備資料報,但將僅僅發送遮罩寫入資料報中之1位元組LSB。在發送遮罩寫入資料報之前,主控器裝置將比較16位元位址之1位元組MSB與影子暫存器中之受控器裝置之基礎位址暫存器的當前複本。若受控器裝置之基礎位址暫存器的值不匹配16位元位址之1位元組MSB,則主控器裝置將首先設定(或更新)受控器裝置上之基礎位址(以改變頁面)以便匹配16位元位址之1位元組MSB。主控器裝置可在發送遮罩寫入資料報之前使用暫存器寫入存取命令或任何其他類型的寫入存取命令(作為優選)以執行受控器裝置基礎位址改變。頁面僅僅當在資料報傳輸之前偵測到頁面失配時才改變。主控器裝置可進一步用經更新受控器裝置基礎位址更新影子暫存器。 In the page addressing scheme, the slave device has a 1-byte base address register. For example, the base address register may contain the hexadecimal value 0x00. The master device maintains a copy of the slave device's base address register at the master device in a shadow register. The master device prepares a datagram based on the 16-bit address (i.e., 1 byte Most Significant Byte (MSB) and 1 byte Least Significant Byte (LSB)), but will only send the mask Write the 1-byte LSB in the datagram. Before sending the mask write datagram, the master device will compare the 1-byte MSB of the 16-bit address with the current copy of the slave device's base address register in the shadow register. If the value of the slave device's base address register does not match the 1-byte MSB of the 16-bit address, the master device will first set (or update) the base address on the slave device ( to change the page) to match the 1-byte MSB of the 16-bit address. The master device may use a register write access command or (preferably) any other type of write access command to perform the slave device base address change before sending the mask write datagram. Pages are changed only when a page mismatch is detected before the datagram is transmitted. The master device may further update the shadow register with the updated slave device base address.

在運用遮罩及資料位元組對之叢發寫入方案中,受控器裝置具有1位元組遮罩寫入叢發長度暫存器。舉例而言,叢發長度暫存器可具有十六進位的值0x01。主控器裝置將主控器裝置處之受控器裝置之遮罩寫入叢發長度暫存器的複本維持在影子暫存器中。主控器裝置基於所指定的遮罩及資料對叢發長度(例如遮罩及資料位元組對之數目)準備資料報,但將不發送遮罩寫入資料報中之叢發長度。在發送遮罩寫入資料報之前,主控器裝置將比較指定之叢發長度與影子暫存器中之受控器裝置之遮罩寫入叢發長度的當前複本。若受控器裝置之遮罩寫入叢發長度不匹配所指定叢發長度,則主控器裝置將首先設定(或更新)受 控器裝置上之遮罩寫入叢發長度以便匹配所指定叢發長度。主控器裝置可在發送遮罩寫入資料報之前使用暫存器寫入存取命令或任何其他類型的寫入存取命令(作為優選)以執行受控器裝置遮罩寫入叢發長度改變。遮罩寫入叢發長度僅僅當在資料報傳輸之前偵測到叢發長度失配時才改變。主控器裝置可進一步運用經更新遮罩寫入叢發長度更新影子暫存器。因此,當16位元位址之1位元組MSB匹配受控器裝置之基礎位址且所指定叢發長度匹配受控器裝置之遮罩寫入叢發長度時,主控器裝置可發送遮罩寫入資料報至受控器裝置。 In a burst write scheme using mask and data byte pairs, the slave device has a 1-byte mask write burst length register. For example, the burst length register may have a hexadecimal value of 0x01. The master device maintains a copy of the slave device's mask write burst length register at the master device in the shadow register. The master device prepares a datagram based on the specified mask and data pair burst length (eg, the number of mask and data byte pairs), but will not send the burst length that the mask writes in the datagram. Before sending the mask write datagram, the master device will compare the specified burst length to the slave device's current copy of the mask write burst length in the shadow register. If the slave device's mask write burst length does not match the specified burst length, the master device will first set (or update) the slave device. The mask on the controller device writes the burst length to match the specified burst length. The master device may use a register write access command or (preferably) any other type of write access command to perform the slave device mask write burst length before sending the mask write datagram. change. The mask write burst length is changed only when a burst length mismatch is detected before the datagram is transmitted. The master device may further update the shadow register using the updated mask write burst length. Therefore, the master device can send when the 1-byte MSB of the 16-bit address matches the slave device's base address and the specified burst length matches the slave device's mask write burst length. Mask write data is reported to the slave device.

圖9為說明支援16位元位址空間及N對遮罩及資料位元組之實例封包結構900的圖式。參看圖9,資料報標頭902可包括具有四個位元之受控器位址(SA(4))、具有八個位元之命令訊框(CMD(8)),及同位位元P。主控器裝置可基於具有1位元組最高有效位元組(MSB)906及1位元組最低有效位元組(LSB)908之16位元位址904準備資料報。主控器裝置將僅僅發送遮罩寫入資料報中之1位元組LSB 908。因此,1位元組MSB 906將並不作為遮罩寫入資料報之部分被傳輸。此外,主控器裝置可基於指定之遮罩及資料對叢發長度910準備資料報。遮罩及資料對叢發長度910指示酬載中之遮罩及資料位元組對之數目(例如遮罩+資料對#0、遮罩+資料#1,…,遮罩+資料對#N)。遮罩及資料對叢發長度910將並不作為遮罩寫入資料報之部分被傳輸。 FIG. 9 is a diagram illustrating an example packet structure 900 that supports a 16-bit address space and N pairs of mask and data bytes. Referring to Figure 9, the datagram header 902 may include a four-bit controller address (SA(4)), an eight-bit command frame (CMD(8)), and a parity bit P . The master device may prepare a data report based on a 16-bit address 904 having a 1-byte Most Significant Byte (MSB) 906 and a 1-byte Least Significant Byte (LSB) 908. The master device will only send the 1 byte LSB 908 in the mask write datagram. Therefore, the 1-byte MSB 906 will not be transmitted as part of the mask write datagram. Additionally, the master device may prepare a data report for the burst length 910 based on the specified mask and data. The mask and data pair burst length 910 indicates the number of mask and data byte pairs in the payload (e.g. mask+data pair #0, mask+data pair #1, ..., mask+data pair #N ). The mask and data pair burst length 910 will not be transmitted as part of the mask write datagram.

圖10為說明傳輸緩衝器中之實例資料報1000的圖式。在頁面定址方案中,受控器裝置1022具有1位元組基礎位址暫存器1024。主控器裝置1012將主控器裝置處之受控器裝置之基礎位址暫存器1024的複本維持在影子暫存器1014中。主控器裝置1012基於具有1位元組最高有效位元組(MSB)1006及1位元組最低有效位元組(LSB)1008之16位元位址1004準備資料報1000,但將僅僅發送遮罩寫入資料報1000中之1位元組LSB 1008。在發送遮罩寫入資料報1000之前,主控器裝置1012將比較1位元組MSB 1006與影子暫存器1014中之 受控器裝置之基礎位址暫存器1024的當前複本。若受控器裝置之基礎位址暫存器1024不匹配1位元組MSB 1006,則主控器裝置1012將首先設定(或更新)受控器裝置1022上之基礎位址1024(以改變頁面)以便匹配1位元組MSB 1006。主控器裝置1012可進一步用經更新受控器裝置基礎位址1024更新影子暫存器1014。 Figure 10 is a diagram illustrating an example datagram 1000 in a transmission buffer. In the page addressing scheme, the slave device 1022 has a 1-byte base address register 1024. The master device 1012 maintains a copy of the slave device's base address register 1024 in the shadow register 1014 at the master device. Master device 1012 prepares datagram 1000 based on 16-bit address 1004 with 1 byte Most Significant Byte (MSB) 1006 and 1 byte Least Significant Byte (LSB) 1008, but will only send The mask is written to 1 byte LSB 1008 in datagram 1000. Before sending the mask write datagram 1000, the master device 1012 will compare the 1-byte MSB 1006 with the one in the shadow register 1014. The current copy of the slave device's base address register 1024. If the base address register 1024 of the slave device does not match the 1-byte MSB 1006, the master device 1012 will first set (or update) the base address 1024 on the slave device 1022 (to change the page ) to match the 1-byte MSB 1006. The master device 1012 may further update the shadow register 1014 with the updated slave device base address 1024 .

在運用遮罩及資料位元組對之叢發寫入方案中,受控器裝置1022具有1位元組遮罩寫入叢發長度暫存器1026。主控器裝置1012將在主控器裝置1012處之受控器裝置之遮罩寫入叢發長度暫存器1026的複本維持在影子暫存器1016中。主控器裝置1012基於所指定的遮罩及資料對叢發長度1010(例如遮罩及資料位元組對之數目)準備資料報1000,但將不發送遮罩寫入資料報1000中之叢發長度1010。在發送遮罩寫入資料報1000之前,主控器裝置將比較所指定叢發長度1010與影子暫存器1016中之受控器裝置之遮罩寫入叢發長度1026的當前複本。若受控器裝置之遮罩寫入叢發長度1026不匹配所指定叢發長度1010,則主控器裝置1012將首先設定(或更新)受控器裝置1022上之遮罩寫入叢發長度1026以便匹配所指定叢發長度1010。主控器裝置1012可進一步運用經更新遮罩寫入叢發長度1026更新影子暫存器1016。因此,當1位元組MSB 1006匹配受控器裝置1022之基礎位址1024且所指定叢發長度1010匹配受控器裝置1022之遮罩寫入叢發長度1026時,主控器裝置1012可發送遮罩寫入資料報1000至受控器裝置1022。 In a burst write scheme using mask and data byte pairs, the slave device 1022 has a 1-byte mask write burst length register 1026. The master device 1012 maintains a copy of the slave device's mask write burst length register 1026 at the master device 1012 in the shadow register 1016 . The master device 1012 prepares the datagram 1000 based on the specified mask and data pair burst length 1010 (eg, the number of mask and data byte pairs), but will not send the mask written in the datagram 1000 . Hair length 1010. Before sending the mask write datagram 1000, the master device will compare the specified burst length 1010 to the slave device's current copy of the mask write burst length 1026 in the shadow register 1016. If the slave device's mask write burst length 1026 does not match the specified burst length 1010, the master device 1012 will first set (or update) the mask write burst length on the slave device 1022 1026 to match the specified burst length of 1010. The master device 1012 may further update the shadow register 1016 using the updated mask write burst length 1026 . Therefore, when the 1-byte MSB 1006 matches the base address 1024 of the slave device 1022 and the specified burst length 1010 matches the mask write burst length 1026 of the slave device 1022, the master device 1012 can Send mask write datagram 1000 to slave device 1022.

圖11為說明用於傳輸緩衝器中之資料報1100之實例操作的圖式。在頁面定址方案中,受控器裝置1122具有1位元組基礎位址暫存器1124。主控器裝置1112將主控器裝置處之受控器裝置之基礎位址暫存器1124的複本維持在影子暫存器1114中。主控器裝置1112基於具有1位元組最高有效位元組(MSB)1106及1位元組最低有效位元組(LSB)1108之16位元位址1104準備資料報1100,但將僅僅發送遮罩寫入資料報1100中之1位元組LSB 1108。在發送遮罩寫入資 料報1100之前,主控器裝置1112將比較1130 1位元組MSB 1106與影子暫存器1114中之受控器裝置之基礎位址暫存器1124的當前複本。若影子暫存器1114中之受控器裝置之基礎位址暫存器1124等於1位元組MSB 1006(參見1132),則不需要設定(或更新)受控器裝置1122上之基礎位址1124。若受控器裝置之基礎位址暫存器1124不等於1位元組MSB1106(參見1134),則主控器裝置1112將設定(或更新)受控器裝置1222上之基礎位址1124(以改變頁面)以便匹配1位元組MSB 1106。主控器裝置1112可在發送遮罩寫入資料報之前使用暫存器寫入存取命令1136或任何其他類型的寫入存取命令(作為優選)以執行受控器裝置基礎位址改變。頁面僅僅當在資料報傳輸之前偵測到頁面失配時才改變。主控器裝置1112可進一步用經更新受控器裝置基礎位址1124更新影子暫存器1114。 Figure 11 is a diagram illustrating example operations for transmitting a datagram 1100 in a buffer. In the page addressing scheme, the slave device 1122 has a 1-byte base address register 1124. The master device 1112 maintains a copy of the slave device's base address register 1124 in the shadow register 1114 at the master device. The master device 1112 prepares a datagram 1100 based on a 16-bit address 1104 with a 1-byte Most Significant Byte (MSB) 1106 and a 1-byte Least Significant Byte (LSB) 1108, but will only send The mask is written to 1 byte LSB 1108 in datagram 1100. When sending mask writing information Before reporting 1100, the master device 1112 will compare 1130 the 1-byte MSB 1106 with the current copy of the slave device's base address register 1124 in the shadow register 1114. If the slave device's base address register 1124 in shadow register 1114 is equal to 1 byte MSB 1006 (see 1132), then there is no need to set (or update) the base address on slave device 1122 1124. If the slave device's base address register 1124 is not equal to 1 byte MSB 1106 (see 1134), then the master device 1112 will set (or update) the base address 1124 on the slave device 1222 (to Change page) to match 1 byte MSB 1106. The master device 1112 may use the register write access command 1136 or (preferably) any other type of write access command to perform the slave device base address change before sending the mask write datagram. Pages are changed only when a page mismatch is detected before the datagram is transmitted. The master device 1112 may further update the shadow register 1114 with the updated slave device base address 1124 .

在運用遮罩及資料位元組對之叢發寫入方案中,受控器裝置1122具有1位元組遮罩寫入叢發長度暫存器1126。主控器裝置1112將主控器裝置1112處之受控器裝置之遮罩寫入叢發長度暫存器1126的複本維持在影子暫存器1116中。主控器裝置1112基於所指定的遮罩及資料對叢發長度1110(例如遮罩及資料位元組對之數目)準備資料報1100,但將不發送遮罩寫入資料報1100中之叢發長度1110。在發送遮罩寫入資料報1100之前,主控器裝置將比較1140所指定叢發長度1110與影子暫存器1116中之受控器裝置之遮罩寫入叢發長度1126的當前複本。若影子暫存器1116中的受控器裝置之遮罩寫入叢發長度1126等於所指定叢發長度1110(參見1142),則不需要設定(或更新)受控器裝置1122上之遮罩寫入叢發長度1126。若受控器裝置之遮罩寫入叢發長度1126不等於所指定叢發長度1110(參見1144),則主控器裝置1112將設定(或更新)受控器裝置1122上之遮罩寫入叢發長度1126以便匹配所指定叢發長度1110。主控器裝置可在發送遮罩寫入資料報之前使用暫存器寫入存取命令1146或任何其他類型的寫入存取命令(作為優選)以執行受控器裝置遮罩寫入叢發長度改變。遮罩寫入叢發長度 僅僅當在資料報傳輸之前偵測到叢發長度失配時才改變。主控器裝置1112可進一步運用經更新遮罩寫入叢發長度1126更新影子暫存器1116。因此,當1位元組MSB 1106匹配受控器裝置1122之基礎位址1124且所指定叢發長度1110匹配受控器裝置1122之遮罩寫入叢發長度1126時,主控器裝置1112可發送遮罩寫入資料報1100至受控器裝置1122。 In a burst write scheme using mask and data byte pairs, the slave device 1122 has a 1-byte mask write burst length register 1126. The master device 1112 maintains a copy of the slave device's mask write burst length register 1126 at the master device 1112 in the shadow register 1116 . The master device 1112 prepares the datagram 1100 based on the specified mask and data pair burst length 1110 (eg, the number of mask and data byte pairs), but will not send the mask written to the burst in the datagram 1100. Hair length 1110. Before sending the mask write datagram 1100, the master device will compare 1140 the specified burst length 1110 to the slave device's current copy of the mask write burst length 1126 in the shadow register 1116. If the mask write burst length 1126 of the slave device in the shadow register 1116 is equal to the specified burst length 1110 (see 1142), then there is no need to set (or update) the mask on the slave device 1122 Write burst length 1126. If the slave device's mask write burst length 1126 is not equal to the specified burst length 1110 (see 1144), the master device 1112 will set (or update) the mask write on the slave device 1122 Burst length 1126 to match the specified burst length 1110. The master device may use the register write access command 1146 or (preferably) any other type of write access command to perform a slave device mask write burst before sending the mask write datagram. Length changes. Mask writes the burst length Only changed if a burst length mismatch is detected before datagram transmission. The master device 1112 may further update the shadow register 1116 using the updated mask write burst length 1126 . Therefore, when the 1-byte MSB 1106 matches the base address 1124 of the slave device 1122 and the specified burst length 1110 matches the mask write burst length 1126 of the slave device 1122, the master device 1112 can Send mask write datagram 1100 to slave device 1122.

在本發明之一態樣中,可使用擴展之暫存器寫入資料報及/或擴展之暫存器長寫入資料報執行遮罩寫入操作。資料包之酬載可用於傳輸若干遮罩及資料對。此操作下文中可被稱作自訂遮罩寫入操作。在一態樣中,正常寫入資料報可藉由定義組態暫存器中之兩個位元區別於自訂遮罩寫入資料報,如下文將描述。圖12及圖13中說明用於遮罩寫入目的的寫入資料報酬載之利用。 In one aspect of the invention, the mask write operation may be performed using an extended register write datagram and/or an extended register long write datagram. The payload of a data packet can be used to transmit several mask and data pairs. This operation may be referred to as a custom mask write operation below. In one aspect, the normal write datagram can be distinguished from the custom mask write datagram by defining two bits in the configuration register, as described below. The use of the write data payload for mask writing purposes is illustrated in FIGS. 12 and 13 .

圖12為說明支援遮罩寫入操作的擴展之暫存器寫入命令1202之實例封包結構1200的圖式。圖13為說明支援遮罩寫入操作之擴展之暫存器長寫入命令1302之實例封包結構1300的圖式。 FIG. 12 is a diagram illustrating an example packet structure 1200 for an extended register write command 1202 that supports mask write operations. 13 is a diagram illustrating an example packet structure 1300 for an extended register length write command 1302 that supports mask write operations.

參看圖12及圖13,自訂遮罩寫入操作可在酬載段中之位元組的數目經指定為偶數以允許傳輸整數數目個遮罩及資料位元組對的情況下利用擴展之暫存器寫入命令1202及擴展之暫存器長寫入命令1302。第一遮罩位元組(亦即,遮罩0)位於在酬載中之位址位元組之後的第一偶數位置(第0個位元組)處。第一遮罩位元組繼之以對應第一資料位元組(亦即,資料0),其位於在位址位元組之後的第一奇數位置處。因此,在酬載中,在位址位元組之後,遮罩位元組(例如遮罩0、遮罩1、遮罩2等)可佔據偶數位置,而資料位元組(例如資料0、資料1、資料2等)可佔據奇數位置。 Referring to Figures 12 and 13, a custom mask write operation can take advantage of the extension when the number of bytes in the payload segment is specified as an even number to allow the transmission of an integer number of mask and data byte pairs. Register write command 1202 and extended register length write command 1302. The first mask byte (ie, mask 0) is located at the first even position (0th byte) after the address byte in the payload. The first mask byte then corresponds to the first data byte (ie, data 0), which is located at the first odd position after the address byte. Therefore, in the payload, after the address bytes, mask bytes (e.g., mask0, mask1, mask2, etc.) can occupy even positions, while data bytes (e.g., data0, mask2, etc.) Data 1, Data 2, etc.) can occupy odd positions.

可在寫入命令中傳輸的遮罩及資料位元組對之最大數目取決於酬載中允許的位元組之最大數目。舉例而言,在擴展之暫存器寫入命令1202中,酬載1204中之最大允許位元組計數為16位元組(128位元)。因此,擴展之暫存 器寫入命令1202可支援一個資料報中最大8個遮罩及資料位元組對的傳輸。如圖12中所示,酬載1204可包括1至8遮罩及資料位元組對(例如遮罩+資料對#0、遮罩+資料對#1,…,遮罩+資料對#7)。在另一實例中,在擴展之暫存器長寫入命令1302中,酬載1304中之最大允許位元組計數為8位元組(64位元)。因此,擴展之暫存器長寫入命令1302可支援一個資料報中最大4個遮罩及資料位元組對的傳輸。如圖13中所示,酬載1304可包括1至4遮罩及資料位元組對(例如遮罩+資料對#0、遮罩+資料對#1,…,遮罩+資料對#3)。 The maximum number of mask and data byte pairs that can be transferred in a write command depends on the maximum number of bytes allowed in the payload. For example, in the extended register write command 1202, the maximum allowed byte count in the payload 1204 is 16 bytes (128 bytes). Therefore, the extended temporary storage The device write command 1202 can support the transmission of a maximum of 8 mask and data byte pairs in a datagram. As shown in Figure 12, payload 1204 may include 1 to 8 mask and data byte pairs (eg, mask+data pair #0, mask+data pair #1, ..., mask+data pair #7 ). In another example, in the extended register length write command 1302, the maximum allowed byte count in the payload 1304 is 8 bytes (64 bits). Therefore, the extended register long write command 1302 can support the transmission of a maximum of 4 mask and data byte pairs in one datagram. As shown in Figure 13, payload 1304 may include 1 to 4 mask and data byte pairs (eg, mask+data pair #0, mask+data pair #1, ..., mask+data pair #3 ).

在本發明之一態樣中,8位元組態暫存器可用以提供控制功能介面以促進使用擴展之暫存器寫入命令及/或擴展之暫存器長寫入命令啟用及停用遮罩寫入操作。組態暫存器可位於一使用者定義之暫存器空間內:在十六進位中,0x01至0x1C。舉例而言,暫存器位置0x18可用作組態暫存器。然而,在替代性態樣中,預期組態暫存器可在全部暫存器空間內之任一位置處。 In one aspect of the invention, the 8-bit configuration register can be used to provide a control function interface to facilitate activation and deactivation using the extended register write command and/or the extended register long write command. Mask write operation. The configuration register can be located in a user-defined register space: in hexadecimal, 0x01 to 0x1C. For example, register location 0x18 can be used as a configuration register. However, in alternative aspects, it is contemplated that the configuration register may be located anywhere within the overall register space.

圖14為說明組態暫存器1402的實例位元結構1400之圖式。如所示,組態暫存器1402包括八個組態暫存器位元D7、D6、D5、D4、D3、D2及D1。在本發明之一態樣中,第三暫存器位元D5 1404及第四暫存器位元D4 1406可用於區分擴展之暫存器寫入及擴展之暫存器長寫入命令將用於正常方式之時與擴展之暫存器寫入及擴展之暫存器長寫入命令將用於自訂遮罩寫入操作之時。 FIG. 14 is a diagram illustrating an example bit structure 1400 of the configuration register 1402. As shown, the configuration register 1402 includes eight configuration register bits D7, D6, D5, D4, D3, D2, and D1. In one aspect of the present invention, the third register bit D5 1404 and the fourth register bit D4 1406 can be used to distinguish the extended register write and the extended register length write command to be used. In normal mode, the extended register write and extended register long write commands will be used for custom mask write operations.

舉例而言,當第三暫存器位元D5 1404經設定至值1時,則啟用自訂遮罩寫入操作,且擴展之暫存器寫入命令或擴展之暫存器長寫入命令將用於遮罩寫入操作。然而,當第三暫存器位元D5 1404經設定至值0時,則停用自訂遮罩寫入操作,且擴展之暫存器寫入命令及擴展之暫存器長寫入命令兩者將用於正常方式。此外,當第四暫存器位元D4 1406經設定至值1時,則若第三暫存器位元D5 1404經設定至值1,則擴展之暫存器長寫入命令(例如擴展之暫存器長寫入命令1302)將特別用於自訂遮罩寫入操作。當第四暫存器位元D4 1406經 設定至值0時,則若第三暫存器位元D5 1404經設定至值1,則擴展之暫存器寫入命令(例如擴展之暫存器寫入命令1202)將特別用於自訂遮罩寫入操作。 For example, when the third register bit D5 1404 is set to a value of 1, a custom mask write operation is enabled, and the extended register write command or the extended register long write command Will be used for mask write operations. However, when third register bit D5 1404 is set to a value of 0, the custom mask write operation is disabled, and both the extended register write command and the extended register long write command will be used in the normal way. In addition, when the fourth register bit D4 1406 is set to the value 1, then if the third register bit D5 1404 is set to the value 1, then the extended register length write command (such as the extended register The scratchpad long write command 1302) will be used specifically for custom mask write operations. When the fourth register bit D4 1406 has When set to a value of 0, then if the third register bit D5 1404 is set to a value of 1, an extended register write command (such as the extended register write command 1202) will be used specifically for custom Mask write operation.

圖15為一RFFE暫存器空間1500之圖式。RFFE暫存器空間1500可按十六進位自暫存器0x0000擴展至暫存器0xFFFF。 Figure 15 is a diagram of an RFFE register space 1500. The RFFE register space 1500 can be extended in hexadecimal from register 0x0000 to register 0xFFFF.

就暫存器空間可存取性而言,命令之一關聯展示於圖15中。擴展之暫存器操作之範圍可限於在0x00暫存器與0xFF暫存器之間的空間。然而,一複雜RFFE受控器可含有在64K暫存器空間內之多個頁面(各自具有0x00至0xFF 1位元組位置),且因此,使擴展之暫存器操作能夠存取全部64K暫存器空間且減少匯流排潛時。為了達成此,可將64K暫存器空間分段成256個頁面(頁面0x00至0xFF),各含有256個暫存器位置。與一頁面位址組合的在一資料庫中之8位元暫存器位址允許在64K空間內之任何暫存器存取。頁面位址可儲存於一已知暫存器位置處,且可與資料報供應之8位元暫存器位址(位址LSB)一起組合成為一位址MSB。對於一擴展之暫存器操作,此可為用於頁面分段存取之基礎。 A correlation of commands in terms of register space accessibility is shown in Figure 15. The range of extended register operations can be limited to the space between the 0x00 register and the 0xFF register. However, a complex RFFE slave can contain multiple pages within the 64K register space (each with 1-byte locations from 0x00 to 0xFF), and thus enable extended register operations to access the entire 64K register space. memory space and reduce bus drain latency. To achieve this, the 64K register space can be segmented into 256 pages (pages 0x00 to 0xFF), each containing 256 register locations. An 8-bit register address in a database combined with a page address allows any register access within the 64K space. The page address can be stored at a known register location and combined with the 8-bit register address (address LSB) provided by the data report to form an address MSB. For an extended register operation, this can be the basis for page segmented accesses.

圖16為具有一組態暫存器及一頁面位址暫存器的一RFFE暫存器空間1600之圖式。為了促進各種特徵之啟用及停用,可使用一8位元組態暫存器。該組態暫存器及一頁面位址暫存器可使用暫存器空間中為暫存器模式可存取之兩個特定暫存器。舉例而言,如圖16中所展示,組態暫存器可定義於暫存器空間中之位置0x18處,且頁面位址暫存器可定義於位置0x19處。0x18及0x19位置皆在一使用者定義之空間中。 Figure 16 is a diagram of an RFFE register space 1600 having a configuration register and a page address register. To facilitate the enabling and disabling of various features, an 8-bit configuration register is used. The configuration register and a page address register can use two specific registers in the register space that are accessible for register mode. For example, as shown in Figure 16, the configuration register may be defined at location 0x18 in the register space, and the page address register may be defined at location 0x19. Positions 0x18 and 0x19 are both in a user-defined space.

圖17說明定義組態暫存器之另一實例位元結構的圖表1700及描繪組態暫存器位元之功能的圖式1750。含有位元位置D7至D0之組態暫存器可在暫存器位置0x18處定義。參考圖表1700及圖式1750,頁面分段存取(PSA)可藉由啟用(例如設定至「1」)或停用(例如設定至「0」)在位元位置D2處之組態位元而啟用或停用。雙資料速率(DDR)模式可藉由啟用或停用位元位置D1處之組 態位元而啟用或停用。另外,自訂遮罩寫入(CMW)可藉由啟用或停用位元位置D0處之組態位元而啟用或停用。對於D0、D1及D2,組態位元值「1」意指啟用對應功能而組態位元值「0」意指停用對應功能。 Figure 17 illustrates a diagram 1700 defining another example bit structure of a configuration register and a diagram 1750 depicting the functions of the configuration register bits. The configuration register containing bit locations D7 to D0 can be defined at register location 0x18. Referring to diagram 1700 and diagram 1750, page segmented access (PSA) may be enabled (eg, set to "1") or disabled (eg, set to "0") by configuring the bit at bit location D2 and enable or disable. Double Data Rate (DDR) mode can be enabled or disabled by enabling or disabling the combination of bit positions D1 status bits to enable or disable. Additionally, Custom Mask Write (CMW) can be enabled or disabled by enabling or disabling the configuration bit at bit location D0. For D0, D1 and D2, configuring a bit value of "1" means enabling the corresponding function and configuring a bit value of "0" means disabling the corresponding function.

圖18為說明頁面分段存取之圖式1800。標準擴展之暫存器操作係基於一8位元暫存器位址。此可限制對暫存器空間之前256個位置(0x00至0xFF)的暫存器存取之此等模式之適用性。因此,就在僅使用資料報中之8位元暫存器位址時存取全部64K暫存器空間而言,用於擴展之暫存器操作的頁面分段存取(PSA)可為對標準擴展之暫存器長操作之一替代。因為僅僅使用8位元暫存器位址,所以頁面分段存取亦允許每資料報16位元組之最大酬載,此比使用16位元位址並具有每資料報8位元組之最大酬載的習知擴展暫存器長操作更高效。 Figure 18 is a diagram 1800 illustrating page segmented access. Standard extended register operations are based on an 8-bit register address. This limits the applicability of these modes to register accesses to the first 256 locations of the register space (0x00 to 0xFF). Therefore, Page Segmented Access (PSA) for extended register operations can be used to access the entire 64K register space using only the 8-bit register address in the datagram. A replacement for one of the standard extended register long operations. Because only 8-bit register addresses are used, page segmentation also allows a maximum payload of 16 bytes per data report, compared to using 16-bit addresses and having 8 bytes per data report. Maximum payload conventional extended register operations are more efficient.

64K暫存器空間存取可藉由使用頁面分段位址暫存器充當暫存器位址(MSB位置)針對擴展暫存器模式啟用。自晶片層級設計觀點,PSA操作可與遮罩寫入操作及雙資料速率(DDR)模式操作正交。可使用擁有組態暫存器中包括之暫存器位址MSB及一單一組態位元的1位元組暫存器啟用針對擴展之暫存器模式之頁面分段存取(PSA)。 64K register space access can be enabled for extended register mode by using the page segmented address register as the register address (MSB location). From a chip-level design perspective, PSA operations can be orthogonal to mask write operations and double data rate (DDR) mode operations. Page Segmented Access (PSA) for extended register mode can be enabled using a 1-byte register with the register address MSB included in the configuration register and a single configuration bit.

用於擴展暫存器操作之PSA可適用於讀取操作及寫入操作兩者。PSA可使用位於暫存器位置0x19處之值作為暫存器位址MSB並將暫存器位址MSB與在擴展之暫存器操作資料報中供應的8位元位址(暫存器位址LSB)串接。組態暫存器中之單一位元可啟用/停用PSA。 The PSA for extended register operations can be applied to both read operations and write operations. The PSA can use the value located at register location 0x19 as the register address MSB and compare the register address MSB with the 8-bit address (register bit) supplied in the extended register operation data report. address LSB) concatenation. A single bit in the configuration register enables/disables PSA.

使用暫存器位置0x19之內容及自擴展暫存器操作資料報擷取的位址LSB之頁面分段存取展示於圖18中。在暫存器位置0x19處之頁面位址暫存器1802可含有用於0x0000至0xFFFF暫存器空間中的暫存器位址之8位元MSB值。來自暫存器位置0x19之值可用作位址MSB並與自擴展暫存器操作資 料報接收到之8位元位址1804(位址LSB)組合。因此,可僅使用擴展暫存器操作資料報中之一8位元暫存器位址1804存取全部64K暫存器空間。若停用頁面分段存取(PSA)模式,則在暫存器位置0x19處之值對擴展之暫存器操作沒有影響。 Page segment access using the contents of register location 0x19 and the address LSB retrieved from the extended register operation data report is shown in Figure 18. Page address register 1802 at register location 0x19 may contain 8-bit MSB values for register addresses in register space 0x0000 to 0xFFFF. The value from register location 0x19 can be used as the address MSB and combined with the self-expanding register operation data. The received 8-bit address 1804 (address LSB) combination is reported. Therefore, the entire 64K register space can be accessed using only one of the 8-bit register addresses 1804 in the extended register operation datagram. If Page Segmented Access (PSA) mode is disabled, the value at register location 0x19 has no effect on extended register operations.

在本發明之一態樣中,用於擴展暫存器操作之頁面分段存取(PSA)允許對任一RFFE裝置之整個16位元位址空間的全存取。啟用此特徵提供優於基於擴展之暫存器長之操作的若干優點。舉例而言,僅僅運用資料報中之8位元位址,全部64K暫存器空間變得可用。另外,由於擴展之暫存器命令與擴展之暫存器長命令對比可具有多達16位元組之酬載,擴展之暫存器長命令可僅僅具有多達8位元組之酬載,所以PSA提供改良之輸送量並減少潛時。 In one aspect of the invention, page segmented access (PSA) for extended register operations allows full access to the entire 16-bit address space of any RFFE device. Enabling this feature provides several advantages over extended register length-based operations. For example, using only the 8-bit address in the datagram, the entire 64K register space becomes available. Additionally, since an extended register command can have a payload of up to 16 bytes compared to an extended register length command, an extended register length command can only have a payload of up to 8 bytes. Therefore PSA provides improved delivery capacity and reduced latency.

PSA可藉由啟用(例如設定至「1」)或停用(例如設定至「0」)位於暫存器位置0x18處的組態暫存器內之單一組態位元(例如在位元位置D2處之組態位元)而啟用或停用。當啟用時,儲存於暫存器位置0x19處之8位元頁面位址可充當暫存器位址MSB且可附接至在擴展之暫存器資料報內供應的8位元位址(充當暫存器位址LSB)。 The PSA can be configured by enabling (e.g., setting to "1") or disabling (e.g., setting to "0") a single configuration bit in the configuration register located at register location 0x18 (e.g., at bit location 0x18). Configuration bit at D2) to enable or disable. When enabled, the 8-bit page address stored at register location 0x19 serves as the register address MSB and can be attached to the 8-bit address supplied within the extended register datagram (acting as Register address LSB).

返回參看圖12,若頁面分段存取(PSA)未啟用,則支援遮罩寫入操作的擴展之暫存器寫入命令1202可限制於暫存器空間之前256個位置(暫存器位置0x00至0xFF)。然而,當PSA啟用時,支援遮罩寫入操作的擴展之暫存器寫入命令1202可具有對全部64K暫存器空間之全存取。如上文所描述,藉由使用儲存於暫存器位置0x19處的8位元頁面位址作為暫存器位址MSB,及將暫存器位址MSB附接至在擴展之暫存器寫入命令1202內供應的8位元位址(用作暫存器位址LSB),促進對全部64K暫存器空間之全存取。 Referring back to Figure 12, if page segmented access (PSA) is not enabled, the extended register write command 1202 that supports mask write operations can be limited to the first 256 locations of the register space (register locations 0x00 to 0xFF). However, when PSA is enabled, the extended register write command 1202 that supports mask write operations may have full access to the entire 64K register space. As described above, by using the 8-bit page address stored at register location 0x19 as the register address MSB, and appending the register address MSB to the extended register write The 8-bit address supplied in command 1202 (used as the register address LSB) facilitates full access to the entire 64K register space.

硬體實施方案之實例 Examples of hardware implementations

圖19為說明用於採用可經組態以執行本文所揭示之一或多個功能的處理電路1902之設備1900的硬體實施方案之簡化實例的概念圖。根據本發明之各種態樣,元件,或元件之任何部分,或如本文所揭示之元件的任何組合可使用處理電路1902來實施。處理電路1902可包括藉由硬體與軟體模組之某一組合控制的一或多個處理器1904。處理器1904之實例包括微處理器、微控制器、數位信號處理器(DSP)、ASIC、場可程式化閘陣列(FPGA)、可程式化邏輯裝置(PLD)、狀態機、定序器、閘控邏輯、離散硬體電路及經組態以執行貫穿本發明所描述之各種功能性的其他合適之硬體。一或多個處理器1904可包括執行特定功能並可藉由軟體模組1916中之一者而組態、擴充或控制之專用處理器。一或多個處理器1904可經由在初始化期間載入的軟體模組1916之組合而組態,並另外藉由在操作期間載入或卸載一或多個軟體模組1916而組態。 19 is a conceptual diagram illustrating a simplified example of a hardware implementation of a device 1900 employing processing circuitry 1902 that can be configured to perform one or more functions disclosed herein. According to various aspects of the invention, an element, or any portion of an element, or any combination of elements as disclosed herein, may be implemented using processing circuitry 1902. Processing circuitry 1902 may include one or more processors 1904 controlled by some combination of hardware and software modules. Examples of processors 1904 include microprocessors, microcontrollers, digital signal processors (DSPs), ASICs, field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, sequencers, Gating logic, discrete hardware circuits, and other suitable hardware configured to perform the various functionality described throughout this disclosure. One or more processors 1904 may include special purpose processors that perform specific functions and may be configured, expanded, or controlled by one of the software modules 1916 . One or more processors 1904 may be configured through a combination of software modules 1916 loaded during initialization and additionally configured by loading or unloading one or more software modules 1916 during operation.

在所說明之實例中,處理電路1902可實施有匯流排架構,該匯流排架構總體上由匯流排1910來表示。匯流排1910可取決於處理電路1902之特定應用及總設計約束而包括任何數目個互連匯流排及橋接器。匯流排1910將包括一或多個處理器1904及儲存器1906之各種電路鏈接在一起。儲存器1906可包括記憶體裝置及大容量儲存裝置,且可在本文中稱為電腦可讀媒體及/或處理器可讀媒體。匯流排1910亦可鏈接各種其他電路,諸如時序源、定時器、周邊裝置、電壓調節器及電力管理電路。匯流排介面1908可提供一在匯流排1910與一或多個線介面電路1912之間的介面。線介面電路1912可經提供用於藉由處理電路支援之每一網路連接技術。在一些情況下,多個網路連接技術可共用在線介面電路1912中發現的電路或處理模組之一些或全部。每一線介面電路1912提供一用於經由傳輸媒體與各種其他設備通信的構件。取決於設備1900之性質,亦可提供使用者介面1918(例如小鍵盤、顯示器、揚聲器、麥克風、操縱桿),且該使用者介面可直接或經由匯流排介面1908以通信方式耦接至匯流排1910。 In the illustrated example, processing circuitry 1902 may be implemented with a bus architecture represented generally by bus 1910 . Bus 1910 may include any number of interconnecting busses and bridges depending on the specific application and overall design constraints of processing circuit 1902 . Bus 1910 links together various circuits including one or more processors 1904 and memory 1906 . Storage 1906 may include memory devices and mass storage devices, and may be referred to herein as computer-readable media and/or processor-readable media. Bus 1910 may also connect various other circuits, such as timing sources, timers, peripheral devices, voltage regulators, and power management circuits. Bus interface 1908 may provide an interface between bus 1910 and one or more line interface circuits 1912 . Line interface circuitry 1912 may be provided for each network connection technology supported by the processing circuitry. In some cases, multiple network connection technologies may share some or all of the circuitry or processing modules found in online interface circuitry 1912. Each line interface circuit 1912 provides a means for communicating with various other devices via transmission media. Depending on the nature of the device 1900, a user interface 1918 (e.g., keypad, display, speakers, microphone, joystick) may also be provided, and the user interface may be communicatively coupled to the bus directly or via the bus interface 1908 1910.

處理器1904可負責管理匯流排1910並負責可包括儲存在可包括儲存器1906之電腦可讀媒體中的軟體之執行的一般處理。就此而言,包括處理器1904之處理電路1902可用於實施本文所揭示之方法、功能及技術中的任一者。儲存器1906可用於儲存在執行軟體時藉由處理器1904操縱的資料,且軟體可經組態以實施本文所揭示之方法中的任一者。 Processor 1904 may be responsible for managing bus 1910 and may be responsible for general processing, which may include execution of software stored in computer-readable media, which may include storage 1906 . In this regard, processing circuitry 1902 including processor 1904 may be used to implement any of the methods, functions, and techniques disclosed herein. Storage 1906 may be used to store data manipulated by processor 1904 when executing software, and the software may be configured to perform any of the methods disclosed herein.

處理電路1902中之一或多個處理器1904可執行軟體。軟件應廣泛地解釋為意謂指令、指令集、代碼、代碼段、程序代碼、程式、子程式、軟體模組、應用程式、軟體應用程式、套裝軟體、常式、次常式、目標、可執行代碼、執行緒、程序、功能、演算法等,無論是被稱作軟體、韌體、中間軟體、微碼、硬體描述語言還是其他者。軟體可以電腦可讀形式駐存在儲存器1906或外部電腦可讀媒體中。外部電腦可讀媒體及/或儲存器1906可包括非暫時性電腦可讀媒體。藉助於實例,非暫時性電腦可讀媒體包括磁性儲存裝置(例如,硬碟、軟碟、磁條)、光碟(例如,緊密光碟(CD)或數位多功能光碟(DVD))、智慧型卡、快閃記憶體裝置(例如,「隨身碟」、卡、棒或保密磁碟)、隨機存取記憶體(RAM)、唯讀記憶體(ROM)、可程式化ROM(PROM)、可抹除PROM(EPROM)、電可抹除PROM(EEPROM)、暫存器、可移除式磁碟,及用於儲存可藉由電腦存取及讀取之軟體及/或指令的任何其他合適之媒體。藉助於實例,電腦可讀媒體及/或儲存器1906亦可包括載波、傳輸線,及用於傳輸可由電腦存取及讀取的軟體及/或指令的任何其他合適之媒體。電腦可讀媒體及/或儲存器1906可駐存在處理電路1902中,處理器1904中,處理電路1902外部,或在包括處理電路1902之多個實體上分佈。電腦可讀媒體及/或儲存器1906可體現在電腦程式產品中。藉助於實例,電腦程式產品可將電腦可讀媒體包括於封裝材料中。熟習此項技術者將認識到取決於特定應用及強加於整個系統上的總設計約束而最佳地實施呈現在整個本發明中之所描述功能性的方式。 One or more processors 1904 in processing circuitry 1902 may execute software. Software shall be construed broadly to mean instructions, sets of instructions, code, code segments, program code, routines, subroutines, software modules, applications, software applications, packages, routines, subroutines, objects, Execution code, thread, program, function, algorithm, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The software may reside in computer-readable form in storage 1906 or on external computer-readable media. External computer-readable media and/or storage 1906 may include non-transitory computer-readable media. By way of example, non-transitory computer-readable media includes magnetic storage devices (e.g., hard disks, floppy disks, magnetic stripes), optical disks (e.g., compact discs (CDs) or digital versatile discs (DVDs)), smart cards , flash memory device (e.g., "pen drive," card, stick, or secure disk), random access memory (RAM), read-only memory (ROM), programmable ROM (PROM), erasable Except for PROM (EPROM), electrically erasable PROM (EEPROM), registers, removable disks, and any other suitable storage medium for storing software and/or instructions that can be accessed and read by a computer. media. By way of example, computer-readable media and/or storage 1906 may also include carrier waves, transmission lines, and any other suitable medium for transmitting software and/or instructions that can be accessed and read by a computer. Computer-readable media and/or storage 1906 may reside within processing circuitry 1902 , within processor 1904 , external to processing circuitry 1902 , or distributed across multiple entities including processing circuitry 1902 . Computer-readable media and/or storage 1906 may be embodied in a computer program product. By way of example, a computer program product may include a computer-readable medium in the packaging material. Those skilled in the art will recognize the manner in which the described functionality presented throughout this disclosure is best implemented depending on the particular application and the overall design constraints imposed on the overall system.

儲存器1906可維持在可載入碼段、模組、應用程式、程式等(其可在本文中稱為軟體模組1916)中維持及/或組織的軟體。軟體模組1916中之每一者可包括指令及資料,其當安裝或加載於處理電路1902上並藉由一或多個處理器1904執行時促成一控制一或多個處理器1904之操作的執行時影像1914。當經執行時,某些指令可使得處理電路1902根據本文中所描述的某些方法、演算法及程序執行功能。 Storage 1906 may maintain software maintained and/or organized in loadable code segments, modules, applications, programs, etc. (which may be referred to herein as software modules 1916). Each of software modules 1916 may include instructions and data that when installed or loaded on processing circuitry 1902 and executed by one or more processors 1904 facilitate a control of the operation of one or more processors 1904 Execution time image 1914. When executed, certain instructions may cause processing circuit 1902 to perform functions in accordance with certain methods, algorithms, and procedures described herein.

一些軟體模組1916可在處理電路1902之初始化期間載入,且此等軟體模組1916可組態處理電路1902以啟用本文所揭示之各種功能的執行。舉例而言,一些軟體模組1916可組態內部裝置及/或處理器1904之邏輯電路1922,且可管理對諸如線介面電路1912、匯流排介面1908、使用者介面1918、定時器、數學共處理器等之外部裝置的存取。軟體模組1916可包括一控制程式及/或一作業系統,其與中斷處置器及裝置驅動器相互作用,並控制對由處理電路1902提供之各種資源的存取。資源可包括記憶體、處理時間、對線介面電路1912之存取、使用者介面1918等等。 Certain software modules 1916 may be loaded during initialization of the processing circuit 1902, and such software modules 1916 may configure the processing circuit 1902 to enable performance of the various functions disclosed herein. For example, some software modules 1916 may configure the internal devices and/or logic circuitry 1922 of the processor 1904 and may manage functions such as line interface circuitry 1912, bus interface 1908, user interface 1918, timers, math commons, etc. Access to external devices such as processors. Software module 1916 may include a control program and/or an operating system that interacts with interrupt handlers and device drivers and controls access to various resources provided by processing circuitry 1902 . Resources may include memory, processing time, access to wire interface circuitry 1912, user interface 1918, etc.

處理電路1902之一或多個處理器1904可為多功能性,藉此一些軟體模組1916經載入並經組態以執行不同功能或相同功能之不同個例。舉例而言,一或多個處理器1904可另外經調適以管理回應於來自使用者介面1918、線介面電路1912及裝置驅動器之輸入而啟動的背景任務。為支援多個功能之執行,一或多個處理器1904可經組態以提供多任務環境,藉此複數個功能中的每一者經實施為根據需要或所要藉由一或多個處理器1904伺服的一組任務。在一個實例中,可使用通過不同任務之間的處理器1904之控制的分時程式1920實施多任務環境,藉此每一任務在完成任何未完成操作後及/或回應於諸如中斷之輸入而將一或多個處理器1904之控制返回至分時程式1920。當任務具有一或多個處理器1904之控制時,處理電路有效地特定用於藉由與控制任務相關聯的功能解決 的目的。分時程式1920可包括作業系統、在循環基礎上傳送控制之主要迴路、根據功能之優先排序分配一或多個處理器1904之控制的功能,及/或藉由提供一或多個處理器1904之控制至處置功能而對外部事件作出回應的中斷驅動主要迴路。用於自傳輸器發送資料報至接收器的例示性方法及裝置 One or more processors 1904 of processing circuit 1902 may be multifunctional, whereby several software modules 1916 are loaded and configured to perform different functions or different instances of the same function. For example, one or more processors 1904 may additionally be adapted to manage background tasks initiated in response to input from user interface 1918, line interface circuitry 1912, and device drivers. To support execution of multiple functions, one or more processors 1904 may be configured to provide a multitasking environment whereby each of the plurality of functions is implemented as needed or desired by one or more processors A set of tasks for the 1904 servo. In one example, a multitasking environment may be implemented using a time-sharing program 1920 through control of the processor 1904 between different tasks, whereby each task completes any outstanding operations and/or in response to input such as an interrupt. Control of one or more processors 1904 is returned to time-sharing routine 1920. When a task has control of one or more processors 1904, the processing circuitry is effectively specified to be solved by the functionality associated with controlling the task. the goal of. Time-sharing program 1920 may include an operating system, a primary loop that delivers control on a round-robin basis, functionality that allocates control to one or more processors 1904 based on priority of functionality, and/or by providing one or more processors 1904 The main interrupt-driven loop controls the processing function and responds to external events. Exemplary methods and apparatus for sending data packets from a transmitter to a receiver

圖20為用於經由匯流排介面發送資料至接收器的方法之流程圖2000。該方法可在作為一傳輸器(例如,匯流排主控器)操作之一裝置處執行。 Figure 20 is a flowchart 2000 of a method for sending data to a receiver via a bus interface. The method may be performed at a device operating as a transmitter (eg, bus master).

裝置可基於16位元位址以及遮罩及資料對叢發長度產生資料報2002。16位元位址包括最高有效位元組(MSB)及最低有效位元組(LSB)。 The device can generate a data report 2002 based on the 16-bit address and the mask and data burst length. The 16-bit address includes the most significant byte (MSB) and the least significant byte (LSB).

裝置接著比較MSB與維持於影子暫存器中之接收器基礎位址(分段或值)2004。此比較包括偵測MSB是否等於維持於影子暫存器中之接收器基礎位址。若MSB並不等於維持於影子暫存器中之接收器基礎位址,則裝置將接收器處之基礎位址設定為等於MSB。裝置可藉由在發送資料報之前發送寫入存取命令至接收器而設定接收器處之基礎位址。裝置進一步將維持於影子暫存器中之接收器基礎位址更新至MSB。 The device then compares the MSB to the receiver base address (segment or value) maintained in the shadow register 2004. This comparison includes detecting whether the MSB is equal to the receiver base address maintained in the shadow register. If the MSB is not equal to the receiver base address maintained in the shadow register, the device sets the base address at the receiver equal to the MSB. The device can set the base address at the receiver by sending a write access command to the receiver before sending a datagram. The device further updates the receiver base address maintained in the shadow register to the MSB.

裝置可進一步比較遮罩及資料對叢發長度與維持於影子暫存器中之接收器遮罩寫入叢發長度(分段或值)2006。此比較包括偵測遮罩及資料對叢發長度是否等於維持於影子暫存器中之接收器遮罩寫入叢發長度。若遮罩及資料對叢發長度不等於維持於影子暫存器中之接收器遮罩寫入叢發長度,則裝置將接收器處之遮罩寫入叢發長度設定為等於遮罩及資料對叢發長度。裝置可藉由在發送資料報之前發送寫入存取命令至接收器而設定接收器處之遮罩寫入叢發長度。裝置進一步將維持於影子暫存器中之接收器遮罩寫入叢發長度更新至遮罩及資料對叢發長度。 The device may further compare the mask and data pair burst lengths to the receiver mask write burst length (segment or value) maintained in the shadow register 2006. This comparison includes detecting whether the mask and data pair burst length is equal to the receiver mask write burst length maintained in the shadow register. If the mask and data pair burst length is not equal to the receiver mask write burst length maintained in the shadow register, the device sets the mask write burst length at the receiver to be equal to the mask and data On the length of the tufts. A device can set the mask write burst length at the receiver by sending a write access command to the receiver before sending a datagram. The device further updates the receiver mask write burst length maintained in the shadow register to the mask and data pair burst length.

最終,當MSB等於維持於影子暫存器中之接收器基礎位址且遮罩及資料對叢發長度等於維持於影子暫存器中之接收器遮罩寫入叢發長度時,裝 置經由匯流排介面發送資料報至接收器2008。發送至接收器之資料報不包括MSB以及遮罩及資料對叢發長度。 Finally, when the MSB is equal to the receiver base address maintained in the shadow register and the mask and data pair burst length is equal to the receiver mask write burst length maintained in the shadow register, the device The device sends data reports to the receiver 2008 via the bus interface. The datagram sent to the receiver does not include the MSB as well as the mask and data pair burst length.

圖21為用於經由匯流排介面發送資料至接收器的另一方法之流程圖2100。該方法可在作為一傳輸器(例如,匯流排主控器)操作之一裝置處執行。 Figure 21 is a flowchart 2100 of another method for sending data to a receiver via a bus interface. The method may be performed at a device operating as a transmitter (eg, bus master).

裝置可產生待經由匯流排介面傳輸至接收器的資料報中之命令欄位2102。命令欄位可指示資料報之遮罩寫入命令之類型,諸如資料報係為擴展之暫存器遮罩寫入命令、擴展之暫存器長遮罩寫入命令、暫存器遮罩寫入命令抑或擴展之暫存器短遮罩寫入命令。 The device may generate command fields 2102 in the datagram to be transmitted to the receiver via the bus interface. The command field can indicate the type of mask write command for the data report. For example, the data report is an extended register mask write command, an extended register long mask write command, or a register mask write command. Enter command or extended register short mask write command.

替代地,裝置可產生資料報中之命令欄位及模式欄位2104。因而,命令欄位可指示資料報為遮罩寫入命令且模式欄位可指示遮罩寫入命令類型,諸如資料報係為擴展之暫存器遮罩寫入命令、擴展之暫存器長遮罩寫入命令、暫存器遮罩寫入命令抑或擴展之暫存器短遮罩寫入命令。 Alternatively, the device may generate the command field and mode field 2104 in the data report. Thus, the command field may indicate that the data report is a mask write command and the mode field may indicate the mask write command type, such as that the data report is an extended register mask write command, an extended register length Mask write command, register mask write command or extended register short mask write command.

裝置可產生資料報中之遮罩欄位2106。遮罩欄位識別待在無線電頻率前端(RFFE)暫存器中改變的至少一個位元。遮罩欄位亦指示待在RFFE暫存器中保持不變的剩餘位元集合。裝置亦可產生資料報中之資料欄位2108。資料欄位提供待在RFFE暫存器中改變的至少一個位元之值。在本發明之一態樣中,遮罩欄位為識別待在RFFE暫存器中改變之位元位置的位元索引欄位,且資料欄位為提供在位元索引欄位中識別的位元位置之位元值的位元值欄位。 The device can generate mask fields 2106 in the data report. The mask field identifies at least one bit to be changed in the radio frequency front end (RFFE) register. The mask field also indicates the remaining set of bits to remain unchanged in the RFFE register. The device may also generate data fields 2108 in the data report. The data field provides the value of at least one bit to be changed in the RFFE register. In one aspect of the invention, the mask field is a bit index field that identifies the bit position to be changed in the RFFE register, and the data field is a bit index field that provides the bit position identified in the bit index field. The bit value field of the bit position value.

最終,裝置可經由介面傳輸資料報,其中資料報經定址至接收器之RFFE暫存器2110。 Finally, the device can transmit a datagram via the interface, where the datagram is addressed to the receiver's RFFE register 2110.

圖22為用於經由匯流排介面發送資料至接收器的另一方法之流程圖2200。該方法可在作為一傳輸器(例如,匯流排主控器)操作之一裝置處執行。 Figure 22 is a flowchart 2200 of another method for sending data to a receiver via a bus interface. The method may be performed at a device operating as a transmitter (eg, bus master).

裝置可設定組態暫存器以指示是否關於待傳輸至接收器之資料報啟用遮罩寫入操作2202。組態暫存器可包括八個暫存器位元。因此,裝置可將 八個暫存器位元之第三暫存器位元(例如暫存器位元D5 1404)設定至值1以指示啟用遮罩寫入操作。替代地,裝置可將第三暫存器位元(例如暫存器位元D5 1404)設定至值0以指示停用遮罩寫入操作。 The device may set the configuration register to indicate whether mask write operations 2202 are enabled on datagrams to be transmitted to the receiver. The configuration register can include eight register bits. Therefore, the device can The third register bit of the eight register bits (eg, register bit D5 1404) is set to a value of 1 to indicate that the mask write operation is enabled. Alternatively, the device may set a third register bit (eg, register bit D5 1404) to a value of 0 to indicate that the mask write operation is disabled.

在一態樣中,資料報可為擴展之暫存器寫入命令或擴展之暫存器長寫入命令。因此,當啟用遮罩寫入操作時,裝置可將組態暫存器中之第四暫存器位元(例如暫存器位元D4 1406)設定至值1以指示關於擴展之暫存器長寫入命令啟用遮罩寫入操作。當啟用遮罩寫入操作時,裝置亦可將第四暫存器位元(例如暫存器位元D4 1406)設定至值0以指示關於擴展之暫存器寫入命令啟用遮罩寫入操作。 In one aspect, the datagram may be an extended register write command or an extended register write command. Therefore, when a mask write operation is enabled, the device can set the fourth register bit (e.g., register bit D4 1406) in the configuration register to a value of 1 to indicate that the extended register The long write command enables mask write operations. When a mask write operation is enabled, the device may also set a fourth register bit (eg, register bit D4 1406) to a value of 0 to indicate that a mask write is enabled for an extended register write command. operate.

裝置可產生資料報中之命令欄位2204。命令欄位可指示資料報係為擴展之暫存器寫入命令抑或擴展之暫存器長寫入命令。 The device can generate the command field 2204 in the data report. The command field may indicate whether the data report is an extended register write command or an extended register long write command.

裝置亦可產生資料報中之酬載欄位2206。當啟用遮罩寫入操作時酬載欄位可包括若干遮罩及資料對。每一遮罩及資料對可包括識別待在無線電頻率前端(RFFE)暫存器中改變之至少一個位元的遮罩欄位及提供待在RFFE暫存器中改變的至少一個位元之值的資料欄位。 The device may also generate the payload field 2206 in the data report. When mask writing is enabled the payload field can contain several mask and data pairs. Each mask and data pair may include a mask field identifying at least one bit to be changed in the radio frequency front end (RFFE) register and providing a value for at least one bit to be changed in the RFFE register data field.

裝置經由匯流排介面傳輸資料報,其中資料報經定址至接收器之RFFE暫存器2208。 The device transmits datagrams through the bus interface, where the datagrams are addressed to the receiver's RFFE register 2208.

圖23為用於經由匯流排介面發送資料至接收器的另一方法之流程圖2300。該方法可在作為一傳輸器(例如,匯流排主控器)操作之一裝置處執行。 Figure 23 is a flowchart 2300 of another method for sending data to a receiver via a bus interface. The method may be performed at a device operating as a transmitter (eg, bus master).

裝置可藉由將接收器處的組態暫存器內之單一位元設定至第一值而啟用遮罩寫入操作2302。另外及/或替代地,裝置可藉由將接收器處的組態暫存器內之單一位元設定至第二值而停用遮罩寫入操作。舉例而言,可藉由執行至接收器之組態暫存器(例如在位置0x18處之暫存器)的寫入操作以便將位元D0設定至值「1」而啟用遮罩寫入操作。在另一實例中,可藉由執行至接收器之組態 暫存器(例如在位置0x18處之暫存器)的寫入操作以便將位元D0設定至值「0」而停用遮罩寫入操作。 The device may enable the mask write operation 2302 by setting a single bit in the configuration register at the receiver to a first value. Additionally and/or alternatively, the device may disable the mask write operation by setting a single bit within the configuration register at the receiver to the second value. For example, a mask write operation can be enabled by performing a write operation to the receiver's configuration register (such as the register at location 0x18) to set bit D0 to the value "1" . In another example, the configuration of the receiver can be performed by A write operation to a register (such as the register at location 0x18) sets bit D0 to the value "0" to disable the mask write operation.

裝置可產生待經由匯流排介面傳輸至接收器的資料報2304。資料報包括或提供位址值(例如圖18中之暫存器位址1804)。資料報可為擴展之暫存器寫入資料報或擴展之暫存器寫入長資料報。 The device may generate a datagram 2304 to be transmitted to the receiver via the bus interface. The datagram includes or provides an address value (eg, register address 1804 in Figure 18). The datagram can be an extended register write datagram or an extended register write long datagram.

裝置亦可產生資料報中之酬載欄位2306。當啟用遮罩寫入操作時酬載欄位包括若干遮罩及資料對。每一遮罩及資料對包括識別待在無線電頻率前端(RFFE)暫存器中改變之至少一個位元的遮罩欄位及提供待在RFFE暫存器中改變的至少一個位元之值的資料欄位。 The device may also generate the payload field 2306 in the data report. When the mask writing operation is enabled the payload field contains several mask and data pairs. Each mask and data pair includes a mask field identifying at least one bit to be changed in the radio frequency front end (RFFE) register and providing a value of at least one bit to be changed in the RFFE register. Data field.

裝置可藉由將接收器處之組態暫存器內的另一單一位元設定至第一值而啟用頁面分段存取操作2308。舉例而言,可藉由執行至接收器之組態暫存器(例如在位置0x18處之暫存器)的寫入操作以便將位元D2設定至值「1」而啟用頁面分段存取操作。當啟用頁面分段存取操作時,RFFE暫存器之位址為位於接收器處之頁面位址暫存器(例如暫存器位置0x19)處的位址值與藉由資料報提供的位址值之組合。 The device may enable the page segment access operation 2308 by setting another single bit within the configuration register at the receiver to the first value. For example, page segmented access can be enabled by performing a write operation to the receiver's configuration register (such as the register at location 0x18) to set bit D2 to the value "1" operate. When the page segment access operation is enabled, the address of the RFFE register is the address value located in the page address register at the receiver (for example, register location 0x19) and the bit provided by the datagram. A combination of address values.

裝置可藉由將接收器處之組態暫存器內的另一單一位元設定至第二值而停用頁面分段存取操作2310。舉例而言,頁面分段存取操作可藉由執行至接收器之組態暫存器(例如在位置0x18處之暫存器)的寫入操作以便將位元D2設定至值「0」而停用。當停用頁面分段存取操作時RFFE暫存器之位址為藉由資料報提供的位址值。 The device may disable the page segment access operation 2310 by setting another single bit within the configuration register at the receiver to the second value. For example, a page segment access operation may be performed by performing a write operation to the receiver's configuration register (such as the register at location 0x18) to set bit D2 to the value "0" Deactivate. When page segmentation is disabled, the address of the RFFE register is the address value provided by the datagram.

裝置可經由匯流排介面傳輸資料報,其中資料報經定址至接收器之RFFE暫存器2312。 The device may transmit datagrams via the bus interface, where the datagrams are addressed to the receiver's RFFE register 2312.

圖24為說明採用處理電路2402的傳輸設備2400之硬體實施方案之簡化實例的圖式。藉由傳輸設備2400執行的操作之實例包括上文關於圖20至 圖23之流程圖所描述的操作。處理電路通常具有可包括微處理器、微控制器、數位信號處理器、定序器及狀態機中之一或多者的處理器2416。處理電路2402可實施有匯流排架構(總體上由匯流排2420表示)。匯流排2420可取決於處理電路2402之特定應用及整體設計約束而包括任何數目個互連匯流排及橋接器。匯流排2420將包括由處理器2416表示之一或多個處理器及/或硬體模組、模組或電路2404、2406、2408、2410、可組態以支援經由連接器或導線2414之通信的匯流排介面電路2412及電腦可讀儲存媒體2418之各種電路鏈接在一起。匯流排2420亦可將此項技術中熟知且因此將不作任何進一步描述的諸如時序源、周邊裝置、電壓調節器及功率管理電路之各種其他電路鏈接在一起。 24 is a diagram illustrating a simplified example of a hardware implementation of a transmission device 2400 employing processing circuitry 2402. Examples of operations performed by transmission device 2400 include those described above with respect to Figures 20 to The operations described in the flowchart of Figure 23. The processing circuitry typically has a processor 2416 that may include one or more of a microprocessor, a microcontroller, a digital signal processor, a sequencer, and a state machine. Processing circuitry 2402 may be implemented with a bus architecture (represented generally by bus 2420). Bus 2420 may include any number of interconnecting busses and bridges depending on the specific application and overall design constraints of processing circuit 2402. Bus 2420 will include one or more processors, represented by processor 2416, and/or hardware modules, modules or circuits 2404, 2406, 2408, 2410 that may be configured to support communications via connectors or wires 2414 Various circuits of the bus interface circuit 2412 and the computer-readable storage medium 2418 are linked together. Bus 2420 may also link together various other circuits such as timing sources, peripherals, voltage regulators, and power management circuits that are well known in the art and therefore will not be described any further.

處理器2416負責一般處理,包括執行儲存於電腦可讀儲存媒體2418上之軟體/指令。軟體/指令在由處理器2416執行時使處理電路2402執行前文針對任一特定設備描述之各種功能。電腦可讀儲存媒體亦可用於儲存藉由處理器2416在執行軟體時操縱的資料,該資料包括用經由連接器或導線2414傳輸之符號進行解碼的資料,該等連接器或導線可經組態為資料通道及時脈通道。處理電路2402進一步包括模組/電路2404、2406、2408及2410中之至少一者。模組/電路2404、2406、2408及2410可為在處理器2416中執行之軟體模組,駐存/儲存於電腦可讀儲存媒體2418中,耦接至處理器2416之一或多個硬體模組,或其某一組合。模組/電路2404、2406、2408及/或2410可包括微控制器指令、狀態機組態參數或其某一組合。 Processor 2416 is responsible for general processing, including executing software/instructions stored on computer-readable storage media 2418. The software/instructions, when executed by processor 2416, cause processing circuitry 2402 to perform the various functions previously described for any particular device. Computer-readable storage media may also be used to store data manipulated by processor 2416 when executing software, including data decoded using symbols transmitted through connectors or wires 2414, which connectors or wires may be configured It is a data channel and a timing channel. Processing circuitry 2402 further includes at least one of modules/circuits 2404, 2406, 2408, and 2410. Modules/circuits 2404, 2406, 2408, and 2410 may be software modules executing in processor 2416, resident/stored in computer-readable storage media 2418, and coupled to one or more hardware components of processor 2416 module, or some combination thereof. Modules/circuits 2404, 2406, 2408, and/or 2410 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

在一個組態中,用於通信之設備2400包括一資料報產生/發送模組/電路2404,其經組態以:基於一16位元位址以及一遮罩及資料對叢發長度產生一資料報,該16位元位址包括最高有效位元組(MSB)及最低有效位元組(LSB);及當MSB等於維持於影子暫存器中之接收器基礎位址,且遮罩及資料對叢發長度等於維持於影子暫存器中之接收器遮罩寫入叢發長度時,經由匯流排介面模 組/電路2412,發送該資料報至接收器。設備2400進一步包括一位址比較模組/電路2406,其經組態以比較MSB與維持於影子暫存器中之接收器基礎位址。設備2400進一步包括一叢發長度比較模組/電路2408,其經組態以比較遮罩及資料對叢發長度與維持於影子暫存器中之接收器遮罩寫入叢發長度。設備2400進一步包括一暫存器設定模組/電路2410,其經組態以設定一組態暫存器以指示是否關於待經由匯流排介面模組/電路2412傳輸至接收器的資料報啟用遮罩寫入操作。 In one configuration, a device for communications 2400 includes a datagram generation/transmission module/circuitry 2404 configured to generate a burst length based on a 16-bit address and a mask and data pair. Data report, the 16-bit address includes the most significant byte (MSB) and the least significant byte (LSB); and when the MSB is equal to the receiver base address maintained in the shadow register, and the mask and The data pair burst length is equal to the receiver mask write burst length maintained in the shadow register, via the bus interface model. Group/Circuit 2412, sends this data report to the receiver. Device 2400 further includes an address comparison module/circuitry 2406 configured to compare the MSB to the receiver base address maintained in the shadow register. The device 2400 further includes a burst length comparison module/circuitry 2408 configured to compare the mask and data pair burst lengths to the receiver mask write burst length maintained in the shadow register. Device 2400 further includes a register setting module/circuitry 2410 configured to set a configuration register to indicate whether masking is enabled with respect to data packets to be transmitted to the receiver via bus interface module/circuitry 2412. Cover write operation.

在另一組態中,資料報產生/發送模組/電路2404經組態以產生待經由匯流排介面模組/電路2412傳輸至接收器的資料報中之命令欄位,產生資料報中之模式欄位,產生資料報中之酬載欄位,產生資料報中之遮罩欄位,產生資料報中之資料欄位,並經由匯流排介面模組/電路2412傳輸資料報,其中資料報經定址至接收器之無線電頻率前端(RFFE)暫存器。 In another configuration, datagram generation/transmission module/circuitry 2404 is configured to generate command fields in the datagram to be transmitted to the receiver via bus interface module/circuitry 2412, generating the command fields in the datagram. The mode field generates the payload field in the data report, generates the mask field in the data report, generates the data field in the data report, and transmits the data report via the bus interface module/circuit 2412, where the data report Addressed to the receiver's radio frequency front-end (RFFE) register.

在另一組態中,資料報產生/發送模組/電路2404經組態以:藉由將接收器處之組態暫存器內的單一位元設定至第一值而啟用遮罩寫入操作;藉由將接收器處之組態暫存器內的單一位元設定至第二值而停用遮罩寫入操作;產生待經由匯流排介面傳輸至接收器的資料報,該資料報提供位址值,產生資料報中之一酬載欄位,當啟用遮罩寫入操作時該酬載欄位包括若干遮罩及資料對,其中每一遮罩及資料對包括識別待在無線電頻率前端(RFFE)暫存器中改變之至少一個位元的一遮罩欄位及提供待在RFFE暫存器中改變之至少一個位元之值的資料欄位;藉由將接收器處之組態暫存器內的另一單一位元設定至第一值而啟用頁面分段存取操作,其中當啟用頁面分段存取操作時RFFE暫存器之位址為位於接收器處之頁面位址暫存器處之位址值與藉由資料報提供的位址值之組合;藉由將接收器處之組態暫存器內的另一單一位元設定至第二值而停用頁面分段存取操作,其中當停用頁面分段存取操作時RFFE暫存器之位址為藉由資料報提 供的位址值;及經由匯流排介面傳輸資料報,其中資料報經定址至接收器之RFFE暫存器。用於在接收器處自傳輸器接收資料報的例示性方法及裝置 In another configuration, datagram generation/transmission module/circuitry 2404 is configured to enable mask writing by setting a single bit in the configuration register at the receiver to a first value Operation; disables the mask write operation by setting a single bit in the configuration register at the receiver to a second value; generates a data report to be transmitted to the receiver via the bus interface, the data report Provides the address value to generate a payload field in the data report. When the mask write operation is enabled, the payload field includes a number of mask and data pairs, where each mask and data pair includes an identification of the radio to be held. A mask field for at least one bit changed in the frequency front end (RFFE) register and a data field providing the value of at least one bit to be changed in the RFFE register; by placing the Another single bit in the configuration register is set to a first value to enable the page segment access operation, wherein the address of the RFFE register is the page located at the receiver when the page segment access operation is enabled Combination of the address value at the address register and the address value provided by the datagram; deactivated by setting another single bit in the configuration register at the receiver to a second value Page segmentation access operation, in which the address of the RFFE register is provided by the data report when the page segmentation access operation is disabled. The address value provided; and the datagram is transmitted through the bus interface, where the datagram is addressed to the RFFE register of the receiver. Exemplary methods and apparatus for receiving datagrams from a transmitter at a receiver

圖25為用於經由匯流排介面自傳輸器接收資料之方法的流程圖2500。該方法可在作為接收器(例如,匯流排受控器)操作之裝置處執行。 Figure 25 is a flow diagram 2500 of a method for receiving data from a transmitter via a bus interface. The method may be performed at a device operating as a receiver (eg, a bus slave).

該裝置可經由匯流排介面自傳輸器接收資料報2502。資料報經定址至接收器之無線電頻率前端(RFFE)暫存器。 The device may receive data packets 2502 from the transmitter via the bus interface. Datagrams are addressed to the receiver's radio frequency front-end (RFFE) registers.

裝置可讀取資料報中之命令欄位2504。命令欄位可指示資料報之遮罩寫入命令之類型,諸如資料報係為擴展之暫存器遮罩寫入命令、擴展之暫存器長遮罩寫入命令、暫存器遮罩寫入命令抑或擴展之暫存器短遮罩寫入命令。 The device can read command field 2504 in the data report. The command field can indicate the type of mask write command for the data report. For example, the data report is an extended register mask write command, an extended register long mask write command, or a register mask write command. Enter command or extended register short mask write command.

替代地,裝置可讀取資料報中之命令欄位及模式欄位2506。因而,命令欄位可指示資料報為遮罩寫入命令且模式欄位可指示遮罩寫入命令類型,諸如資料報係為擴展之暫存器遮罩寫入命令、擴展之暫存器長遮罩寫入命令、暫存器遮罩寫入命令抑或擴展之暫存器短遮罩寫入命令。 Alternatively, the device may read the command field and mode field 2506 in the data report. Thus, the command field may indicate that the data report is a mask write command and the mode field may indicate the mask write command type, such as that the data report is an extended register mask write command, an extended register length Mask write command, register mask write command or extended register short mask write command.

裝置可讀取資料報中之遮罩欄位2508。遮罩欄位識別待在RFFE暫存器中改變的至少一個位元。遮罩欄位亦指示待在RFFE暫存器中保持不變的剩餘位元集合。裝置亦可讀取資料報中之資料欄位2510。資料欄位提供待在RFFE暫存器中改變的至少一個位元之值。在本發明之一態樣中,遮罩欄位為識別待在RFFE暫存器中改變之位元位置的位元索引欄位,且資料欄位為提供在位元索引欄位中識別的位元位置之位元值的位元值欄位。 The device can read the mask field 2508 in the data report. The mask field identifies at least one bit to be changed in the RFFE register. The mask field also indicates the remaining set of bits to remain unchanged in the RFFE register. The device can also read data field 2510 in the data report. The data field provides the value of at least one bit to be changed in the RFFE register. In one aspect of the invention, the mask field is a bit index field that identifies the bit position to be changed in the RFFE register, and the data field is a bit index field that provides the bit position identified in the bit index field. The bit value field of the bit position value.

最終,裝置可根據資料欄位中提供之值改變在遮罩欄位中識別的RFFE暫存器中之至少一個位元2512。 Ultimately, the device may change at least one bit 2512 of the RFFE register identified in the mask field based on the value provided in the data field.

圖26為用於經由匯流排介面自傳輸器接收資料之另一方法的流程圖2600。該方法可在作為接收器(例如,匯流排受控器)操作之裝置處執行。 Figure 26 is a flow diagram 2600 of another method for receiving data from a transmitter via a bus interface. The method may be performed at a device operating as a receiver (eg, a bus slave).

裝置可讀取組態暫存器以偵測是否關於待自傳輸器接收到之資料報啟用遮罩寫入操作2602。組態暫存器包括八個暫存器位元。因此,裝置可在八個暫存器位元之第三暫存器位元(例如暫存器位元D5 1404)經設定至值1時偵測到遮罩寫入操作被啟用。裝置亦可在第三暫存器位元(例如暫存器位元D5 1404)經設定至值0時偵測到遮罩寫入操作被停用。 The device may read the configuration register to detect whether mask write operation 2602 is enabled for datagrams to be received from the transmitter. The configuration register consists of eight register bits. Therefore, the device can detect that the mask write operation is enabled when the third register bit of the eight register bits (eg, register bit D5 1404) is set to a value of 1. The device may also detect that the mask write operation is disabled when a third register bit (eg, register bit D5 1404) is set to a value of zero.

在一態樣中,資料報可為擴展之暫存器寫入命令或擴展之暫存器長寫入命令。因此,當啟用遮罩寫入操作時,裝置可在組態暫存器中之第四暫存器位元(例如暫存器位元D4 1406)經設定至值1時偵測到關於擴展之暫存器長寫入命令啟用遮罩寫入操作。當啟用遮罩寫入操作時,裝置亦可在第四暫存器位元(例如暫存器位元D4 1406)經設定至值0時偵測到關於擴展之暫存器寫入命令啟用遮罩寫入操作。 In one aspect, the datagram may be an extended register write command or an extended register write command. Therefore, when a mask write operation is enabled, the device can detect an extension when the fourth register bit (e.g., register bit D4 1406) in the configuration register is set to a value of 1. The scratchpad long write command enables mask write operations. When a mask write operation is enabled, the device may also detect that the extended register write command enables the mask when the fourth register bit (eg, register bit D4 1406) is set to a value of 0. Cover write operation.

該裝置可經由匯流排介面自傳輸器接收資料報2604,其中資料報經定址至接收器之無線電頻率前端(RFFE)暫存器。 The device may receive datagrams 2604 from the transmitter via the bus interface, where the datagrams are addressed to the radio frequency front-end (RFFE) registers of the receiver.

裝置可讀取資料報中之命令欄位2606。命令欄位指示資料報係為擴展之暫存器寫入命令抑或擴展之暫存器長寫入命令。 The device can read command field 2606 in the data report. The command field indicates whether the data report is an extended register write command or an extended register write command.

裝置亦可讀取資料報中之酬載欄位2608。當啟用遮罩寫入操作時酬載欄位包括若干遮罩及資料對。每一遮罩及資料對包括識別待在RFFE暫存器中改變之至少一個位元的一遮罩欄位及提供待在RFFE暫存器中改變的該至少一個位元之值的一資料欄位。最終,裝置可根據每一遮罩及資料對之資料欄位中提供的值改變在遮罩欄位中識別的RFFE暫存器中之至少一個位元2610。 The device can also read payload field 2608 in the data report. When the mask writing operation is enabled the payload field contains several mask and data pairs. Each mask and data pair includes a mask field identifying at least one bit to be changed in the RFFE register and a data field providing the value of the at least one bit to be changed in the RFFE register. Bit. Ultimately, the device may change at least one bit 2610 in the RFFE register identified in the mask field based on the value provided in the data field of each mask and data pair.

圖27為用於經由匯流排介面自傳輸器接收資料之另一方法的流程圖2700。該方法可在作為接收器(例如,匯流排受控器)操作之裝置處執行。 Figure 27 is a flow diagram 2700 of another method for receiving data from a transmitter via a bus interface. The method may be performed at a device operating as a receiver (eg, a bus slave).

裝置可自傳輸器接收用於設定接收器處的組態暫存器內之單一位元的第一資料報2702。裝置可在組態暫存器內之單一位元經設定至第一值時偵 測到遮罩寫入操作被啟用。替代地,裝置可在接收器處的組態暫存器內之單一位元經設定至第二值時偵測到遮罩寫入操作被停用2704。舉例而言,裝置可在接收器之組態暫存器(例如在位置0x18處之暫存器)中的位元D0具有如藉由傳輸器經由寫入操作設定的值「1」時偵測到遮罩寫入操作被啟用。在另一實例中,裝置可在接收器之組態暫存器(例如在位置0x18處之暫存器)中的位元D0具有如藉由傳輸器經由寫入操作設定的值「0」時偵測到遮罩寫入操作被停用。 The device may receive a first datagram 2702 from the transmitter for setting a single bit in the configuration register at the receiver. The device can detect when a single bit in the configuration register is set to the first value. Detected that mask write operation is enabled. Alternatively, the device may detect that the mask write operation is disabled 2704 when a single bit within the configuration register at the receiver is set to the second value. For example, a device may detect when bit D0 in the receiver's configuration register (e.g., the register at location 0x18) has the value "1" as set by the transmitter via a write operation. To mask writing operations are enabled. In another example, the device may operate when bit D0 in the receiver's configuration register (e.g., the register at location 0x18) has a value of "0" as set by the transmitter via a write operation. Mask writing disabled was detected.

裝置可自傳輸器接收第二資料報2706。第二資料報包括或提供位址值(例如圖18中之暫存器位址1804)。第二資料報可為擴展之暫存器寫入資料報或擴展之暫存器寫入長資料報。 The device may receive a second datagram 2706 from the transmitter. The second datagram includes or provides an address value (eg, register address 1804 in Figure 18). The second datagram may be an extended register write datagram or an extended register write long datagram.

裝置可讀取第二資料報中之酬載欄位2708。當啟用遮罩寫入操作時酬載欄位包括若干遮罩及資料對。每一遮罩及資料對包括識別待在接收器之無線電頻率前端(RFFE)暫存器中改變之至少一個位元的遮罩欄位及提供待在RFFE暫存器中改變的至少一個位元之值的資料欄位。 The device can read the payload field 2708 in the second data report. When the mask writing operation is enabled the payload field contains several mask and data pairs. Each mask and data pair includes a mask field identifying at least one bit to be changed in a radio frequency front end (RFFE) register of the receiver and providing at least one bit to be changed in the RFFE register A data field with a value.

裝置可自傳輸器接收用於設定接收器處的組態暫存器內之另一單一位元的第三資料報2710。裝置可在接收器處之組態暫存器內的另一單一位元經設定至第一值時偵測到頁面分段存取操作被啟用2712。舉例而言,裝置可在接收器之組態暫存器(例如在位置0x18處之暫存器)中的位元D2具有如藉由傳輸器經由寫入操作設定的值「1」時偵測到頁面分段存取操作被啟用。當啟用頁面分段存取操作時,RFFE暫存器之位址為位於接收器處之頁面位址暫存器(例如暫存器位置0x19)處的位址值與藉由資料報提供的位址值之組合。 The device may receive a third data report 2710 from the transmitter for setting another single bit in the configuration register at the receiver. The device may detect that the page segmentation access operation is enabled 2712 when another single bit in the configuration register at the receiver is set to the first value. For example, a device may detect when bit D2 in the receiver's configuration register (e.g., the register at location 0x18) has the value "1" as set by the transmitter via a write operation. Staging access to the page is enabled. When the page segment access operation is enabled, the address of the RFFE register is the address value located in the page address register at the receiver (for example, register location 0x19) and the bit provided by the datagram. A combination of address values.

裝置可在接收器處之組態暫存器內的另一單一位元經設定至第二值時偵測到頁面分段存取操作被停用2714。舉例而言,裝置可在接收器之組態暫存器(例如在位置0x18處的暫存器)中之位元D2具有如藉由傳輸器經由寫入操 作設定之值「0」時偵測到頁面分段存取操作被停用。當停用頁面分段存取操作時RFFE暫存器之位址為藉由資料報提供的位址值。 The device may detect that the page segmentation access operation is disabled 2714 when another single bit in the configuration register at the receiver is set to the second value. For example, a device may have bit D2 in the receiver's configuration register (e.g., the register at location 0x18) as configured by the transmitter via a write operation. When setting the value of "0", it is detected that the page segmentation operation is disabled. When page segmentation is disabled, the address of the RFFE register is the address value provided by the datagram.

裝置可根據每一遮罩及資料對之資料欄位中提供的值改變在遮罩欄位中識別的RFFE暫存器中之至少一個位元2716。 The device may change at least one bit 2716 in the RFFE register identified in the mask field based on the value provided in the data field of each mask and data pair.

圖28為說明採用處理電路2802的接收設備2800之硬體實施方案之簡化實例的圖式。藉由接收設備2800執行的操作之實例包括上文關於圖25及圖27之流程圖所描述的操作。處理電路通常具有可包括微處理器、微控制器、數位信號處理器、定序器及狀態機中之一或多者的處理器2816。處理電路2802可實施有匯流排架構(總體上由匯流排2820表示)。匯流排2820可取決於處理電路2802之特定應用及整體設計約束而包括任何數目個互連匯流排及橋接器。匯流排2820將包括由處理器2816表示之一或多個處理器及/或硬體模組、模組或電路2804、2806、2808、2810、可組態以支援經由連接器或導線2814之通信的匯流排介面電路2812及電腦可讀儲存媒體2818之各種電路鏈接在一起。匯流排2820亦可將此項技術中熟知且因此將不作任何進一步描述的諸如時序源、周邊裝置、電壓調節器及功率管理電路之各種其他電路鏈接在一起。 Figure 28 is a diagram illustrating a simplified example of a hardware implementation of a receiving device 2800 employing processing circuitry 2802. Examples of operations performed by receiving device 2800 include the operations described above with respect to the flowcharts of Figures 25 and 27. The processing circuitry typically has a processor 2816 that may include one or more of a microprocessor, a microcontroller, a digital signal processor, a sequencer, and a state machine. Processing circuitry 2802 may be implemented with a bus architecture (represented generally by bus 2820). Bus 2820 may include any number of interconnecting busses and bridges depending on the specific application and overall design constraints of processing circuit 2802. Bus 2820 will include one or more processors, represented by processor 2816, and/or hardware modules, modules or circuits 2804, 2806, 2808, 2810 that may be configured to support communications via connectors or wires 2814 Various circuits of the bus interface circuit 2812 and the computer-readable storage medium 2818 are linked together. Bus 2820 may also link together various other circuits such as timing sources, peripherals, voltage regulators, and power management circuits that are well known in the art and therefore will not be described any further.

處理器2816負責一般處理,包括執行儲存於電腦可讀儲存媒體2818上之軟體/指令。軟體/指令在由處理器2816執行時使處理電路2802執行前文針對任一特定設備描述之各種功能。電腦可讀儲存媒體亦可用於儲存藉由處理器2816在執行軟體時操縱的資料,該資料包括用經由連接器或導線2814傳輸之符號進行解碼的資料,該等連接器或導線可經組態為資料通道及時脈通道。處理電路2802進一步包括模組/電路2804、2806、2808及2810中之至少一者。模組/電路2804、2806、2808及2810可為在處理器2816中執行之軟體模組,駐存/儲存於電腦可讀儲存媒體2818中,耦接至處理器2816之一或多個硬體模組,或 其某一組合。模組/電路2804、2806、2808及/或2810可包括微控制器指令、狀態機組態參數或其某一組合。 Processor 2816 is responsible for general processing, including executing software/instructions stored on computer-readable storage media 2818. The software/instructions, when executed by processor 2816, cause processing circuitry 2802 to perform the various functions previously described for any particular device. Computer-readable storage media may also be used to store data manipulated by processor 2816 when executing software, including data decoded using symbols transmitted through connectors or wires 2814, which connectors or wires may be configured It is a data channel and a pulse channel. Processing circuitry 2802 further includes at least one of modules/circuits 2804, 2806, 2808, and 2810. Modules/circuits 2804, 2806, 2808, and 2810 may be software modules executing in processor 2816, resident/stored in computer-readable storage media 2818, and coupled to one or more hardware components of processor 2816 module, or a certain combination thereof. Modules/circuits 2804, 2806, 2808, and/or 2810 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

在一個組態中,用於通信之設備2800包括一資料報接收模組/電路2804,其經組態以經由匯流排介面模組/電路2812自傳輸器接收資料報,其中資料報經定址至設備2800之無線電頻率前端(RFFE)暫存器。設備2800進一步包括一欄位讀取模組/電路2806,其經組態以讀取資料報中之命令欄位,讀取資料報中之酬載欄位,讀取資料報中之模式欄位,讀取資料報中之遮罩欄位,並讀取資料報中之資料欄位。設備2800進一步包括一位元改變模組/電路2808,其經組態以根據資料欄位中提供的值改變遮罩欄位中識別的RFFE暫存器中之至少一個位元。設備2800亦包括一暫存器讀取模組/電路2810,其經組態以讀取組態暫存器以偵測是否關於待自傳輸器接收到之資料報啟用遮罩寫入操作。 In one configuration, a device for communications 2800 includes a datagram receiving module/circuitry 2804 configured to receive datagrams from a transmitter via a bus interface module/circuitry 2812, where the datagrams are addressed to Device 2800 Radio Frequency Front End (RFFE) register. Device 2800 further includes a field reading module/circuitry 2806 configured to read the command field in the data report, read the payload field in the data report, and read the mode field in the data report. , read the mask field in the data report, and read the data field in the data report. Device 2800 further includes a bit change module/circuitry 2808 configured to change at least one bit in the RFFE register identified in the mask field based on the value provided in the data field. Device 2800 also includes a register read module/circuitry 2810 configured to read the configuration register to detect whether a mask write operation is enabled for a datagram to be received from the transmitter.

在另一組態中,資料報接收模組/電路2804經組態以:自傳輸器接收用於設定接收器處之組態暫存器內之單一位元的第一資料報;在組態暫存器內之單一位元經設定至第一值時偵測到遮罩寫入操作被啟用;在接收器處之組態暫存器內的單一位元經設定至第二值時偵測到遮罩寫入操作被停用;自傳輸器接收第二資料報,該第二資料報提供一位址值;自傳輸器接收用於設定接收器處的組態暫存器內之另一單一位元的第三資料報;在接收器處的組態暫存器內之另一單一位元經設定至第一值時偵測到頁面分段存取操作被啟用,其中當啟用頁面分段存取操作時,RFFE暫存器之位址為位於接收器處之頁面位址暫存器處的位址值與藉由資料報提供的位址值之組合;及在接收器處之組態暫存器內的另一單一位元經設定至第二值時偵測到頁面分段存取操作被停用,其中當停用頁面分段存取操作時,RFFE暫存器之位址為藉由資料報提供的位址值, In another configuration, the datagram receiving module/circuit 2804 is configured to: receive a first datagram from the transmitter that sets a single bit in the configuration register at the receiver; in the configuration A mask write operation is enabled when a single bit in the register is set to a first value; a mask write operation is enabled when a single bit in the configuration register at the receiver is set to a second value. until the mask write operation is disabled; receive a second datagram from the transmitter that provides an address value; receive from the transmitter another value in the configuration register used to set the receiver. A third datagram of a single bit; detecting that the page segmentation access operation is enabled when another single bit in the configuration register at the receiver is set to the first value, wherein when page segmentation is enabled During a segment access operation, the address of the RFFE register is a combination of the address value at the page address register at the receiver and the address value provided by the datagram; and the combination at the receiver When another single bit in the status register is set to the second value, it is detected that the page segmentation access operation is disabled, wherein when the page segmentation access operation is disabled, the address of the RFFE register is the address value provided via the datagram,

在另一組態中,欄位讀取模組/電路2806經組態以讀取第二資料報中之酬載欄位,當啟用遮罩寫入操作時該酬載欄位包括若干遮罩及資料對,其 中每一遮罩及資料對包括識別待在接收器之無線電頻率前端(RFFE)暫存器中改變的至少一個位元的遮罩欄位及提供待在RFFE暫存器中改變的至少一個位元之值的資料欄位。 In another configuration, the field read module/circuitry 2806 is configured to read a payload field in the second data report that includes a number of masks when a mask write operation is enabled. and data pair, its Each mask and data pair includes a mask field identifying at least one bit to be changed in the radio frequency front end (RFFE) register of the receiver and providing at least one bit to be changed in the RFFE register Data field for dollar value.

在另一組態中,欄位讀取模組/電路2806經組態以根據在每一遮罩及資料對之資料欄位中提供的值改變在遮罩欄位中識別的RFFE暫存器中之至少一個位元。 In another configuration, the field read module/circuitry 2806 is configured to change the RFFE register identified in the mask field based on the value provided in the data field of each mask and data pair. At least one bit in it.

用於無線電頻率前端(RFFE)裝置之另一例示性遮罩寫入操作環境 Another exemplary mask writing operating environment for a radio frequency front-end (RFFE) device

圖29為說明用於一裝置2900的架構之實例之方塊示意圖,該裝置可採用一RFFE匯流排2902將匯流排主控器裝置2904與受控器裝置2906(1)至2906(N)連接。RFFE匯流排2902可根據應用需求組態,且可將對多個匯流排2902之存取提供至裝置2904及2906(1)至2906(N)中之某些。在一態樣中,匯流排主控器裝置2904及受控器裝置2906(1)至2906(N)可經組態以以與上文所描述(例如關於圖2及圖3)的匯流排主控器裝置及受控器裝置相同之方式操作。 29 is a block diagram illustrating an example architecture for a device 2900 that may employ an RFFE bus 2902 to connect bus master device 2904 to slave devices 2906(1)-2906(N). RFFE bus 2902 can be configured according to application requirements, and access to multiple buses 2902 can be provided to some of devices 2904 and 2906(1)-2906(N). In one aspect, bus master device 2904 and slave devices 2906(1)-2906(N) may be configured to operate with the bus described above (eg, with respect to FIGS. 2 and 3). The master controller device and the slave controller device operate in the same manner.

在另一態樣中,受控器裝置2906(1)至2906(N)中的任一者(例如源受控器裝置)可產生經定向至RFFE匯流排2902上之另一受控器裝置的遮罩寫入資料報。遮罩寫入資料報可包括識別待在經定向受控器裝置之RFFE暫存器中改變之至少一個位元的遮罩欄位及提供待在RFFE暫存器中改變的至少一個位元之值的資料欄位。在源受控器裝置發送遮罩寫入資料報至經定向受控器裝置之前,源受控器裝置可向匯流排主控器裝置2904請求執行受控器至受控器通信。其後,若藉由匯流排主控器裝置2904准許,則源受控器裝置可發送遮罩寫入資料報至經定向受控器裝置。 In another aspect, any of the slave devices 2906(1)-2906(N) (eg, a source slave device) may generate another slave device directed onto the RFFE bus 2902 The mask is written into the data report. The mask write datagram may include a mask field identifying at least one bit to be changed in the RFFE register of the directed slave device and providing at least one bit to be changed in the RFFE register. Value data field. Before the source slave device sends a mask write data packet to the directed slave device, the source slave device may request the bus master device 2904 to perform slave-to-slave communication. Thereafter, if permitted by bus master device 2904, the source slave device may send a mask write data report to the directed slave device.

在一態樣中,匯流排主控器裝置2904可經組態以執行關於RFFE匯流排2902上之受控器至受控器通信的安全功能。舉例而言,匯流排主控器裝 置2904可包括一鑑認電路/模組2916,其經組態以例如基於經允許交互之圖表查詢判定是否允許受控器至受控器通信。 In one aspect, bus master device 2904 may be configured to perform security functions regarding slave-to-slave communications on RFFE bus 2902 . For example, the bus master controller Setup 2904 may include an authentication circuit/module 2916 configured to determine whether slave-to-controller communication is allowed, for example, based on a graph query of allowed interactions.

一般而言,當受控器裝置2906(1)至2906(N)中之一者指示於RFFE匯流排2902上發送遮罩寫入資料報至另一受控器裝置的請求時,匯流排主控器裝置2904可考慮該請求(經由鑑認電路/模組2916)並比較所意欲受控器至受控器通信與經允許交互之系統定義。此比較可包括與安全實體之通信。若匯流排主控器裝置2904批准經請求之受控器至受控器通信,則匯流排主控器裝置2904可不採取特定動作或可確認對請求受控器裝置之批准。若匯流排主控器裝置2904不批准請求之受控器至受控器通信,則匯流排主控器裝置2904可阻止於RFFE匯流排2902上之遮罩寫入資料報的發送,將請求未被批准通知請求受控器裝置,及/或採取某其他動作。 Generally speaking, when one of slave devices 2906(1) through 2906(N) indicates a request to send a mask write datagram on RFFE bus 2902 to another slave device, the bus master Controller device 2904 may consider the request (via authentication circuitry/module 2916) and compare the intended controller-to-controller communication to the system definition for which the interaction is allowed. This comparison may include communications with the security entity. If bus master device 2904 approves the requested slave-to-slave communication, bus master device 2904 may not take a particular action or may confirm approval of the requesting slave device. If the bus master device 2904 does not approve the requested slave-to-slave communication, the bus master device 2904 can prevent the sending of the mask write datagram on the RFFE bus 2902 and send the requested slave to the slave. Approved notification requests the controlled device, and/or takes some other action.

圖30為用於經由RFFE匯流排在受控器裝置之間傳達遮罩寫入資料包之方法的流程圖3000。 Figure 30 is a flow diagram 3000 of a method for communicating mask write packets between slave devices over an RFFE bus.

在3002處,受控器裝置可產生經定向至RFFE匯流排上之另一受控器裝置的遮罩寫入資料報。受控器裝置可進一步向匯流排主控器裝置指示發送遮罩寫入資料報至另一受控器裝置的一請求。 At 3002, the slave device may generate a mask write datagram directed to another slave device on the RFFE bus. The slave device may further instruct the bus master device a request to send a mask write data packet to another slave device.

在3004處,匯流排主控器裝置可接收該請求並決定是否授權受控器裝置以發送遮罩寫入資料報至另一受控器裝置。舉例而言,匯流排主控器裝置可比較請求之受控器至受控器通信與經允許交互之系統定義。 At 3004, the bus master device may receive the request and determine whether to authorize the slave device to send a mask write data report to another slave device. For example, the bus master device may compare the requested slave-to-slave communication to the system definition that is allowed to interact.

在3006處,若匯流排主控器裝置授權受控器至受控器通信,則匯流排主控器裝置(在3008處)准許受控器裝置發送遮罩寫入資料報至另一受控器裝置。舉例而言,匯流排主控器裝置可藉由不採取特定動作或向請求受控器裝置指示批准受控器受控器通信而准許發送遮罩寫入資料報。 At 3006, if the bus master device authorizes slave-to-slave communication, the bus master device (at 3008) permits the slave device to send a mask write data packet to another slave. device. For example, the bus master device may permit sending of the mask write datagram by not taking a specific action or by indicating to the requesting slave device that slave slave communication is approved.

替代地,在3006處,若匯流排主控器裝置不授權受控器至受控器通信,則匯流排主控器裝置(在3010處)可防止受控器裝置發送遮罩寫入資料報至另一受控器裝置。舉例而言,匯流排主控器裝置可藉由向請求受控器裝置指示未批准受控器至受控器通信及/或在RFFE匯流排上發出匯流排停放循環以阻止遮罩寫入資料報之通信而防止遮罩寫入資料報之發送。用於促進在匯流排上之資料通信的例示性方法及裝置 Alternatively, at 3006, if the bus master device does not authorize slave-to-slave communication, the bus master device (at 3010) may prevent the slave device from sending a mask write data report. to another controlled device. For example, the bus master device can prevent the mask from writing data by indicating to the requesting slave device that slave-to-slave communication is not approved and/or issuing a bus park cycle on the RFFE bus. The communication of the message prevents the sending of the mask write data message. Exemplary methods and apparatus for facilitating data communication on a bus

圖31為用於促進匯流排上之資料通信之方法的流程圖3100。方法可在主控器裝置處執行。 Figure 31 is a flow diagram 3100 of a method for facilitating data communication on a bus. Methods can be executed at the master device.

主控器裝置可自第一受控器裝置接收經由匯流排發送一遮罩寫入資料報至一第二受控器裝置的一請求3102。該遮罩寫入資料報經定址至第二受控器裝置之無線電頻率前端(RFFE)暫存器。遮罩寫入資料報可包括識別待在RFFE暫存器中改變之至少一個位元的一遮罩欄位及提供待在RFFE暫存器中改變的至少一個位元之一值的一資料欄位。遮罩欄位可進一步識別第二受控器裝置之RFFE暫存器中保持不變的剩餘位元集合。在一態樣中,遮罩欄位為識別待在第二受控器裝置之RFFE暫存器中改變之位元位置的位元索引欄位且資料欄位為提供在位元索引欄位中識別的位元位置之位元值的位元值欄位。 The master device may receive a request 3102 from a first slave device to send a mask write data packet to a second slave device via the bus. The mask write datagram is addressed to the radio frequency front end (RFFE) register of the second slave device. The mask write datagram may include a mask field identifying at least one bit to be changed in the RFFE register and a data field providing a value of at least one bit to be changed in the RFFE register. Bit. The mask field further identifies the remaining set of bits that remain unchanged in the RFFE register of the second slave device. In one aspect, the mask field is a bit index field that identifies a bit location to be changed in the RFFE register of the second slave device and the data field is provided in the bit index field The bit value field of the bit value of the identified bit position.

主控器裝置可偵測第一受控器裝置是否經授權以發送遮罩寫入資料報至第二受控器裝置3104。舉例而言,主控器裝置可比較請求之遮罩寫入資料報通信與受控器裝置之間的經允許交互之系統定義。在一態樣中,主控器裝置可與安全實體通信以判定是否允許遮罩寫入資料報通信。 The master device may detect whether the first slave device is authorized to send a mask write data report to the second slave device 3104. For example, the master device may compare the requested mask write datagram communication to the system definition of allowed interactions between the slave device. In one aspect, the master device may communicate with the security entity to determine whether the mask write datagram communication is allowed.

若偵測到授權,則主控器裝置可准許第一受控器裝置發送遮罩寫入資料報至第二受控器裝置3106。在一態樣中,主控器裝置可藉由將第一受控器裝置經授權以發送遮罩寫入資料報通知第一受控器裝置而准許。替代地,主控器裝置可藉由不採取特定動作而准許。 If authorization is detected, the master device may allow the first slave device to send the mask write data report to the second slave device 3106. In one aspect, the master device may grant permission by notifying the first slave device that the first slave device is authorized to send a mask write datagram. Alternatively, the master device may grant permission by not taking a specific action.

若未偵測到授權,則主控器裝置可防止第一受控器裝置發送遮罩寫入資料報至第二受控器裝置3108。在一態樣中,主控器裝置可藉由將第一受控器裝置未經授權以發送遮罩寫入資料報通知第一受控器裝置而防止。另外及/或替代地,主控器裝置可藉由在匯流排上發出匯流排停放循環以阻止遮罩寫入資料報之發送而防止。 If authorization is not detected, the master device may prevent the first slave device from sending a mask write data report to the second slave device 3108. In one aspect, the master device may prevent the first slave device from notifying the first slave device of unauthorized sending of a mask write datagram. Additionally and/or alternatively, the master device may prevent the sending of the mask write datagram by issuing a bus park cycle on the bus.

圖32為說明採用處理電路3202的主控器設備3200之硬體實施方案之簡化實例的圖式。藉由主控器設備3200執行的操作之實例包括上文關於圖30及圖31之流程圖所描述的操作。處理電路通常具有可包括微處理器、微控制器、數位信號處理器、定序器及狀態機中之一或多者的處理器3216。處理電路3202可實施有匯流排架構(總體上由匯流排3220表示)。匯流排3220可取決於處理電路3202之特定應用及整體設計約束而包括任何數目個互連匯流排及橋接器。匯流排3220將包括由處理器3216表示之一或多個處理器及/或硬體模組、模組或電路3204、3206、3208、3210、可組態以支援經由連接器或導線3214之通信的匯流排介面電路3212及電腦可讀儲存媒體3218之各種電路鏈接在一起。匯流排3220亦可將此項技術中熟知且因此將不作任何進一步描述的諸如時序源、周邊裝置、電壓調節器及功率管理電路之各種其他電路鏈接在一起。 32 is a diagram illustrating a simplified example of a hardware implementation of a master device 3200 employing processing circuitry 3202. Examples of operations performed by host device 3200 include the operations described above with respect to the flowcharts of FIGS. 30 and 31 . The processing circuitry typically has a processor 3216 which may include one or more of a microprocessor, microcontroller, digital signal processor, sequencer, and state machine. Processing circuitry 3202 may be implemented with a bus architecture (represented generally by bus 3220). Bus 3220 may include any number of interconnecting busses and bridges depending on the specific application and overall design constraints of processing circuit 3202. Bus 3220 will include one or more processors, represented by processor 3216, and/or hardware modules, modules or circuits 3204, 3206, 3208, 3210 that may be configured to support communications via connectors or wires 3214 The various circuits of the bus interface circuit 3212 and the computer-readable storage medium 3218 are linked together. Bus 3220 may also link together various other circuits such as timing sources, peripherals, voltage regulators, and power management circuits that are well known in the art and therefore will not be described any further.

處理器3216負責一般處理,包括執行儲存於電腦可讀儲存媒體3218上之軟體/指令。軟體/指令在由處理器3216執行時使處理電路3202執行前文針對任一特定設備描述之各種功能。電腦可讀儲存媒體亦可用於儲存藉由處理器3216在執行軟體時操縱的資料,該資料包括用經由連接器或導線3214傳輸之符號進行解碼的資料,該等連接器或導線可經組態為資料通道及時脈通道。處理電路3202進一步包括模組/電路3204、3206、3208及3210中之至少一者。模組/電路3204、3206、3208及3210可為在處理器3216中執行之軟體模組,駐存/儲存於電腦可讀儲存媒體3218中,耦接至處理器3216之一或多個硬體模組,或 其某一組合。模組/電路3204、3206、3208及/或3210可包括微控制器指令、狀態機組態參數或其某一組合。 Processor 3216 is responsible for general processing, including executing software/instructions stored on computer-readable storage media 3218. The software/instructions, when executed by processor 3216, cause processing circuitry 3202 to perform the various functions described above for any particular device. Computer-readable storage media may also be used to store data manipulated by processor 3216 when executing software, including data decoded using symbols transmitted through connectors or wires 3214, which connectors or wires may be configured It is a data channel and a timing channel. Processing circuitry 3202 further includes at least one of modules/circuits 3204, 3206, 3208, and 3210. Modules/circuits 3204, 3206, 3208, and 3210 may be software modules executing in processor 3216, resident/stored in computer-readable storage media 3218, and coupled to one or more hardware components of processor 3216 module, or a certain combination thereof. Modules/circuits 3204, 3206, 3208, and/or 3210 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

在一個組態中,用於通信之設備3200包括一請求接收模組/電路3204,其經組態以自第一受控器裝置接收經由匯流排發送遮罩寫入資料報至第二受控器裝置的請求,其中該遮罩寫入資料報經定址至第二受控器裝置之無線電頻率前端(RFFE)暫存器,該遮罩寫入資料報包括識別待在RFFE暫存器中改變的至少一個位元之遮罩欄位及提供待在RFFE暫存器中改變的至少一個位元之值的資料欄位。設備3200進一步包括資料報授權模組/電路3206,其經組態以偵測第一受控器裝置是否經授權以發送遮罩寫入資料報至第二受控器裝置。設備3200亦包括資料報發送准許模組/電路3208,其經組態以若偵測到授權,則准許第一受控器裝置發送遮罩寫入資料報至第二受控器裝置。設備3200進一步包括資料報發送防止模組/電路3210,其經組態以若未偵測到授權,則防止第一受控器裝置發送遮罩寫入資料報至第二受控器裝置。用於在匯流排上將資料自第一受控器裝置傳達至第二受控器裝置的例示性方法及裝置 In one configuration, the apparatus for communicating 3200 includes a request receive module/circuitry 3204 configured to receive a mask write data packet from a first slave device over the bus to a second slave device. a request from a slave device, wherein the mask write datagram is addressed to a radio frequency front-end (RFFE) register of the second slave device, the mask write datagram including identifying changes to be made in the RFFE register A mask field of at least one bit and a data field providing the value of at least one bit to be changed in the RFFE register. Apparatus 3200 further includes a datagram authorization module/circuitry 3206 configured to detect whether the first slave device is authorized to send the mask write datagram to the second slave device. Apparatus 3200 also includes a datagram transmission permission module/circuitry 3208 configured to permit the first slave device to send a mask write datagram to the second slave device if authorization is detected. Apparatus 3200 further includes a datagram transmission prevention module/circuitry 3210 configured to prevent a first slave device from sending a mask write datagram to a second slave device if authorization is not detected. Exemplary methods and apparatus for communicating data from a first slave device to a second slave device over a bus

圖33為用於在匯流排上在受控器裝置之間傳達資料之方法的流程圖3300。方法可在第一受控器裝置處執行。 Figure 33 is a flow diagram 3300 of a method for communicating data between slave devices over a bus. The method may be performed at the first control device.

第一受控器裝置可產生待經由匯流排發送至第二受控器裝置的遮罩寫入資料報3302。遮罩寫入資料報可經定址至第二受控器裝置之無線電頻率前端(RFFE)暫存器。該遮罩寫入資料報可包括識別待在該(RFFE)暫存器中改變之至少一個位元的一遮罩欄位及提供待在該RFFE暫存器中改變的該至少一個位元之一值的一資料欄位。遮罩欄位可進一步識別第二受控器裝置之RFFE暫存器中保持不變的剩餘位元集合。在一態樣中,遮罩欄位為識別待在第二受控器裝置之RFFE暫存器中改變之位元位置的位元索引欄位且資料欄位為提供在位元索引欄位中識別的位元位置之位元值的位元值欄位。 The first slave device may generate a mask write datagram 3302 to be sent to the second slave device via the bus. The mask write datagram may be addressed to the radio frequency front end (RFFE) register of the second slave device. The mask write datagram may include a mask field identifying at least one bit to be changed in the (RFFE) register and providing the at least one bit to be changed in the RFFE register. A data field of one value. The mask field further identifies the remaining set of bits that remain unchanged in the RFFE register of the second slave device. In one aspect, the mask field is a bit index field that identifies a bit location to be changed in the RFFE register of the second slave device and the data field is provided in the bit index field The bit value field of the bit value of the identified bit position.

第一受控器裝置可向主控器裝置請求發送遮罩寫入資料報至第二受控器裝置的權限3304。第一受控器裝置接著可偵測發送遮罩寫入資料報之權限是否藉由主控器裝置授予3306。 The first slave device may request permission 3304 from the master device to send a mask write data packet to the second slave device. The first slave device may then detect whether permission to send the mask write datagram is granted 3306 by the master device.

舉例而言,第一受控器裝置可在第一受控器裝置自主控器裝置接收第一受控器裝置經准許以發送遮罩寫入資料報的通知時偵測到權限被授予。在另一實例中,若在臨限時間量已經過之後第一受控器裝置未接收到對於請求之回應,則第一受控器裝置可偵測到權限被授予。因此,若由主控器裝置准許,則第一受控器裝置可發送遮罩寫入資料報至第二受控器裝置3308。 For example, the first slave device may detect that permission is granted when the first slave device receives a notification from the master device that the first slave device is permitted to send a mask write datagram. In another example, the first control device may detect that permission is granted if the first control device does not receive a response to the request after a threshold amount of time has elapsed. Therefore, if permitted by the master device, the first slave device may send a mask write data report to the second slave device 3308.

在另一實例中,第一受控器裝置可在第一受控器裝置自主控器裝置接收第一受控器裝置未經准許以發送遮罩寫入資料報的通知時偵測到權限未被授予。在又一實例中,第一受控器裝置可藉由觀測藉由主控器裝置在匯流排上發出以阻止發送遮罩寫入資料報的匯流排停放循環而偵測到權限未被授予。因此,若未由主控器裝置准許,則第一受控器裝置可制止發送遮罩寫入資料報至第二受控器裝置3310。 In another example, the first slave device may detect the permission failure when the first slave device receives a notification from the master device that the first slave device is not permitted to send the mask write datagram. be awarded. In yet another example, the first slave device may detect that permission is not granted by observing a bus park cycle issued by the master device on the bus to prevent the sending of a mask write datagram. Therefore, the first slave device may refrain from sending the mask write data report to the second slave device 3310 if not permitted by the master device.

圖34為說明採用處理電路3402的受控器設備3400之硬體實施方案之簡化實例的圖式。藉由受控器設備3400執行的操作之實例包括上文關於圖30及圖33之流程圖所描述的操作。處理電路通常具有可包括微處理器、微控制器、數位信號處理器、定序器及狀態機中之一或多者的處理器3416。處理電路3402可實施有匯流排架構(總體上由匯流排3420表示)。匯流排3420可取決於處理電路3402之特定應用及整體設計約束而包括任何數目個互連匯流排及橋接器。匯流排3420將包括由處理器3416表示之一或多個處理器及/或硬體模組、模組或電路3404、3406、3408、3410、可組態以支援經由連接器或導線3414之通信的匯流排介面電路3412及電腦可讀儲存媒體3418之各種電路鏈接在一起。匯流 排3420亦可將此項技術中熟知且因此將不作任何進一步描述的諸如時序源、周邊裝置、電壓調節器及功率管理電路之各種其他電路鏈接在一起。 34 is a diagram illustrating a simplified example of a hardware implementation of a slave device 3400 employing processing circuitry 3402. Examples of operations performed by slave device 3400 include the operations described above with respect to the flowcharts of Figures 30 and 33. The processing circuitry typically has a processor 3416 which may include one or more of a microprocessor, microcontroller, digital signal processor, sequencer, and state machine. Processing circuitry 3402 may be implemented with a bus architecture (represented generally by bus 3420). Bus 3420 may include any number of interconnecting busses and bridges depending on the specific application and overall design constraints of processing circuit 3402. Bus 3420 will include one or more processors, represented by processor 3416, and/or hardware modules, modules or circuits 3404, 3406, 3408, 3410 that may be configured to support communications via connectors or wires 3414 Various circuits of the bus interface circuit 3412 and the computer-readable storage medium 3418 are linked together. Confluence Bank 3420 may also link together various other circuits such as timing sources, peripherals, voltage regulators, and power management circuits that are well known in the art and therefore will not be described any further.

處理器3416負責一般處理,包括執行儲存於電腦可讀儲存媒體3418上之軟體/指令。軟體/指令在由處理器3416執行時使得處理電路3402執行上文針對任何特定設備描述的各種功能。電腦可讀儲存媒體亦可用於儲存藉由處理器3416在執行軟體時操縱的資料,該資料包括用經由連接器或導線3414傳輸之符號進行解碼的資料,該等連接器或導線可經組態為資料通道及時脈通道。處理電路3402進一步包括模組/電路3404、3406、3408及3410中之至少一者。模組/電路3404、3406、3408及3410可為在處理器3416中執行之軟體模組,駐存/儲存於電腦可讀儲存媒體3418中,耦接至處理器3416之一或多個硬體模組,或其某一組合。模組/電路3404、3406、3408及/或3410可包括微控制器指令、狀態機組態參數或其某一組合。 Processor 3416 is responsible for general processing, including executing software/instructions stored on computer-readable storage media 3418. The software/instructions, when executed by processor 3416, cause processing circuitry 3402 to perform the various functions described above for any particular device. Computer-readable storage media may also be used to store data manipulated by processor 3416 when executing software, including data decoded using symbols transmitted through connectors or wires 3414, which connectors or wires may be configured It is a data channel and a timing channel. Processing circuitry 3402 further includes at least one of modules/circuits 3404, 3406, 3408, and 3410. Modules/circuits 3404, 3406, 3408, and 3410 may be software modules executing in processor 3416, resident/stored in computer-readable storage media 3418, and coupled to one or more hardware components of processor 3416 module, or some combination thereof. Modules/circuits 3404, 3406, 3408, and/or 3410 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

在一個組態中,用於通信之設備3400包括一資料報產生模組/電路3404,其經組態以在第一受控器裝置處產生待經由匯流排發送至第二受控器裝置的遮罩寫入資料報,其中該遮罩寫入資料報經定址至第二受控器裝置之無線電頻率前端(RFFE)暫存器,該遮罩寫入資料報包括識別待在(RFFE)暫存器中改變的至少一個位元之遮罩欄位及提供待在RFFE暫存器中改變的至少一個位元之值的資料欄位。設備3400進一步包括一權限請求模組/電路3406,其經組態以向主控器裝置請求發送遮罩寫入資料報至第二受控器裝置的權限。設備3400亦包括一權限偵測模組/電路3408,其經組態以偵測第一受控器裝置是否經准許以發送遮罩寫入資料報至第二受控器裝置。設備3400進一步包括一資料報發送模組/電路3410,其經組態以若由主控器裝置准許,則發送遮罩寫入資料報至第二受控器裝置且若未由主控器裝置准許,則制止發送遮罩寫入資料報至第二受控器裝置。 In one configuration, apparatus for communications 3400 includes a datagram generation module/circuitry 3404 configured to generate a datagram at a first slave device to be sent to a second slave device via the bus. A mask write datagram, wherein the mask write datagram is addressed to a radio frequency front end (RFFE) register of the second slave device, the mask write datagram includes an identification stay (RFFE) temporary A mask field for at least one bit changed in the register and a data field providing the value of at least one bit to be changed in the RFFE register. Apparatus 3400 further includes a permission request module/circuitry 3406 configured to request permission from the master device to send the mask write data report to the second slave device. Apparatus 3400 also includes an permission detection module/circuitry 3408 configured to detect whether the first slave device is authorized to send mask write data reports to the second slave device. Apparatus 3400 further includes a datagram sending module/circuitry 3410 configured to send a mask write datagram to the second slave device if permitted by the master device and if not enabled by the master device. If allowed, it is prohibited to send mask write data reports to the second slave device.

應理解,所揭示程序中之步驟的特定次序或層次為例示性方法之說明。處理程序中之步驟的特定次序或階層可基於設計偏好而重新佈置。隨附方法請求項以樣本次序呈現各種步驟之元件,且並不意謂受限於所呈現之特定次序或層次。 It is understood that the specific order or hierarchy of steps in the disclosed procedures is an illustration of an illustrative approach. The specific order or hierarchy of steps in a process can be rearranged based on design preferences. The accompanying method requests present elements of the various steps in a sample order and are not meant to be limited to the specific order or hierarchy presented.

提供先前描述以使任何熟習此項技術者能夠實踐本文中所描述之各種態樣。對此等態樣之各種修改對於熟習此項技術者而言將為顯而易見的,且本文中定義之一般原理可應用於其他態樣。因此,申請專利範圍不意欲限於本文中所展示的態樣,而是將被賦予與語言申請專利範圍一致的完整範圍,其中以單數形式參考一元件不意欲意謂「一個且僅有一個」,除非明確地如此陳述,而是表示「一或多個」。除非另外特定地陳述,否則術語「一些」指代一或多個。一般熟習此項技術者已知或稍後將知曉的貫穿本發明所描述之各種態樣的元件之所有結構及功能等效物以引用的方式明確地併入本文中,且意欲由申請專利範圍涵蓋。此外,本文中所揭示之任何內容均不意欲專用於公眾,無論申請專利範圍中是否明確敍述此揭示內容。沒有申請專利範圍元件將被解釋為手段加功能,除非元件係使用片語「用於……之構件」來明確地敍述。 The preceding description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to such aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Accordingly, the patentable scope is not intended to be limited to the aspects shown herein, but is to be given the full scope consistent with the language claimed, wherein reference to an element in the singular is not intended to mean "one and only one," Unless expressly stated so, it means "one or more". Unless specifically stated otherwise, the term "some" refers to one or more. All structural and functional equivalents to the elements in the various aspects described throughout this invention that are known to or hereafter come to be known to those skilled in the art are expressly incorporated by reference herein and are intended to be patentable by the claims. Covered. Furthermore, nothing disclosed herein is intended to be exclusive to the public, whether or not such disclosure is expressly recited in the patent claims. Unclaimed components will be construed as means plus function unless the component is explicitly recited using the phrase "means for".

1300:實例封包結構 1300:Instance packet structure

1302:擴展之暫存器長寫入命令 1302: Extended register long write command

1304:酬載 1304: Payload

Claims (28)

一種在一主控器裝置處執行之用於促進在一匯流排上的資料通信的方法,其包含:自一第一受控器裝置接收經由該匯流排發送一遮罩寫入資料報至一第二受控器裝置的一請求,其中該遮罩寫入資料報經定址至該第二受控器裝置之一無線電頻率前端(RFFE)暫存器,該遮罩寫入資料報包括識別待在該RFFE暫存器中改變的至少一個位元的一遮罩欄位及提供待在該RFFE暫存器中改變的該至少一個位元之一值的一資料欄位;偵測該第一受控器裝置是否經授權以發送該遮罩寫入資料報至該第二受控器裝置;及若偵測到授權,則准許該第一受控器裝置發送該遮罩寫入資料報至該第二受控器裝置。 A method executed at a master device for facilitating data communication on a bus includes receiving from a first slave device a mask write data packet sent over the bus to a A request from a second slave device, wherein the mask write datagram is addressed to a radio frequency front end (RFFE) register of the second slave device, the mask write datagram including the identification to be a mask field of at least one bit changed in the RFFE register and a data field providing a value of the at least one bit to be changed in the RFFE register; detecting the first Whether the slave device is authorized to send the mask write data report to the second slave device; and if authorization is detected, allowing the first slave device to send the mask write data report to the second controlled device. 如請求項1之方法,其中該准許包括將該第一受控器裝置經授權以發送該遮罩寫入資料報通知該第一受控器裝置。 The method of claim 1, wherein the granting includes notifying the first slave device that the first slave device is authorized to send the mask write datagram. 如請求項1之方法,其進一步包括:若未偵測到授權,則防止該第一受控器裝置發送該遮罩寫入資料報至該第二受控器裝置。 The method of claim 1, further comprising: if no authorization is detected, preventing the first slave device from sending the mask write data report to the second slave device. 如請求項3之方法,其中該防止包括將該第一受控器裝置未經授權以發送該遮罩寫入資料報通知該第一受控器裝置。 The method of claim 3, wherein the preventing includes notifying the first slave device that the first slave device is unauthorized to send the mask write data packet. 如請求項3之方法,其中該防止包括在該匯流排上發出一匯流排停放循環以阻止該遮罩寫入資料報之該發送。 The method of claim 3, wherein the preventing includes issuing a bus park cycle on the bus to prevent the sending of the mask write datagram. 如請求項1之方法,其中該遮罩欄位進一步識別待在該第二受控器裝置之該RFFE暫存器中保持不變的一剩餘位元集合。 The method of claim 1, wherein the mask field further identifies a remaining set of bits to remain unchanged in the RFFE register of the second slave device. 如請求項1之方法,其中:該遮罩欄位為識別待在該第二受控器裝置之該RFFE暫存器中改變的一位元位置之一位元索引欄位;且該資料欄位為提供用於在該位元索引欄位中識別的該位元位置之一位元值的一位元值欄位。 The method of claim 1, wherein: the mask field is a bit index field identifying a bit position to be changed in the RFFE register of the second slave device; and the data field Bits is a bit value field that provides the bit value for one of the bit positions identified in the bit index field. 一種用於促進在一匯流排上之資料通信的主控器裝置,其包含:一匯流排介面;及一處理電路,其經組態以:經由該匯流排介面自一第一受控器裝置接收經由該匯流排發送一遮罩寫入資料報至一第二受控器裝置的一請求,其中該遮罩寫入資料報經定址至該第二受控器裝置之一無線電頻率前端(RFFE)暫存器,該遮罩寫入資料報包括識別待在該RFFE暫存器中改變的至少一個位元的一遮罩欄位及提供待在該RFFE暫存器中改變的該至少一個位元之一值的一資料欄位,偵測該第一受控器裝置是否經授權以發送該遮罩寫入資料報至該第二受控器裝置,及 若偵測到授權,則准許該第一受控器裝置發送該遮罩寫入資料報至該第二受控器裝置。 A master device for facilitating data communication on a bus, including: a bus interface; and a processing circuit configured to: from a first slave device via the bus interface Receive a request to send a mask write datagram to a second slave device via the bus, wherein the mask write datagram is addressed to a radio frequency front end (RFFE) of the second slave device ) register, the mask write datagram includes a mask field identifying at least one bit to be changed in the RFFE register and providing the at least one bit to be changed in the RFFE register a data field of one value that detects whether the first slave device is authorized to send the mask write data report to the second slave device, and If authorization is detected, the first slave device is allowed to send the mask write data report to the second slave device. 如請求項8之主控器裝置,其中經組態以准許之該處理電路經組態以將該第一受控器裝置經授權以發送該遮罩寫入資料報通知該第一受控器裝置。 The master device of claim 8, wherein the processing circuit configured to allow is configured to notify the first slave device that the first slave device is authorized to send the mask write data packet device. 如請求項8之主控器裝置,其中該處理電路進一步經組態以:若未偵測到授權,則防止該第一受控器裝置發送該遮罩寫入資料報至該第二受控器裝置。 The master controller device of claim 8, wherein the processing circuit is further configured to prevent the first slave device from sending the mask write data report to the second slave device if authorization is not detected. device. 如請求項10之主控器裝置,其中經組態以防止之該處理電路經組態以將該第一受控器裝置未經授權以發送該遮罩寫入資料報通知該第一受控器裝置。 The master device of claim 10, wherein the processing circuit configured to prevent is configured to notify the first slave device of unauthorized transmission of the mask write data packet. device. 如請求項10之主控器裝置,其中經組態以防止之該處理電路經組態以在該匯流排上發出一匯流排停放循環以阻止該遮罩寫入資料報之該發送。 The master device of claim 10, wherein the processing circuit configured to prevent is configured to issue a bus park cycle on the bus to prevent the sending of the mask write datagram. 如請求項8之主控器裝置,其中該遮罩欄位進一步識別待在該第二受控器裝置之該RFFE暫存器中保持不變的一剩餘位元集合。 The master device of claim 8, wherein the mask field further identifies a remaining set of bits to remain unchanged in the RFFE register of the second slave device. 如請求項8之主控器裝置,其中:該遮罩欄位為識別待在該第二受控器裝置之該RFFE暫存器中改變的一 位元位置之一位元索引欄位;且該資料欄位為提供用於在該位元索引欄位中識別的該位元位置之一位元值的一位元值欄位。 The master device of claim 8, wherein: the mask field identifies a parameter to be changed in the RFFE register of the second slave device. a bit index field for a bit position; and the data field is a bit value field that provides a bit value for the bit position identified in the bit index field. 一種在一第一受控器裝置之處執行之用於經由一匯流排傳達資料至一第二受控器裝置的方法,其包含:在該第一受控器裝置之處產生待經由該匯流排發送至該第二受控器裝置之一遮罩寫入資料報,其中該遮罩寫入資料報經定址至該第二受控器裝置之一無線電頻率前端(RFFE)暫存器,該遮罩寫入資料報包括識別待在該RFFE暫存器中改變的至少一個位元的一遮罩欄位及提供待在該RFFE暫存器中改變的該至少一個位元之一值的一資料欄位;向一主控器裝置請求發送該遮罩寫入資料報至該第二受控器裝置的權限;偵測該權限是否被授予;及若由該主控器裝置准許,則發送該遮罩寫入資料報至該第二受控器裝置。 A method performed at a first slave device for communicating data to a second slave device via a bus, comprising: generating data at the first slave device to be transmitted via the bus. sending a mask write datagram to the second slave device, wherein the mask write datagram is addressed to a radio frequency front end (RFFE) register of the second slave device, the The mask write datagram includes a mask field identifying at least one bit to be changed in the RFFE register and a mask field providing a value of the at least one bit to be changed in the RFFE register. data field; requests permission from a master device to send the mask write data report to the second slave device; detects whether the permission is granted; and if granted by the master device, sends The mask write data is reported to the second slave device. 如請求項15之方法,其中該偵測包括自該主控器裝置接收該第一受控器裝置經准許以發送該遮罩寫入資料報的一通知。 The method of claim 15, wherein the detecting includes receiving a notification from the master device that the first slave device is permitted to send the mask write datagram. 如請求項15之方法,其進一步包括若未由該主控器裝置准許,則制止發送該遮罩寫入資料報至該第二受控器裝置。 The method of claim 15, further comprising inhibiting sending the mask write data report to the second slave device if not permitted by the master device. 如請求項17之方法,其中該偵測包括自該主控器裝置接收該第一受控器裝置未經准許以發送該遮罩寫入資料報的一通知。 The method of claim 17, wherein the detecting includes receiving a notification from the master device that the first slave device is not authorized to send the mask write datagram. 如請求項17之方法,其中該偵測包括觀測藉由該主控器裝置在該匯流排上發出以阻止該遮罩寫入資料報之該發送的一匯流排停放循環。 The method of claim 17, wherein the detecting includes observing a bus park cycle issued by the master device on the bus to prevent the transmission of the mask write datagram. 如請求項15之方法,其中該遮罩欄位進一步識別待在該第二受控器裝置之該RFFE暫存器中保持不變的一剩餘位元集合。 The method of claim 15, wherein the mask field further identifies a remaining set of bits to remain unchanged in the RFFE register of the second slave device. 如請求項15之方法,其中:該遮罩欄位為識別待在該第二受控器裝置之該RFFE暫存器中改變的一位元位置之一位元索引欄位;且該資料欄位為提供用於在該位元索引欄位中識別的該位元位置之一位元值的一位元值欄位。 The method of claim 15, wherein: the mask field is a bit index field identifying a bit position to be changed in the RFFE register of the second slave device; and the data field Bits is a bit value field that provides the bit value for one of the bit positions identified in the bit index field. 一種用於經由一匯流排傳達資料至一第二受控器裝置的受控器裝置,其包含:一匯流排介面;及一處理電路,其經組態以:在該受控器裝置之處產生待經由該匯流排發送至該第二受控器裝置之一遮罩寫入資料報,其中該遮罩寫入資料報經定址至該第二受控器裝置之一無線電頻率前端(RFFE)暫存器,該遮罩寫入資料報包括識別待在該RFFE暫存器中改變的至少一個位元的一遮罩欄位及提供待在該RFFE暫存器中改變的該至少一個位元之一值的一資料欄位,向一主控器裝置請求發送該遮罩寫入資料報至該第二受控器裝置的權限, 偵測該權限是否被授予,及若由該主控器裝置准許,則經由該匯流排介面發送該遮罩寫入資料報至該第二受控器裝置。 A slave device for communicating data to a second slave device via a bus, including: a bus interface; and a processing circuit configured to: at the slave device Generating a mask write datagram to be sent to the second slave device via the bus, wherein the mask write datagram is addressed to a radio frequency front end (RFFE) of the second slave device register, the mask write datagram includes a mask field identifying at least one bit to be changed in the RFFE register and providing the at least one bit to be changed in the RFFE register a data field of value requesting permission from a master device to send the mask write data report to the second slave device, Detect whether the permission is granted, and if granted by the master device, send the mask write data report to the second slave device via the bus interface. 如請求項22之受控器裝置,其中該處理電路進一步經組態以自該主控器裝置接收該受控器裝置經准許以發送該遮罩寫入資料報的一通知。 The slave device of claim 22, wherein the processing circuit is further configured to receive a notification from the master device that the slave device is permitted to send the mask write datagram. 如請求項22之受控器裝置,其中該處理電路進一步經組態以若未由該主控器裝置准許,則制止發送該遮罩寫入資料報至該第二受控器裝置。 The slave device of claim 22, wherein the processing circuit is further configured to inhibit sending the mask write data report to the second slave device if not permitted by the master device. 如請求項24之受控器裝置,其中該處理電路進一步經組態以自該主控器裝置接收該受控器裝置未經准許以發送該遮罩寫入資料報的一通知。 The slave device of claim 24, wherein the processing circuit is further configured to receive a notification from the master device that the slave device is not authorized to send the mask write datagram. 如請求項24之受控器裝置,其中該處理電路進一步經組態以觀測藉由該主控器裝置在該匯流排上發出以阻止該遮罩寫入資料報之該發送的一匯流排停放循環。 The slave device of claim 24, wherein the processing circuit is further configured to observe a bus park issued by the master device on the bus to prevent the transmission of the mask write datagram. cycle. 如請求項22之受控器裝置,其中該遮罩欄位進一步識別待在該第二受控器裝置之該RFFE暫存器中保持不變的一剩餘位元集合。 The slave device of claim 22, wherein the mask field further identifies a remaining set of bits to remain unchanged in the RFFE register of the second slave device. 如請求項22之受控器裝置,其中:該遮罩欄位為識別待在該第二受控器裝置之該RFFE暫存器中改變的一 位元位置之一位元索引欄位;且該資料欄位為提供用於在該位元索引欄位中識別的該位元位置之一位元值的一位元值欄位。 The slave device of claim 22, wherein: the mask field identifies a parameter to be changed in the RFFE register of the second slave device. a bit index field for a bit position; and the data field is a bit value field that provides a bit value for the bit position identified in the bit index field.
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