TWI827137B - Memory device and data search method for in-memory search - Google Patents

Memory device and data search method for in-memory search Download PDF

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TWI827137B
TWI827137B TW111126271A TW111126271A TWI827137B TW I827137 B TWI827137 B TW I827137B TW 111126271 A TW111126271 A TW 111126271A TW 111126271 A TW111126271 A TW 111126271A TW I827137 B TWI827137 B TW I827137B
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voltage
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bias
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TW202403760A (en
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曾柏皓
栢添賜
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旺宏電子股份有限公司
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Abstract

A memory device for in-memory search, the memory device includes a plurality of memory cells, and each of the memory cells stores a stored data and receives a search data, including a first transistor and a second transistor. The first transistor has a first threshold voltage and receives a first gate bias. The second transistor is connected to the first transistor, and the second transistor has a second threshold voltage and receives a second gate bias. The stored data is encoded according to the first threshold voltage and the second threshold voltage, and the search data is encoded according to the first gate bias and the second gate bias. There is a mismatch distance between the stored data and the search data. An output current generated by each of the memory cells is related to the mismatch distance.

Description

用於記憶體內搜尋的記憶體裝置及資料搜尋方法 Memory device and data search method for in-memory search

本揭示關於一種半導體裝置及資料處理方法,特別有關於一種用於記憶體內搜尋(in-memory search,IMS)的記憶體裝置及資料搜尋方法。 The present disclosure relates to a semiconductor device and a data processing method, and in particular to a memory device and a data search method for in-memory search (IMS).

因應於人工智慧(AI)及大數據(big data)的需求,在各種形式的演算法中常需要執行大量的資料處理,包括資料搜尋與資料比對。隨著半導體技術的成熟發展,可在記憶體裝置儲存大量的儲存資料,根據此些儲存資料在記憶體裝置的內部執行資料處理。例如,執行記憶體內搜尋(in-memory search,IMS)與記憶體內運算(in-memory computation,IMC)。 In response to the needs of artificial intelligence (AI) and big data, various forms of algorithms often require a large amount of data processing, including data search and data comparison. With the mature development of semiconductor technology, a large amount of storage data can be stored in a memory device, and data processing is performed inside the memory device based on the storage data. For example, perform in-memory search (IMS) and in-memory computation (IMC).

記憶體內搜尋的運算中,可使用精確匹配(exact matching)的機制,當記憶體裝置儲存的儲存資料完全匹配於搜尋資料時,儲存上述儲存資料的記憶胞對應的位元線始產生輸出電流。即,當儲存資料不匹配於搜尋資料時,無論「不匹配程度」,對應的位元線不產生輸出電流。然而,精確匹配機制無法進一步判斷儲存資料與搜尋資料之間的「不匹配程度」,將嚴重限制匹配的彈性。 In the search operation in the memory, an exact matching mechanism can be used. When the storage data stored in the memory device completely matches the search data, the bit line corresponding to the memory cell storing the storage data starts to generate an output current. That is, when the stored data does not match the search data, no matter the "mismatch degree", the corresponding bit line does not generate an output current. However, the exact matching mechanism cannot further determine the "degree of mismatch" between stored data and search data, which will seriously limit the flexibility of matching.

有鑑於精確匹配機制的上述缺陷,需提出一種改良的資料搜尋方法及對應的記憶體裝置之架構,可實施近似搜尋(approximate searching)以達到近似匹配(approximate matching)的技術功效。 In view of the above-mentioned shortcomings of the exact matching mechanism, it is necessary to propose an improved data search method and a corresponding memory device architecture that can implement approximate searching to achieve the technical effect of approximate matching.

根據本揭示之一方面,提供一種用於記憶體內搜尋的記憶體裝置,包括複數個記憶胞,各記憶胞儲存儲存資料並接收搜尋資料,各記憶胞包括第一電晶體與第二電晶體。第一電晶體具有第一臨界電壓並接收第一閘極偏壓。第二電晶體連接於第一電晶體,第二電晶體具有第二臨界電壓並接收第二閘極偏壓。儲存資料係根據第一臨界電壓與第二臨界電壓編碼而成,搜尋資料係根據第一閘極偏壓與第二閘極偏壓編碼而成。儲存資料與搜尋資料之間具有不匹配距離,各記憶胞根產生的輸出電流相關於不匹配距離。 According to one aspect of the present disclosure, a memory device for in-memory searching is provided, including a plurality of memory cells. Each memory cell stores storage data and receives search data. Each memory cell includes a first transistor and a second transistor. The first transistor has a first threshold voltage and receives a first gate bias voltage. The second transistor is connected to the first transistor, has a second threshold voltage and receives a second gate bias voltage. The stored data is encoded according to the first threshold voltage and the second threshold voltage, and the search data is encoded according to the first gate bias voltage and the second gate bias voltage. There is a mismatch distance between the stored data and the search data, and the output current generated by each memory cell root is related to the mismatch distance.

根據本揭示之另一方面,提供一種用於記憶體的資料搜尋方法,記憶體包括複數個記憶胞,各記憶胞包括第一電晶體與第二電晶體,資料搜尋方法包括以下步驟。根據第一電晶體的第一臨界電壓與第二電晶體的第二臨界電壓編碼儲存資料。根據第一閘極偏壓與第二閘極偏壓編碼搜尋資料,儲存資料與搜尋資料之間具不匹配距離。其中各記憶胞產生的輸出電流相關於不匹配距離。 According to another aspect of the disclosure, a data search method for a memory is provided. The memory includes a plurality of memory cells, and each memory cell includes a first transistor and a second transistor. The data search method includes the following steps. Data is encoded and stored according to the first threshold voltage of the first transistor and the second threshold voltage of the second transistor. The search data is encoded according to the first gate bias voltage and the second gate bias voltage, and there is a mismatch distance between the stored data and the search data. The output current generated by each memory cell is related to the mismatch distance.

透過閱讀以下圖式、詳細說明以及申請專利範圍,可見本揭示之其他方面以及優點。 By reading the following drawings, detailed descriptions and patent claims, other aspects and advantages of the present disclosure can be seen.

VH1:第一偏壓值 VH1: first bias value

VH2:第二偏壓值 VH2: second bias value

VH3:第三偏壓值 VH3: third bias value

VH4:第四偏壓值 VH4: The fourth bias value

VH5:第五偏壓值 VH5: fifth bias value

VH6:第六偏壓值 VH6: The sixth bias value

VH7:第七偏壓值 VH7: seventh bias value

VH8:第八偏壓值 VH8: The eighth bias value

VH9:第九偏壓值 VH9: Ninth bias value

VH10:第十偏壓值 VH10: tenth bias value

VH11:第十一偏壓值 VH11: Eleventh bias value

VH12:第十二偏壓值 VH12: Twelfth bias value

VH13:第十三偏壓值 VH13: Thirteenth bias value

VH14:第十四偏壓值 VH14: Fourteenth bias value

VH15:第十五偏壓值 VH15: Fifteenth bias value

VH16:第十六偏壓值 VH16: sixteenth bias value

VH(n):第n偏壓值 VH(n): nth bias value

VT1:第一電壓分布 VT1: first voltage distribution

VT2:第二電壓分布 VT2: Second voltage distribution

VT3:第三電壓分布 VT3: The third voltage distribution

VT4:第四電壓分布 VT4: The fourth voltage distribution

VT5:第五電壓分布 VT5: fifth voltage distribution

VT6:第六電壓分布 VT6: The sixth voltage distribution

VT7:第七電壓分布 VT7: seventh voltage distribution

VT8:第八電壓分布 VT8: The eighth voltage distribution

VT9:第九電壓分布 VT9: Ninth voltage distribution

VT10:第十電壓分布 VT10: Tenth voltage distribution

VT11:第十一電壓分布 VT11: Eleventh voltage distribution

VT12:第十二電壓分布 VT12: Twelfth voltage distribution

VT13:第十三電壓分布 VT13: Thirteenth voltage distribution

VT14:第十四電壓分布 VT14: Fourteenth voltage distribution

VT15:第十五電壓分布 VT15: Fifteenth voltage distribution

VT16:第十六電壓分布 VT16: Sixteenth voltage distribution

VT(n):第n電壓分布 VT(n): nth voltage distribution

1L:1倍的級距 1L: 1 times the grade distance

2L:2倍的級距 2L: 2 times the grade span

3L:3倍的級距 3L: 3 times the grade span

4L:4倍的級距 4L: 4 times the grade pitch

5L:5倍的級距 5L: 5 times the step distance

6L:6倍的級距 6L: 6 times the grade pitch

100,100-1,100-2,100-M:記憶胞 100,100-1,100-2,100-M: memory cells

1000:記憶體裝置 1000:Memory device

400:位元線驅動電路 400: Bit line driver circuit

500:字元線驅動電路 500: Character line driver circuit

600-1,600-2,600-N:感應放大器 600-1,600-2,600-N: Sense amplifier

M1,M2:電晶體 M1, M2: transistor

WL1(1),WL2(1),WLM(1):第一字元線 WL1(1),WL2(1),WLM(1): first character line

WL1(2),WL2(2),WLM(2):第二字元線 WL1(2),WL2(2),WLM(2): second character line

BL1~BL8,BLN:位元線 BL1~BL8, BLN: bit lines

WL1~WL24:第1~24組字元線 WL1~WL24: The 1st~24th group of character lines

Is1~Is8,IsN:輸出電流 Is1~Is8,IsN: output current

Vg1:第一閘極偏壓 Vg1: first gate bias

Vg2:第二閘極偏壓 Vg2: second gate bias

g1:第一閘極 g1: first gate

g2:第二閘極 g2: second gate

d1:第一汲極 d1: first drain

d2:第二汲極 d2: The second drain

s1:第一源極 s1: first source

s2:第二源極 s2: second source

SW:搜尋資料 SW: Search data

DAT:儲存資料 DAT: store data

WCD:萬用符 WCD: wildcard

DNC:隨意項 DNC: optional

第1圖繪示本揭示一實施例的記憶胞的示意圖。 Figure 1 is a schematic diagram of a memory cell according to an embodiment of the disclosure.

第2圖繪示第一至第四偏壓值與第一至第四電壓分布的電壓值大小關係。 Figure 2 illustrates the relationship between the first to fourth bias voltage values and the voltage values of the first to fourth voltage distributions.

第3圖繪示第一至第四偏壓值、第一至第四電壓分布、第一電壓差及第二電壓差的電壓值示例。 FIG. 3 illustrates voltage value examples of the first to fourth bias values, the first to fourth voltage distributions, the first voltage difference, and the second voltage difference.

第4A~4D圖繪示當搜尋資料為[0 0]時,搜尋不同內容的儲存資料的示意圖。 Figures 4A to 4D illustrate schematic diagrams of searching for stored data with different contents when the search data is [0 0].

第5A~5D圖繪示當搜尋資料為[1 0]時,搜尋不同內容的儲存資料的示意圖。 Figures 5A to 5D illustrate a schematic diagram of searching for stored data with different contents when the search data is [1 0].

第6A~6D圖繪示當搜尋資料為[0 1]時,搜尋不同內容的儲存資料的示意圖。 Figures 6A to 6D illustrate a schematic diagram of searching for stored data with different contents when the search data is [0 1].

第7A~7D圖繪示當搜尋資料為[1 1]時,搜尋不同內容的儲存資料的示意圖。 Figures 7A to 7D illustrate a schematic diagram of searching for stored data with different contents when the search data is [1 1].

第8A~8D圖繪示當搜尋資料為萬用符時,搜尋不同內容的儲存資料的示意圖。 Figures 8A to 8D illustrate schematic diagrams of searching for stored data with different contents when the search data is a wildcard.

第9A~9D圖繪示當儲存資料為隨意項時,以不同內容的搜尋資料進行搜尋的示意圖。 Figures 9A to 9D illustrate a schematic diagram of searching with search data of different contents when the stored data is a random item.

第10圖繪示TLC的電晶體的第二數量的偏壓值與第二數量的電壓分布的電壓值大小關係。 Figure 10 illustrates the relationship between the second number of bias voltage values of the TLC transistor and the voltage value of the second number of voltage distributions.

第11圖繪示QLC的電晶體的第三數量的偏壓值與第三數量 的電壓分布的電壓值大小關係。 Figure 11 illustrates the third number of bias voltage values and the third number of QLC transistors. The relationship between the voltage value of the voltage distribution.

第12圖繪示N階記憶單元的電晶體的第四數量的偏壓值與第四數量的電壓分布的電壓值大小關係。 FIG. 12 illustrates the relationship between the fourth number of bias voltage values and the fourth number of voltage distributions of the transistor of the N-level memory cell.

第13圖繪示本揭示一實施例的記憶體裝置的示意圖。 FIG. 13 is a schematic diagram of a memory device according to an embodiment of the present disclosure.

第14A圖繪示第一至第四偏壓值VH1~VH4與第一至第四電壓分布VT1~VT4的電壓值的另一示例。 FIG. 14A illustrates another example of the first to fourth bias values VH1 to VH4 and the voltage values of the first to fourth voltage distributions VT1 to VT4.

第14B圖繪示第一至第四偏壓值VH1~VH4與第一至第四電壓分布VT1~VT4的電壓值的又一示例。 Figure 14B shows another example of the first to fourth bias values VH1 to VH4 and the voltage values of the first to fourth voltage distributions VT1 to VT4.

本說明書的技術用語係參照本技術領域之習慣用語,如本說明書對部分用語有加以說明或定義,該部分用語之解釋係以本說明書之說明或定義為準。本揭示之各個實施例分別具有一或多個技術特徵。在可能實施的前提下,本技術領域具有通常知識者可選擇性地實施任一實施例中部分或全部的技術特徵,或者選擇性地將這些實施例中部分或全部的技術特徵加以組合。 The technical terms in this specification refer to the idioms in the technical field. If there are explanations or definitions for some terms in this specification, the explanation or definition of this part of the terms shall prevail. Each embodiment of the present disclosure has one or more technical features. Under the premise that implementation is possible, a person with ordinary skill in the art can selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

第1圖為本揭示一實施例的記憶胞100的示意圖,記憶胞100為記憶體裝置的一個單元,記憶體裝置用於執行記憶體內搜尋(in-memory search)。參見第1圖,記憶胞100包括串聯連接的兩個電晶體M1、M2。電晶體M1可稱為「第一電晶體」,電晶體M2可稱為「第二電晶體」。電晶體M1包括第一汲極d1、第一源極s1及第一閘極g1。電晶體M2包括第二汲極d2、第二源極s2及第二閘極g2。電晶體M1的第一汲極d1連接於記憶體裝置的其中 一條位元線(例如,第1條位元線BL1)。電晶體M1的第一源極s1連接於電晶體M2的第二汲極d2。電晶體M1的第一閘極g1及電晶體M2的第二閘極g2連接於記憶體裝置的其中一組字元線。例如,記憶體裝置的第1組字元線WL1包括第一字元線WL1(1)及第二字元線WL1(2),電晶體M1的第一閘極g1連接於第一字元線WL1(1),電晶體M2的第二閘極g2連接於第二字元線WL1(2)。 Figure 1 is a schematic diagram of a memory cell 100 according to an embodiment of the disclosure. The memory cell 100 is a unit of a memory device. The memory device is used to perform in-memory search. Referring to Figure 1, the memory cell 100 includes two transistors M1 and M2 connected in series. The transistor M1 can be called the "first transistor", and the transistor M2 can be called the "second transistor". The transistor M1 includes a first drain electrode d1, a first source electrode s1 and a first gate electrode g1. The transistor M2 includes a second drain d2, a second source s2 and a second gate g2. The first drain d1 of the transistor M1 is connected to the memory device. One bit line (for example, bit line 1 BL1). The first source s1 of the transistor M1 is connected to the second drain d2 of the transistor M2. The first gate g1 of the transistor M1 and the second gate g2 of the transistor M2 are connected to one group of word lines of the memory device. For example, the first group of word lines WL1 of the memory device includes a first word line WL1(1) and a second word line WL1(2), and the first gate g1 of the transistor M1 is connected to the first word line WL1(1), the second gate g2 of the transistor M2 is connected to the second word line WL1(2).

電晶體M1具有第一臨界電壓Vth1,電晶體M2具有第二臨界電壓Vth2。電晶體M1、M2具有浮動閘極(floating gate),可施加編程電壓以改變第一臨界電壓Vth1與第二臨界電壓Vth2。在一種示例中,電晶體M1、M2皆為二階記憶單元(multi-level cell,MLC)。電晶體M1的第一臨界電壓Vth1與電晶體M2的第二臨界電壓Vth2皆可調整為第一數量的電壓分布,第一數量為「4」。4個電壓分布依電壓大小關係依序為:第四電壓分布VT4、第三電壓分布VT3、第二電壓分布VT2、第一電壓分布VT1。在另一種示例中,電晶體M1、M2皆為三階記憶單元(triple-level cell,TLC),第一臨界電壓Vth1與第二臨界電壓Vth2皆可調整為第二數量的電壓分布,第二數量為「8」。在又一種示例中,電晶體M1、M2皆為四階記憶單元(quad-level cell,QLC),第一臨界電壓Vth1與第二臨界電壓Vth2皆可調整為第三數量的電壓分布,第三數量為「16」。下文中,第2、3、4A~4B、5A~5B、6A~6B、7A~7B、8A~8B、9A~9B圖的各實施例以MLC的電晶體M1、M2為例進行說明。 Transistor M1 has a first threshold voltage Vth1, and transistor M2 has a second threshold voltage Vth2. The transistors M1 and M2 have floating gates, and a programming voltage can be applied to change the first threshold voltage Vth1 and the second threshold voltage Vth2. In one example, the transistors M1 and M2 are both second-level memory cells (multi-level cells, MLC). Both the first threshold voltage Vth1 of the transistor M1 and the second threshold voltage Vth2 of the transistor M2 can be adjusted to a first number of voltage distributions, and the first number is "4". The four voltage distributions are, in order according to the voltage magnitude relationship: the fourth voltage distribution VT4, the third voltage distribution VT3, the second voltage distribution VT2, and the first voltage distribution VT1. In another example, the transistors M1 and M2 are both triple-level cells (TLC), and both the first threshold voltage Vth1 and the second threshold voltage Vth2 can be adjusted to a second number of voltage distributions. The quantity is "8". In another example, the transistors M1 and M2 are both quad-level cells (QLC), and both the first critical voltage Vth1 and the second critical voltage Vth2 can be adjusted to a third number of voltage distributions. The quantity is "16". In the following, each embodiment of Figures 2, 3, 4A~4B, 5A~5B, 6A~6B, 7A~7B, 8A~8B, and 9A~9B will be described by taking the transistors M1 and M2 of the MLC as an example.

記憶胞100可儲存一儲存資料DAT,其中儲存資料DAT包括第一位元D1及第二位元D2。儲存資料DAT根據第一臨界電壓Vth1與第二臨界電壓Vth2編碼而成。即,根據第一臨界電壓Vth1的第一至第四電壓分布VT1~VT4與第二臨界電壓Vth2的第一至第四電壓分布VT1~VT4編碼儲存資料DAT,如表1所示:

Figure 111126271-A0305-02-0008-1
The memory cell 100 can store a storage data DAT, where the storage data DAT includes a first bit D1 and a second bit D2. The storage data DAT is encoded according to the first threshold voltage Vth1 and the second threshold voltage Vth2. That is, the stored data DAT is encoded according to the first to fourth voltage distributions VT1 to VT4 of the first critical voltage Vth1 and the first to fourth voltage distributions VT1 to VT4 of the second critical voltage Vth2, as shown in Table 1:
Figure 111126271-A0305-02-0008-1

在表1的示例中,當第一臨界電壓Vth1與第二臨界電 壓Vth2分別為第一電壓分布VT1、第四電壓分布VT4時,編碼而成的儲存資料DAT的第一位元D1、第二位元D2為「0」、「0」。當第一臨界電壓Vth1與第二臨界電壓Vth2皆為第四電壓分布VT4時,編碼而成的儲存資料DAT為無效資料(invalid data)。當第一臨界電壓Vth1與第二臨界電壓Vth2皆為第一電壓分布VT1時,編碼而成的儲存資料DAT為隨意項DNC(don’t care)。 In the example of Table 1, when the first critical voltage Vth1 and the second critical voltage When the voltage Vth2 is the first voltage distribution VT1 and the fourth voltage distribution VT4 respectively, the first bit D1 and the second bit D2 of the encoded storage data DAT are "0" and "0". When the first critical voltage Vth1 and the second critical voltage Vth2 are both the fourth voltage distribution VT4, the encoded storage data DAT is invalid data. When the first critical voltage Vth1 and the second critical voltage Vth2 are both the first voltage distribution VT1, the encoded storage data DAT is a random term DNC (don’t care).

並且,當第一臨界電壓Vth1與第二臨界電壓Vth2分別為第一電壓分布VT1、第三電壓分布VT3時,編碼而成的儲存資料DAT的第一位元D1、第二位元D2為「0」、「X」,可表示儲存資料DAT為[0 0]或[0 1]。當第一臨界電壓Vth1與第二臨界電壓Vth2分別為第一電壓分布VT1、第二電壓分布VT2時,編碼而成的儲存資料DAT的第一位元D1、第二位元D2為「X」、「0」,可表示儲存資料DAT為[1 0]或[0 0]。 Moreover, when the first critical voltage Vth1 and the second critical voltage Vth2 are the first voltage distribution VT1 and the third voltage distribution VT3 respectively, the first bit D1 and the second bit D2 of the encoded storage data DAT are " 0", "X" can mean that the stored data DAT is [0 0] or [0 1]. When the first critical voltage Vth1 and the second critical voltage Vth2 are the first voltage distribution VT1 and the second voltage distribution VT2 respectively, the first bit D1 and the second bit D2 of the encoded storage data DAT are "X" , "0", can mean that the stored data DAT is [1 0] or [0 0].

類似的,當第一臨界電壓Vth1與第二臨界電壓Vth2分別為第三電壓分布VT3、第一電壓分布VT1時,編碼而成的儲存資料DAT為[1 X],即,儲存資料DAT為[1 0]或[1 1]。當第一臨界電壓Vth1與第二臨界電壓Vth2分別為第二電壓分布VT2、第一電壓分布VT1時,編碼而成的儲存資料DAT為[X 1],即,儲存資料DAT為[0 1]或[1 1]。 Similarly, when the first critical voltage Vth1 and the second critical voltage Vth2 are the third voltage distribution VT3 and the first voltage distribution VT1 respectively, the encoded storage data DAT is [1 X], that is, the storage data DAT is [ 1 0] or [1 1]. When the first critical voltage Vth1 and the second critical voltage Vth2 are the second voltage distribution VT2 and the first voltage distribution VT1 respectively, the encoded storage data DAT is [X 1], that is, the storage data DAT is [0 1] or [1 1].

當進行記憶體內搜尋時,電晶體M1經由第一字元線WL1(1)接收第一閘極偏壓Vg1,電晶體M2經由第二字元線WL1(2)接收第二閘極偏壓Vg2。在運作上,第一閘極偏壓Vg1、 第二閘極偏壓Vg2可分別調整為第一數量的偏壓值(即,4個偏壓值),依電壓值大小排序為:第四偏壓值VH4、第三偏壓值VH3、第二偏壓值VH2、第一偏壓值VH1。並且,第一至第四偏壓值VH1~VH4每一者的電壓值皆大於第一至第四電壓分布VT1~VT4。其大小關係為:第四偏壓值VH4>第三偏壓值VH3>第二偏壓值VH2>第一偏壓值VH1>第四電壓分布VT4>第三電壓分布VT3>第二電壓分布VT2>第一電壓分布VT1。即,電壓值最低的第一偏壓值VH1仍然大於電壓值最高的第四電壓分布VT4。上述之第一至第四偏壓值VH1~VH4與第一至第四電壓分布VT1~VT4的電壓大小關係可見於第2圖。 When searching in the memory, the transistor M1 receives the first gate bias Vg1 via the first word line WL1(1), and the transistor M2 receives the second gate bias Vg2 via the second word line WL1(2). . In operation, the first gate bias voltage Vg1, The second gate bias voltage Vg2 can be adjusted to a first number of bias values (ie, 4 bias values) respectively. The order according to the voltage value is: the fourth bias value VH4, the third bias value VH3, The second bias value VH2 and the first bias value VH1. Moreover, the voltage value of each of the first to fourth bias voltage values VH1 to VH4 is greater than the first to fourth voltage distributions VT1 to VT4. The relationship is: fourth bias value VH4>third bias value VH3>second bias value VH2>first bias value VH1>fourth voltage distribution VT4>third voltage distribution VT3>second voltage distribution VT2 >First voltage distribution VT1. That is, the first bias value VH1 with the lowest voltage value is still greater than the fourth voltage distribution VT4 with the highest voltage value. The voltage magnitude relationship between the above-mentioned first to fourth bias values VH1 to VH4 and the first to fourth voltage distributions VT1 to VT4 can be seen in Figure 2 .

記憶胞100可接收搜尋資料SW,其中搜尋資料SW包括第一位元S1及第二位元S2。可根據第一閘極偏壓Vg1與第二閘極偏壓Vg2編碼搜尋資料SW。即,根據第一閘極偏壓Vg1的第一至第四偏壓值VH1~VH4與第二閘極偏壓Vg2的第一至第四偏壓值VH1~VH4編碼搜尋資料SW,如表2所示:

Figure 111126271-A0305-02-0010-2
Figure 111126271-A0305-02-0011-3
The memory cell 100 can receive search data SW, where the search data SW includes a first bit S1 and a second bit S2. The search data SW can be encoded according to the first gate bias voltage Vg1 and the second gate bias voltage Vg2. That is, the search data SW is encoded according to the first to fourth bias values VH1 to VH4 of the first gate bias Vg1 and the first to fourth bias values VH1 to VH4 of the second gate bias Vg2, as shown in Table 2. Shown:
Figure 111126271-A0305-02-0010-2
Figure 111126271-A0305-02-0011-3

在表2的示例中,當第一閘極偏壓Vg1、第二閘極偏壓Vg2分別為第一偏壓值VH1、第四偏壓值VH4時,編碼而成的搜尋資料SW的第一位元S1、第二位元S2分別為「0」、「0」。當第一閘極偏壓Vg1、第二閘極偏壓Vg2皆為第四偏壓值VH4時,編碼而成的搜尋資料SW為萬用符WCD(wildcard)。 In the example of Table 2, when the first gate bias Vg1 and the second gate bias Vg2 are the first bias value VH1 and the fourth bias value VH4 respectively, the first value of the encoded search data SW is Bit S1 and the second bit S2 are "0" and "0" respectively. When the first gate bias voltage Vg1 and the second gate bias voltage Vg2 are both the fourth bias value VH4, the encoded search data SW is a wildcard WCD (wildcard).

在運作上,電晶體M1接收的第一閘極偏壓Vg1與電晶體M1的第一臨界電壓Vth1之間具有第一電壓差,電晶體M1根據第一電壓差產生電流I1。類似的,電晶體M2接收的第二閘極偏壓Vg2與電晶體M2的第二臨界電壓Vth2之間具有第二電壓差,電晶體M2根據第二電壓差產生電流I2。由於電晶體M1串聯連接於電晶體M2,記憶胞100在位元線BL1產生的輸出電流Is1的電流值大致相等於為電流I1與電流I2的電流值之較小者。輸出電流Is1產生於電晶體M2的第二源極s2。 In operation, there is a first voltage difference between the first gate bias voltage Vg1 received by the transistor M1 and the first threshold voltage Vth1 of the transistor M1, and the transistor M1 generates the current I1 according to the first voltage difference. Similarly, there is a second voltage difference between the second gate bias voltage Vg2 received by the transistor M2 and the second critical voltage Vth2 of the transistor M2, and the transistor M2 generates the current I2 according to the second voltage difference. Since the transistor M1 is connected to the transistor M2 in series, the current value of the output current Is1 generated by the memory cell 100 on the bit line BL1 is approximately equal to the smaller of the current value of the current I1 and the current I2. The output current Is1 is generated from the second source s2 of the transistor M2.

第3圖繪示第一至第四偏壓值VH1~VH4、第一至第四電壓分布VT1~VT4、第一電壓差及第二電壓差的電壓值示例。在第3圖的示例中,第一至第四偏壓值VH1~VH4分別為5.5V、7V、8.5V、10V。並且,第一電壓分布VT1的最低電壓值為0V、最高電壓值為1V、峰點(peak)電壓值為0.5V。第二電壓分布VT2 的最低電壓值為1.5V、最高電壓值為2.5V、峰點電壓值為2V。第三電壓分布VT3的最低電壓值為3V、最高電壓值為4V、峰點電壓值為3.5V。第四電壓分布VT4的最低電壓值為4.5V、最高電壓值為5.5V、峰點電壓值為5V。 Figure 3 illustrates voltage value examples of the first to fourth bias values VH1 to VH4, the first to fourth voltage distributions VT1 to VT4, the first voltage difference and the second voltage difference. In the example in Figure 3, the first to fourth bias values VH1 to VH4 are 5.5V, 7V, 8.5V, and 10V respectively. Furthermore, the lowest voltage value of the first voltage distribution VT1 is 0V, the highest voltage value is 1V, and the peak voltage value is 0.5V. Second voltage distribution VT2 The lowest voltage value is 1.5V, the highest voltage value is 2.5V, and the peak voltage value is 2V. The lowest voltage value of the third voltage distribution VT3 is 3V, the highest voltage value is 4V, and the peak voltage value is 3.5V. The lowest voltage value of the fourth voltage distribution VT4 is 4.5V, the highest voltage value is 5.5V, and the peak voltage value is 5V.

在運作上,可提供不同的搜尋資料SW以搜尋記憶胞100儲存的儲存資料DAT。第4A~4D圖為當搜尋資料SW為[0 0]時,搜尋不同內容的儲存資料DAT的示意圖。請先參見第4A圖,當搜尋資料SW為[0 0]時,電晶體M1接收的第一閘極偏壓Vg1為第一偏壓值VH1,電晶體M2接收的第二閘極偏壓Vg2為第四偏壓值VH4。當儲存資料DAT為[0 0]時,第一臨界電壓Vth1為第一電壓分布VT1,第二臨界電壓Vth2為第四電壓分布VT4。 In operation, different search data SW can be provided to search the storage data DAT stored in the memory cell 100 . Figures 4A to 4D are schematic diagrams of searching for stored data DAT with different contents when the search data SW is [0 0]. Please refer to Figure 4A first. When the search data SW is [0 0], the first gate bias Vg1 received by the transistor M1 is the first bias value VH1, and the second gate bias Vg2 received by the transistor M2 is the fourth bias value VH4. When the stored data DAT is [0 0], the first critical voltage Vth1 is the first voltage distribution VT1, and the second critical voltage Vth2 is the fourth voltage distribution VT4.

電晶體M1的第一閘極偏壓Vg1與第一臨界電壓Vth1之間的第一電壓差為「閘極過驅(gate overdrive)電壓差」。當搜尋資料SW為[0 0]且儲存資料DAT為[0 0]時,第一閘極偏壓Vg1為第一偏壓值VH1,第一臨界電壓Vth1為第一電壓分布VT1。第一偏壓值VH1(5.5V)與第一電壓分布VT1的最高電壓值(1V)之間的電壓差為4.5V。即,電晶體M1的第一閘極偏壓Vg1與第一臨界電壓Vth1之間的第一電壓差為4.5V。 The first voltage difference between the first gate bias voltage Vg1 and the first threshold voltage Vth1 of the transistor M1 is the "gate overdrive voltage difference". When the search data SW is [0 0] and the storage data DAT is [0 0], the first gate bias Vg1 is the first bias value VH1, and the first threshold voltage Vth1 is the first voltage distribution VT1. The voltage difference between the first bias value VH1 (5.5V) and the highest voltage value (1V) of the first voltage distribution VT1 is 4.5V. That is, the first voltage difference between the first gate bias voltage Vg1 of the transistor M1 and the first threshold voltage Vth1 is 4.5V.

第一至第四偏壓值VH1~VH4之中的相鄰兩個偏壓值之間的電壓差定義為預定的級距(level),可稱為「1倍的級距」,(1-level,(1L))。類似的,對於第一至第四電壓分布VT1~VT4而言,其中的相鄰兩個電壓分布各自的最大電壓值之間的電壓差 亦相等於1倍的級距(1L)。第3圖的實施例中,相鄰兩個偏壓值之間的電壓差為1.5V,則1.5V作為預定的級距(即,一倍的級距(1L))。據此,電晶體M1的第一電壓差4.5V為3倍的級距(3L)。 The voltage difference between two adjacent bias values among the first to fourth bias values VH1 ~ VH4 is defined as a predetermined level, which can be called "1 times the level", (1- level, (1L)). Similarly, for the first to fourth voltage distributions VT1~VT4, the voltage difference between the maximum voltage values of the two adjacent voltage distributions is It is also equivalent to 1 times the grade distance (1L). In the embodiment of Figure 3, the voltage difference between two adjacent bias values is 1.5V, and 1.5V is used as the predetermined step pitch (ie, one time step pitch (1L)). Accordingly, the first voltage difference 4.5V of the transistor M1 is three times the pitch (3L).

另一方面。當搜尋資料SW為[0 0]且儲存資料DAT為[0 0]時,電晶體M2的第四偏壓值VH4(10V)與第四電壓分布VT4的最高電壓值(5.5V)之間的電壓差為4.5V。即,電晶體M2的第二閘極偏壓Vg2與第二臨界電壓Vth2之間的第二電壓差為4.5V,其為3倍的級距(3L)。 on the other hand. When the search data SW is [0 0] and the storage data DAT is [0 0], the gap between the fourth bias value VH4 (10V) of the transistor M2 and the highest voltage value (5.5V) of the fourth voltage distribution VT4 The voltage difference is 4.5V. That is, the second voltage difference between the second gate bias voltage Vg2 of the transistor M2 and the second threshold voltage Vth2 is 4.5V, which is three times the pitch (3L).

電晶體M1產生的電流I1的電流值對應於電晶體M1的第一電壓差(為3倍的級距(3L)),電晶體M2產生的電流I2的電流值對應於電晶體M2的第二電壓差(為3倍的級距(3L))。電流I1相等於電流I2,因此記憶胞100產生的輸出電流Is1的電流值相等於電流I1及電流I2。輸出電流Is1的電流值對應的閘極過驅電壓差為3倍的級距(3L)。 The current value of the current I1 generated by the transistor M1 corresponds to the first voltage difference of the transistor M1 (which is three times the step pitch (3L)), and the current value of the current I2 generated by the transistor M2 corresponds to the second voltage difference of the transistor M2. Voltage difference (3 times the step pitch (3L)). The current I1 is equal to the current I2, so the current value of the output current Is1 generated by the memory cell 100 is equal to the current I1 and the current I2. The gate overdrive voltage difference corresponding to the current value of the output current Is1 is 3 times the step distance (3L).

儲存資料DAT與搜尋資料SW皆為[0 0],儲存資料DAT與搜尋資料SW之間的不匹配距離(mismatch distance)為「0」(即,完全匹配)。當儲存資料DAT與搜尋資料SW完全匹配時,輸出電流Is1的電流值對應的閘極過驅電壓差為3倍的級距(3L)。 Both the stored data DAT and the search data SW are [0 0], and the mismatch distance between the stored data DAT and the search data SW is "0" (ie, a perfect match). When the storage data DAT and the search data SW completely match, the gate overdrive voltage difference corresponding to the current value of the output current Is1 is 3 times the step distance (3L).

接著,請參見第4B圖,當搜尋資料SW為[0 0]且儲存資料DAT為[0 1]時,儲存資料DAT與搜尋資料SW的不匹配距離為「1」。電晶體M1的第一偏壓值VH1(5.5V)與第二電 壓分布VT2的最高電壓值(2.5V)之間的第一電壓差為3V(即,2倍的級距(2L))。電晶體M2的第四偏壓值VH4(10V)與第三電壓分布VT3的最高電壓值(4V)之間的第二電壓差為6V(即,4倍的級距(4L))。 Next, please refer to Figure 4B. When the search data SW is [0 0] and the stored data DAT is [0 1], the mismatch distance between the stored data DAT and the search data SW is "1". The first bias value VH1 (5.5V) of the transistor M1 and the second bias value The first voltage difference between the highest voltage value (2.5V) of the voltage distribution VT2 is 3V (ie, 2 times the step pitch (2L)). The second voltage difference between the fourth bias value VH4 (10V) of the transistor M2 and the highest voltage value (4V) of the third voltage distribution VT3 is 6V (ie, 4 times the step pitch (4L)).

據此,電流I1的電流值對應於電晶體M1的第一電壓差(為2倍的級距(2L)),電流I2的電流值對應於電晶體M2的第二電壓差(為4倍的級距(4L))。電流I1小於電流I2,記憶胞100產生的輸出電流Is1為電流I1與電流I2的較小者,輸出電流Is1的電流值相等於電流I1。輸出電流Is1的電流值對應的閘極過驅電壓差為2倍的級距(2L)。 Accordingly, the current value of the current I1 corresponds to the first voltage difference of the transistor M1 (which is 2 times the step pitch (2L)), and the current value of the current I2 corresponds to the second voltage difference of the transistor M2 (which is 4 times the step pitch (2L)). Grade distance (4L)). The current I1 is smaller than the current I2. The output current Is1 generated by the memory cell 100 is the smaller of the current I1 and the current I2. The current value of the output current Is1 is equal to the current I1. The gate overdrive voltage difference corresponding to the current value of the output current Is1 is 2 times the step pitch (2L).

接著,請參見第4C圖,當搜尋資料SW為[0 0]且儲存資料DAT為[1 0]時,儲存資料DAT與搜尋資料SW的不匹配距離為「2」。電晶體M1的第一偏壓值VH1(5.5V)與第三電壓分布VT3的最高電壓值(4V)之間的第一電壓差為1.5V(即,1倍的級距(1L))。電晶體M2的第四偏壓值VH4(10V)與第二電壓分布VT2的最高電壓值(2.5V)之間的第二電壓差為7.5V(即,5倍的級距(5L))。電流I1小於電流I2,輸出電流Is1的電流值相等於電流I1,輸出電流Is1的電流值對應的閘極過驅電壓差為1倍的級距(1L)。 Next, please refer to Figure 4C. When the search data SW is [0 0] and the stored data DAT is [1 0], the mismatch distance between the stored data DAT and the search data SW is "2". The first voltage difference between the first bias value VH1 (5.5V) of the transistor M1 and the highest voltage value (4V) of the third voltage distribution VT3 is 1.5V (ie, 1 times the step pitch (1L)). The second voltage difference between the fourth bias value VH4 (10V) of the transistor M2 and the highest voltage value (2.5V) of the second voltage distribution VT2 is 7.5V (ie, 5 times the step pitch (5L)). The current I1 is smaller than the current I2, the current value of the output current Is1 is equal to the current I1, and the gate overdrive voltage difference corresponding to the current value of the output current Is1 is 1 times the step distance (1L).

接著,請參見第4D圖,當搜尋資料SW為[0 0]且儲存資料DAT為[1 1]時,儲存資料DAT與搜尋資料SW的不匹配距離為「3」。電晶體M1的第一偏壓值VH1(5.5V)與第四電 壓分布VT4的最高電壓值(5.5V)之間的第一電壓差為0V(即,0倍的級距(0L))。電晶體M2的第四偏壓值VH4(10V)與第一電壓分布VT1的最高電壓值(1V)之間的第一電壓差為9V(即,6倍的級距(6L))。據此,輸出電流Is1的電流值對應的閘極過驅電壓差為0倍的級距(0L)。 Next, please refer to Figure 4D. When the search data SW is [0 0] and the stored data DAT is [1 1], the mismatch distance between the stored data DAT and the search data SW is "3". The first bias value VH1 (5.5V) of the transistor M1 and the fourth voltage The first voltage difference between the highest voltage value (5.5V) of the voltage distribution VT4 is 0V (ie, 0 times the step pitch (0L)). The first voltage difference between the fourth bias value VH4 (10V) of the transistor M2 and the highest voltage value (1V) of the first voltage distribution VT1 is 9V (ie, 6 times the step pitch (6L)). Accordingly, the gate overdrive voltage difference corresponding to the current value of the output current Is1 is 0 times the step pitch (0L).

由上,當搜尋資料SW與儲存資料DAT之間的不匹配距離為「0」、「1」、「2」、「3」時,輸出電流Is1的電流值對應的閘極過驅電壓差的級距為「3L」、「2L」、「1L」、「0L」。當搜尋資料SW與儲存資料DAT的不匹配程度(mismatch degree)越高時,不匹配距離越大,產生的輸出電流Is1的電流值越小。據此,可根據記憶胞100的輸出電流Is1的電流值判斷搜尋資料SW與儲存資料DAT的不匹配距離與不匹配程度。 From the above, when the mismatch distance between the search data SW and the stored data DAT is "0", "1", "2", or "3", the current value of the output current Is1 corresponds to the gate overdrive voltage difference The grade intervals are "3L", "2L", "1L", and "0L". When the mismatch degree between the search data SW and the stored data DAT is higher, the mismatch distance is larger, and the current value of the generated output current Is1 is smaller. Accordingly, the mismatch distance and degree of mismatch between the search data SW and the stored data DAT can be determined based on the current value of the output current Is1 of the memory cell 100 .

第5A~5D圖為當搜尋資料SW為[1 0]時,搜尋不同內容的儲存資料DAT的示意圖。請先參見第5A圖,當搜尋資料SW為[1 0]且儲存資料DAT為[0 0]時,不匹配距離為「2」。電晶體M1的第三偏壓值VH3(8.5V)與第一電壓分布VT1的最高電壓值(1V)之間的第一電壓差為7.5V(即,5倍的級距(5L))。電晶體M2的第二偏壓值VH2(7V)與第四電壓分布VT4的最高電壓值(5.5V)之間的第二電壓差為1.5V(即,1倍的級距(1L))。輸出電流Is1的電流值對應的閘極過驅電壓差為1倍的級距(1L)。 Figures 5A to 5D are schematic diagrams of searching for stored data DAT with different contents when the search data SW is [1 0]. Please refer to Figure 5A first. When the search data SW is [1 0] and the stored data DAT is [0 0], the mismatch distance is "2". The first voltage difference between the third bias value VH3 (8.5V) of the transistor M1 and the highest voltage value (1V) of the first voltage distribution VT1 is 7.5V (ie, 5 times the step pitch (5L)). The second voltage difference between the second bias value VH2 (7V) of the transistor M2 and the highest voltage value (5.5V) of the fourth voltage distribution VT4 is 1.5V (ie, 1 times the step pitch (1L)). The gate overdrive voltage difference corresponding to the current value of the output current Is1 is 1 times the step pitch (1L).

參見第5B圖,當搜尋資料SW為[1 0]且儲存資料DAT為[0 1]時,不匹配距離為「1」。電晶體M1的第一電壓差為4倍的級距(4L),電晶體M2的第二電壓差為2倍的級距(2L)。輸出電流Is1的電流值對應的閘極過驅電壓差為2倍的級距(2L)。 Referring to Figure 5B, when the search data SW is [1 0] and the stored data DAT is [0 1], the mismatch distance is "1". The first voltage difference of the transistor M1 is four times the step pitch (4L), and the second voltage difference of the transistor M2 is two times the step pitch (2L). The gate overdrive voltage difference corresponding to the current value of the output current Is1 is 2 times the step pitch (2L).

參見第5C圖,當搜尋資料SW為[1 0]且儲存資料DAT為[1 0]時,不匹配距離為「0」。電晶體M1的第一電壓差為3倍的級距(3L),電晶體M2的第二電壓差為3倍的級距(3L)。輸出電流Is1的電流值對應的閘極過驅電壓差為3倍的級距(3L)。 Referring to Figure 5C, when the search data SW is [1 0] and the stored data DAT is [1 0], the mismatch distance is "0". The first voltage difference of the transistor M1 is three times the step pitch (3L), and the second voltage difference of the transistor M2 is three times the step pitch (3L). The gate overdrive voltage difference corresponding to the current value of the output current Is1 is 3 times the step distance (3L).

參見第5D圖,當搜尋資料SW為[1 0]且儲存資料DAT為[1 1]時,不匹配距離為「1」。電晶體M1的第一電壓差為2倍的級距(2L),電晶體M2的第二電壓差為4倍的級距(4L)。輸出電流Is1的電流值對應的閘極過驅電壓差為2倍的級距(2L)。 Referring to Figure 5D, when the search data SW is [1 0] and the stored data DAT is [1 1], the mismatch distance is "1". The first voltage difference of the transistor M1 is 2 times the step pitch (2L), and the second voltage difference of the transistor M2 is 4 times the step pitch (4L). The gate overdrive voltage difference corresponding to the current value of the output current Is1 is 2 times the step pitch (2L).

基於類似的運作方式,參見第6A~6D圖,當搜尋資料SW為[0 1]時,若儲存資料DAT分別為[0 0]、[0 1]、[1 0]、[1 1]時,不匹配距離分別為「1」、「0」、「1」、「2」,輸出電流Is1的電流值對應的閘極過驅電壓差的級距分別為「2L」、「3L」、「2L」、「1L」。 Based on a similar operation method, see Figures 6A~6D. When the search data SW is [0 1], if the stored data DAT is [0 0], [0 1], [1 0], [1 1] respectively , the mismatch distances are "1", "0", "1", and "2" respectively, and the gate overdrive voltage difference levels corresponding to the current value of the output current Is1 are "2L", "3L", and " "2L", "1L".

類似的,參見第7A~7D圖,當搜尋資料SW為[1 1]時,若儲存資料DAT分別為[0 0]、[0 1]、[1 0]、[1 1]時,不匹 配距離分別為「3」、「2」、「1」、「0」,輸出電流Is1的電流值對應的閘極過驅電壓差的級距分別為「0L」、「1L」、「2L」、「3L」。 Similarly, see Figures 7A~7D. When the search data SW is [1 1], if the stored data DAT is [0 0], [0 1], [1 0], [1 1] respectively, there will be no match. The matching distances are "3", "2", "1", and "0" respectively. The gate overdrive voltage difference corresponding to the current value of the output current Is1 is "0L", "1L", and "2L" respectively. , "3L".

第8A~8D圖為當搜尋資料SW為萬用符WCD時,搜尋不同內容的儲存資料DAT的示意圖。請先參見第8A圖,當搜尋資料SW為萬用符WCD時,第一閘極偏壓Vg1與第二閘極偏壓Vg2皆為第四偏壓值VH4。當儲存資料DAT為[0 0]時,電晶體M1的第一電壓差為6倍的級距(6L),電晶體M2的第二電壓差為3倍的級距(3L)。參見第8B圖,當儲存資料DAT為[0 1]時,電晶體M1的第一電壓差為5倍的級距(5L),電晶體M2的第二電壓差為4倍的級距(4L)。參見第8C圖,當儲存資料DAT為[1 0]時,電晶體M1的第一電壓差為4倍的級距(4L),電晶體M2的第二電壓差為5倍的級距(5L)。參見第8D圖,當儲存資料DAT為[1 1]時,電晶體M1的第一電壓差為3倍的級距(3L),電晶體M2的第二電壓差為6倍的級距(6L)。 Figures 8A to 8D are schematic diagrams of searching for stored data DAT with different contents when the search data SW is the wildcard WCD. Please refer to Figure 8A first. When the search data SW is the wild sign WCD, the first gate bias Vg1 and the second gate bias Vg2 are both the fourth bias value VH4. When the stored data DAT is [0 0], the first voltage difference of the transistor M1 is 6 times the step pitch (6L), and the second voltage difference of the transistor M2 is 3 times the step pitch (3L). Referring to Figure 8B, when the stored data DAT is [0 1], the first voltage difference of the transistor M1 is 5 times the level (5L), and the second voltage difference of the transistor M2 is 4 times the level (4L). ). Referring to Figure 8C, when the stored data DAT is [1 0], the first voltage difference of the transistor M1 is 4 times the level (4L), and the second voltage difference of the transistor M2 is 5 times the level (5L). ). Referring to Figure 8D, when the stored data DAT is [1 1], the first voltage difference of the transistor M1 is 3 times the level (3L), and the second voltage difference of the transistor M2 is 6 times the level (6L). ).

據此,當儲存資料DAT分別為[0 0]、[0 1]、[1 0]、[1 1]時,輸出電流Is1的電流值對應的閘極過驅電壓差的級距分別為「3L」、「4L」、「4L」、「3L」。在閘極過驅電壓差的級距為「3L」或「4L」的狀況下,電晶體M1、M2皆操作於飽和區間(saturation region),因此,級距為「4L」的閘極過驅電壓差對應的輸出電流Is1的電流值大致相等於級距為「3L」對應的輸出電流Is1的電流值,皆相關於不匹配距離「0」。據此,當搜尋 資料SW為萬用符WCD時,不論儲存資料DAT的內容為何,輸出電流Is1的電流值皆相關於不匹配距離「0」,皆判斷為搜尋資料SW與儲存資料DAT完全匹配。 According to this, when the stored data DAT is [0 0], [0 1], [1 0], [1 1] respectively, the gate overdrive voltage difference corresponding to the current value of the output current Is1 is " 3L", "4L", "4L", "3L". When the gate overdrive voltage difference step is "3L" or "4L", both transistors M1 and M2 operate in the saturation region. Therefore, the gate overdrive step is "4L". The current value of the output current Is1 corresponding to the voltage difference is roughly equal to the current value of the output current Is1 corresponding to the step distance "3L", both of which are related to the mismatch distance "0". Accordingly, when searching for When the data SW is the wildcard WCD, regardless of the content of the stored data DAT, the current value of the output current Is1 is related to the mismatch distance "0", and it is determined that the search data SW and the stored data DAT completely match.

第9A~9D圖為當儲存資料DAT為隨意項DNC時,以不同內容的搜尋資料SW進行搜尋的示意圖。請先參見第9A圖,當儲存資料DAT為隨意項DNC時,第一臨界電壓Vth1與第二臨界電壓Vth2皆為第一電壓分布VT1。當搜尋資料SW為[0 0]時,電晶體M1的第一電壓差為3倍的級距(3L),電晶體M2的第二電壓差為6倍的級距(6L)。輸出電流Is1的電流值對應的閘極過驅電壓差為3倍的級距(3L)。 Figures 9A to 9D are schematic diagrams of searching with search data SW of different contents when the stored data DAT is a random item DNC. Please refer to Figure 9A first. When the storage data DAT is an optional item DNC, both the first critical voltage Vth1 and the second critical voltage Vth2 are the first voltage distribution VT1. When the search data SW is [0 0], the first voltage difference of the transistor M1 is three times the step pitch (3L), and the second voltage difference of the transistor M2 is six times the step pitch (6L). The gate overdrive voltage difference corresponding to the current value of the output current Is1 is 3 times the step distance (3L).

類似的,參見第9B圖,當搜尋資料SW為[0 1]時,電晶體M1的第一電壓差為4倍的級距(4L),電晶體M2的第二電壓差為5倍的級距(5L)。參見第9C圖,當搜尋資料SW為[1 0]時,電晶體M1的第一電壓差為5倍的級距(5L),電晶體M2的第二電壓差為4倍的級距(4L)。參見第9D圖,當搜尋資料SW為[1 1]時,電晶體M1的第一電壓差為6倍的級距(6L),電晶體M2的第二電壓差為3倍的級距(3L)。 Similarly, see Figure 9B, when the search data SW is [0 1], the first voltage difference of the transistor M1 is 4 times the level (4L), and the second voltage difference of the transistor M2 is 5 times the level. Distance (5L). Referring to Figure 9C, when the search data SW is [1 0], the first voltage difference of the transistor M1 is 5 times the step pitch (5L), and the second voltage difference of the transistor M2 is 4 times the step pitch (4L ). Referring to Figure 9D, when the search data SW is [1 1], the first voltage difference of the transistor M1 is 6 times the step pitch (6L), and the second voltage difference of the transistor M2 is 3 times the step pitch (3L ).

據此,若搜尋資料SW分別為[0 0]、[0 1]、[1 0]、[1 1]時,輸出電流Is1的電流值對應的閘極過驅電壓差的級距分別為「3L」、「4L」、「4L」、「3L」。級距為「3L」或「4L」的閘極過驅電壓差皆為電晶體M1或電晶體M2操作在飽和區間,對應的輸出電流Is1的電流值相關於不匹配距離「0」。據此,當 儲存資料DAT為隨意項DNC時,不論搜尋資料SW的內容為何,輸出電流Is1皆相關於不匹配距離「0」,皆判斷為搜尋資料SW與儲存資料DAT完全匹配。 According to this, if the search data SW are [0 0], [0 1], [1 0], [1 1] respectively, the gate overdrive voltage difference corresponding to the current value of the output current Is1 is " 3L", "4L", "4L", "3L". The gate overdrive voltage difference of the step pitch "3L" or "4L" means that the transistor M1 or the transistor M2 operates in the saturation range, and the corresponding current value of the output current Is1 is related to the mismatch distance "0". Accordingly, when When the stored data DAT is an arbitrary item DNC, no matter what the content of the search data SW is, the output current Is1 is related to the mismatch distance "0", and it is determined that the search data SW and the stored data DAT completely match.

下文中,第10、11、12圖的各實施例分別以TLC、QLC、N階記憶單元的電晶體M1、M2為例進行說明。 In the following, each embodiment of Figures 10, 11, and 12 will be described using transistors M1 and M2 of TLC, QLC, and N-level memory cells respectively as examples.

第10圖繪示TLC的電晶體M1(或電晶體M2)的第二數量的偏壓值與第二數量的電壓分布的電壓大小關係。如第10圖所示,當電晶體M1、M2皆為TLC記憶單元時,第二數量相等於「8」。第一臨界電壓Vth1與第二臨界電壓Vth2皆可調整為8個電壓分布,依電壓值大小排序為:第八電壓分布VT8、第七電壓分布VT7、第六電壓分布VT6、第五電壓分布VT5、第四電壓分布VT4、第三電壓分布VT3、第二電壓分布VT2、第一電壓分布VT1。對應的,電晶體M1、M2的第一閘極偏壓Vg1、第二閘極偏壓Vg2可分別調整為8個偏壓值,依電壓值大小排序為:第八偏壓值VH8、第七偏壓值VH7、第六偏壓值VH6、第五偏壓值VH5、第四偏壓值VH4、第三偏壓值VH3、第二偏壓值VH2、第一偏壓值VH1。即,電壓值最低的第一偏壓值VH1仍然大於電壓值最高的第八電壓分布VT8。 FIG. 10 illustrates the relationship between the voltage magnitude of the second number of bias voltage values of the transistor M1 (or the transistor M2) of the TLC and the second number of voltage distributions. As shown in Figure 10, when the transistors M1 and M2 are both TLC memory cells, the second number is equal to "8". Both the first critical voltage Vth1 and the second critical voltage Vth2 can be adjusted to 8 voltage distributions. The order according to the voltage value is: the eighth voltage distribution VT8, the seventh voltage distribution VT7, the sixth voltage distribution VT6, and the fifth voltage distribution VT5. , the fourth voltage distribution VT4, the third voltage distribution VT3, the second voltage distribution VT2, and the first voltage distribution VT1. Correspondingly, the first gate bias voltage Vg1 and the second gate bias voltage Vg2 of the transistors M1 and M2 can be adjusted to 8 bias values respectively. The order according to the voltage value is: the eighth bias value VH8, the seventh bias value VH8, and the seventh bias value Vg2. The bias value VH7, the sixth bias value VH6, the fifth bias value VH5, the fourth bias value VH4, the third bias value VH3, the second bias value VH2, and the first bias value VH1. That is, the first bias value VH1 with the lowest voltage value is still greater than the eighth voltage distribution VT8 with the highest voltage value.

第11圖繪示QLC的電晶體M1(或電晶體M2)的第三數量的偏壓值與第三數量的電壓分布的電壓值大小關係。如第11圖所示,當電晶體M1、M2皆為QLC記憶單元時,第三數量相等於「16」。第一臨界電壓Vth1與第二臨界電壓Vth2皆可調 整為16個電壓分布,依電壓值大小排序為:第十六電壓分布VT16至第一電壓分布VT1。對應的,電晶體M1、M2的第一閘極偏壓Vg1、第二閘極偏壓Vg2可分別調整為16個偏壓值,依電壓值大小排序為:第十六偏壓值VH16至第一偏壓值VH1。即,電壓值最低的第一偏壓值VH1仍然大於電壓值最高的第十六電壓分布VT16。 Figure 11 illustrates the relationship between the voltage values of the third number of bias values of the QLC transistor M1 (or the transistor M2) and the third number of voltage distributions. As shown in Figure 11, when the transistors M1 and M2 are both QLC memory cells, the third number is equal to "16". Both the first threshold voltage Vth1 and the second threshold voltage Vth2 are adjustable It is divided into 16 voltage distributions, and the order according to the voltage value is: the sixteenth voltage distribution VT16 to the first voltage distribution VT1. Correspondingly, the first gate bias voltage Vg1 and the second gate bias voltage Vg2 of the transistors M1 and M2 can be adjusted to 16 bias values respectively. The order according to the voltage value is: the 16th bias value VH16 to the 16th bias value. A bias value VH1. That is, the first bias value VH1 with the lowest voltage value is still greater than the sixteenth voltage distribution VT16 with the highest voltage value.

第12圖繪示N階記憶單元的電晶體M1(或電晶體M2)的第四數量的偏壓值與第四數量的電壓分布的電壓值大小關係。如第12圖所示,當電晶體M1、M2皆為N階記憶單元時,第四數量相等於「n」,n相等於2的N次方。第一臨界電壓Vth1與第二臨界電壓Vth2皆可調整為n個電壓分布,依電壓值大小排序為:第n電壓分布VT(n)至第一電壓分布VT1。對應的,電晶體M1、M2的第一閘極偏壓Vg1、第二閘極偏壓Vg2可分別調整為n個偏壓值,依電壓值大小排序為:第n偏壓值VH(n)至第一偏壓值VH1。即,電壓值最低的第一偏壓值VH1仍然大於電壓值最高的第n電壓分布VT(n)。 Figure 12 illustrates the relationship between the fourth number of bias voltage values of the transistor M1 (or the transistor M2) of the N-level memory cell and the voltage value of the fourth number of voltage distributions. As shown in Figure 12, when the transistors M1 and M2 are both N-level memory cells, the fourth quantity is equal to "n", and n is equal to the Nth power of 2. Both the first critical voltage Vth1 and the second critical voltage Vth2 can be adjusted to n voltage distributions, and the order according to the voltage value is: nth voltage distribution VT(n) to the first voltage distribution VT1. Correspondingly, the first gate bias voltage Vg1 and the second gate bias voltage Vg2 of the transistors M1 and M2 can be adjusted to n bias values respectively, and the order according to the voltage value is: nth bias value VH(n) to the first bias value VH1. That is, the first bias value VH1 with the lowest voltage value is still larger than the nth voltage distribution VT(n) with the highest voltage value.

第13圖為本揭示一實施例的記憶體裝置1000的示意圖。記憶體裝置1000包括排列為N個縱向行與M個橫向列的複數個記憶胞,每一個縱向行的記憶胞形成一個NAND記憶串。例如,第1個縱向行的記憶胞100-1、100-2、...、100-M組成一個NAND記憶串。其中,記憶胞100-1連接於第1組字元線WL1的第一字元線WL1(1)與第二字元線WL1(2),記憶胞100-2連接 於第2組字元線WL2的第一字元線WL2(1)與第二字元線WL2(2)。依此類推,記憶胞100-M連接於第M組的第一字元線WLM(1)與第二字元線WLM(2)。 FIG. 13 is a schematic diagram of a memory device 1000 according to an embodiment of the present disclosure. The memory device 1000 includes a plurality of memory cells arranged in N vertical rows and M horizontal columns. The memory cells in each vertical row form a NAND memory string. For example, the memory cells 100-1, 100-2, ..., 100-M in the first vertical row form a NAND memory string. Among them, the memory cell 100-1 is connected to the first word line WL1(1) and the second word line WL1(2) of the first group of word lines WL1, and the memory cell 100-2 is connected to The first word line WL2(1) and the second word line WL2(2) of the second group of word lines WL2. By analogy, the memory cell 100-M is connected to the first word line WLM(1) and the second word line WLM(2) of the M-th group.

記憶胞100-1、100-2、...、100-M共同連接於第1條位元線BL1,並產生輸出電流Is1。感應放大器(sensing amplifier,SA)600-1連接於位元線BL1以接收輸出電流Is1。類似的,第2個縱向行的記憶胞共同連接於第2條位元線BL2,感應放大器600-2連接於位元線BL2以接收輸出電流Is2。第N個縱向行的記憶胞共同連接於第N條位元線BLN,感應放大器600-N連接於位元線BLN以接收輸出電流IsN。 The memory cells 100-1, 100-2, ..., 100-M are jointly connected to the first bit line BL1 and generate an output current Is1. A sensing amplifier (SA) 600-1 is connected to the bit line BL1 to receive the output current Is1. Similarly, the memory cells in the second vertical row are commonly connected to the second bit line BL2, and the sense amplifier 600-2 is connected to the bit line BL2 to receive the output current Is2. The memory cells in the Nth vertical row are commonly connected to the Nth bit line BLN, and the sense amplifier 600-N is connected to the bit line BLN to receive the output current IsN.

位元線驅動電路400連接於位元線BL1、BL2、...、BLN。字元線驅動電路500連接於第一字元線WL1(1)、WL2(1)、...、WLM(1)與第二字元線WL1(2)、WL2(2)、...、WLM(2)。字元線驅動電路500可作為搜尋資料SW的緩衝器(search buffer)以暫存搜尋資料SW。 The bit line driving circuit 400 is connected to the bit lines BL1, BL2, ..., BLN. The word line driving circuit 500 is connected to the first word lines WL1(1), WL2(1), ..., WLM(1) and the second word lines WL1(2), WL2(2), ... ,WLM(2). The word line driver circuit 500 can be used as a search buffer to temporarily store the search data SW.

以M=24且N=8的記憶體裝置1000為例,其包括8個縱向行與24個橫向列的記憶胞。每個記憶胞的電晶體M1、M2皆為MLC記憶單元。此些記憶胞形成8個NAND記憶串。在表3的示例中,係提供搜尋資料SW=[0 0]對於M=24且N=8的記憶體裝置1000儲存的儲存資料DAT進行搜尋:表3

Figure 111126271-A0305-02-0022-4
Figure 111126271-A0305-02-0023-5
Taking the memory device 1000 with M=24 and N=8 as an example, it includes 8 vertical rows and 24 horizontal columns of memory cells. The transistors M1 and M2 of each memory cell are MLC memory cells. These memory cells form 8 NAND memory strings. In the example of Table 3, the search data SW=[0 0] is provided to search the storage data DAT stored in the memory device 1000 with M=24 and N=8: Table 3
Figure 111126271-A0305-02-0022-4
Figure 111126271-A0305-02-0023-5

如表3所示,當搜尋資料SW為[0 0]時,第二閘極偏壓Vg2為第四偏壓值VH4,第一閘極偏壓Vg1為第一偏壓值VH1。對於位元線BL1的NAND記憶串而言,每一個記憶胞的儲存資料DAT皆為[0 0],第一與第二臨界電壓Vth1、Vth2為[VT4 VT1]。據此,位元線BL1的每一個記憶胞的儲存資料DAT完全匹配於搜尋資料SW。位元線BL1的每一個記憶胞的不匹配距離為「0」,每一個記憶胞的輸出電流Is1的電流值對應的閘極過驅電壓差的級距為「3L」,位元線BL1的輸出電流Is1的總電流值對應的總級距為「72L」(即,24×3L)。不匹配距離對應的級距為「0L」。 As shown in Table 3, when the search data SW is [0 0], the second gate bias Vg2 is the fourth bias value VH4, and the first gate bias Vg1 is the first bias value VH1. For the NAND memory string of bit line BL1, the stored data DAT of each memory cell is [0 0], and the first and second critical voltages Vth1 and Vth2 are [VT4 VT1]. Accordingly, the stored data DAT of each memory cell of bit line BL1 completely matches the search data SW. The mismatch distance of each memory cell of bit line BL1 is "0". The current value of the output current Is1 of each memory cell corresponds to the gate overdrive voltage difference step pitch of "3L". The total current value corresponding to the output current Is1 is "72L" (ie, 24×3L). The level distance corresponding to the mismatch distance is "0L".

對於位元線BL2的NAND記憶串而言,每一個記憶胞的儲存資料DAT皆為[0 1],第一與第二臨界電壓Vth1、Vth2為[VT3 VT2]。每一個記憶胞的不匹配距離為「1」,每一個記憶胞的輸出電流Is1的電流值對應的級距為「2L」。位元線BL2的輸出電流Is2的總電流值對應的總級距為「48L」(即,24×2L),其小於位元線BL1的輸出電流Is1。不匹配距離對應的級距為「24L」。 For the NAND memory string of bit line BL2, the stored data DAT of each memory cell is [0 1], and the first and second critical voltages Vth1 and Vth2 are [VT3 VT2]. The mismatch distance of each memory cell is "1", and the current value corresponding to the output current Is1 of each memory cell is "2L". The total current value of the output current Is2 of the bit line BL2 corresponds to a total step pitch of "48L" (ie, 24×2L), which is smaller than the output current Is1 of the bit line BL1. The corresponding level distance of the mismatch distance is "24L".

位元線BL3的每一個記憶胞的儲存資料DAT皆為[1 0],第一與第二臨界電壓Vth1、Vth2為[VT2 VT3]。每一個 記憶胞的不匹配距離為「2」,每一個記憶胞的輸出電流Is1的電流值對應的級距為「1L」。位元線BL3的輸出電流Is3的總電流值對應的總級距為「24L」(即,24×1L),其小於位元線BL2的輸出電流Is2。不匹配距離的級距為「48L」。 The stored data DAT of each memory cell of bit line BL3 is [1 0], and the first and second critical voltages Vth1 and Vth2 are [VT2 VT3]. every The mismatch distance of the memory cell is "2", and the current value corresponding to the output current Is1 of each memory cell is "1L". The total current value corresponding to the total current value of the output current Is3 of the bit line BL3 is "24L" (ie, 24×1L), which is smaller than the output current Is2 of the bit line BL2. The level of mismatch distance is "48L".

位元線BL4的每一個記憶胞的儲存資料DAT皆為[1 1],第一與第二臨界電壓Vth1、Vth2為[VT1 VT4]。每一個記憶胞的不匹配距離為「3」,每一個記憶胞的輸出電流Is1的電流值對應的級距為「0L」。位元線BL4的輸出電流Is4的總電流值對應的總級距為「0L」(即,24×0L),其小於位元線BL3的輸出電流Is3。不匹配距離的級距為「72L」。 The stored data DAT of each memory cell of bit line BL4 is [1 1], and the first and second critical voltages Vth1 and Vth2 are [VT1 VT4]. The mismatch distance of each memory cell is "3", and the current value corresponding to the output current Is1 of each memory cell is "0L". The total current value corresponding to the total current value of the output current Is4 of the bit line BL4 is "0L" (ie, 24×0L), which is smaller than the output current Is3 of the bit line BL3. The level of mismatch distance is "72L".

位元線BL52對應的第1~12組字元線WL1~WL12的記憶胞的儲存資料DAT皆為[0 0],第一與第二臨界電壓Vth1、Vth2為[VT4 VT1],不匹配距離為「0」,輸出電流Is1的電流值對應的級距為「3L」。位元線BL5對應的第13~24組字元線WL13~WL24的記憶胞的儲存資料DAT皆為[0 1],第一與第二臨界電壓Vth1、Vth2為[VT3 VT2],不匹配距離為「1」,輸出電流Is1的電流值對應的級距為「2L」。位元線BL5的輸出電流Is5的總電流值對應的總級距為「60L」(即,12×3L+12×2L)。不匹配距離的級距為「12L」。 The storage data DAT of the memory cells of the 1st to 12th group of word lines WL1 to WL12 corresponding to the bit line BL52 are all [0 0], the first and second critical voltages Vth1 and Vth2 are [VT4 VT1], and the mismatch distance is "0", the current value corresponding to the output current Is1 is "3L". The storage data DAT of the memory cells of the 13th to 24th group of word lines WL13 to WL24 corresponding to the bit line BL5 are all [0 1], the first and second critical voltages Vth1 and Vth2 are [VT3 VT2], and the mismatch distance is "1", and the current value corresponding to the output current Is1 is "2L". The total current value corresponding to the total current value of the output current Is5 of the bit line BL5 is "60L" (ie, 12×3L+12×2L). The level of mismatch distance is "12L".

位元線BL6的第1~18組字元線WL1~WL18的記憶胞的儲存資料DAT皆為[0 0],不匹配距離為「0」,輸出電流Is1的電流值對應的級距為「3L」。位元線BL6的第19~24組字 元線WL19~WL24的記憶胞的儲存資料DAT皆為[0 1],不匹配距離為「1」,輸出電流Is1的電流值對應的級距為「2L」。位元線BL6的輸出電流Is6的總電流值對應的總級距為「66L」(即,18×3L+6×2L)。不匹配距離的級距為「6L」。 The storage data DAT of the memory cells of the 1st to 18th group of word lines WL1 to WL18 of the bit line BL6 are all [0 0], the mismatch distance is "0", and the corresponding level distance of the current value of the output current Is1 is " 3L". The 19th~24th group of words of bit line BL6 The storage data DAT of the memory cells of element lines WL19~WL24 are all [0 1], the mismatch distance is "1", and the corresponding step distance of the current value of the output current Is1 is "2L". The total current value corresponding to the total current value of the output current Is6 of the bit line BL6 is "66L" (ie, 18×3L+6×2L). The level of mismatch distance is "6L".

位元線BL7的第1~21組字元線WL1~WL21的記憶胞的儲存資料DAT皆為[0 0],不匹配距離為「0」,輸出電流Is1的電流值對應的級距為「3L」。位元線BL7的第22~24組字元線WL22~WL24的記憶胞的儲存資料DAT皆為[1 0],不匹配距離為「2」,輸出電流Is1的電流值對應的級距為「1L」。位元線BL7的輸出電流Is7的總電流值對應的總級距為「66L」(即,21×3L+3×1L)。不匹配距離的級距為「6L」。 The storage data DAT of the memory cells of the 1st to 21st groups of word lines WL1 to WL21 of the bit line BL7 are all [0 0], the mismatch distance is "0", and the corresponding level distance of the current value of the output current Is1 is " 3L". The storage data DAT of the memory cells of the 22nd to 24th group of word lines WL22 to WL24 of the bit line BL7 are all [1 0], the mismatch distance is "2", and the corresponding step distance of the current value of the output current Is1 is " 1L". The total current value corresponding to the total current value of the output current Is7 of the bit line BL7 is "66L" (ie, 21×3L+3×1L). The level of mismatch distance is "6L".

位元線BL8的第1~22組字元線WL1~WL22的記憶胞的儲存資料DAT皆為[0 0],不匹配距離為「0」,輸出電流Is1的電流值對應的級距為「3L」。位元線BL8的第23、24組字元線WL23、WL24的記憶胞的儲存資料DAT皆為[1 1],不匹配距離為「3」,輸出電流Is1的電流值對應的級距為「0L」。位元線BL8的輸出電流Is8的總電流值對應的總級距為「66L」(即,22×3L+2×0L)。不匹配距離的級距為「6L」。 The storage data DAT of the memory cells of the 1st to 22nd groups of word lines WL1 to WL22 of the bit line BL8 are all [0 0], the mismatch distance is "0", and the corresponding step distance of the current value of the output current Is1 is " 3L". The storage data DAT of the memory cells of the 23rd and 24th groups of word lines WL23 and WL24 of the bit line BL8 are both [1 1], the mismatch distance is "3", and the corresponding step distance of the current value of the output current Is1 is " 0L". The total current value corresponding to the total current value of the output current Is8 of the bit line BL8 is "66L" (ie, 22×3L+2×0L). The level of mismatch distance is "6L".

根據表3的示例,當位元線BL1~BL8各自的儲存資料DAT與搜尋資料SW具有不同的匹配程度時,位元線BL1~BL8各自的輸出電流Is1~Is8具有不同的總電流值。可根據 輸出電流Is1~Is8的總電流值分別計算位元線BL1~BL8各自的匹配程度,以達到近似匹配(approximate matching)的技術功效。 According to the example of Table 3, when the respective stored data DAT and the search data SW of the bit lines BL1 ~ BL8 have different matching degrees, the respective output currents Is1 ~ Is8 of the bit lines BL1 ~ BL8 have different total current values. can be based on The total current value of the output currents Is1 ~ Is8 is used to calculate the respective matching degrees of the bit lines BL1 ~ BL8 to achieve the technical effect of approximate matching.

第14A圖繪示第一至第四偏壓值VH1~VH4與第一至第四電壓分布VT1~VT4的電壓值的另一示例。第14A圖的示例類似於第3圖的示例,差異處在於:在第14A圖的示例中,第一至第四偏壓值VH1~VH4之中的相鄰兩個偏壓值之間的電壓差為1V。即,1倍的級距(1L)為1V。 FIG. 14A illustrates another example of the first to fourth bias values VH1 to VH4 and the voltage values of the first to fourth voltage distributions VT1 to VT4. The example in Figure 14A is similar to the example in Figure 3 . The difference is that in the example in Figure 14A , the voltage between two adjacent bias values among the first to fourth bias values VH1 ~ VH4 The difference is 1V. That is, 1 times the pitch (1L) is 1V.

並且,第一至第四電壓分布VT1~VT4的相鄰兩個電壓分布的峰點電壓值之間的電壓差為1V,相鄰兩個電壓分布的最高電壓值之間的電壓差為1V,且相鄰兩個電壓分布的最低電壓值之間的電壓差亦為1V。再者,第一偏壓值VH1相等於第四電壓分布VT4的峰點電壓值(為5V)。 Moreover, the voltage difference between the peak voltage values of two adjacent voltage distributions of the first to fourth voltage distributions VT1 to VT4 is 1V, and the voltage difference between the highest voltage values of two adjacent voltage distributions is 1V. And the voltage difference between the lowest voltage values of two adjacent voltage distributions is also 1V. Furthermore, the first bias value VH1 is equal to the peak voltage value of the fourth voltage distribution VT4 (which is 5V).

第14B圖繪示第一至第四偏壓值VH1~VH4與第一至第四電壓分布VT1~VT4的電壓值的又一示例。第14B圖的示例類似於第14A圖的示例,差異處在於:在第14B圖的示例中,第一偏壓值VH1相等於第四電壓分布VT4的最低電壓值(為4.5V)。 Figure 14B shows another example of the first to fourth bias values VH1 to VH4 and the voltage values of the first to fourth voltage distributions VT1 to VT4. The example of FIG. 14B is similar to the example of FIG. 14A , except that in the example of FIG. 14B , the first bias value VH1 is equal to the lowest voltage value of the fourth voltage distribution VT4 (which is 4.5V).

雖然本發明已以較佳實施例及範例詳細揭示如上,可理解的是,此些範例意指說明而非限制之意義。可預期的是,所屬技術領域中具有通常知識者可想到多種修改及組合,其多種修改及組合落在本發明之精神以及後附之申請專利範圍之範圍內。 Although the present invention has been disclosed in detail above with preferred embodiments and examples, it should be understood that these examples are meant to be illustrative rather than limiting. It is expected that those with ordinary skill in the art can think of various modifications and combinations, and the various modifications and combinations fall within the spirit of the present invention and the scope of the appended patent application.

VH1:第一偏壓值 VH1: first bias value

VH2:第二偏壓值 VH2: second bias value

VH3:第三偏壓值 VH3: third bias value

VH4:第四偏壓值 VH4: The fourth bias value

VT1:第一電壓分布 VT1: first voltage distribution

VT2:第二電壓分布 VT2: Second voltage distribution

VT3:第三電壓分布 VT3: The third voltage distribution

VT4:第四電壓分布 VT4: The fourth voltage distribution

1L:1倍的級距 1L: 1 times the grade distance

2L:2倍的級距 2L: 2 times the grade span

3L:3倍的級距 3L: 3 times the grade span

4L:4倍的級距 4L: 4 times the grade pitch

5L:5倍的級距 5L: 5 times the step distance

6L:6倍的級距 6L: 6 times the grade pitch

Claims (16)

一記憶體裝置,該記憶體裝置包括複數個記憶胞,各該記憶胞儲存一儲存資料並接收一搜尋資料,各該記憶胞包括:第一電晶體,具有一第一臨界電壓並接收一第一閘極偏壓;以及第二電晶體,連接於該第一電晶體,該第二電晶體具有一第二臨界電壓並接收一第二閘極偏壓;其中,該儲存資料係根據該第一臨界電壓與該第二臨界電壓編碼而成,該搜尋資料係根據該第一閘極偏壓與該第二閘極偏壓編碼而成,該儲存資料與該搜尋資料之間具有一不匹配距離,且該不匹配距離具有複數個數值,各該記憶胞產生的一輸出電流的複數個電流值分別對應於該不匹配距離的該些數值。 A memory device, the memory device includes a plurality of memory cells, each memory cell stores a storage data and receives a search data, each memory cell includes: a first transistor, has a first critical voltage and receives a first a gate bias; and a second transistor connected to the first transistor, the second transistor having a second threshold voltage and receiving a second gate bias; wherein the stored data is based on the first transistor. A threshold voltage and the second threshold voltage are encoded, the search data is encoded according to the first gate bias voltage and the second gate bias voltage, and there is a mismatch between the stored data and the search data. distance, and the mismatch distance has a plurality of values, and the plurality of current values of an output current generated by each memory cell respectively correspond to the values of the mismatch distance. 如請求項1所述之記憶體裝置,其中:該第一臨界電壓與該第二臨界電壓皆具有複數個電壓分布,該第一閘極偏壓與該第二閘極偏壓皆具有複數個偏壓值,該些電壓分布的數量相等於一第一數量,該些偏壓值的數量相等於該第一數量;以及該儲存資料係根據該第一數量的該些電壓分布編碼而成,該搜尋資料係根據該第一數量的該些偏壓值編碼而成。 The memory device of claim 1, wherein: the first threshold voltage and the second threshold voltage each have a plurality of voltage distributions, and the first gate bias voltage and the second gate bias voltage each have a plurality of voltage distributions. bias values, the number of the voltage distributions is equal to a first number, the number of the bias values is equal to the first number; and the stored data is encoded according to the first number of the voltage distributions, The search data is encoded according to the first number of bias values. 如請求項2所述之記憶體裝置,其中該第一電晶體與該第二電晶體皆為二階記憶單元(MLC),該第一數量相等於「四」,該儲存資料具有兩個位元,該搜尋資料具有兩個位元。 The memory device of claim 2, wherein both the first transistor and the second transistor are second-level memory cells (MLC), the first number is equal to "four", and the stored data has two bits , the search data has two bits. 如請求項2所述之記憶體裝置,其中該第一電晶體與該第二電晶體皆為三階記憶單元(TLC),該第一數量相等於「八」。 The memory device of claim 2, wherein the first transistor and the second transistor are third-level memory cells (TLC), and the first number is equal to "eight". 如請求項2所述之記憶體裝置,其中該第一電晶體與該第二電晶體皆為四階記憶單元(QLC),該第一數量相等於「十六」。 The memory device of claim 2, wherein both the first transistor and the second transistor are fourth-level memory cells (QLC), and the first number is equal to "sixteen". 如請求項3所述之記憶體裝置,其中該第一數量的該些電壓分布包括:一第一電壓分布、一第二電壓分布、一第三電壓分布及一第四電壓分布,該第四電壓分布的電壓值最高,該第一電壓分布的電壓值最低;其中,當該第一臨界電壓具有該第一電壓分布且該第二臨界電壓具有該第一電壓分布時,該儲存資料被編碼為一隨意項,該搜尋資料完全匹配於該儲存資料,該不匹配距離為「0」。 The memory device of claim 3, wherein the first number of voltage distributions includes: a first voltage distribution, a second voltage distribution, a third voltage distribution and a fourth voltage distribution, the fourth voltage distribution The voltage value of the voltage distribution is the highest, and the voltage value of the first voltage distribution is the lowest; wherein, when the first critical voltage has the first voltage distribution and the second critical voltage has the first voltage distribution, the stored data is encoded For an arbitrary item, the search data exactly matches the stored data, and the mismatch distance is "0". 如請求項3所述之記憶體裝置,其中該第一數量的該些偏壓值包括:一第一偏壓值、一第二偏壓值、一第三偏壓值及一第四偏壓值,該第四偏壓值的電壓值最高,該第一偏壓值的電壓值最低;其中,當該第一閘極偏壓具有該第四偏壓值且該第二閘極偏壓具有該第四偏壓值時,該搜尋資料被編碼為一萬用符,該搜尋資料完全匹配於該儲存資料,該不匹配距離為「0」。 The memory device of claim 3, wherein the first number of bias values includes: a first bias value, a second bias value, a third bias value and a fourth bias value. value, the voltage value of the fourth bias value is the highest, and the voltage value of the first bias value is the lowest; wherein, when the first gate bias has the fourth bias value and the second gate bias has At the fourth bias value, the search data is encoded as a wildcard, the search data completely matches the stored data, and the mismatch distance is "0". 如請求項1所述之記憶體裝置,其中該第一電晶體具有一第一閘極、一第一汲極與一第一源極,該第二電晶體具有一第二閘極、一第二汲極與一第二源極;其中,該第一電晶體的該第一閘極連接於一第一字元線以接收該第一閘極偏壓,該第二電晶體的該第二閘極連接於一第二字元線以接收該第二閘極偏壓,該第一電晶體的該第一汲極連接於一位元線,該第一電晶體的該第一源極連接於該第二電晶體的該第二汲極,該第二電晶體的該第二源極輸出該輸出電流。 The memory device of claim 1, wherein the first transistor has a first gate, a first drain and a first source, and the second transistor has a second gate, a first source. Two drains and a second source; wherein, the first gate of the first transistor is connected to a first word line to receive the first gate bias, and the second gate of the second transistor The gate is connected to a second word line to receive the second gate bias, the first drain of the first transistor is connected to a bit line, and the first source of the first transistor is connected to At the second drain of the second transistor, the second source of the second transistor outputs the output current. 如請求項2所述之記憶體裝置,其中該第一電晶體的該第一閘極偏壓與該第一臨界電壓之間具有一第一電壓差,該第二電晶體的該第二閘極偏壓與該第二臨界電壓之間具有一第二電壓差,該第一電壓差與該第二電壓差之較小者相關於該輸出電流的該些電流值。 The memory device of claim 2, wherein there is a first voltage difference between the first gate bias voltage of the first transistor and the first critical voltage, and the second gate bias voltage of the second transistor There is a second voltage difference between the extreme bias voltage and the second critical voltage, and the smaller of the first voltage difference and the second voltage difference is related to the current values of the output current. 如請求項9所述之記憶體裝置,其中該些偏壓值之中的相鄰兩個偏壓值之間的一電壓差相等於一預定級距,該些電壓分布之中的相鄰兩個電壓分布各自的最大電壓值之間的一電壓差相等於該預定級距,該第一電壓差相等於整數倍的該預定級距,該第二電壓差相等於整數倍的該預定級距。 The memory device of claim 9, wherein a voltage difference between two adjacent bias values among the bias values is equal to a predetermined interval, and two adjacent bias values among the voltage distributions are A voltage difference between the maximum voltage values of the respective voltage distributions is equal to the predetermined step distance, the first voltage difference is equal to an integer multiple of the predetermined step distance, and the second voltage difference is equal to an integer multiple of the predetermined step distance. . 如請求項10所述之記憶體裝置,其中該第一電晶體與該第二電晶體皆為二階記憶單元(MLC),當該搜尋資料完全匹配於該儲存資料時,該不匹配距離為「0」,該第一電壓差相等於三倍的該預定級距,該第二電壓差相等於三倍的該預定級距。 The memory device of claim 10, wherein both the first transistor and the second transistor are second-level memory cells (MLC), and when the search data completely matches the stored data, the mismatch distance is " 0", the first voltage difference is equal to three times of the predetermined level span, and the second voltage difference is equal to three times of the predetermined level span. 用於一記憶體的一資料搜尋方法,該記憶體包括複數個記憶胞,各該記憶胞包括一第一電晶體與一第二電晶體,該資料搜尋方法包括:根據該第一電晶體的一第一臨界電壓與該第二電晶體的一第二臨界電壓編碼一儲存資料;以及根據一第一閘極偏壓與一第二閘極偏壓編碼一搜尋資料,該儲存資料與該搜尋資料之間具有一不匹配距離,且該不匹配距離具有複數個數值,其中各該記憶胞產生的一輸出電流的複數個電流值分別對應於該不匹配距離的該些數值。 A data search method for a memory, the memory includes a plurality of memory cells, each memory cell includes a first transistor and a second transistor, the data search method includes: according to the first transistor A first threshold voltage and a second threshold voltage of the second transistor encode a stored data; and a first gate bias voltage and a second gate bias encode a search data, the stored data and the search There is a mismatch distance between the data, and the mismatch distance has a plurality of values, wherein the plurality of current values of an output current generated by each memory cell respectively correspond to the values of the mismatch distance. 如請求項12所述之資料搜尋方法,其中該第一臨界電壓與該第二臨界電壓皆具有複數個電壓分布,該些電壓分布的數量相等於一第一數量,該資料搜尋方法包括:根據該第一數量的該些電壓分布編碼該儲存資料。 The data search method as described in claim 12, wherein both the first critical voltage and the second critical voltage have a plurality of voltage distributions, and the number of these voltage distributions is equal to a first number, the data search method includes: according to The first number of voltage distributions encodes the stored data. 如請求項13所述之資料搜尋方法,其中該第一電晶體與該第二電晶體皆為二階記憶單元(MLC),該第一數量相等於「四」,該第一數量的該些電壓分布包括一第一電壓分布、一第二電壓分布、一第三電壓分布及一第四電壓分布,該資料搜尋方法包括:編程該第一臨界電壓為該第一電壓分布;編程該第二臨界電壓為該第一電壓分布;根據該第一臨界電壓與該第二臨界電壓編碼該儲存資料為一隨意項;判斷該不匹配距離為「0」;以及判斷該搜尋資料完全匹配於該儲存資料。 The data search method as described in claim 13, wherein both the first transistor and the second transistor are second-level memory cells (MLC), the first number is equal to "four", and the first number of voltages The distribution includes a first voltage distribution, a second voltage distribution, a third voltage distribution and a fourth voltage distribution, and the data search method includes: programming the first critical voltage to be the first voltage distribution; programming the second critical voltage The voltage is the first voltage distribution; the stored data is encoded as a random item according to the first critical voltage and the second critical voltage; the mismatch distance is determined to be "0"; and the search data is determined to completely match the stored data . 如請求項14所述之資料搜尋方法,其中該第一閘極偏壓與該第二閘極偏壓皆具有複數個偏壓值,該些偏壓值的數量相等於該第一數量,該資料搜尋方法包括:根據該第一數量的該些偏壓值編碼該搜尋資料。 The data search method as described in claim 14, wherein both the first gate bias voltage and the second gate bias voltage have a plurality of bias values, and the number of the bias values is equal to the first number, and the The data search method includes: encoding the search data according to the first number of bias values. 如請求項15所述之資料搜尋方法,其中該第一數量的該些偏壓值包括一第一偏壓值、一第二偏壓值、一第三偏壓值及一第四偏壓值,該資料搜尋方法包括:將該第四偏壓值作為該第一閘極偏壓;將該第四偏壓值作為該第二閘極偏壓;根據該第一閘極偏壓與該第二閘極偏壓編碼該搜尋資料為一萬用符;判斷該不匹配距離為「0」;以及判斷該搜尋資料完全匹配於該儲存資料。 The data search method as claimed in claim 15, wherein the first number of bias values includes a first bias value, a second bias value, a third bias value and a fourth bias value. , the data search method includes: using the fourth bias value as the first gate bias; using the fourth bias value as the second gate bias; based on the first gate bias and the third gate bias. Two gate biases encode the search data as a wildcard; determine the mismatch distance as "0"; and determine that the search data completely matches the stored data.
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US6166938A (en) * 1999-05-21 2000-12-26 Sandisk Corporation Data encoding for content addressable memories
US7251148B2 (en) * 2000-05-01 2007-07-31 Mosaid Technologies Incorporated Matchline sense circuit and method
WO2016167821A1 (en) * 2015-04-14 2016-10-20 Cambou Bertrand F Memory circuits using a blocking state
TWI766706B (en) * 2020-08-26 2022-06-01 旺宏電子股份有限公司 Ternary content addressable memory and decision generation method for the same

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