TWI827137B - Memory device and data search method for in-memory search - Google Patents

Abstract

A memory device for in-memory search, the memory device includes a plurality of memory cells, and each of the memory cells stores a stored data and receives a search data, including a first transistor and a second transistor. The first transistor has a first threshold voltage and receives a first gate bias. The second transistor is connected to the first transistor, and the second transistor has a second threshold voltage and receives a second gate bias. The stored data is encoded according to the first threshold voltage and the second threshold voltage, and the search data is encoded according to the first gate bias and the second gate bias. There is a mismatch distance between the stored data and the search data. An output current generated by each of the memory cells is related to the mismatch distance.

Description

Memory device and data search method for in-memory search

The present disclosure relates to a semiconductor device and a data processing method, and in particular to a memory device and a data search method for in-memory search (IMS).

In response to the needs of artificial intelligence (AI) and big data, various forms of algorithms often require a large amount of data processing, including data search and data comparison. With the mature development of semiconductor technology, a large amount of storage data can be stored in a memory device, and data processing is performed inside the memory device based on the storage data. For example, perform in-memory search (IMS) and in-memory computation (IMC).

In the search operation in the memory, an exact matching mechanism can be used. When the storage data stored in the memory device completely matches the search data, the bit line corresponding to the memory cell storing the storage data starts to generate an output current. That is, when the stored data does not match the search data, no matter the "mismatch degree", the corresponding bit line does not generate an output current. However, the exact matching mechanism cannot further determine the "degree of mismatch" between stored data and search data, which will seriously limit the flexibility of matching.

In view of the above-mentioned shortcomings of the exact matching mechanism, it is necessary to propose an improved data search method and a corresponding memory device architecture that can implement approximate searching to achieve the technical effect of approximate matching.

According to one aspect of the present disclosure, a memory device for in-memory searching is provided, including a plurality of memory cells. Each memory cell stores storage data and receives search data. Each memory cell includes a first transistor and a second transistor. The first transistor has a first threshold voltage and receives a first gate bias voltage. The second transistor is connected to the first transistor, has a second threshold voltage and receives a second gate bias voltage. The stored data is encoded according to the first threshold voltage and the second threshold voltage, and the search data is encoded according to the first gate bias voltage and the second gate bias voltage. There is a mismatch distance between the stored data and the search data, and the output current generated by each memory cell root is related to the mismatch distance.

According to another aspect of the disclosure, a data search method for a memory is provided. The memory includes a plurality of memory cells, and each memory cell includes a first transistor and a second transistor. The data search method includes the following steps. Data is encoded and stored according to the first threshold voltage of the first transistor and the second threshold voltage of the second transistor. The search data is encoded according to the first gate bias voltage and the second gate bias voltage, and there is a mismatch distance between the stored data and the search data. The output current generated by each memory cell is related to the mismatch distance.

By reading the following drawings, detailed descriptions and patent claims, other aspects and advantages of the present disclosure can be seen.

VH1: first bias value

VH2: second bias value

VH3: third bias value

VH4: The fourth bias value

VH5: fifth bias value

VH6: The sixth bias value

VH7: seventh bias value

VH8: The eighth bias value

VH9: Ninth bias value

VH10: tenth bias value

VH11: Eleventh bias value

VH12: Twelfth bias value

VH13: Thirteenth bias value

VH14: Fourteenth bias value

VH15: Fifteenth bias value

VH16: sixteenth bias value

VH(n): nth bias value

VT1: first voltage distribution

VT2: Second voltage distribution

VT3: The third voltage distribution

VT4: The fourth voltage distribution

VT5: fifth voltage distribution

VT6: The sixth voltage distribution

VT7: seventh voltage distribution

VT8: The eighth voltage distribution

VT9: Ninth voltage distribution

VT10: Tenth voltage distribution

VT11: Eleventh voltage distribution

VT12: Twelfth voltage distribution

VT13: Thirteenth voltage distribution

VT14: Fourteenth voltage distribution

VT15: Fifteenth voltage distribution

VT16: Sixteenth voltage distribution

VT(n): nth voltage distribution

1L: 1 times the grade distance

2L: 2 times the grade span

3L: 3 times the grade span

4L: 4 times the grade pitch

5L: 5 times the step distance

6L: 6 times the grade pitch

100,100-1,100-2,100-M: memory cells

1000:Memory device

400: Bit line driver circuit

500: Character line driver circuit

600-1,600-2,600-N: Sense amplifier

M1, M2: transistor

WL1(1),WL2(1),WLM(1): first character line

WL1(2),WL2(2),WLM(2): second character line

BL1~BL8, BLN: bit lines

WL1~WL24: The 1st~24th group of character lines

Is1~Is8,IsN: output current

Vg1: first gate bias

Vg2: second gate bias

g1: first gate

g2: second gate

d1: first drain

d2: The second drain

s1: first source

s2: second source

SW: Search data

DAT: store data

WCD: wildcard

DNC: optional

Figure 1 is a schematic diagram of a memory cell according to an embodiment of the disclosure.

Figure 2 illustrates the relationship between the first to fourth bias voltage values and the voltage values of the first to fourth voltage distributions.

FIG. 3 illustrates voltage value examples of the first to fourth bias values, the first to fourth voltage distributions, the first voltage difference, and the second voltage difference.

Figures 4A to 4D illustrate schematic diagrams of searching for stored data with different contents when the search data is [0 0].

Figures 5A to 5D illustrate a schematic diagram of searching for stored data with different contents when the search data is [1 0].

Figures 6A to 6D illustrate a schematic diagram of searching for stored data with different contents when the search data is [0 1].

Figures 7A to 7D illustrate a schematic diagram of searching for stored data with different contents when the search data is [1 1].

Figures 8A to 8D illustrate schematic diagrams of searching for stored data with different contents when the search data is a wildcard.

Figures 9A to 9D illustrate a schematic diagram of searching with search data of different contents when the stored data is a random item.

Figure 10 illustrates the relationship between the second number of bias voltage values of the TLC transistor and the voltage value of the second number of voltage distributions.

Figure 11 illustrates the third number of bias voltage values and the third number of QLC transistors. The relationship between the voltage value of the voltage distribution.

FIG. 12 illustrates the relationship between the fourth number of bias voltage values and the fourth number of voltage distributions of the transistor of the N-level memory cell.

FIG. 13 is a schematic diagram of a memory device according to an embodiment of the present disclosure.

FIG. 14A illustrates another example of the first to fourth bias values VH1 to VH4 and the voltage values of the first to fourth voltage distributions VT1 to VT4.

Figure 14B shows another example of the first to fourth bias values VH1 to VH4 and the voltage values of the first to fourth voltage distributions VT1 to VT4.

The technical terms in this specification refer to the idioms in the technical field. If there are explanations or definitions for some terms in this specification, the explanation or definition of this part of the terms shall prevail. Each embodiment of the present disclosure has one or more technical features. Under the premise that implementation is possible, a person with ordinary skill in the art can selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

Figure 1 is a schematic diagram of a memory cell 100 according to an embodiment of the disclosure. The memory cell 100 is a unit of a memory device. The memory device is used to perform in-memory search. Referring to Figure 1, the memory cell 100 includes two transistors M1 and M2 connected in series. The transistor M1 can be called the "first transistor", and the transistor M2 can be called the "second transistor". The transistor M1 includes a first drain electrode d1, a first source electrode s1 and a first gate electrode g1. The transistor M2 includes a second drain d2, a second source s2 and a second gate g2. The first drain d1 of the transistor M1 is connected to the memory device. One bit line (for example, bit line 1 BL1). The first source s1 of the transistor M1 is connected to the second drain d2 of the transistor M2. The first gate g1 of the transistor M1 and the second gate g2 of the transistor M2 are connected to one group of word lines of the memory device. For example, the first group of word lines WL1 of the memory device includes a first word line WL1(1) and a second word line WL1(2), and the first gate g1 of the transistor M1 is connected to the first word line WL1(1), the second gate g2 of the transistor M2 is connected to the second word line WL1(2).

Transistor M1 has a first threshold voltage Vth1, and transistor M2 has a second threshold voltage Vth2. The transistors M1 and M2 have floating gates, and a programming voltage can be applied to change the first threshold voltage Vth1 and the second threshold voltage Vth2. In one example, the transistors M1 and M2 are both second-level memory cells (multi-level cells, MLC). Both the first threshold voltage Vth1 of the transistor M1 and the second threshold voltage Vth2 of the transistor M2 can be adjusted to a first number of voltage distributions, and the first number is "4". The four voltage distributions are, in order according to the voltage magnitude relationship: the fourth voltage distribution VT4, the third voltage distribution VT3, the second voltage distribution VT2, and the first voltage distribution VT1. In another example, the transistors M1 and M2 are both triple-level cells (TLC), and both the first threshold voltage Vth1 and the second threshold voltage Vth2 can be adjusted to a second number of voltage distributions. The quantity is "8". In another example, the transistors M1 and M2 are both quad-level cells (QLC), and both the first critical voltage Vth1 and the second critical voltage Vth2 can be adjusted to a third number of voltage distributions. The quantity is "16". In the following, each embodiment of Figures 2, 3, 4A~4B, 5A~5B, 6A~6B, 7A~7B, 8A~8B, and 9A~9B will be described by taking the transistors M1 and M2 of the MLC as an example.

The memory cell 100 can store a storage data DAT, where the storage data DAT includes a first bit D1 and a second bit D2. The storage data DAT is encoded according to the first threshold voltage Vth1 and the second threshold voltage Vth2. That is, the stored data DAT is encoded according to the first to fourth voltage distributions VT1 to VT4 of the first critical voltage Vth1 and the first to fourth voltage distributions VT1 to VT4 of the second critical voltage Vth2, as shown in Table 1:

In the example of Table 1, when the first critical voltage Vth1 and the second critical voltage When the voltage Vth2 is the first voltage distribution VT1 and the fourth voltage distribution VT4 respectively, the first bit D1 and the second bit D2 of the encoded storage data DAT are "0" and "0". When the first critical voltage Vth1 and the second critical voltage Vth2 are both the fourth voltage distribution VT4, the encoded storage data DAT is invalid data. When the first critical voltage Vth1 and the second critical voltage Vth2 are both the first voltage distribution VT1, the encoded storage data DAT is a random term DNC (don’t care).

Moreover, when the first critical voltage Vth1 and the second critical voltage Vth2 are the first voltage distribution VT1 and the third voltage distribution VT3 respectively, the first bit D1 and the second bit D2 of the encoded storage data DAT are " 0", "X" can mean that the stored data DAT is [0 0] or [0 1]. When the first critical voltage Vth1 and the second critical voltage Vth2 are the first voltage distribution VT1 and the second voltage distribution VT2 respectively, the first bit D1 and the second bit D2 of the encoded storage data DAT are "X" , "0", can mean that the stored data DAT is [1 0] or [0 0].

Similarly, when the first critical voltage Vth1 and the second critical voltage Vth2 are the third voltage distribution VT3 and the first voltage distribution VT1 respectively, the encoded storage data DAT is [1 X], that is, the storage data DAT is [ 1 0] or [1 1]. When the first critical voltage Vth1 and the second critical voltage Vth2 are the second voltage distribution VT2 and the first voltage distribution VT1 respectively, the encoded storage data DAT is [X 1], that is, the storage data DAT is [0 1] or [1 1].

When searching in the memory, the transistor M1 receives the first gate bias Vg1 via the first word line WL1(1), and the transistor M2 receives the second gate bias Vg2 via the second word line WL1(2). . In operation, the first gate bias voltage Vg1, The second gate bias voltage Vg2 can be adjusted to a first number of bias values (ie, 4 bias values) respectively. The order according to the voltage value is: the fourth bias value VH4, the third bias value VH3, The second bias value VH2 and the first bias value VH1. Moreover, the voltage value of each of the first to fourth bias voltage values VH1 to VH4 is greater than the first to fourth voltage distributions VT1 to VT4. The relationship is: fourth bias value VH4>third bias value VH3>second bias value VH2>first bias value VH1>fourth voltage distribution VT4>third voltage distribution VT3>second voltage distribution VT2 >First voltage distribution VT1. That is, the first bias value VH1 with the lowest voltage value is still greater than the fourth voltage distribution VT4 with the highest voltage value. The voltage magnitude relationship between the above-mentioned first to fourth bias values VH1 to VH4 and the first to fourth voltage distributions VT1 to VT4 can be seen in Figure 2 .

The memory cell 100 can receive search data SW, where the search data SW includes a first bit S1 and a second bit S2. The search data SW can be encoded according to the first gate bias voltage Vg1 and the second gate bias voltage Vg2. That is, the search data SW is encoded according to the first to fourth bias values VH1 to VH4 of the first gate bias Vg1 and the first to fourth bias values VH1 to VH4 of the second gate bias Vg2, as shown in Table 2. Shown:

In the example of Table 2, when the first gate bias Vg1 and the second gate bias Vg2 are the first bias value VH1 and the fourth bias value VH4 respectively, the first value of the encoded search data SW is Bit S1 and the second bit S2 are "0" and "0" respectively. When the first gate bias voltage Vg1 and the second gate bias voltage Vg2 are both the fourth bias value VH4, the encoded search data SW is a wildcard WCD (wildcard).

In operation, there is a first voltage difference between the first gate bias voltage Vg1 received by the transistor M1 and the first threshold voltage Vth1 of the transistor M1, and the transistor M1 generates the current I1 according to the first voltage difference. Similarly, there is a second voltage difference between the second gate bias voltage Vg2 received by the transistor M2 and the second critical voltage Vth2 of the transistor M2, and the transistor M2 generates the current I2 according to the second voltage difference. Since the transistor M1 is connected to the transistor M2 in series, the current value of the output current Is1 generated by the memory cell 100 on the bit line BL1 is approximately equal to the smaller of the current value of the current I1 and the current I2. The output current Is1 is generated from the second source s2 of the transistor M2.

Figure 3 illustrates voltage value examples of the first to fourth bias values VH1 to VH4, the first to fourth voltage distributions VT1 to VT4, the first voltage difference and the second voltage difference. In the example in Figure 3, the first to fourth bias values VH1 to VH4 are 5.5V, 7V, 8.5V, and 10V respectively. Furthermore, the lowest voltage value of the first voltage distribution VT1 is 0V, the highest voltage value is 1V, and the peak voltage value is 0.5V. Second voltage distribution VT2 The lowest voltage value is 1.5V, the highest voltage value is 2.5V, and the peak voltage value is 2V. The lowest voltage value of the third voltage distribution VT3 is 3V, the highest voltage value is 4V, and the peak voltage value is 3.5V. The lowest voltage value of the fourth voltage distribution VT4 is 4.5V, the highest voltage value is 5.5V, and the peak voltage value is 5V.

In operation, different search data SW can be provided to search the storage data DAT stored in the memory cell 100 . Figures 4A to 4D are schematic diagrams of searching for stored data DAT with different contents when the search data SW is [0 0]. Please refer to Figure 4A first. When the search data SW is [0 0], the first gate bias Vg1 received by the transistor M1 is the first bias value VH1, and the second gate bias Vg2 received by the transistor M2 is the fourth bias value VH4. When the stored data DAT is [0 0], the first critical voltage Vth1 is the first voltage distribution VT1, and the second critical voltage Vth2 is the fourth voltage distribution VT4.

The first voltage difference between the first gate bias voltage Vg1 and the first threshold voltage Vth1 of the transistor M1 is the "gate overdrive voltage difference". When the search data SW is [0 0] and the storage data DAT is [0 0], the first gate bias Vg1 is the first bias value VH1, and the first threshold voltage Vth1 is the first voltage distribution VT1. The voltage difference between the first bias value VH1 (5.5V) and the highest voltage value (1V) of the first voltage distribution VT1 is 4.5V. That is, the first voltage difference between the first gate bias voltage Vg1 of the transistor M1 and the first threshold voltage Vth1 is 4.5V.

The voltage difference between two adjacent bias values among the first to fourth bias values VH1 ~ VH4 is defined as a predetermined level, which can be called "1 times the level", (1- level, (1L)). Similarly, for the first to fourth voltage distributions VT1~VT4, the voltage difference between the maximum voltage values of the two adjacent voltage distributions is It is also equivalent to 1 times the grade distance (1L). In the embodiment of Figure 3, the voltage difference between two adjacent bias values is 1.5V, and 1.5V is used as the predetermined step pitch (ie, one time step pitch (1L)). Accordingly, the first voltage difference 4.5V of the transistor M1 is three times the pitch (3L).

on the other hand. When the search data SW is [0 0] and the storage data DAT is [0 0], the gap between the fourth bias value VH4 (10V) of the transistor M2 and the highest voltage value (5.5V) of the fourth voltage distribution VT4 The voltage difference is 4.5V. That is, the second voltage difference between the second gate bias voltage Vg2 of the transistor M2 and the second threshold voltage Vth2 is 4.5V, which is three times the pitch (3L).

The current value of the current I1 generated by the transistor M1 corresponds to the first voltage difference of the transistor M1 (which is three times the step pitch (3L)), and the current value of the current I2 generated by the transistor M2 corresponds to the second voltage difference of the transistor M2. Voltage difference (3 times the step pitch (3L)). The current I1 is equal to the current I2, so the current value of the output current Is1 generated by the memory cell 100 is equal to the current I1 and the current I2. The gate overdrive voltage difference corresponding to the current value of the output current Is1 is 3 times the step distance (3L).

Both the stored data DAT and the search data SW are [0 0], and the mismatch distance between the stored data DAT and the search data SW is "0" (ie, a perfect match). When the storage data DAT and the search data SW completely match, the gate overdrive voltage difference corresponding to the current value of the output current Is1 is 3 times the step distance (3L).

Next, please refer to Figure 4B. When the search data SW is [0 0] and the stored data DAT is [0 1], the mismatch distance between the stored data DAT and the search data SW is "1". The first bias value VH1 (5.5V) of the transistor M1 and the second bias value The first voltage difference between the highest voltage value (2.5V) of the voltage distribution VT2 is 3V (ie, 2 times the step pitch (2L)). The second voltage difference between the fourth bias value VH4 (10V) of the transistor M2 and the highest voltage value (4V) of the third voltage distribution VT3 is 6V (ie, 4 times the step pitch (4L)).

Accordingly, the current value of the current I1 corresponds to the first voltage difference of the transistor M1 (which is 2 times the step pitch (2L)), and the current value of the current I2 corresponds to the second voltage difference of the transistor M2 (which is 4 times the step pitch (2L)). Grade distance (4L)). The current I1 is smaller than the current I2. The output current Is1 generated by the memory cell 100 is the smaller of the current I1 and the current I2. The current value of the output current Is1 is equal to the current I1. The gate overdrive voltage difference corresponding to the current value of the output current Is1 is 2 times the step pitch (2L).

Next, please refer to Figure 4C. When the search data SW is [0 0] and the stored data DAT is [1 0], the mismatch distance between the stored data DAT and the search data SW is "2". The first voltage difference between the first bias value VH1 (5.5V) of the transistor M1 and the highest voltage value (4V) of the third voltage distribution VT3 is 1.5V (ie, 1 times the step pitch (1L)). The second voltage difference between the fourth bias value VH4 (10V) of the transistor M2 and the highest voltage value (2.5V) of the second voltage distribution VT2 is 7.5V (ie, 5 times the step pitch (5L)). The current I1 is smaller than the current I2, the current value of the output current Is1 is equal to the current I1, and the gate overdrive voltage difference corresponding to the current value of the output current Is1 is 1 times the step distance (1L).

Next, please refer to Figure 4D. When the search data SW is [0 0] and the stored data DAT is [1 1], the mismatch distance between the stored data DAT and the search data SW is "3". The first bias value VH1 (5.5V) of the transistor M1 and the fourth voltage The first voltage difference between the highest voltage value (5.5V) of the voltage distribution VT4 is 0V (ie, 0 times the step pitch (0L)). The first voltage difference between the fourth bias value VH4 (10V) of the transistor M2 and the highest voltage value (1V) of the first voltage distribution VT1 is 9V (ie, 6 times the step pitch (6L)). Accordingly, the gate overdrive voltage difference corresponding to the current value of the output current Is1 is 0 times the step pitch (0L).

From the above, when the mismatch distance between the search data SW and the stored data DAT is "0", "1", "2", or "3", the current value of the output current Is1 corresponds to the gate overdrive voltage difference The grade intervals are "3L", "2L", "1L", and "0L". When the mismatch degree between the search data SW and the stored data DAT is higher, the mismatch distance is larger, and the current value of the generated output current Is1 is smaller. Accordingly, the mismatch distance and degree of mismatch between the search data SW and the stored data DAT can be determined based on the current value of the output current Is1 of the memory cell 100 .

Figures 5A to 5D are schematic diagrams of searching for stored data DAT with different contents when the search data SW is [1 0]. Please refer to Figure 5A first. When the search data SW is [1 0] and the stored data DAT is [0 0], the mismatch distance is "2". The first voltage difference between the third bias value VH3 (8.5V) of the transistor M1 and the highest voltage value (1V) of the first voltage distribution VT1 is 7.5V (ie, 5 times the step pitch (5L)). The second voltage difference between the second bias value VH2 (7V) of the transistor M2 and the highest voltage value (5.5V) of the fourth voltage distribution VT4 is 1.5V (ie, 1 times the step pitch (1L)). The gate overdrive voltage difference corresponding to the current value of the output current Is1 is 1 times the step pitch (1L).

Referring to Figure 5B, when the search data SW is [1 0] and the stored data DAT is [0 1], the mismatch distance is "1". The first voltage difference of the transistor M1 is four times the step pitch (4L), and the second voltage difference of the transistor M2 is two times the step pitch (2L). The gate overdrive voltage difference corresponding to the current value of the output current Is1 is 2 times the step pitch (2L).

Referring to Figure 5C, when the search data SW is [1 0] and the stored data DAT is [1 0], the mismatch distance is "0". The first voltage difference of the transistor M1 is three times the step pitch (3L), and the second voltage difference of the transistor M2 is three times the step pitch (3L). The gate overdrive voltage difference corresponding to the current value of the output current Is1 is 3 times the step distance (3L).

Referring to Figure 5D, when the search data SW is [1 0] and the stored data DAT is [1 1], the mismatch distance is "1". The first voltage difference of the transistor M1 is 2 times the step pitch (2L), and the second voltage difference of the transistor M2 is 4 times the step pitch (4L). The gate overdrive voltage difference corresponding to the current value of the output current Is1 is 2 times the step pitch (2L).

Based on a similar operation method, see Figures 6A~6D. When the search data SW is [0 1], if the stored data DAT is [0 0], [0 1], [1 0], [1 1] respectively , the mismatch distances are "1", "0", "1", and "2" respectively, and the gate overdrive voltage difference levels corresponding to the current value of the output current Is1 are "2L", "3L", and " "2L", "1L".

Similarly, see Figures 7A~7D. When the search data SW is [1 1], if the stored data DAT is [0 0], [0 1], [1 0], [1 1] respectively, there will be no match. The matching distances are "3", "2", "1", and "0" respectively. The gate overdrive voltage difference corresponding to the current value of the output current Is1 is "0L", "1L", and "2L" respectively. , "3L".

Figures 8A to 8D are schematic diagrams of searching for stored data DAT with different contents when the search data SW is the wildcard WCD. Please refer to Figure 8A first. When the search data SW is the wild sign WCD, the first gate bias Vg1 and the second gate bias Vg2 are both the fourth bias value VH4. When the stored data DAT is [0 0], the first voltage difference of the transistor M1 is 6 times the step pitch (6L), and the second voltage difference of the transistor M2 is 3 times the step pitch (3L). Referring to Figure 8B, when the stored data DAT is [0 1], the first voltage difference of the transistor M1 is 5 times the level (5L), and the second voltage difference of the transistor M2 is 4 times the level (4L). ). Referring to Figure 8C, when the stored data DAT is [1 0], the first voltage difference of the transistor M1 is 4 times the level (4L), and the second voltage difference of the transistor M2 is 5 times the level (5L). ). Referring to Figure 8D, when the stored data DAT is [1 1], the first voltage difference of the transistor M1 is 3 times the level (3L), and the second voltage difference of the transistor M2 is 6 times the level (6L). ).

According to this, when the stored data DAT is [0 0], [0 1], [1 0], [1 1] respectively, the gate overdrive voltage difference corresponding to the current value of the output current Is1 is " 3L", "4L", "4L", "3L". When the gate overdrive voltage difference step is "3L" or "4L", both transistors M1 and M2 operate in the saturation region. Therefore, the gate overdrive step is "4L". The current value of the output current Is1 corresponding to the voltage difference is roughly equal to the current value of the output current Is1 corresponding to the step distance "3L", both of which are related to the mismatch distance "0". Accordingly, when searching for When the data SW is the wildcard WCD, regardless of the content of the stored data DAT, the current value of the output current Is1 is related to the mismatch distance "0", and it is determined that the search data SW and the stored data DAT completely match.

Figures 9A to 9D are schematic diagrams of searching with search data SW of different contents when the stored data DAT is a random item DNC. Please refer to Figure 9A first. When the storage data DAT is an optional item DNC, both the first critical voltage Vth1 and the second critical voltage Vth2 are the first voltage distribution VT1. When the search data SW is [0 0], the first voltage difference of the transistor M1 is three times the step pitch (3L), and the second voltage difference of the transistor M2 is six times the step pitch (6L). The gate overdrive voltage difference corresponding to the current value of the output current Is1 is 3 times the step distance (3L).

Similarly, see Figure 9B, when the search data SW is [0 1], the first voltage difference of the transistor M1 is 4 times the level (4L), and the second voltage difference of the transistor M2 is 5 times the level. Distance (5L). Referring to Figure 9C, when the search data SW is [1 0], the first voltage difference of the transistor M1 is 5 times the step pitch (5L), and the second voltage difference of the transistor M2 is 4 times the step pitch (4L ). Referring to Figure 9D, when the search data SW is [1 1], the first voltage difference of the transistor M1 is 6 times the step pitch (6L), and the second voltage difference of the transistor M2 is 3 times the step pitch (3L ).

According to this, if the search data SW are [0 0], [0 1], [1 0], [1 1] respectively, the gate overdrive voltage difference corresponding to the current value of the output current Is1 is " 3L", "4L", "4L", "3L". The gate overdrive voltage difference of the step pitch "3L" or "4L" means that the transistor M1 or the transistor M2 operates in the saturation range, and the corresponding current value of the output current Is1 is related to the mismatch distance "0". Accordingly, when When the stored data DAT is an arbitrary item DNC, no matter what the content of the search data SW is, the output current Is1 is related to the mismatch distance "0", and it is determined that the search data SW and the stored data DAT completely match.

In the following, each embodiment of Figures 10, 11, and 12 will be described using transistors M1 and M2 of TLC, QLC, and N-level memory cells respectively as examples.

FIG. 10 illustrates the relationship between the voltage magnitude of the second number of bias voltage values of the transistor M1 (or the transistor M2) of the TLC and the second number of voltage distributions. As shown in Figure 10, when the transistors M1 and M2 are both TLC memory cells, the second number is equal to "8". Both the first critical voltage Vth1 and the second critical voltage Vth2 can be adjusted to 8 voltage distributions. The order according to the voltage value is: the eighth voltage distribution VT8, the seventh voltage distribution VT7, the sixth voltage distribution VT6, and the fifth voltage distribution VT5. , the fourth voltage distribution VT4, the third voltage distribution VT3, the second voltage distribution VT2, and the first voltage distribution VT1. Correspondingly, the first gate bias voltage Vg1 and the second gate bias voltage Vg2 of the transistors M1 and M2 can be adjusted to 8 bias values respectively. The order according to the voltage value is: the eighth bias value VH8, the seventh bias value VH8, and the seventh bias value Vg2. The bias value VH7, the sixth bias value VH6, the fifth bias value VH5, the fourth bias value VH4, the third bias value VH3, the second bias value VH2, and the first bias value VH1. That is, the first bias value VH1 with the lowest voltage value is still greater than the eighth voltage distribution VT8 with the highest voltage value.

Figure 11 illustrates the relationship between the voltage values of the third number of bias values of the QLC transistor M1 (or the transistor M2) and the third number of voltage distributions. As shown in Figure 11, when the transistors M1 and M2 are both QLC memory cells, the third number is equal to "16". Both the first threshold voltage Vth1 and the second threshold voltage Vth2 are adjustable It is divided into 16 voltage distributions, and the order according to the voltage value is: the sixteenth voltage distribution VT16 to the first voltage distribution VT1. Correspondingly, the first gate bias voltage Vg1 and the second gate bias voltage Vg2 of the transistors M1 and M2 can be adjusted to 16 bias values respectively. The order according to the voltage value is: the 16th bias value VH16 to the 16th bias value. A bias value VH1. That is, the first bias value VH1 with the lowest voltage value is still greater than the sixteenth voltage distribution VT16 with the highest voltage value.

Figure 12 illustrates the relationship between the fourth number of bias voltage values of the transistor M1 (or the transistor M2) of the N-level memory cell and the voltage value of the fourth number of voltage distributions. As shown in Figure 12, when the transistors M1 and M2 are both N-level memory cells, the fourth quantity is equal to "n", and n is equal to the Nth power of 2. Both the first critical voltage Vth1 and the second critical voltage Vth2 can be adjusted to n voltage distributions, and the order according to the voltage value is: nth voltage distribution VT(n) to the first voltage distribution VT1. Correspondingly, the first gate bias voltage Vg1 and the second gate bias voltage Vg2 of the transistors M1 and M2 can be adjusted to n bias values respectively, and the order according to the voltage value is: nth bias value VH(n) to the first bias value VH1. That is, the first bias value VH1 with the lowest voltage value is still larger than the nth voltage distribution VT(n) with the highest voltage value.

FIG. 13 is a schematic diagram of a memory device 1000 according to an embodiment of the present disclosure. The memory device 1000 includes a plurality of memory cells arranged in N vertical rows and M horizontal columns. The memory cells in each vertical row form a NAND memory string. For example, the memory cells 100-1, 100-2, ..., 100-M in the first vertical row form a NAND memory string. Among them, the memory cell 100-1 is connected to the first word line WL1(1) and the second word line WL1(2) of the first group of word lines WL1, and the memory cell 100-2 is connected to The first word line WL2(1) and the second word line WL2(2) of the second group of word lines WL2. By analogy, the memory cell 100-M is connected to the first word line WLM(1) and the second word line WLM(2) of the M-th group.

The memory cells 100-1, 100-2, ..., 100-M are jointly connected to the first bit line BL1 and generate an output current Is1. A sensing amplifier (SA) 600-1 is connected to the bit line BL1 to receive the output current Is1. Similarly, the memory cells in the second vertical row are commonly connected to the second bit line BL2, and the sense amplifier 600-2 is connected to the bit line BL2 to receive the output current Is2. The memory cells in the Nth vertical row are commonly connected to the Nth bit line BLN, and the sense amplifier 600-N is connected to the bit line BLN to receive the output current IsN.

The bit line driving circuit 400 is connected to the bit lines BL1, BL2, ..., BLN. The word line driving circuit 500 is connected to the first word lines WL1(1), WL2(1), ..., WLM(1) and the second word lines WL1(2), WL2(2), ... ,WLM(2). The word line driver circuit 500 can be used as a search buffer to temporarily store the search data SW.

Taking the memory device 1000 with M=24 and N=8 as an example, it includes 8 vertical rows and 24 horizontal columns of memory cells. The transistors M1 and M2 of each memory cell are MLC memory cells. These memory cells form 8 NAND memory strings. In the example of Table 3, the search data SW=[0 0] is provided to search the storage data DAT stored in the memory device 1000 with M=24 and N=8: Table 3

As shown in Table 3, when the search data SW is [0 0], the second gate bias Vg2 is the fourth bias value VH4, and the first gate bias Vg1 is the first bias value VH1. For the NAND memory string of bit line BL1, the stored data DAT of each memory cell is [0 0], and the first and second critical voltages Vth1 and Vth2 are [VT4 VT1]. Accordingly, the stored data DAT of each memory cell of bit line BL1 completely matches the search data SW. The mismatch distance of each memory cell of bit line BL1 is "0". The current value of the output current Is1 of each memory cell corresponds to the gate overdrive voltage difference step pitch of "3L". The total current value corresponding to the output current Is1 is "72L" (ie, 24×3L). The level distance corresponding to the mismatch distance is "0L".

For the NAND memory string of bit line BL2, the stored data DAT of each memory cell is [0 1], and the first and second critical voltages Vth1 and Vth2 are [VT3 VT2]. The mismatch distance of each memory cell is "1", and the current value corresponding to the output current Is1 of each memory cell is "2L". The total current value of the output current Is2 of the bit line BL2 corresponds to a total step pitch of "48L" (ie, 24×2L), which is smaller than the output current Is1 of the bit line BL1. The corresponding level distance of the mismatch distance is "24L".

The stored data DAT of each memory cell of bit line BL3 is [1 0], and the first and second critical voltages Vth1 and Vth2 are [VT2 VT3]. every The mismatch distance of the memory cell is "2", and the current value corresponding to the output current Is1 of each memory cell is "1L". The total current value corresponding to the total current value of the output current Is3 of the bit line BL3 is "24L" (ie, 24×1L), which is smaller than the output current Is2 of the bit line BL2. The level of mismatch distance is "48L".

The stored data DAT of each memory cell of bit line BL4 is [1 1], and the first and second critical voltages Vth1 and Vth2 are [VT1 VT4]. The mismatch distance of each memory cell is "3", and the current value corresponding to the output current Is1 of each memory cell is "0L". The total current value corresponding to the total current value of the output current Is4 of the bit line BL4 is "0L" (ie, 24×0L), which is smaller than the output current Is3 of the bit line BL3. The level of mismatch distance is "72L".

The storage data DAT of the memory cells of the 1st to 12th group of word lines WL1 to WL12 corresponding to the bit line BL52 are all [0 0], the first and second critical voltages Vth1 and Vth2 are [VT4 VT1], and the mismatch distance is "0", the current value corresponding to the output current Is1 is "3L". The storage data DAT of the memory cells of the 13th to 24th group of word lines WL13 to WL24 corresponding to the bit line BL5 are all [0 1], the first and second critical voltages Vth1 and Vth2 are [VT3 VT2], and the mismatch distance is "1", and the current value corresponding to the output current Is1 is "2L". The total current value corresponding to the total current value of the output current Is5 of the bit line BL5 is "60L" (ie, 12×3L+12×2L). The level of mismatch distance is "12L".

The storage data DAT of the memory cells of the 1st to 18th group of word lines WL1 to WL18 of the bit line BL6 are all [0 0], the mismatch distance is "0", and the corresponding level distance of the current value of the output current Is1 is " 3L". The 19th~24th group of words of bit line BL6 The storage data DAT of the memory cells of element lines WL19~WL24 are all [0 1], the mismatch distance is "1", and the corresponding step distance of the current value of the output current Is1 is "2L". The total current value corresponding to the total current value of the output current Is6 of the bit line BL6 is "66L" (ie, 18×3L+6×2L). The level of mismatch distance is "6L".

The storage data DAT of the memory cells of the 1st to 21st groups of word lines WL1 to WL21 of the bit line BL7 are all [0 0], the mismatch distance is "0", and the corresponding level distance of the current value of the output current Is1 is " 3L". The storage data DAT of the memory cells of the 22nd to 24th group of word lines WL22 to WL24 of the bit line BL7 are all [1 0], the mismatch distance is "2", and the corresponding step distance of the current value of the output current Is1 is " 1L". The total current value corresponding to the total current value of the output current Is7 of the bit line BL7 is "66L" (ie, 21×3L+3×1L). The level of mismatch distance is "6L".

The storage data DAT of the memory cells of the 1st to 22nd groups of word lines WL1 to WL22 of the bit line BL8 are all [0 0], the mismatch distance is "0", and the corresponding step distance of the current value of the output current Is1 is " 3L". The storage data DAT of the memory cells of the 23rd and 24th groups of word lines WL23 and WL24 of the bit line BL8 are both [1 1], the mismatch distance is "3", and the corresponding step distance of the current value of the output current Is1 is " 0L". The total current value corresponding to the total current value of the output current Is8 of the bit line BL8 is "66L" (ie, 22×3L+2×0L). The level of mismatch distance is "6L".

According to the example of Table 3, when the respective stored data DAT and the search data SW of the bit lines BL1 ~ BL8 have different matching degrees, the respective output currents Is1 ~ Is8 of the bit lines BL1 ~ BL8 have different total current values. can be based on The total current value of the output currents Is1 ~ Is8 is used to calculate the respective matching degrees of the bit lines BL1 ~ BL8 to achieve the technical effect of approximate matching.

FIG. 14A illustrates another example of the first to fourth bias values VH1 to VH4 and the voltage values of the first to fourth voltage distributions VT1 to VT4. The example in Figure 14A is similar to the example in Figure 3 . The difference is that in the example in Figure 14A , the voltage between two adjacent bias values among the first to fourth bias values VH1 ~ VH4 The difference is 1V. That is, 1 times the pitch (1L) is 1V.

Moreover, the voltage difference between the peak voltage values of two adjacent voltage distributions of the first to fourth voltage distributions VT1 to VT4 is 1V, and the voltage difference between the highest voltage values of two adjacent voltage distributions is 1V. And the voltage difference between the lowest voltage values of two adjacent voltage distributions is also 1V. Furthermore, the first bias value VH1 is equal to the peak voltage value of the fourth voltage distribution VT4 (which is 5V).

Figure 14B shows another example of the first to fourth bias values VH1 to VH4 and the voltage values of the first to fourth voltage distributions VT1 to VT4. The example of FIG. 14B is similar to the example of FIG. 14A , except that in the example of FIG. 14B , the first bias value VH1 is equal to the lowest voltage value of the fourth voltage distribution VT4 (which is 4.5V).

Although the present invention has been disclosed in detail above with preferred embodiments and examples, it should be understood that these examples are meant to be illustrative rather than limiting. It is expected that those with ordinary skill in the art can think of various modifications and combinations, and the various modifications and combinations fall within the spirit of the present invention and the scope of the appended patent application.

VH1: first bias value

VH2: second bias value

VH3: third bias value

VH4: The fourth bias value

VT1: first voltage distribution

VT2: Second voltage distribution

VT3: The third voltage distribution

VT4: The fourth voltage distribution

1L: 1 times the grade distance

2L: 2 times the grade span

3L: 3 times the grade span

4L: 4 times the grade pitch

5L: 5 times the step distance

6L: 6 times the grade pitch

Claims (16)

A memory device, the memory device includes a plurality of memory cells, each memory cell stores a storage data and receives a search data, each memory cell includes: a first transistor, has a first critical voltage and receives a first a gate bias; and a second transistor connected to the first transistor, the second transistor having a second threshold voltage and receiving a second gate bias; wherein the stored data is based on the first transistor. A threshold voltage and the second threshold voltage are encoded, the search data is encoded according to the first gate bias voltage and the second gate bias voltage, and there is a mismatch between the stored data and the search data. distance, and the mismatch distance has a plurality of values, and the plurality of current values of an output current generated by each memory cell respectively correspond to the values of the mismatch distance. The memory device of claim 1, wherein: the first threshold voltage and the second threshold voltage each have a plurality of voltage distributions, and the first gate bias voltage and the second gate bias voltage each have a plurality of voltage distributions. bias values, the number of the voltage distributions is equal to a first number, the number of the bias values is equal to the first number; and the stored data is encoded according to the first number of the voltage distributions, The search data is encoded according to the first number of bias values. The memory device of claim 2, wherein both the first transistor and the second transistor are second-level memory cells (MLC), the first number is equal to "four", and the stored data has two bits , the search data has two bits. The memory device of claim 2, wherein the first transistor and the second transistor are third-level memory cells (TLC), and the first number is equal to "eight". The memory device of claim 2, wherein both the first transistor and the second transistor are fourth-level memory cells (QLC), and the first number is equal to "sixteen". The memory device of claim 3, wherein the first number of voltage distributions includes: a first voltage distribution, a second voltage distribution, a third voltage distribution and a fourth voltage distribution, the fourth voltage distribution The voltage value of the voltage distribution is the highest, and the voltage value of the first voltage distribution is the lowest; wherein, when the first critical voltage has the first voltage distribution and the second critical voltage has the first voltage distribution, the stored data is encoded For an arbitrary item, the search data exactly matches the stored data, and the mismatch distance is "0". The memory device of claim 3, wherein the first number of bias values includes: a first bias value, a second bias value, a third bias value and a fourth bias value. value, the voltage value of the fourth bias value is the highest, and the voltage value of the first bias value is the lowest; wherein, when the first gate bias has the fourth bias value and the second gate bias has At the fourth bias value, the search data is encoded as a wildcard, the search data completely matches the stored data, and the mismatch distance is "0". The memory device of claim 1, wherein the first transistor has a first gate, a first drain and a first source, and the second transistor has a second gate, a first source. Two drains and a second source; wherein, the first gate of the first transistor is connected to a first word line to receive the first gate bias, and the second gate of the second transistor The gate is connected to a second word line to receive the second gate bias, the first drain of the first transistor is connected to a bit line, and the first source of the first transistor is connected to At the second drain of the second transistor, the second source of the second transistor outputs the output current. The memory device of claim 2, wherein there is a first voltage difference between the first gate bias voltage of the first transistor and the first critical voltage, and the second gate bias voltage of the second transistor There is a second voltage difference between the extreme bias voltage and the second critical voltage, and the smaller of the first voltage difference and the second voltage difference is related to the current values of the output current. The memory device of claim 9, wherein a voltage difference between two adjacent bias values among the bias values is equal to a predetermined interval, and two adjacent bias values among the voltage distributions are A voltage difference between the maximum voltage values of the respective voltage distributions is equal to the predetermined step distance, the first voltage difference is equal to an integer multiple of the predetermined step distance, and the second voltage difference is equal to an integer multiple of the predetermined step distance. . The memory device of claim 10, wherein both the first transistor and the second transistor are second-level memory cells (MLC), and when the search data completely matches the stored data, the mismatch distance is " 0", the first voltage difference is equal to three times of the predetermined level span, and the second voltage difference is equal to three times of the predetermined level span. A data search method for a memory, the memory includes a plurality of memory cells, each memory cell includes a first transistor and a second transistor, the data search method includes: according to the first transistor A first threshold voltage and a second threshold voltage of the second transistor encode a stored data; and a first gate bias voltage and a second gate bias encode a search data, the stored data and the search There is a mismatch distance between the data, and the mismatch distance has a plurality of values, wherein the plurality of current values of an output current generated by each memory cell respectively correspond to the values of the mismatch distance. The data search method as described in claim 12, wherein both the first critical voltage and the second critical voltage have a plurality of voltage distributions, and the number of these voltage distributions is equal to a first number, the data search method includes: according to The first number of voltage distributions encodes the stored data. The data search method as described in claim 13, wherein both the first transistor and the second transistor are second-level memory cells (MLC), the first number is equal to "four", and the first number of voltages The distribution includes a first voltage distribution, a second voltage distribution, a third voltage distribution and a fourth voltage distribution, and the data search method includes: programming the first critical voltage to be the first voltage distribution; programming the second critical voltage The voltage is the first voltage distribution; the stored data is encoded as a random item according to the first critical voltage and the second critical voltage; the mismatch distance is determined to be "0"; and the search data is determined to completely match the stored data . The data search method as described in claim 14, wherein both the first gate bias voltage and the second gate bias voltage have a plurality of bias values, and the number of the bias values is equal to the first number, and the The data search method includes: encoding the search data according to the first number of bias values. The data search method as claimed in claim 15, wherein the first number of bias values includes a first bias value, a second bias value, a third bias value and a fourth bias value. , the data search method includes: using the fourth bias value as the first gate bias; using the fourth bias value as the second gate bias; based on the first gate bias and the third gate bias. Two gate biases encode the search data as a wildcard; determine the mismatch distance as "0"; and determine that the search data completely matches the stored data.

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