TWI826921B - semiconductor memory device - Google Patents

Abstract

Embodiments provide a semiconductor memory device with good characteristics. The semiconductor memory device of the embodiment includes: a substrate; a plurality of first conductive layers arranged at a first pitch in a first direction crossing the surface of the substrate; a plurality of second conductive layers disposed on the substrate and a plurality of between the first conductive layers and arranged at a second pitch in the first direction; a plurality of third conductive layers arranged between the substrate and a plurality of second conductive layers and arranged at a third pitch in the first direction arranged at intervals; and a semiconductor layer extending in a first direction and facing a plurality of first conductive layers, a plurality of second conductive layers and a plurality of third conductive layers. The semiconductor layer includes: a first region extending in the first direction and facing a plurality of first conductive layers and a plurality of second conductive layers; and a second region extending in the first direction and facing a plurality of second conductive layers. 3 conductive layers facing each other. The second pitch is larger than the first pitch and the third pitch.

Description

semiconductor memory device

This embodiment relates to a semiconductor memory device.

A semiconductor memory device is known which includes: a substrate; a plurality of first conductive layers arranged in a first direction crossing the surface of the substrate; and a semiconductor layer extending in the first direction and connected to a plurality of first conductive layers. 1 conductive layer facing each other.

Embodiments provide a semiconductor memory device with good characteristics.

A semiconductor memory device according to one embodiment includes: a substrate; a plurality of first conductive layers arranged at a first pitch in a first direction crossing the surface of the substrate; and a plurality of second conductive layers disposed between the substrate and the plurality of between a plurality of first conductive layers and arranged at a second pitch in the first direction; a plurality of third conductive layers arranged between the substrate and a plurality of second conductive layers and arranged at a second pitch in the first direction arranged at 3 pitches; and a semiconductor layer extending in a first direction and facing a plurality of first conductive layers, a plurality of second conductive layers and a plurality of third conductive layers. The semiconductor layer includes: a first region extending in the first direction and facing a plurality of first conductive layers and a plurality of second conductive layers; and a second region extending in the first direction and facing a plurality of second conductive layers. 3 conductive layers facing each other. The second pitch is larger than the first pitch and the third pitch.

Next, the semiconductor memory device according to the embodiment will be described in detail with reference to the drawings. In addition, the following embodiment is only an example, and is not intended to limit this invention. In addition, the following drawings are schematic diagrams, and some components may be omitted for convenience of explanation. In addition, common parts in a plurality of embodiments are denoted by the same reference numerals, and descriptions may be omitted.

In addition, when "semiconductor memory device" is mentioned in this specification, it sometimes refers to memory chips, and sometimes refers to memory chips, memory cards, SSD (Solid State Drive, solid state drive), etc. including controller chips. Granular memory system. Furthermore, it sometimes refers to the configuration including the host computer such as smartphones, tablet terminals, and personal computers.

Furthermore, in this specification, when it is said that the first configuration is "connected between" the second configuration and the third configuration, it may mean that the first configuration, the second configuration, and the third configuration are connected in series, and that the third configuration is connected in series. The two configurations are connected to the third configuration via the first configuration.

In addition, in this specification, the specific direction parallel to the upper surface of the substrate is called the X direction, the direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and the direction perpendicular to the upper surface of the substrate is called the Y direction. Z direction.

Furthermore, in this specification, the direction along a specific surface may be referred to as the first direction, the direction along the specific surface intersecting the first direction may be referred to as the second direction, and the direction intersecting the specific surface may be referred to as the second direction. The direction is called the 3rd direction. The first direction, the second direction and the third direction may or may not correspond to any one of the X direction, the Y direction and the Z direction.

In addition, in this specification, expressions such as "upper" or "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called upward, and the direction toward the substrate along the Z direction is called down. Furthermore, when a lower surface or lower end is mentioned for a certain component, it refers to the surface or end of the component on the side of the substrate. When an upper surface or upper end is mentioned, it refers to the surface or end of the component on the opposite side to the substrate. department. In addition, the surface intersecting the X direction or the Y direction is called a side surface, etc.

In addition, in this specification, when referring to the "width", "length" or "film thickness" in a specific direction regarding the structure, members, etc., this may refer to the measurement by SEM (Scanning electron microscopy, scanning electron microscope). Or the width, length or thickness of the cross-section observed by TEM (Transmission electron microscopy), etc.

[First Embodiment] FIG. 1 is a schematic circuit diagram showing a part of the structure of a semiconductor memory device according to the first embodiment. The semiconductor memory device of the first embodiment includes a memory cell array MCA and a peripheral circuit PC.

The memory cell array MCA has a plurality of memory blocks BLK. Each of the plurality of memory blocks BLK has a plurality of string units SU. Each of the plurality of string units SU has a plurality of memory strings MS. One ends of the plurality of memory strings MS are respectively connected to the peripheral circuit PC via bit lines BL. In addition, the other ends of the plurality of memory strings MS are respectively connected to the peripheral circuit PC through a common source line SL.

The memory string MS includes a drain-side selection transistor STD, a plurality of memory cells MC (memory transistors), and a source-side selection transistor STS. The drain side selection transistor STD, the plurality of memory cells MC and the source side selection transistor STS are connected between the bit line BL and the source line SL. Hereinafter, the drain-side selection transistor STD and the source-side selection transistor STS may be simply referred to as selection transistors (STD, STS).

Memory cell MC is a field effect transistor. The memory cell MC has a semiconductor layer, a gate insulating film and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film contains a charge accumulation film. The threshold voltage of the memory cell MC changes according to the amount of charge in the charge accumulation film. The memory cell MC stores one or more bits of data. In addition, the gate electrodes of a plurality of memory cells MC corresponding to one memory string MS are respectively connected to word lines WL. The word lines WL are respectively commonly connected to all memory strings MS in a memory block BLK.

Selective transistors (STD, STS) are field-effect transistors. Selective transistors (STD, STS) include a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate electrodes of the selection transistors (STD, STS) are respectively connected to the selection gate lines (SGD, SGS). A drain-side select gate line SGD is commonly connected to all memory strings MS in a string unit SU. A source-side select gate line SGS is commonly connected to all memory strings MS in a memory block BLK.

The peripheral circuit PC includes, for example, a voltage generation circuit that generates an operating voltage, and transmits the generated operating voltage to the selected bit line BL, word line WL, source line SL, select gate line (SGD, SGS), etc. The voltage transmission circuit, the sense amplifier module connected to the bit line BL, and the sequencer that controls them.

FIG. 2 is a schematic plan view showing a part of the structure of the semiconductor memory device according to the first embodiment. The semiconductor memory device of this embodiment includes a semiconductor substrate 100. The semiconductor substrate 100 is, for example, a semiconductor substrate including P-type silicon (Si) containing P-type impurities such as boron (B). In the illustrated example, the semiconductor substrate 100 is provided with four memory cell array areas R _MCA arranged in the X direction and the Y direction. In addition, a plurality of memory blocks BLK arranged in the Y direction are provided in each memory cell array area R _MCA .

FIG. 3 is a schematic perspective view showing a part of the structure of the semiconductor memory device according to the first embodiment. FIG. 4 is a schematic plan view showing a part of the structure of the semiconductor memory device according to the first embodiment. FIG. 5 is a schematic cross-sectional view of the structure shown in FIG. 4 taken along line BB' and viewed in the direction of the arrow. FIG. 6 is a schematic cross-sectional view enlarging area D shown in FIG. 5 .

For example, as shown in FIG. 3 , the semiconductor memory device of this embodiment includes a transistor layer L _TR disposed on the semiconductor substrate 100 and a memory cell array layer L _MCA disposed above the transistor layer L _TR .

[Structure of transistor layer L _TR ] For example, as shown in FIG. 3 , a wiring layer GC is provided on the upper surface of the semiconductor substrate 100 via an insulating layer (not shown). The wiring layer GC includes a plurality of electrodes gc facing the surface of the semiconductor substrate 100 . In addition, the plurality of electrodes gc included in each region of the semiconductor substrate 100 and the wiring layer GC are respectively connected to the contacts CS.

Each of the plurality of electrodes gc faces the surface of the semiconductor substrate 100 and functions as a gate electrode of a plurality of transistors Tr constituting the peripheral circuit PC, an electrode of a plurality of capacitors, and the like.

The plurality of contacts CS extend in the Z direction and are connected to the upper surface of the semiconductor substrate 100 or the electrode gc at the lower end. An impurity region containing N-type impurities or P-type impurities is provided at a connection portion between the contact CS and the semiconductor substrate 100 . The contact CS may include, for example, a laminated film including a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

The wiring layers D0, D1, and D2 respectively include a plurality of wirings, and the plurality of wirings are electrically connected to at least one of the components in the memory cell array MCA and the component in the peripheral circuit PC. The plurality of wirings may include, for example, a laminated film including a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[Structure of Memory Cell Array Layer L _MCA ] For example, as shown in FIG. 3 , a memory block BLK is provided in the memory cell array layer L _MCA .

In the example of Figure 4, the memory block BLK has five string units SUa~ arranged from one side of the Y direction (the positive side of the Y direction in Figure 4) to the other side of the Y direction (the negative side of the Y direction in Figure 4). Sue. The plurality of string units SUa to SUe respectively correspond to the string units SU described with reference to FIG. 1 . An inter-string unit insulating layer SHE of silicon oxide (SiO ₂ ) or the like is provided between two adjacent string units SU in the Y direction. An inter-block structure ST is provided between two adjacent memory blocks BLK in the Y direction.

As shown in FIGS. 3 and 5 , in the memory cell array layer L _MCA , the memory block BLK includes a memory cell array layer L _MCA1 and a memory cell array layer L _MCA2 disposed above the memory cell array layer L _MCA1 . The memory cell array layer L _MCA1 and the memory cell array layer L _MCA2 include a plurality of conductive layers 110 arranged in the Z direction, a plurality of semiconductor layers 120 extending in the Z direction, and are provided on the plurality of conductive layers 110 and the plurality of semiconductor layers. A plurality of gate insulating films 130 between 120 .

The conductive layer 110 is a substantially plate-shaped conductive layer extending in the X direction. As shown in FIG. 6 , the conductive layer 110 may also include a laminated film including a barrier conductive film 116 such as titanium nitride (TiN) and a metal film 115 such as tungsten (W). In addition, an insulating metal oxide film 134 such as aluminum oxide (AlO) may be provided at a position covering the outer periphery of the barrier conductive film 116 . In addition, the conductive layer 110 may include, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). Contact points CC are respectively provided at the ends of the plurality of conductive layers 110 in the X direction (Fig. 3). An insulating layer 101 of silicon oxide (SiO ₂ ) or the like is provided between a plurality of conductive layers 110 arranged in the Z direction.

As shown in FIG. 5 , a semiconductor layer 111 , a semiconductor layer 113 and a semiconductor layer 112 are provided below the plurality of conductive layers 110 with the insulating layer 101 interposed therebetween. A part of the gate insulating film 130 is provided between the semiconductor layer 111 and the semiconductor layer 112 and the semiconductor layer 120 . The semiconductor layer 113 is connected to the lower end of the semiconductor layer 120 .

The upper surface of the semiconductor layer 113 is connected to the semiconductor layer 111 , and the lower surface is connected to the semiconductor layer 112 . A conductive layer 114 may also be provided on the lower surface of the semiconductor layer 112 . The semiconductor layer 111, the semiconductor layer 113, the semiconductor layer 112, and the conductive layer 114 function as the source line SL (FIG. 1). The source line SL is, for example, commonly provided for all memory blocks BLK included in the memory cell array area R _MCA (FIG. 2). The semiconductor layer 111 , the semiconductor layer 113 and the semiconductor layer 112 include, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). The conductive layer 114 may also include, for example, a metal such as tungsten (W), a conductive layer such as tungsten silicide, or other conductive layers.

The conductive layer 110 located at the bottom among the conductive layers 110 of the memory cell array layer L _MCA1 serves as the source-side selection gate line SGS (Fig. 1) and the plurality of source-side selection transistors STS (Fig. 1) connected thereto. The gate electrode in Figure 1) functions. The conductive layer 110 is electrically independent for each memory block BLK.

In addition, among the plurality of conductive layers 110 provided in the memory cell array layer L _MCA1 , one or a plurality of conductive layers 110 located above the above-mentioned conductive layer are provided as dummies. Hereinafter, such conductive layer 110 is referred to as dummy conductive layer 110DM. The dummy conductive layer 110DM does not function as the select gate lines (SGD, SGS) and word lines WL. There is no memory cell MC for recording data between the dummy conductive layer 110DM and the semiconductor layer 120 .

In addition, among the plurality of conductive layers 110 provided in the memory cell array layer L _MCA1 , the plurality of conductive layers 110 located above the above-mentioned conductive layer serve as the word line WL (Fig. 1) and the plurality of memory cells MC connected thereto (Fig. 1 ) gate electrode functions. Memory cells MC for performing data recording operations are disposed between the conductive layers 110 and the semiconductor layers 120 . The plurality of conductive layers 110 are electrically independent for each memory block BLK.

In addition, the lowermost one or the plurality of conductive layers 110 among the plurality of conductive layers 110 provided in the memory cell array layer L _MCA2 is the dummy conductive layer 110DM.

In addition, among the plurality of conductive layers 110 provided in the memory cell array layer L _MCA2 , the plurality of conductive layers 110 located above the above-mentioned conductive layer serve as the word line WL (Fig. 1) and the plurality of memory cells MC connected thereto (Fig. 1 ) gate electrode functions. Memory cells MC for performing data recording operations are disposed between the conductive layers 110 and the semiconductor layers 120 . The plurality of conductive layers 110 are electrically independent for each memory block BLK.

In addition, one or a plurality of conductive layers 110 located above the above-mentioned conductive layer function as the gate electrode of the drain-side selection gate line SGD (FIG. 1) and the plurality of drain-side selection transistors STD (FIG. 1) connected thereto. Function. The width of the plurality of conductive layers 110 in the Y direction is smaller than that of other conductive layers 110 . In addition, an inter-string unit insulating layer SHE is provided between two adjacent conductive layers 110 in the Y direction. The plurality of conductive layers 110 are electrically independent for each string unit SU.

For example, as shown in FIG. 3 and FIG. 4 , the semiconductor layer 120 is arranged in a specific pattern in the X direction and the Y direction. The semiconductor layer 120 functions as a channel region for a plurality of memory cells MC and selection transistors (STD, STS) included in a memory string MS (FIG. 1). The semiconductor layer 120 is, for example, a semiconductor layer made of polycrystalline silicon (Si) or the like. For example, as shown in FIG. 3 , the semiconductor layer 120 has a substantially bottomed cylindrical shape, and an insulating layer 125 of silicon oxide or the like is provided in the center.

As shown in FIG. 5 , the semiconductor layer 120 includes a semiconductor region 120 _L included in the memory cell array layer L _MCA1 and a semiconductor region 120 _U included in the memory cell array layer L _MCA2 . Furthermore, the semiconductor layer 120 includes: a semiconductor region 120 _J connected to the upper end of the semiconductor region 120 _L and a lower end of the semiconductor region 120 _U ; an impurity region 122 connected to the lower end of the semiconductor region 120 _L ; and an impurity region 121 connected to on the upper end of the semiconductor region 120 _U.

The semiconductor region 120 _L is a substantially cylindrical region extending in the Z direction. The outer peripheral surface of the semiconductor region 120 _L is surrounded by a plurality of conductive layers 110 included in the memory cell array layer L _MCA1 and is opposed to the plurality of conductive layers 110 .

The semiconductor region 120 _U is a substantially cylindrical region extending in the Z direction. The outer peripheral surface of the semiconductor region 120 _U is surrounded by a plurality of conductive layers 110 included in the memory cell array layer L _MCA2 and faces the plurality of conductive layers 110 .

The semiconductor region 120 _J is disposed above the plurality of conductive layers 110 included in the memory cell array layer L _MCA1 and disposed below the plurality of conductive layers 110 included in the memory cell array layer L _MCA2 .

The impurity region 122 is connected to the semiconductor layer 113 . The impurity region 122 contains, for example, N-type impurities such as phosphorus (P) or P-type impurities such as boron (B). The portion of the semiconductor layer 120 located directly above the impurity region 122 functions as a channel region of the source-side selection transistor STS.

The impurity region 121 contains, for example, N-type impurities such as phosphorus (P). The impurity region 121 is connected to the bit line BL via the contact point Ch and the contact point Vy (FIG. 3).

The gate insulating film 130 has a substantially bottomed cylindrical shape covering the outer peripheral surface of the semiconductor layer 120 . For example, as shown in FIG. 6 , the gate insulating film 130 includes a tunnel insulating film 131 , a charge accumulation film 132 and a barrier insulating film 133 laminated between the semiconductor layer 120 and the conductive layer 110 . The tunnel insulating film 131 and the barrier insulating film 133 are, for example, insulating films of silicon oxide (SiO ₂ ). The charge accumulation film 132 is, for example, silicon nitride (Si ₃ N ₄ ) or the like, and is a film capable of accumulating charges. The tunnel insulating film 131 , the charge accumulation film 132 and the barrier insulating film 133 have a substantially cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor layer 120 .

In addition, the gate insulating film 130 may include a floating gate made of polycrystalline silicon containing N-type or P-type impurities, for example.

The inter-block structure ST extends in the Z direction and the X direction, and divides the plurality of insulating layers 101 , the plurality of conductive layers 110 , the semiconductor layer 111 and the semiconductor layer 113 in the Y direction to reach the semiconductor layer 112 . The inter-block structure ST is, for example, an insulating layer of silicon oxide (SiO ₂ ). In addition, the inter-block structure ST may also include a conductive layer such as tungsten extending in the X and Z directions in the center of the Y direction, and the lower end of the conductive layer may also be connected to the semiconductor layer 112 .

[Radial Widths of Semiconductor Regions 120 _L , 120 _U , and 120 _J ] Next, the radial widths of the semiconductor regions 120 _L , 120 _U , and 120 _J will be described. Hereinafter, in this specification, the width of the semiconductor layer in the X direction and the Y direction respectively intersecting the Z direction, which is the extension direction of the semiconductor regions 120 _L and 120 _U , is referred to as the width in the radial direction. In addition, for convenience of explanation, the width in the Y direction is shown as the width in the radial direction in FIG. 5 and other figures.

The radial width W 120LL of the lower end of the semiconductor region 120 _L (for example, the portion located below the plurality of conductive layers 110 included in the memory cell array layer L _MCA1 ) is smaller than the upper end of the semiconductor region _{120 L} (for example, , the width W _120LU in the radial direction of the portion located above the plurality of conductive layers 110 included in the memory cell array layer L _MCA1 ). That is, the semiconductor region 120 _L is provided such that the closer it is to the bottom of the substrate, the smaller its radial width becomes.

The radial width _{W 120UL of the lower end of the semiconductor region 120 U} (for example, the portion located below the plurality of conductive layers 110 included in the memory cell array layer L _MCA2 ) is smaller than the upper end of the semiconductor region _{120 U} (for example, , the width in the radial direction W _120UU (the portion located above the plurality of conductive layers 110 included in the memory cell array layer L _MCA2 ). That is, the semiconductor region 120 _U is provided such that its radial width is smaller as it is closer to the substrate and below the semiconductor region 120 _J , and its radial width is the smallest near right above the semiconductor region 120 _J.

The radial width W _120J of the semiconductor region 120 _J is set larger than the radial width W _120LL , W _120LU , W _120UL , and W _120UU of any one of the semiconductor regions 120 _L and 120 _U .

[The distance between the plurality of conductive layers 110] Next, the distance between the plurality of conductive layers 110 in the Z direction will be described. In addition, in the following description, the distance between two adjacent conductive layers 110 in the Z direction among the plurality of conductive layers 110 is called a pitch. In this case, the pitch may represent the film thickness of the insulating layer 101 provided between two adjacent conductive layers 110 or the like in the Z direction.

For example, as shown in FIG. 5 , among the plurality of conductive layers 110 disposed on the memory cell array layer L _MCA2 , the conductive layers 110 disposed relatively above are arranged at a first pitch D ₁₁₁ in the Z direction. In addition, among the plurality of conductive layers 110 disposed in the memory cell array layer L _MCA2 , the conductive layers 110 disposed relatively below are arranged at the second pitch D ₁₁₂ in the Z direction, and the dummy conductive layer 110DM and the conductive layer directly above it are arranged. 110 are similarly arranged at the second pitch D ₁₁₂ in the Z direction. In addition, in the memory cell array layer L _MCA1 , a plurality of conductive layers 110 are arranged at a third pitch D ₁₁₃ in the Z direction. Likewise, the dummy conductive layer 110DM and the conductive layer 110 directly above it are arranged at a third pitch D 113 in the Z direction. Spacing D ₁₁₃ arranged. The second distance D ₁₁₂ is larger than the first distance D ₁₁₁ and the third distance D ₁₁₃ .

In this structure, the film thickness of the plurality of insulating layers 101 in the area where the conductive layers 110 are arranged at the second pitch D ₁₁₂ is greater than the thickness of the plurality of insulating layers 101 in the area where the conductive layers 110 are arranged at the first pitch D ₁₁₁ and the third pitch D ₁₁₃ The film thickness of the insulating layer 101.

[Film thickness of the plurality of conductive layers 110] Also, for example, in FIG. 5, among the plurality of conductive layers 110 provided in the memory cell array layer L _MCA2 , the film in the Z direction of the conductive layer 110 provided relatively above is The thickness is shown as the first film thickness T ₁₁₁ . In addition, the film thickness in the Z direction of the conductive layer 110 provided at the relatively lower position among the plurality of conductive layers 110 provided in the memory cell array layer L _MCA2 is shown as the second film thickness T ₁₁₂ . In addition, the film thickness in the Z direction of the plurality of conductive layers 110 provided in the memory cell array layer L _MCA1 is shown as the third film thickness T ₁₁₃ . The first film thickness T ₁₁₁ , the second film thickness T ₁₁₂ and the third film thickness T ₁₁₃ are about the same film thickness.

[Manufacturing method] Next, the manufacturing method of the semiconductor memory device according to the first embodiment will be described with reference to FIGS. 7 to 20 . 7 to 20 are schematic cross-sectional views for explaining this manufacturing method, showing a cross-section corresponding to FIG. 5 .

When manufacturing the semiconductor memory device of the first embodiment, first, the transistor layer L _TR (FIG. 3) including the peripheral circuit PC (FIG. 1) is formed on the semiconductor substrate 100.

Next, as shown in _FIG . 7 , a conductive layer 114, a semiconductor layer 112, a sacrificial layer 113A of silicon oxide, etc., a sacrificial layer 113B of silicon nitride, etc., and a sacrificial layer 113C of silicon oxide, etc. are formed on the transistor layer L TR. , and semiconductor layer 111. In addition, a plurality of insulating layers 101 and a plurality of sacrificial layers 110A are alternately formed to form an insulating layer 151 of silicon oxide or the like. In addition, the plurality of insulating layers 101 are each provided with a film thickness that is approximately the same as the third pitch D ₁₁₃ . In addition, each of the plurality of sacrificial layers 110A is provided with a film thickness that is approximately the same as the third film thickness T ₁₁₃ . This process is performed, for example, by a method such as CVD (Chemical Vapor Deposition).

Next, as shown in FIG. 8 , a plurality of openings MH _L are formed at positions corresponding to the semiconductor region 120 _L. The opening MH _L extends in the Z direction, penetrating the insulating layer 151, the plurality of sacrificial layers 110A, the plurality of insulating layers 101, the semiconductor layer 111, the sacrificial layer 113C, the sacrificial layer 113B, and the sacrificial layer 113A, exposing the semiconductor layer 112. This step is performed, for example, by a method such as RIE (Reactive Ion Etching).

Next, as shown in FIG. 9 , an insulating layer 111_D and an insulating layer 112_D of silicon oxide or the like are respectively formed on the portions of the semiconductor layer 111 and the semiconductor layer 112 that are exposed to the opening _MHL . This process is performed by thermal oxidation etc., for example. In addition, amorphous silicon or the like is formed inside the opening MH _L , and the upper surface of the amorphous silicon or the like is removed to a position between the upper and lower surfaces of the insulating layer 151, and a sacrificial layer 120A' is formed inside the opening MH _L. . This process is performed by CVD, RIE, etc., for example.

Next, as shown in FIG. 10 , after expanding the opening at the upper end of the opening MH _L , amorphous silicon or the like is formed, and the upper surface position of the amorphous silicon or the like is removed to the same position as the upper surface of the insulating layer 151 At this position, a sacrificial layer 120A is formed. This process is performed by RIE, CVD, etc., for example.

Next, as shown in FIG. 11 , a plurality of sacrificial layers 110A and a plurality of insulating layers 101 are alternately formed on the insulating layer 151 (at a position corresponding to the memory cell array layer L _MCA2 ). In addition, among the plurality of insulating layers 101 , the insulating layers 101 disposed relatively below are respectively disposed with a film thickness that is approximately the same as the second pitch D ₁₁₂ . In addition, among the plurality of insulating layers 101 , the insulating layers 101 disposed relatively above each other are provided with a film thickness that is approximately the same as the first pitch D ₁₁₁ . In addition, the sacrificial layer 110A disposed relatively below among the plurality of sacrificial layers 110A is disposed to have a film thickness that is approximately the same as the second film thickness T ₁₁₂ . In addition, the sacrificial layer 110A disposed relatively above among the plurality of sacrificial layers 110A is provided with a film thickness that is approximately the same as the first film thickness T ₁₁₁ . This process is performed by a method such as CVD.

Next, as shown in FIG. 12 , a plurality of openings _MHU are formed at positions corresponding to the semiconductor region 120 _U. The opening MH _U extends in the Z direction, penetrates the plurality of sacrificial layers 110A and the plurality of insulating layers 101, and exposes the sacrificial layer 120A. This step is performed, for example, by a method such as RIE.

Next, as shown in FIG. 13 , the sacrificial layer 120A is removed through a plurality of openings MH _U to form openings MH _UL . In this process, the insulating layer 111_D and the insulating layer 112_D are etching stop layers, and the semiconductor layer 111 and the semiconductor layer 112 are not etched at the same time. This process is performed by a method such as wet etching.

Next, as shown in FIG. 14 , on the upper surface of the uppermost insulating layer 101 and the inner peripheral surface of the opening MH _UL , a gate insulating film 130 ′, including the same laminated film as the gate insulating film 130 , and an amorphous film are formed. A semiconductor layer 120' of silicon or the like and an insulating layer 125' of silicon oxide or the like. This process is performed by a method such as CVD. In addition, when forming the semiconductor layer 120', for example, an amorphous silicon film is formed by CVD or the like, and then the crystal structure of the amorphous silicon film is modified by annealing or the like.

Next, as shown in FIG. 15 , a portion of the upper surfaces of the insulating layer 125 ′, the semiconductor layer 120 ′, and the gate insulating film 130 ′ are removed to a point between the upper and lower surfaces of the insulating layer 101 that becomes the uppermost layer. position, thereby forming the gate insulating film 130, the semiconductor layer 120 and the insulating layer 125. Next, an impurity region 121 is formed near the upper end of the semiconductor layer 120 . This process is performed by methods such as RIE and CVD, for example.

Next, as shown in FIG. 16 , after forming the same insulating layer as the insulating layer 101 on the insulating layer 101 , a trench STA′ is formed at a position corresponding to the inter-block structure ST. The trench STA′ extends in the Z direction and the X direction, and separates the plurality of insulating layers 101 and the sacrificial layer 110A in the Y direction to expose the semiconductor layer 111 . In addition, an insulating layer 161 of silicon oxide or the like and a semiconductor layer 162 of amorphous silicon or the like are formed inside the trench STA′ by methods such as CVD. This process is performed by methods such as RIE and CVD, for example.

Next, as shown in FIG. 17 , trench STA is formed. The trench STA is formed by further dividing the semiconductor layer 162, the insulating layer 161, the semiconductor layer 111 and the sacrificial layers 113C, 113B, and 113A in the Y direction from the bottom surface of the trench STA', so that the semiconductor Layer 112 is exposed. This process is performed by RIE etc., for example. Furthermore, the semiconductor layer 162 on the Y-direction side of the trench STA and a portion of the semiconductor layer 112 exposed on the bottom surface are oxidized to form an insulating layer 163 and an insulating layer 164 of silicon oxide or the like respectively. This process is performed by thermal oxidation etc., for example.

Next, as shown in FIG. 18 , the sacrificial layer 113B is removed through the trench STA, and then the sacrificial layers 113A, 113C and part of the gate insulating film 130 are removed to form a cavity CAV, exposing part of the semiconductor layer 120 . This process is performed by a method such as wet etching.

Next, as shown in FIG. 19 , the semiconductor layer 113 is formed at the location where the cavity CAV is located through the trench STA. This process is performed by a method such as epitaxial growth, for example. Furthermore, the semiconductor layer 162 and the insulating layer 161 are removed from the Y-direction side of the trench STA. This process is performed by a method such as wet etching.

Next, as shown in FIG. 20 , the sacrificial layer 110A is removed through the trench STA. Furthermore, the conductive layer 110 and the dummy conductive layer 110DM are formed in the plurality of cavities formed by removing the sacrificial layer 110A. This process is performed by methods such as wet etching and CVD.

Next, an insulating layer is formed in the trench STA to form the inter-block structure ST. Furthermore, the contact point Ch connected to the impurity region 121 and the inter-string cell insulating layer SHE are formed to form the structure described with reference to FIG. 5 .

[Comparative Example] Next, a semiconductor memory device of a comparative example will be described with reference to FIG. 21 . FIG. 21 is a schematic cross-sectional view illustrating a semiconductor memory device according to a comparative example.

For example, as shown in FIG. 21 , the semiconductor memory device of the comparative example includes a plurality of conductive layers 110_x instead of a plurality of conductive layers 110 . In the memory cell array layer L _MCA1 and the memory cell array layer L _MCA2 , a plurality of conductive layers 110_x are arranged with a fourth pitch _DX in the Z direction. That is, the plurality of conductive layers 110_x are all arranged in the Z direction with the same pitch.

In the semiconductor memory device of the comparative example, the closer to the substrate and the lower part of the semiconductor region 120 _J , the smaller the radial width of the semiconductor region 120 _U is. Here, near the lower end of the semiconductor region 120 _U , the electrical influence between adjacent memory cells MC in the Z direction may sometimes increase. Therefore, the data storage characteristics of this type of memory cell MC may be worse than those of other memory cells MC.

[Effects of the First Embodiment] In the semiconductor memory device of the first embodiment, among the plurality of conductive layers 110 provided in the memory cell array layer L _MCA2 , the conductive layer 110 provided at the relatively lower position has a relatively large second conductive layer 110. Pitch D ₁₁₂ arranged. According to this structure, the electrical influence between adjacent memory cells MC in the Z direction can be suppressed. Therefore, in this structure, good data storage characteristics can be obtained even in the memory cells MC disposed at a height position with a small width in the radial direction of the semiconductor layer 120 .

[Modification of the first embodiment] Next, a semiconductor memory device according to a modification of the first embodiment will be described with reference to FIG. 22 . FIG. 22 is a schematic cross-sectional view of a semiconductor memory device for explaining a variation of the first embodiment.

[Film Thickness of Plural Conductive Layers 110] For example, as shown in FIG. 22, in the semiconductor memory device according to the variation of the first embodiment, among the plurality of conductive layers 110 provided in the memory cell array layer L _MCA2 , The film thickness in the Z direction of the conductive layer 110 located relatively below is the fourth film thickness T ₁₂₂ instead of the second film thickness T ₁₁₂ . The fourth film thickness T ₁₂₂ is larger than the first film thickness T ₁₁₁ and the third film thickness T ₁₁₃ .

[Effects of Modification of First Embodiment] In the semiconductor memory device according to the modification of the first embodiment, among the plurality of conductive layers 110 provided in the memory cell array layer L _MCA2 , one of the conductive layers 110 provided at the opposite side is The film thickness is relatively large. By increasing the film thickness of the conductive layer 110, the volume of the charge accumulation film 132 facing it also increases, and relatively more charges can be accumulated in the charge accumulation film 132. In this structure, it can be less susceptible to the electrical influence of adjacent memory cells MC in the Z direction. Therefore, in this structure, good data storage characteristics can be obtained even in the memory cells MC disposed at positions with small radial widths.

[Second Embodiment] Next, a semiconductor memory device according to a second embodiment will be described with reference to FIG. 23 . FIG. 23 is a schematic cross-sectional view for explaining the semiconductor memory device according to the second embodiment.

The semiconductor memory device of the second embodiment is basically configured in the same manner as the semiconductor memory device of the first embodiment. However, the semiconductor memory device of the second embodiment includes a plurality of conductive layers 110_2 instead of the plurality of conductive layers 110, and a dummy conductive layer 110_2DM instead of the dummy conductive layer 110DM.

[The distance between the plurality of conductive layers 110_2] For example, as shown in FIG. 23, among the plurality of conductive layers 110_2 disposed in the memory cell array layer L _MCA2 , the conductive layer 110_2 disposed relatively above is 5th in the Z direction. Spacing D ₂₁₁ arrangement. In addition, among the plurality of conductive layers 110_2 disposed in the memory cell array layer L _MCA2 , the conductive layers 110_2 disposed relatively lower are arranged at the sixth pitch D ₂₁₂ in the Z direction, and the dummy conductive layer 110_2DM and the conductive layer directly above it are arranged. 110_2 are similarly arranged at the sixth pitch D ₂₁₂ in the Z direction. In addition, among the plurality of conductive layers 110_2 disposed on the memory cell array layer L _MCA1 , the conductive layers 110_2 disposed relatively above are arranged at the seventh pitch D ₂₁₃ in the Z direction. In addition, among the plurality of conductive layers 110_2 disposed in the memory cell array layer L _MCA1 , the conductive layers 110_2 disposed relatively downward are arranged at the eighth pitch D ₂₁₄ in the Z direction, and the dummy conductive layer 110_2DM and the conductive layer directly above it are arranged 110_2 are similarly arranged at the eighth pitch D ₂₁₄ in the Z direction. The sixth distance D ₂₁₂ and the eighth distance D ₂₁₄ are larger than the fifth distance D ₂₁₁ and the seventh distance D ₂₁₃ .

In this structure, the film thickness of the plurality of insulating layers 101 in the area where the conductive layer 110_2 is arranged at the 6th pitch D ₂₁₂ and the 8th pitch D ₂₁₄ is greater than that in the area where the conductive layer 110_2 is arranged at the 5th pitch D ₂₁₁ and the 7th pitch D ₂₁₃ The film thickness of the plurality of insulating layers 101 in the area.

[Film thickness of the plurality of conductive layers 110_2] Also, for example, in FIG. 23, among the plurality of conductive layers 110_2 provided in the memory cell array layer L _MCA2 , the film in the Z direction of the conductive layer 110_2 provided relatively above is The thickness is shown as the fifth film thickness T ₂₁₁ . In addition, the film thickness in the Z direction of the conductive layer 110_2 provided at the relatively lower position among the plurality of conductive layers 110_2 provided in the memory cell array layer L _MCA2 is shown as the sixth film thickness T ₂₁₂ . In addition, the film thickness in the Z direction of the conductive layer 110_2 provided relatively above among the plurality of conductive layers 110_2 provided in the memory cell array layer L _MCA1 is shown as the seventh film thickness T ₂₁₃ . In addition, the film thickness in the Z direction of the conductive layer 110_2 provided at the relatively lower position among the plurality of conductive layers 110_2 provided in the memory cell array layer L _MCA1 is shown as the eighth film thickness T ₂₁₄ . The fifth film thickness T ₂₁₁ , the sixth film thickness T ₂₁₂ , the seventh film thickness T ₂₁₃ and the eighth film thickness T ₂₁₄ are film thicknesses of the same degree.

[Effects of the Second Embodiment] In the semiconductor memory device of the second embodiment, among the plurality of conductive layers 110 provided in the memory cell array layer L _MCA1 , the conductive layer 110 provided at the relatively lower position has a relatively large 8 Spacing D ₂₁₄ arranged. Therefore, in this structure, not only the conductive layer 110_2 disposed relatively below among the plurality of conductive layers 110_2 disposed on the memory cell array layer L _MCA2 , but also the plurality of conductive layers 110_2 disposed on the memory cell array layer L _MCA1 The conductive layer 110_2 disposed relatively below the layer 110_2 can also obtain good data retention characteristics.

[Modification of the second embodiment] Next, a semiconductor memory device according to a modification of the second embodiment will be described with reference to FIG. 24 . FIG. 24 is a schematic cross-sectional view of a semiconductor memory device for explaining a variation of the second embodiment.

[Film Thickness of Plural Conductive Layers 110_2] For example, as shown in FIG. 24, in the semiconductor memory device according to the variation of the second embodiment, among the plurality of conductive layers 110_2 provided in the memory cell array layer L _MCA2 , The film thickness of the relatively lower conductive layer 110_2 in the Z direction is the ninth film thickness T ₂₂₂ instead of the sixth film thickness T ₂₁₂ . In addition, among the plurality of conductive layers 110_2 provided in the memory cell array layer L _MCA1 , the film thickness in the Z direction of the conductive layer 110_2 provided relatively downward is the 10th film thickness T ₂₂₄ instead of the 8th film thickness T ₂₁₄ . At least one of the ninth film thickness T ₂₂₂ and the tenth film thickness T ₂₂₄ is greater than the fifth film thickness T ₂₁₁ and the seventh film thickness T ₂₁₃ .

[Third Embodiment] Next, a semiconductor memory device according to a third embodiment will be described with reference to FIG. 25 . FIG. 25 is a schematic cross-sectional view for explaining the semiconductor memory device according to the third embodiment.

The semiconductor memory device of the third embodiment is basically configured in the same manner as the semiconductor memory device of the first embodiment. However, the semiconductor memory device of the third embodiment includes a plurality of conductive layers 110_3 instead of the plurality of conductive layers 110 and a dummy conductive layer 110_3DM instead of the dummy conductive layer 110DM.

[The distance between the plurality of conductive layers 110_3] For example, as shown in FIG. 25, among the plurality of conductive layers 110_3 disposed in the memory cell array layer L _MCA2 , the conductive layer 110_3 disposed relatively above is 9th in the Z direction. Spacing D ₃₁₁ arrangement. In addition, among the plurality of conductive layers 110_3 disposed in the memory cell array layer L _MCA2 , the conductive layers 110_3 disposed relatively below are arranged at the 10th pitch D ₃₁₂ in the Z direction. In addition, among the plurality of conductive layers 110_3 disposed on the memory cell array layer L _MCA1 , the conductive layers 110_3 disposed relatively above are arranged at an 11th pitch D ₃₁₃ in the Z direction. In addition, among the plurality of conductive layers 110_3 disposed on the memory cell array layer L _MCA1 , the conductive layers 110_3 disposed relatively downward are arranged at a twelfth pitch D ₃₁₄ in the Z direction. At least one of the 10th distance D ₃₁₂ and the 12th distance D ₃₁₄ is larger than the 9th distance D ₃₁₁ and the 11th distance D ₃₁₃ .

[Spacing between dummy conductive layers 110_3DM] For example, as shown in FIG. 25, in the memory cell array layer L _MCA2 , the dummy conductive layer 110_3DM and the conductive layer 110_3 adjacent to the dummy conductive layer 110_3DM are spaced at the 13th spacing in the Z direction. D ₃₁₅ arrangement. In addition, below the memory cell array layer L _MCA1 , the dummy conductive layer 110_3DM and the conductive layer 110_3 adjacent to the dummy conductive layer 110_3DM are arranged at a 14th pitch D ₃₁₆ in the Z direction. The 13th distance D ₃₁₅ and the 14th distance D ₃₁₆ are approximately the same as the 9th distance D ₃₁₁ and the 11th distance D ₃₁₃ .

In this structure, the film thickness of the insulating layer 101 provided between the dummy conductive layer 110_3DM and the conductive layer 110_3 adjacent to the dummy conductive layer 110_3DM can also be at the 9th pitch D ₃₁₁ and the 11th pitch with the conductive layer 110_3. The film thicknesses of the plurality of insulating layers 101 in the area where D ₃₁₃ is arranged are approximately the same.

[Film thickness of the plurality of conductive layers 110_3] Also, for example, in FIG. 25, among the plurality of conductive layers 110_3 provided in the memory cell array layer L _MCA2 , the film in the Z direction of the conductive layer 110_3 provided relatively above is The thickness is shown as the 11th film thickness T ₃₁₁ . In addition, the film thickness in the Z direction of the conductive layer 110_3 provided at a relatively lower position among the plurality of conductive layers 110_3 provided in the memory cell array layer L _MCA2 is shown as a twelfth film thickness T ₃₁₂ . In addition, the film thickness in the Z direction of the conductive layer 110_3 provided at the relatively upper position among the plurality of conductive layers 110_3 provided in the memory cell array layer L _MCA1 is shown as the 13th film thickness T ₃₁₃ . In addition, the film thickness in the Z direction of the conductive layer 110_3 provided at the relatively lower position among the plurality of conductive layers 110_3 provided in the memory cell array layer L _MCA1 is shown as the 14th film thickness T ₃₁₄ .

The 11th film thickness T ₃₁₁ , the 12th film thickness T ₃₁₂ , the 13th film thickness T ₃₁₃ and the 14th film thickness T ₃₁₄ may be the same film thickness. In addition, at least one of the 12th film thickness T ₃₁₂ and the 14th film thickness T ₃₁₄ may be larger than the 11th film thickness T ₃₁₁ and the 13th film thickness T ₃₁₃ .

[Effects of the third embodiment] There is no memory cell MC for recording data between the dummy conductive layer 110_3DM and the semiconductor layer 120. Therefore, the distance between the dummy conductive layer 110_3DM and the conductive layer 110_3 adjacent to the dummy conductive layer 110_3DM will not affect the data storage characteristics of the memory cell MC. Therefore, it is not necessary to increase the film thickness of the insulating layer 101 between them, and a higher integrated semiconductor memory device can be manufactured.

[Other Embodiments] Next, with reference to FIG. 26 , a semiconductor memory device according to other embodiments will be described. FIG. 26 is a schematic cross-sectional view for explaining a semiconductor memory device according to another embodiment.

The semiconductor memory device of other embodiments is basically configured in the same manner as the semiconductor memory device of the first embodiment. However, the semiconductor memory device of other embodiments has a plurality of conductive layers 110_4 instead of the plurality of conductive layers 110, and a dummy conductive layer 110_4DM instead of the dummy conductive layer 110DM.

[The distance between the plurality of conductive layers 110_4] For example, as shown in FIG. 26, among the plurality of conductive layers 110_4 provided in the memory cell array layer L _MCA2 , the conductive layers 110_4 provided relatively above are at the 15th pitch in the Z direction. D ₄₁₁ arrangement.

Alternatively, among the plurality of conductive layers 110_4 provided in the memory cell array layer L _MCA2 , the conductive layers 110_4 provided below may be arranged with a larger pitch in the Z direction. For example, as shown in Figure 26, the Z-direction spacing between the plurality of conductive layers 110_4 and the dummy conductive layer 110_4DM can be from below to above the memory cell array layer L _MCA2 , from the 16_1th pitch D _{412_1} to the 16_nth pitch D _{412_n} (n is an integer above 1) gradually decreases. The 16th_1st distance D _{412_1} may be greater than the 15th distance D ₄₁₁ , and the 16th_nth distance D _{412_n} may be the same as the 15th distance D ₄₁₁ .

In addition, among the plurality of conductive layers 110_4 provided in the memory cell array layer L _MCA1 , the conductive layers 110_4 provided relatively above are arranged at the 17th pitch D ₄₁₃ in the Z direction.

Furthermore, among the plurality of conductive layers 110_4 provided in the memory cell array layer L _MCA1 , the conductive layers 110_4 provided at a lower position may be arranged with a larger pitch in the Z direction. For example, as shown in FIG. 26 , the distance between the dummy conductive layer 110_4DM and the plurality of conductive layers 110_4 above it in the Z direction can be from the bottom of the memory cell array layer L _MCA1 to the top, and from the 18th_1st distance D _{414_1} to the top. 18_m spacing D _{414_m} (m is an integer above 1) gradually decreases. The 18th_1st distance D _{414_1} may be larger than the 17th distance D ₄₁₃ , and the 18th_m distance D _{414_m} may be the same as the 17th distance D ₄₁₃ .

[Film Thickness of Plural Conductive Layers 110_4] Also, for example, in FIG. 26, among the plurality of conductive layers 110_4 provided in the memory cell array layer L _MCA2 , the film thickness in the Z direction of the conductive layer 110_4 provided relatively above It is shown as the 15th film thickness T ₄₁₁ . In addition, among the plurality of conductive layers 110_4 provided in the memory cell array layer L _MCA2 , the film thickness in the Z direction of the conductive layer 110_4 provided relatively below is shown as the 16th film thickness T ₄₁₂ . In addition, the film thickness in the Z direction of the conductive layer 110_4 provided relatively above among the plurality of conductive layers 110_4 provided in the memory cell array layer L _MCA1 is shown as the 17th film thickness T ₄₁₃ . In addition, the film thickness in the Z direction of the conductive layer 110_4 provided at the relatively lower position among the plurality of conductive layers 110_4 provided in the memory cell array layer L _MCA1 is shown as the 18th film thickness T ₄₁₄ .

The 15th film thickness T ₄₁₁ , the 16th film thickness T ₄₁₂ , the 17th film thickness T ₄₁₃ and the 18th film thickness T ₄₁₄ may also be the same film thickness. In addition, at least one of the 16th film thickness T ₄₁₂ and the 18th film thickness T ₄₁₄ may be larger than the 15th film thickness T ₄₁₁ and the 17th film thickness T ₄₁₃ .

[Others] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments or variations thereof are included in the scope or gist of the invention, and are included in the scope of the invention described in the patent application and its equivalent scope.

[Cross-reference to related applications] This application enjoys the priority of the application based on Japanese Patent Application No. 2021-138871 (filing date: August 27, 2021). This application incorporates the entire contents of the basic application by reference to the basic application.

100: Semiconductor substrate 101: Insulating layer 110: Conductive layer 110_2: Conductive layer 110_2DM: Dummy conductive layer 110_3: Conductive layer 110_3DM: Dummy conductive layer 110_4: Conductive layer 110_4DM: Dummy conductive layer 110_x: Conductive layer 110A: Sacrificial layer 110DM: Dummy Conductive layer 111: Semiconductor layer 111_D: Insulating layer 112: Semiconductor layer 112_D: Insulating layer 113: Semiconductor layer 113A: Sacrificial layer 113B: Sacrificial layer 113C: Sacrificial layer 114: Conductive layer 115: Metal film 116: Barrier conductive film 120: Semiconductor Layer 120': semiconductor layer 120A: sacrificial layer 120A': sacrificial layer 120 _J : semiconductor region 120 _L : semiconductor region 120 _U : semiconductor region 121: impurity region 122: impurity region 125: insulating layer 125': insulating layer 130: gate Electrode insulation film 130': Gate insulation film 131: Tunnel insulation film 132: Charge accumulation film 133: Barrier insulation film 134: Metal oxide film 151: Insulation layer 161: Insulation layer 162: Semiconductor layer 163: Insulation layer 164: Insulation layer BL: bit line BLK: memory block CAV: cavity CC: contact Ch: contact CS: contact D: area D0: wiring layer D1: wiring layer D2: wiring layer D ₁₁₁ : 1st pitch D ₁₁₂ : 1st pitch D 2 pitch D ₁₁₃ : 3rd pitch D ₂₁₁ : 5th pitch D ₂₁₂ : 6th pitch D ₂₁₃ : 7th pitch D ₂₁₄ : 8th pitch D ₃₁₁ : 9th pitch D ₃₁₂ : 10th pitch D ₃₁₃ : 11th pitch D ₃₁₄ : 12th pitch D ₃₁₅ : 13th pitch D ₃₁₆ : 14th pitch D ₄₁₁ : 15th pitch D ₄₁₁ : 15th pitch D _{412_1} ~ D _{412_n} : 16th_1 pitch ~ 16_n pitch D ₄₁₃ : 17th pitch D _{414_1} ~ _{D 414_m} : _{18_1st pitch ~} 18_m pitch _D Crystal layer MC: Memory cell (memory transistor) MCA: Memory cell array MH _L : Opening MH _U : Opening MH _UL : Opening MS: Memory string PC: Peripheral circuit R _MCA : Memory cell array area SGD: Select gate line SGS: select gate line SHE: insulating layer between string units SL: source line ST: inter-block structure STA: trench STA': trench STD: drain side selection transistor STS: source side selection transistor SU: String unit SUa～Sue: String unit Tr: Transistor T ₁₁₁ : 1st film thickness T ₁₁₂ : 2nd film thickness T ₁₁₃ : 3rd film thickness T ₁₂₂ : 4th film thickness T ₂₁₁ : 5th film thickness T ₂₁₂ : 6th film thickness T ₂₁₃ : 7th film thickness T ₂₁₄ : 8th film thickness T ₂₂₂ : 9th film thickness T ₂₂₄ : 10th film thickness T ₃₁₁ : 11th film thickness T ₃₁₂ : 12th film thickness T ₃₁₃ : 12th film thickness 13th film thickness T ₃₁₄ : 14th film thickness T ₄₁₁ : 15th film thickness T ₄₁₂ : 16th film thickness T ₄₁₃ : 17th film thickness T ₄₁₄ : 18th film thickness Vy: contact WL: word line W _120J : Width W _120LL : Width W _120LU : Width W _120UL : Width W _120UU : Width

FIG. 1 is a schematic circuit diagram showing a part of the structure of the semiconductor memory device according to the first embodiment. 2 is a schematic plan view showing a part of the semiconductor memory device. 3 is a schematic perspective view showing a part of the semiconductor memory device. 4 is a schematic plan view showing a part of the structure of the semiconductor memory device. 5 is a schematic cross-sectional view showing a part of the structure of the semiconductor memory device. 6 is a schematic cross-sectional view showing a partial structure of the semiconductor memory device. 7 to 20 are schematic cross-sectional views for explaining the manufacturing method of the semiconductor memory device. 21 is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to a comparative example. 22 is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to a variation of the first embodiment. 23 is a schematic cross-sectional view showing a part of the structure of the semiconductor memory device according to the second embodiment. 24 is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to a variation of the second embodiment. 25 is a schematic cross-sectional view showing a part of the structure of the semiconductor memory device according to the third embodiment. 26 is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to another embodiment.

101:Insulation layer

110: Conductive layer

110DM: Dummy conductive layer

111: Semiconductor layer

112: Semiconductor layer

113: Semiconductor layer

114:Conductive layer

120: Semiconductor layer

120 _J : Semiconductor area

120 _L : Semiconductor area

120 _U : Semiconductor area

121: Impurity area

122: Impurity area

125:Insulation layer

130: Gate insulation film

151:Insulation layer

D:Area

D ₁₁₁ : 1st pitch

D ₁₁₂ : 2nd pitch

D ₁₁₃ : 3rd pitch

L _MCA1 : memory cell array layer

L _MCA2 : memory cell array layer

SGD: select gate line

SGS: select gate line

SHE: insulation layer between string units

ST: inter-block structure

T ₁₁₁ : 1st film thickness

T ₁₁₂ : 2nd film thickness

T ₁₁₃ : 3rd film thickness

W _120J : Width

W _120LL : Width

W _120LU : Width

W _120UL : Width

W _120UU : Width

Claims (6)

A semiconductor memory device, which is provided with: a substrate; a plurality of first conductive layers arranged at a first pitch in a first direction crossing the surface of the substrate; a plurality of second conductive layers disposed between the substrate and The above-mentioned plurality of first conductive layers are arranged at a second pitch in the above-mentioned first direction; a plurality of third conductive layers are provided between the above-mentioned substrate and the above-mentioned plurality of second conductive layers, between the above-mentioned first conductive layers direction with a third pitch; and a semiconductor layer extending in the above-mentioned first direction and opposing the above-mentioned plurality of first conductive layers, the above-mentioned plurality of second conductive layers and the above-mentioned plurality of third conductive layers; the above-mentioned semiconductor The layer has: a first region extending in the above-mentioned first direction and opposing the plurality of first conductive layers and the plurality of second conductive layers; and a second region extending in the above-mentioned first direction and opposite to the plurality of first conductive layers and the plurality of second conductive layers; The above-mentioned plurality of third conductive layers face each other; the above-mentioned second spacing is larger than the above-mentioned first spacing and the above-mentioned third spacing. The semiconductor memory device of claim 1, wherein when the end of the first region on the opposite side of the substrate in the first direction is set as the first end, the end of the first region in the first direction is Let the end on the substrate side be the second end, let the end of the second region on the opposite side of the substrate in the first direction be the third end, and let the end of the second region on the first direction be Let the end on the substrate side be the fourth end, let the width of the first end in the second direction intersecting the first direction be the first width, and let the width of the second end in the second direction When the width in the above-mentioned second direction of the above-mentioned third end is set as the third width, and the width in the above-mentioned second direction of the above-mentioned 4th end is set as the fourth width, The first width and the third width are respectively larger than the second width and the fourth width. The semiconductor memory device of claim 2, wherein the semiconductor layer has a third region disposed between the first region and the second region, when the width of the third region in the second direction is set to the fifth width When , the above-mentioned fifth width is greater than the above-mentioned second width and the above-mentioned third width. The semiconductor memory device according to any one of claims 1 to 3, wherein when the film thickness in the first direction of the plurality of first conductive layers is set as the first film thickness, the above-mentioned thickness of the plurality of second conductive layers is When the film thickness in the first direction is set as the second film thickness, and the film thickness in the first direction of the plurality of third conductive layers is set as the third film thickness, the above-mentioned second film thickness is greater than the above-mentioned first film thickness and the above-mentioned 3rd film thickness. The semiconductor memory device of any one of claims 1 to 3 is provided with a plurality of fourth conductive layers, and the plurality of fourth conductive layers are disposed between the above-mentioned substrate and the above-mentioned plurality of third conductive layers and between the above-mentioned third conductive layers. Arranged at the 4th spacing in the 1 direction, the above 4th spacing is greater than the above 1st spacing and the above 3rd spacing. The semiconductor memory device according to any one of claims 1 to 3, which is provided with a first dummy conductive layer disposed between the plurality of second conductive layers and the plurality of third conductive layers, and Opposite to the above-mentioned first region, when the second conductive layer closest to the above-mentioned substrate among the above-mentioned plurality of second conductive layers is set as the fifth conductive layer, the gap between the above-mentioned first dummy conductive layer and the above-mentioned fifth conductive layer The pitch is smaller than the above-mentioned second pitch.