TWI824191B - Computer program product and method and apparatus for adjusting equalization - Google Patents

Abstract

A computer program product for adjusting equalization includes program code that can be loaded and executed by a processing unit of a storage device, to: repeatedly adjusting parameters of an equalizer, and repeatedly outputting fillers to a media access control (MAC) layer to replace output results from a symbol decoder until an adjustment failure or a detection that continuous waveforms output from the equalizer belong to an eye open state after detecting a symbol decode error. With the aforementioned filler outputs, it would avoid that the MAC layer does not wait for the result of the equalization adjustment and directly trigger the error correction mechanism initiated by a host.

Description

Computer program products, methods and devices for equalization adjustment

The present invention relates to a storage device, and in particular, to a computer program product, method and device for balance adjustment.

Flash memory devices are generally divided into NOR flash memory devices and NAND flash memory devices. The NOR flash memory device is a random access device. The host-side can provide any address for accessing the NOR flash memory device on the address pin and obtain the data pin of the NOR flash memory device in real time. Get the data stored at that address. In contrast, NAND flash memory devices do not have random access, but sequential access. NAND flash memory devices cannot access any random address like NOR flash memory devices. Instead, the host needs to write a sequence of Bytes values into the NAND flash memory device to define the request. The type of command (such as read, write, erase, etc.), and the address used for this command. The address can point to a page (the smallest block of data for a write operation in a flash memory device) or a block (the smallest block of data for an erase operation in a flash memory device).

During high-speed transmission between the host and the device, for example, at a transmission rate higher than 6Gb/sec, data is susceptible to jitter, voltage changes on the motherboard, and inter-symbol interference (ISI). The error occurs due to the influence. Therefore, the physical layer on the host side and the device side can be equipped with equalizers (Equalizers) to eliminate or suppress data errors during high-speed transmission by adjusting parameters through equalization. According to standard specifications, such as Universal Flash Storage (UFS), balancing adjustments can only be initiated by the host side. The host may find an error rate in receiving data from the device before switching the transmission mode to a high speed gear (such as High Speed Gear 4, HS-G4, or higher). When the threshold is reached or exceeded, balanced adjustments are initiated. However, in some cases, the device will discover that the error rate of received data has reached or exceeded the threshold earlier than the host. Relying only on the host to initiate balancing adjustments will delay the opportunity to correct errors. Therefore, the present invention proposes a computer program product, method and device that can initiate balance adjustment from the device side.

In view of this, how to alleviate or eliminate the deficiencies in the above-mentioned related fields is a problem that needs to be solved.

This specification relates to an embodiment of a computer program product for equalization adjustment, including a program code loaded and executed by a processing unit of a storage device: after detecting a code decoding error, iteratively adjusts the parameters of the equalizer and continuously outputs padding The element is given to the media access control layer and is used to replace the output result of the code decoder until the adjustment fails or the continuous waveform output by the equalizer is detected to belong to the eye-open state.

This specification also relates to an embodiment of a balance adjustment method, which is implemented when the processing unit of the storage device loads and executes the program code shown above.

This specification also relates to an embodiment of an equalization adjustment device, including an equalizer, a code decoder, a processing unit, a stuffing element generator, a media access control layer and a multiplexer. The code decoder is coupled to the equalizer and is used for receiving host data from the equalizer. The processing unit is coupled to the equalizer and the symbol decoder. After detecting the symbol decoding error transmitted from the symbol decoder, the processing unit repeatedly adjusts the parameters of the equalizer until the adjustment fails or it is detected that the continuous waveform output by the equalizer belongs to Until the eyes are open. The multiplexer includes an input terminal and an output terminal. The input terminal is coupled to the symbol code decoder and the filling element generator, and the output terminal is coupled to the media access control layer. After detecting a code decoding error, the processing unit controls the multiplexer to connect the padding element generator to the media access control layer, so that the padding element generator continuously outputs padding elements to the media access control layer to replace symbols. The output result of the code decoder is until the adjustment fails or it is detected that the continuous waveform output by the equalizer belongs to the eye-opening state.

One of the advantages of the above embodiment is that the padding element output as described above prevents the media access control layer from directly triggering the error correction mechanism initiated by the host without waiting for the result of the equalization adjustment.

Other advantages of the present invention will be explained in more detail in conjunction with the following description and drawings.

The following description is a preferred implementation manner for completing the invention, and its purpose is to describe the basic spirit of the invention, but is not intended to limit the invention. For the actual invention, reference must be made to the following claims.

It must be understood that the words "including" and "include" used in this specification are used to indicate the existence of specific technical features, numerical values, method steps, work processes, components and/or components, but do not exclude the possibility of adding further technical features, values, method steps, processes, components, components, or any combination of the above.

The use of words such as "first", "second" and "third" in the claims is used to modify the elements in the claims, and is not used to indicate a priority, precedence relationship between them, or that they are one element. Prior to another element, or the chronological order in which method steps are performed, it is only used to distinguish elements with the same name.

It must be understood that when an element is described as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, and intervening elements may be present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between elements could be interpreted in a similar fashion, such as "between" versus "directly between," or "adjacent" versus "directly adjacent," etc.

Refer to Figure 1. The storage device 10 can be provided in an electronic device, such as a personal computer, a laptop computer (Laptop PC), a tablet computer, a mobile phone, a digital camera, a digital video camera, a pen drive, a memory card, or a solid state disk (SSD). and other electronic products. The storage device 10 includes a physical layer (Physical Layer, may be referred to as PHY) 110, a media access control layer (Media Access Control Layer, may be referred to as MAC layer) 130, a processing unit 150 and an interrupt generator 170. The processing unit 150 may be implemented in a variety of ways, such as using general-purpose hardware (eg, a single processor, multiple processors with parallel processing capabilities, a graphics processor, or other processors with computing capabilities), and when executing software and/or Provides specified functions when executing firmware commands. The processing unit 150 can receive host commands from the host through the physical layer 110 and the media access control layer 130, such as read, write, and erase commands that comply with the Universal Flash Storage (UFS) standard.

The storage device 10 includes a storage unit (not shown in Figure 1) that provides a large amount of storage space, usually hundreds of gigabytes (Gigabytes) or even several terabytes (Terabytes), for storage A large amount of user data, such as high-resolution images, videos, etc. The storage unit includes a control circuit and a memory array. The memory cells in the memory array can include Single Level Cells (SLCs), Multiple Level Cells (MLCs), and Triple Level Cells. , TLCs), Quad-Level Cells (QLCs), or any combination of the above.

The physical layer 110 is built on an 8b/10b, 64b/66b or 128b/130b serializer/deserializer (SerDes) environment and includes a pair of functional circuits to make up for the shortcomings of limited input/output. It provides data transmission over a differential pair, minimizing input and output pins and wiring between them. Specifically, the transmitting end of the host converts the low-speed parallel signal into a high-speed serial signal, and transmits it to the receiving end of the storage device 10 through the differential pair. The physical layer 110 includes a deserializer 124 for converting the high-speed serial signal received via the equalizer 122 into a low-speed parallel signal. The signal transmitted from the transmitting end of the host to the receiving end of the storage device 10 can also be called host data.

In order to solve the technical problem that data is susceptible to deviations caused by jitter, voltage changes on the motherboard, and inter-symbol interference during high-speed transmission between the host and the device, the physical layer 110 sets an equalizer between the transmission channel and the deserializer 124 122. The equalizer 122 includes a register 1225, allowing the processing unit 150 to adjust the parameters of the equalizer 122 when it is running by setting the value in the register 1225. Referring to Figure 2, for example, the equalizer 122 includes a first-order Continuous Time Linear Equalizer (CTLE) 210 and a first-order decision feedback equalizer (1-tap Decision Feedback Equalizer, DFE) 230 . Although the embodiment describes the equalizer architecture as shown in Figure 2, those skilled in the art can use other well-known architectures to design the equalizer 122. For example, the equalizer 122 only includes the first-stage continuous-time linear equalizer 210, and the second-stage continuous-time linear equalizer 210. The first-order continuous-time linear equalizer 210 is changed to other equivalent continuous-time linear equalizers, and the first-order decision feedback equalizer 230 is changed to a multi-order decision feedback equalizer or other equivalent decision feedback equalizers. The present invention does not Therefore it is limited.

The characteristics of CTLE can be expressed using the following transformation function: Among them, A _DC represents DC gain, represent , f _z represents 0, f _P1 represents the first pole (Pole), f _P2 represents the second pole.

The characteristics of DFE can be expressed by the following formula: y _k =x _k -V _{DFE_RX} y _k =x _k -d ₁ sgn(y _k-1 ) where, y _k represents the output voltage signal of DFE, and x _k represents the input voltage to DFE Voltage signal, V _{DFE_RX} represents the feedback voltage signal of DFE, k represents the sampling index value of the data bit, and d ₁ represents the feedback coefficient of DFE.

The physical layer 110 includes an eye diagram analyzer 123, and the processing unit 150 can send a signal to the eye diagram analyzer 123 for starting the eye diagram analyzer 123. Traditionally, the eye diagram analyzer 123 is used in the factory to allow engineers to calibrate the equalizer 122, but is not used in the actual operation of the storage device 10 after it leaves the factory. The eye diagram analyzer 123 calculates a value representing the eye diagram, and determines whether the calculated value belongs to the eye open state (Eye Open State, as shown in Figure 3) or the eye closed state (Eye Close State, as shown in Figure 4), and the eye diagram It is a merged pattern formed by superimposing the continuous waveforms output by the equalizer 122. When the calculated value belongs to the eye-opening state, the signal output by the equalizer 122 is acceptable. When the calculated value belongs to the eyes-closed state, it means that the equalizer 122 currently cannot eliminate interference and needs further adjustment. In order to save power consumption, under normal circumstances, the eye diagram analyzer 123 may be turned off and not run. The processing unit 150 may optionally send a control signal to the eye diagram analyzer 123 to activate the eye diagram analyzer 123 . When the eye diagram analyzer 123 detects that the continuous waveform output by the equalizer 122 belongs to the eyes-closed state, the calculated value is sent to the processing unit 150 so that the processing unit 150 adjusts the equalizer 122 accordingly. When the eye diagram analyzer 123 detects that the continuous waveform output by the equalizer 122 belongs to the eye-open state, it sends a message to notify the processing unit 150 that the current signal output by the equalizer 122 is acceptable.

The physical layer 110 includes a symbol decoder (Symbol Decoder) 128, which can be an 8b/10b converter (Converter), a 64b/66b converter or a 128b/130b converter according to different SerDes environments. The code decoder 128 includes a mapping table for converting input data bits into codes represented by fewer bits, for example, mapping input 10, 66 or 130-bit data into 8, 64 or 128-bit codes. . For example, in an 8b/10b SerDes environment, 10 bits can represent 2 ¹⁰ =1024 states, and the mapping table only contains 2 ⁸ =256 mapping relationships. When any input data bit cannot be converted into any valid code according to the mapping table, the symbol code decoder 128 determines that the input data bit is incorrect, and can set the register in the interrupt generator 170 to notify the processing unit 150 of the symbol occurrence. Code decoding error.

When the contents of the register in the interrupt generator 170 are changed, the interrupt generator 170 will send an interrupt signal (Interrupt, referred to as INT for short) to the processing unit 150 to trigger the processing unit 150 to execute an interrupt service routine (Interrupt Service Routine). In the interrupt service routine, the processing unit 150 checks the contents of the register and thereby knows the status detected by the physical layer 110, such as a code decoding error. When a code decoding error is detected, the processing unit 150 loads and executes appropriate firmware code for implementing the equalization adjustment method according to the embodiment of the present invention.

The entity layer 110 includes a filler generator (Filler Generator) 126, which is used to generate continuous filler elements, such as K.28.1 codes, etc. When the MAC layer 130 or the processing unit 150 detects padding elements, it knows that these symbols are not data transmitted from the host.

The physical layer 110 includes a multiplexer (Multiplexer, MUX) 129, the input end of which is coupled to the symbol decoder 128 and the padding element generator 126, and the output end of which is coupled to the MAC 130. Under normal circumstances, the multiplexer 129 connects the output of the code decoder 128 to the input of the MAC 130 for transmitting host-side data to the MAC 130 via the multiplexer 129 . Furthermore, the multiplexer 129 can be controlled by the processing unit 150 to connect the output of the stuffing element generator 126 to the input of the MAC 130 for transmitting the stuffing elements generated by the stuffing element generator 126 to the MAC 130, in other words, preventing the host from The data from the client is transferred to the MAC 130.

In order to enable the storage device 10 to actively adjust the equalizer 122 to resolve errors occurring during data reception, the processing unit 150 may load and execute firmware code to complete the method flowchart shown in FIG. 5 . This method process can limit the execution between the host and the storage device 10 in a high-speed transmission environment, such as High Speed Gear 4 (HS-G4) or a higher speed, or no matter where it is. It can be executed at any transmission rate. The characteristic of the equalization adjustment method described in the embodiment of the present invention is that after detecting a symbol decoding error, the parameters of the equalizer 122 are repeatedly adjusted until the adjustment fails or it is detected that the continuous waveform output by the equalizer 122 belongs to the eye-open state. So far. The details are as follows:

Step S510: A code decoding error occurs in the code decoder 128 through the interrupt signal INT. The code decoding error can be regarded as a condition for the storage device 10 to initiate equalization adjustment. Since the interrupt signal INT is the signal with the highest priority, the processing unit 150 will first execute the program code that reflects the code decoding error.

Step S520: Send a control signal to the multiplexer 129 for connecting the parallel output of the filling element generator 126 to the parallel input of the MAC 130, so that the filling elements generated by the filling element generator 126 are transmitted to the MAC 130 through the multiplexer 129 , and avoid sending incorrect host data to the MAC 130.

Step S530: Send a control signal to the eye diagram analyzer 123 for starting the eye diagram analyzer 123. After being started, the eye diagram analyzer 123 will continuously transmit values corresponding to the eye diagram to the processing unit 150 . In addition, when it is detected that the eye diagram belongs to the eye-open state, a corresponding message may be sent to notify the processing unit 150 .

Step S540: An algorithm known to those skilled in the art can be used to set the register 1225 based on the value calculated by the eye diagram analyzer to adjust the parameters of the equalizer 122.

Step S550: Determine whether an eye-open state is detected based on the data and/or messages received from the eye diagram analyzer 123. If yes, proceed to step S580; otherwise, proceed to step S560.

Step S560: Determine whether the adjustment fails. If yes, perform the process of step S570; otherwise, perform the process of step S540. In some embodiments, the processor 150 may start a timer in step S510 for counting a period of time, representing the time allowed for adjustment. When it is detected that the timer has exceeded this time, it means that the balance adjustment has exceeded the allowed time, and the adjustment cannot be continued and the adjustment fails. In other embodiments, processor 150 may determine whether all candidate parameter value combinations for adjusting equalizer 122 have been tried. If so, it means that the equalizer 122 cannot continue to adjust and the adjustment fails.

Step S570: Start other error correction mechanisms. For example, the processing unit 150 sends a message to the host through the physical layer 110 to notify the host that a code decoding error occurs. The host may try to reduce the transmission speed between the host and the storage device 10 and then increase the speed, activate the feed forward equalizer (FFE) of the sending end in the host, and continuously transmit training frames (such as PRBS9) to the storage device 10. Assist with equalization adjustments, or use other mechanisms to attempt to resolve code decoding errors that occur in the storage device 10 .

Step S580: Send a control signal to the multiplexer 129 for connecting the parallel output of the code decoder 128 to the parallel input of the MAC 130 to return to the default connection state.

Step S590: Send a control signal to the eye diagram analyzer 123 to close the eye diagram analyzer 123 to save power consumption.

Steps S540 to S560 form a loop and can be executed once every millisecond (Millisecond) or several milliseconds.

When the eye diagram analyzer 123 detects that the continuous waveform output by the equalizer 122 belongs to the eye-opening state ("Yes" path in step S550), it means that the adjustment of the equalizer 122 is successful and the loop is exited. Then, the processing unit 150 restores the multiplexer 129 and the eye diagram analyzer 123 to the originally preset states (steps S580 and S590).

When the output of the equalizer 122 cannot be adjusted to the eye-opening state after a preset period of time or all candidate parameter value combinations have been tried (the "YES" path in step S560), it means that the adjustment of the equalizer 122 fails and leaves the return state. lock up. Then, the processing unit 150 activates other error correction mechanisms (step S570) and restores the multiplexer 129 and the eye diagram analyzer 123 to their original default states (steps S580 and S590).

The execution of step S530 and step S580 is used to allow the processing unit 150 to continuously output padding elements to the media access control layer 130 after detecting a code decoding error to replace the output data of the code decoder 128 until the adjustment It fails or until it is detected that the continuous waveform output by the equalizer 122 belongs to the eye-open state. In some cases, the MAC layer 130 may receive a symbol decoding error message from the symbol decoder 128 of the physical layer 110 but directly trigger the error correction mechanism initiated by the host without waiting for the result of the equalization adjustment. The above steps can prevent code decoding error messages from being transmitted to the MAC layer 130, further preventing the host-initiated error correction mechanism from being triggered.

However, the physical layer 110 in FIG. 1 will lose the data transmitted from the host during the period from when a code decoding error occurs in the code decoder 128 to when the equalizer 122 adjusts successfully. Referring to another embodiment of the storage device 60 described in FIG. 6 , in order to retain the data transmitted from the host during this period, the physical layer 600 further includes a data cache (Data Cache) 620 and a control circuit (Control Circuit) 640 . The processing unit 150 can send a control signal to drive the control circuit 640 to start sequentially writing data from the host into the data register 620 . In addition, in order to allow the data in the data buffer 620 to be re-entered into the equalizer 122, the physical layer 600 further includes a multiplexer 660, the input terminal is coupled to the output of the receiver and the output of the control circuit 640, and the output terminal is coupled to the equalizer 122 input. Under normal conditions, the receiver of physical layer 600 is coupled to equalizer 122 via multiplexer 660 . The processing unit 150 can send a control signal to the multiplexer 660 for coupling the output of the control circuit 640 to the equalizer 122, and send a control signal to drive the control circuit 640 to sequentially read the data in the data register 620 and pass it through Multiplexer 660 re-inputs equalizer 122 . For purposes of distinction, the multiplexer 129 in the physical layer 600 may be referred to as a first multiplexer, while the multiplexer 660 in the physical layer 600 may be referred to as a second multiplexer.

According to the architecture shown in FIG. 6 , the processing unit 150 loads and executes another firmware code to complete the method flow chart shown in FIG. 7 . In the new process, step S510 is followed by step S710, and the path of "Yes" in step S550 is followed by step S730. The details are as follows:

Step S710: The drive control circuit 640 begins to write the data transmitted from the host end (that is, the data transmitted from the host end after detecting the code decoding error) into the data register 620 sequentially.

Step S730: Control the multiplexer 660 to couple the output of the control circuit 640 to the equalizer 122 (the equalizer 122 has been adjusted at this time), and send a control signal to drive the control circuit 640 to sequentially read the data register 620 The data is re-entered into the equalizer 122 via the multiplexer 660 . If a code decoding error occurs in the code decoder 128 and the equalizer 122 adjusts successfully, the period is too long so that the data buffer 620 cannot store all the data. The processing unit 150 may give up re-entering the data in the data buffer 620 until the adjustment is successful. Equalizer 122.

All or part of the steps in the method of the present invention can be implemented by computer instructions, such as drivers or software programs for specific hardware in the storage device. In addition, it can also be implemented in other types of programs. Persons skilled in the art can write the methods of the embodiments of the present invention as computer instructions, which will not be described for the sake of simplicity. Computer instructions implemented according to the methods of the embodiments of the present invention can be stored in appropriate computer-readable media, such as DVD, CD-ROM, USB disk, hard disk, or can be placed in a computer that can be accessed through a network (for example, the Internet, or A web server accessible by other appropriate vehicles).

Although the above-described elements are included in Figures 1, 2 and 6, it does not rule out the use of other additional elements to achieve better technical effects without violating the spirit of the invention. In addition, although the flow charts of Figures 5 and 7 are executed in a specified order, those skilled in the art can modify the order of these steps without violating the spirit of the invention and achieving the same effect. Therefore, The present invention is not limited to the use of only the sequence described above. In addition, those skilled in the art can also integrate several steps into one step, or in addition to these steps, perform more steps sequentially or in parallel, and the invention is not limited thereby.

Although the present invention is described using the above embodiments, it should be noted that these descriptions are not intended to limit the present invention. On the contrary, this invention covers modifications and similar arrangements which will be obvious to one skilled in the art. Therefore, the scope of the claims of the application must be interpreted in the broadest manner to include all obvious modifications and similar arrangements.

10,60:Storage device 110,600:Solid layer 122:Equalizer 1225:Register 123:Eye diagram analyzer 124:Deserializer 126: Fill element generator 128: Code decoder 129,660:Mux 130:Media access control layer 150: Processing unit 170:Interrupt generator 210: First level continuous time linear equalizer 230: First-order decision feedback equalizer S510~S590, S710~S730: Method steps 620: Data cache 640:Control circuit

FIG. 1 is a block diagram of a storage device according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of an equalizer according to an embodiment of the present invention.

FIG. 3 is an eye diagram in an eye-open state according to an embodiment of the present invention.

FIG. 4 is an eye diagram in an eye-open state according to an embodiment of the present invention.

FIG. 5 is a flow chart of a method of equalization adjustment according to an embodiment of the present invention.

FIG. 6 is a block diagram of a storage device according to an embodiment of the present invention.

FIG. 7 is a flow chart of a method of equalization adjustment according to an embodiment of the present invention.

S510~S590: Method steps

Claims (13)

A computer program product for equalization adjustment, comprising program code loaded and executed by a processing unit of a storage device: After detecting a code decoding error, repeatedly adjust the parameters of an equalizer until the adjustment fails or it is detected that the continuous waveform output by the equalizer belongs to an eye-opening state; and After detecting the above-mentioned symbol decoding error, a padding element is continuously output to a media access control layer to replace the output result of a symbol decoder until the adjustment fails or the continuous waveform output by the above-mentioned equalizer is detected. Until it reaches the above-mentioned eye-opening state. A computer program product as described in request 1, containing program code: After receiving an interrupt signal, it is known that the above code decoding error has occurred by checking the contents of a register in an interrupt generator. A computer program product as described in request 1, containing program code: After detecting that the continuous waveform output by the equalizer belongs to the eye-opening state or the adjustment fails, the decoding result of the code decoder is output to the media access control layer to replace the filling element. The computer program product as claimed in claim 1, wherein if the continuous waveform output by the equalizer is not detected to belong to the eye-opening state after a preset period of time after detecting the code decoding error, it represents an adjustment failure. The computer program product as described in claim 1, wherein after trying all candidate parameter value combinations to adjust the equalizer, it is still not detected that the continuous waveform output by the equalizer belongs to the eye-opening state, indicating that the adjustment has failed. The computer program product as claimed in claim 1, wherein the code decoding error means that no valid code can be converted from the data output by the equalizer. A balance adjustment method is implemented when a processing unit of a storage device loads and executes program code, including: After detecting a code decoding error, repeatedly adjust the parameters of an equalizer until the adjustment fails or it is detected that the continuous waveform output by the equalizer belongs to an eye-opening state; and After detecting the above-mentioned symbol decoding error, a padding element is continuously output to a media access control layer to replace the output result of a symbol decoder until the adjustment fails or the continuous waveform output by the above-mentioned equalizer is detected. Until it reaches the above-mentioned eye-opening state. The equalization adjustment method as described in request item 7 includes: After detecting that the continuous waveform output by the equalizer belongs to the eye-opening state or the adjustment fails, the decoding result of the code decoder is output to the media access control layer to replace the filling element. An equalization adjustment device, including: an equalizer; a code decoder, coupled to the above-mentioned equalizer, for receiving host data from the above-mentioned equalizer; A processing unit, coupled to the above-mentioned equalizer and the above-mentioned symbol decoder, after detecting a symbol decoding error transmitted from the above-mentioned symbol decoder, repeatedly adjusts the parameters of the above-mentioned equalizer until the adjustment fails or detects a The continuous waveform output by the above-mentioned equalizer belongs to the eye-opening state; a fill element generator; a media access control layer coupled to the above processing unit; and A multiplexer, including an input terminal and an output terminal, the input terminal is coupled to the code decoder and the stuffing element generator, and the output terminal is coupled to the media access control layer, Wherein, after detecting the code decoding error, the processing unit controls the multiplexer to connect the stuffing unit generator to the media access control layer, so that the stuffing unit generator continuously outputs a stuffing unit. The media access control layer replaces the output result of the code decoder until the adjustment fails or it is detected that the continuous waveform output by the equalizer belongs to the eye-opening state. The equalization adjustment device as described in claim 9, including: an interrupt generator, including a register, coupled to the above-mentioned code decoder and the above-mentioned processing unit, Wherein, after receiving an interrupt signal from the interrupt generator, the processing unit knows that the code decoding error occurs by checking the contents of the register in the interrupt generator. The equalization adjustment device according to claim 9, wherein the processing unit controls the multiplexer to connect the code decoder to the The above-mentioned media access control layer is used to output the decoding result of the above-mentioned code decoder to the above-mentioned media access control layer, replacing the above-mentioned padding element. The equalization adjustment device according to claim 9, wherein the processing unit has not detected that the continuous waveform output by the equalizer belongs to the eye-opening state after a preset period of time after detecting the symbol decoding error, or the above-mentioned After trying all candidate parameter value combinations to adjust the equalizer, the processing unit has not detected that the continuous waveform output by the equalizer belongs to the eye-opening state, indicating that the adjustment failed. The equalization adjustment device as described in claim 9, including: a data buffer; a control circuit coupled to the above data register; and A multiplexer including an input terminal and an output terminal, the input terminal is coupled to the control circuit and the receiver, and the output terminal is coupled to the equalizer, Wherein, after detecting that the continuous waveform output by the equalizer belongs to the eye-open state, the processing unit controls the multiplexer to connect the control circuit to the equalizer, and drives the control circuit to detect the decoding of the symbol After an error cached host data is re-entered into the above equalizer.

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