TWI818419B - Manufacturing method of package structure of electronic device - Google Patents

Abstract

A manufacturing method of a package structure of an electronic device including steps below is provided. Forming a first seed layer on a carrier plate. Forming a first metal layer on the first seed layer. Forming a first insulating layer on the first metal layer, wherein the first insulating layer exposes a portion of the first metal layer. Performing a first plasma treatment on the first insulating layer and the portion of exposed first metal layer. Placing the carrier plate on which the first seed layer, the first metal layer, and the first insulating layer are formed in a microenvironment controlling box after performing the first plasma treatment. Forming a second seed layer on the first insulating layer and the portion of exposed first metal layer after taking out the carrier plate from the microenvironment controlling box.

Description

Method for manufacturing packaging structure of electronic device

The present invention relates to a manufacturing method of a packaging structure, and in particular, to a manufacturing method of a packaging structure of an electronic device.

In the process of manufacturing the packaging structure of the electronic device, before forming a seed layer for growing the subsequent metal layer on the surface of the insulating layer and the metal layer, a surface treatment device is used to treat the formed insulating layer and the metal layer. The surface of the metal layer is surface treated to remove residues on the surface and improve the adhesion between the seed layer and the surface; however, after surface treatment is performed on the surface, the next process (such as When the seed layer is formed using a coating device) and is exposed to the atmospheric environment for a long time, defects will occur on the surface of the formed insulating layer and metal layer (such as water vapor intrusion) or oxides will be generated (such as oxidation of the metal layer). ), resulting in a decrease in the adhesion between the seed layer and the surface, that is, a decrease in the effect of the surface treatment, thereby decreasing the reliability and/or electrical properties of the electronic device including the package structure.

The present disclosure provides a method for manufacturing a packaging structure of an electronic device. When the manufactured packaging structure is used in an electronic device, the electronic device can have improved reliability and/or electrical properties.

A method for manufacturing a packaging structure provided according to some embodiments of the present disclosure includes the following steps. First, a first seed layer is formed on the carrier plate. Next, a first metal layer is formed on the first seed layer. Afterwards, a first insulating layer is formed on the first metal layer, wherein the first insulating layer exposes part of the first metal layer. Next, a first plasma treatment is performed on the first insulating layer and the exposed portion of the first metal layer. Then, after performing the first plasma treatment, the carrier plate on which the first seed layer, the first metal layer and the first insulating layer are formed is placed in the micro-environment control box. Then, after the carrier board is taken out from the micro-environment control box, a second seed layer is formed on the first insulating layer and the exposed portion of the first metal layer.

In order to make the above features and advantages of the present disclosure more obvious and understandable, embodiments are given below and described in detail with reference to the accompanying drawings.

The present disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that, for the sake of ease of understanding for the reader and simplicity of the drawings, many of the drawings in the disclosure only depict a part of the electronic device, and Certain elements in the drawings are not drawn to actual scale. In addition, the number and size of components in the figures are only for illustration and are not intended to limit the scope of the present disclosure.

Certain words are used throughout the specification and appended claims to refer to specific elements. Those skilled in the art will appreciate that manufacturers of electronic devices may refer to the same component by different names. This article is not intended to differentiate between components that have the same function but have different names. In the following description and patent application, words such as "include", "contains", and "have" are open-ended words, so they should be interpreted as meaning "including but not limited to...". Therefore, when the terms "comprises," "containing," and/or "having" are used in the description of the present disclosure, they specify the presence of the corresponding features, regions, steps, operations, and/or components, but do not exclude the presence of one or more The existence of corresponding features, regions, steps, operations and/or components.

The directional terms mentioned in this article, such as "up", "down", "front", "back", "left", "right", etc., are only for reference to the directions in the accompanying drawings. Accordingly, the directional terms used are illustrative and not limiting of the disclosure. In the drawings, each figure illustrates the general features of methods, structures, and/or materials used in particular embodiments. However, these drawings should not be interpreted as defining or limiting the scope or nature encompassed by these embodiments. For example, the relative sizes, thicknesses, and locations of various layers, regions, and/or structures may be reduced or exaggerated for clarity.

When a corresponding component (such as a layer or region) is referred to as being "on" another component, it can be directly on the other component, or other components may be present between the two components. On the other hand, when a component is said to be "directly on" another component, there are no components in between. In addition, when a component is referred to as being "on" another component, it means that the two have a vertical relationship in the top direction, and the component can be above or below the other component, and the vertical relationship depends on the orientation of the device ( orientation).

The terms "about", "substantially" or "substantially" are generally interpreted to mean within 20% of a given value or range, or to mean 10%, 5%, 3% of a given value or range. , 2%, 1% or within 0.5%.

The ordinal numbers used in the specification and the scope of the patent application, such as "first", "second", etc., are used to modify elements. They themselves do not imply and represent that the element (or elements) have any previous ordinal number, nor do they mean that the element (or elements) has any previous ordinal number. It does not represent the order of one element with another element, or the order of the manufacturing method. The use of these numbers is only used to clearly distinguish an element with a certain name from another element with the same name. The same words may not be used in the patent application scope and the description. Accordingly, the first component in the description may be the second component in the patent application scope.

It should be noted that the following embodiments can be replaced, reorganized, and mixed with features of several different embodiments to complete other embodiments without departing from the spirit of the present disclosure. Features in various embodiments may be mixed and matched as long as they do not violate the spirit of the invention or conflict with each other.

The electrical connection or coupling described in this disclosure can refer to direct connection or indirect connection. In the case of direct connection, the end points of the components on the two circuits are directly connected or connected to each other with a conductor line segment, and in the indirect connection In the case of , there are switches, diodes, capacitors, inductors, other suitable components, or combinations of the above components between the end points of the components on the two circuits, but are not limited to this.

In the present disclosure, the thickness, length and width can be measured using an optical microscope, and the thickness can be measured using cross-sectional images in an electron microscope, but are not limited thereto. In addition, any two values or directions used for comparison may have certain errors. If the first value is equal to the second value, it implies that there may be an error of about 10% between the first value and the second value; if the first direction is perpendicular to the second direction, then the difference between the first direction and the second direction The angle between them can be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction can be between 0 degrees and 10 degrees.

The electronic device may have the composite layer circuit structure of the embodiments of the present disclosure. The electronic device of the present disclosure may include display, antenna (such as liquid crystal antenna), lighting, sensing, touch, splicing, other suitable functions, or a combination of the above functions, but is not limited thereto. Electronic devices include, but are not limited to, rollable or flexible electronic devices. The electronic device may include, for example, liquid crystal (liquid crystal), light emitting diode (LED), quantum dot (QD), fluorescence, phosphorescence, other suitable materials, or the above. combination. The light emitting diode may include, for example, an organic light emitting diode (OLED), a micro light emitting diode (micro-LED, mini-LED) or a quantum dot light emitting diode (QLED, QDLED), but not This is the limit. In the following, a display device or a splicing device will be used as an electronic device to illustrate the disclosure, but the disclosure is not limited thereto. Electronic components may include passive components and active components, such as capacitance, resistor, inductance, diodes, transistors, circuit boards, chips, dies, Integrated circuits (ICs) or combinations of the above components or other suitable electronic components are not limited to this. Diodes may include light emitting diodes or photodiodes. The light emitting diode may include, for example, an organic light emitting diode (OLED), a sub-millimeter light emitting diode (mini LED), a micro light emitting diode (micro LED) or a quantum dot light emitting diode (quantum LED). dot LED), but not limited to this.

Examples of exemplary embodiments of the present disclosure are given below. The same reference symbols are used in the drawings and descriptions to represent the same or similar parts.

FIG. 1 is a flow chart of a manufacturing method of a packaging structure of an electronic device according to an embodiment of the disclosure. FIG. 2 is a schematic cross-sectional view of a packaging structure of an electronic device according to an embodiment of the disclosure. FIG. 3 is a packaging of the electronic device according to FIG. 2 4 is a schematic diagram of a micro-environment control device according to an embodiment of the present disclosure.

Please refer to FIG. 1 and FIG. 2 simultaneously. In step S100 of this embodiment, a first seed layer SEED1 is formed on the carrier CP. The material of the carrier CP can be, for example, an organic material or an inorganic material, such as glass, quartz, sapphire, silicon wafer, stainless steel, ceramic, polycarbonate (PC), polyimide (PI) , polyethylene terephthalate (PET), resin, organic silicon compounds, other suitable substrate materials, or combinations of the foregoing. In this embodiment, the carrier CP includes a glass carrier, but the disclosure is not limited thereto. In addition, in this embodiment, before forming the first seed layer SEED1 on the carrier CP, a release layer RL may be formed on the carrier CP. The provision of the release layer RL allows subsequent components placed on the carrier CP to be easily separated from it. In some embodiments, the release layer RL has good heat resistance to withstand subsequent heat treatment processes. The material of the release layer RL can be, for example, a suitable organic material, and the present disclosure is not limited thereto. In some embodiments, the top surface of the release layer RL (the surface away from the carrier CP) may be planarized to have a high degree of coplanarity. The first seed layer SEED1 may be formed by, for example, a physical vapor deposition process or a chemical vapor deposition process, but the present disclosure is not limited thereto. The material of the first seed layer SEED1 may be, for example, a metal, and may, for example, have a single-layer structure or a composite layer structure with multiple sub-layers formed of different metals, wherein the sub-layers are stacked on each other. For example, the first seed layer SEED1 in this embodiment may include a titanium layer (not shown) and a copper layer (not shown) laminated on the titanium layer, and have a composite layer structure, but this disclosure does not use this. is limited.

In some embodiments, the carrier CP may have panel-scale dimensions. Based on this, in the subsequent process of this embodiment, for example, a rewiring structure is provided on a carrier CP with a panel-level size and then the chip is packaged; or the chip can be placed on a carrier CP with a panel-level size. The packaging on the CP, that is, the manufacturing method of the packaging structure shown in this embodiment can be used, for example, as a fan-out panel level package (FOPLP) application, where the fan-out panel level package can include rewiring. Structure first (RDL first) process or chip first (chip first) process. In this embodiment, the fan-out panel-level packaging uses a carrier CP with a panel-level size, which can significantly increase production capacity compared to wafer-level packaging. At the same time, the carrier CP with panel-level dimensions has a rectangular outline, which can also significantly improve the utilization rate of the carrier CP compared to wafer-level packaging. Therefore, the packaging structure of the electronic device manufactured in this embodiment can be used to meet high production capacity requirements.

In step S110 of this embodiment, the first metal layer M1 is formed on the first seed layer SEED1. In this embodiment, forming the first metal layer M1 may include performing the following steps, but the disclosure is not limited thereto. A first photoresist layer (not shown) is formed on the surface of the first seed layer SEED1 away from the carrier CP. The first photoresist layer can be formed by, for example, a spin coating process or other suitable processes followed by a patterning process. , and the first photoresist layer includes a plurality of openings exposing part of the first seed layer SEED1. Next, a first metal layer M1 is formed in the openings by growing the first seed layer SEED1 using, for example, an electroplating process. Based on this, the material of the first metal layer M1 may be the same as the material of the first seed layer SEED1, for example. In this embodiment, the first metal layer M1 may be a copper layer, that is, the material of the first metal layer M1 includes copper. Afterwards, the first photoresist layer can be removed, for example, by performing an ashing process or other suitable stripping processes, but the present disclosure is not limited thereto.

In step S120 of this embodiment, a first insulating layer IL1 is formed on the first metal layer M1, where the first insulating layer IL1 exposes part of the first metal layer M1. In this embodiment, forming the first insulating layer IL1 may include performing the following steps, but the disclosure is not limited thereto. First, a first insulating material layer (not shown) covering the first metal layer M1 is formed on the surface of the first seed layer SEED1 away from the carrier CP, where the first insulating material layer may be formed by, for example, a chemical vapor deposition process. or other suitable processes, and this disclosure is not limited thereto. Next, a patterning process is performed on the first insulating material layer to form a first insulating layer IL1 having a plurality of first openings OP1, wherein the first openings OP1 expose part of the first metal layer M1. The material of the first insulating layer IL1 may be, for example, organic materials, oxides, nitrides, oxynitrides or combinations thereof, and the present disclosure is not limited thereto. In this embodiment, the material of the first insulating layer IL1 includes photosensitive polyimide.

In step S130 of this embodiment, a first plasma treatment is performed on the first insulating layer IL1 and the exposed portion of the first metal layer M1. In some embodiments, the surface treatment device of the prior art can be used to perform the first plasma treatment on the first insulating layer IL1 and the exposed portion of the first metal layer M1, but the present disclosure is not limited thereto. Performing a first plasma treatment on the first insulating layer IL1 and the exposed portion of the first metal layer M1 may, for example, achieve the following effects. Increase the surface roughness of the first insulating layer IL1 and/or increase the cross-linking degree of the material in the first insulating layer IL1; and/or remove the native oxide (native oxide) formed on the first metal layer M1. That is, after the surface of the first insulating layer IL1 and the exposed portion of the first metal layer M1 are treated with the first plasma, the adhesion between the seed layer to be formed subsequently and the surface thereof can be improved. In some embodiments, the gas used in the first plasma treatment may include oxygen, hydrogen, argon, or combinations thereof, but the present disclosure is not limited thereto.

In step S140 of this embodiment, after performing the first plasma treatment, the carrier CP on which the first seed layer SEED1, the first metal layer M1 and the first insulating layer IL1 are formed is placed in the micro-environment control box 110 . In an embodiment shown in FIG. 4 , the micro-environment control box 110 is one of the components in the micro-environment control device 100 . The micro-environment control device 100 may include a micro-environment control box 110 , a gas supply device 120 , and a gas supply device 120 . The delivery pipeline 130 and the gas condition control device 140 are provided, but the present disclosure is not limited thereto. The micro-environment control box 110 may include, for example, an upper bracket 112, a lower bracket 114, a plurality of pillars 116 and a plurality of struts 118, wherein the plurality of pillars 116 are disposed between the upper bracket 112 and the lower bracket 114 to form a micro-environment control box. 110, a plurality of struts 118 are spaced apart on each pillar 116, and the extension direction of the plurality of struts 118 is perpendicular to the extension direction of the pillars 116, for example, for carrying the carrier plate CP, but this disclosure does not use This is the limit. The gas supply device 120 is loaded with nitrogen, clean dry air (Clean Dry Air; CDA) or other suitable gases for providing to the microenvironment control box 110 , for example. The gas delivery pipeline 130 is, for example, used to deliver the gas loaded in the gas supply device 120 to the micro-environment control box 110 . The gas condition control device 140 is, for example, used to control the conditions of the gas delivered to the micro-environment control box 110 . Specifically, in this embodiment, the gas condition control device 140 includes an oxygen condition control element 142 and a water gas condition control element 144, where the oxygen condition control element 142 can control the concentration of gas delivered to the micro-environment control box 110, And the water vapor condition control element 144 can control the relative humidity of the gas delivered to the micro-environment control box 110 . In this embodiment, the oxygen concentration in the microenvironment control box 110 is less than 1000 ppm, and the relative humidity in the microenvironment control box 110 is less than 50%. In addition, in some embodiments, the temperature in the microenvironment control box 110 is greater than or equal to 25°C and less than or equal to 30°C, the air pressure in the microenvironment control box 110 is greater than 1 atm, and the temperature in the microenvironment control box 110 The gas may include nitrogen or clean dry air (delivered by gas supply 120). Based on this, after the carrier CP on which the first seed layer SEED1, the first metal layer M1 and the first insulating layer IL1 are formed is placed in the micro-environment control box 110, due to the oxygen and water vapor in the micro-environment control box 110 The content is significantly less than the content of oxygen and water vapor in the atmospheric environment. The exposed part of the surface of the first metal layer M1 may not be quickly oxidized and/or the rough surface of the first insulating layer IL1 may not be penetrated by a large amount of water vapor. This allows the second seed layer SEED2 to be formed subsequently to be stably formed and attached to the exposed portion of the surface of the first metal layer M1 and the surface of the first insulating layer IL1, that is, it can allow the second seed layer The adhesion between SEED2 and part of the surface of the first metal layer M1 and the surface of the first insulating layer IL1 increases. In addition, in some embodiments, before performing the first plasma treatment on the first insulating layer IL1 and the exposed part of the first metal layer M1, the carrier CP may also be transported to the coating device to the surface treatment device. Utilize microenvironment control box 110. In some embodiments, the surface roughness of the first metal layer M1 becomes larger after plasma treatment. In other words, the surface roughness of the first metal layer M1 after plasma treatment may be greater than that without plasma treatment. Surface roughness of the first metal layer M1. In some embodiments, roughness can be measured using an atomic force microscope (AFM) or other suitable measuring instrument. In addition, the aforementioned "roughness" can be the arithmetic average roughness (Ra), that is, the arithmetic average of the deviation values from the centerline distance over the length of the sampled portion, but the present disclosure is not limited to this.

In step S150 of this embodiment, after the carrier board CP is taken out from the micro-environment control box 110, a second seed layer SEED2 is formed on the first insulating layer IL1 and the exposed part of the first metal layer M1. The step of forming the second seed layer SEED2 may refer to the aforementioned step S100 and will not be described again. In addition, after the carrier CP is taken out of the micro-environment control box 110, it can be selectively put into the atmospheric environment for subsequent processes. However, the time it takes is not long for the first metal layer M1 located on the carrier CP to interact with the first metal layer M1. The surface of the insulating layer IL1 may not be affected. In addition, the present disclosure does not need to deliberately connect the surface treatment device and the coating device, which improves the process efficiency of manufacturing the packaging structure of the electronic device.

In this embodiment, at least one cycle of the steps of forming the metal layer and the insulating layer can be repeated to form the redistribution structure RDL as shown in FIG. 2 , wherein the redistribution structure RDL can be used as the wiring of the electronic device. layer to provide the required conductive transmission path. For example, as shown in FIG. 2 , the redistribution structure RDL may include a first seed layer SEED1, a first metal layer M1, a first insulating layer IL1 with a plurality of first openings OP1, and a second seed layer SEED2. , the second metal layer M2, the second insulating layer IL2 with a plurality of second openings OP2, the third seed layer SEED3, the third metal layer M3, the third insulating layer IL3 with a plurality of third openings OP3, the fourth The seed layer SEED4 and the fourth metal layer M4 have an insulating layer IL4 with a plurality of fourth openings OP4, the fifth seed layer SEED5 and the fifth metal layer M5, but the disclosure is not limited thereto. In detail, after forming the second seed layer SEED2 on the first insulating layer IL1 and the exposed portion of the first metal layer M1 (step S150 ), it may also include, for example, performing at least one cycle of the following steps in sequence: first , forming the second metal layer M2 on the second seed layer SEED2. This step can refer to step S110 of the previous embodiment. In addition, during the process of forming the second metal layer M2, part of the second seed layer SEED2 is also was removed. Next, a second insulating layer IL2 is formed on the second metal layer M2, where the second insulating layer IL2 exposes part of the second metal layer M2. For this step, please refer to step S120 of the previous embodiment. Afterwards, a second plasma treatment is performed on the second insulating layer IL2 and the exposed part of the second metal layer M2. For this step, please refer to step S130 of the previous embodiment. Next, after performing the second plasma treatment, the first seed layer SEED1, the first metal layer M1, the first insulating layer IL1, the second seed layer SEED2, the second metal layer M2 and the second insulating layer are formed. The carrier board CP of IL2 is placed in the micro-environment control box 110. For this step, please refer to step S140 of the previous embodiment. Then, after the carrier board CP is taken out from the micro-environment control box 110, a third seed layer SEED3 is formed on the second insulating layer IL2 and the exposed part of the second metal layer M2. This step can refer to the previous embodiment. Step S150.

In some embodiments, as shown in FIG. 3 , the first opening OP1 may have a width W in a direction perpendicular to the normal direction of the carrier CP, where the width W may be greater than or equal to 10 microns and less than or equal to 20 micron, so that the resistance of the second seed layer SEED2 and the second metal layer M2 formed in the first opening OP1 can be less than or equal to 0.05 ohm (ohm), but the disclosure is not limited thereto. In addition, the second opening OP2, the third opening OP3 and the fourth opening OP4 may also have a width W greater than or equal to 10 microns and less than or equal to 20 microns, and the present disclosure is not limited thereto.

At this point, the production of the packaging structure 10 of the disclosed embodiment is completed. It is worth noting that although the method for manufacturing the packaging structure 10 of this embodiment is explained by taking the above method as an example; however, the method for forming the packaging structure of the present disclosure is not limited to this. For example, after the redistribution structure RDL is formed, the process of forming a semiconductor wafer can be continued. That is, the manufacturing method of the package structure 10 of this embodiment is a redistribution structure first (RDL first) process. In addition, although the packaging structure 10 of the embodiment of the disclosure is used in panel-level packaging as an example; however, the packaging structure 10 of the disclosure can be applied to various semiconductor devices and/or semiconductor manufacturing processes, and the disclosure is not limited thereto. . In addition, the packaging structure 10 of the embodiment of the disclosure can be bonded to electronic components such as integrated circuit chips and/or printed circuit boards in subsequent processes, but the disclosure is not limited thereto. The above-mentioned bonding method may, for example, provide bonding pads between the redistribution structure RDL and the electronic components, but the disclosure is not limited thereto.

In summary, some embodiments of the present disclosure provide a method for manufacturing a package structure by performing plasma treatment on the insulating layer and the exposed metal layer provided on the carrier board and forming subsequent wafers on the carrier board. Before the seed layer, the carrier plate including the metal layer and the insulating layer formed in the previous process is placed in a micro-environment control box, which can make the subsequent formation of the seed layer and the surface of the metal layer on the carrier plate and the insulating layer The adhesion between the surfaces increases, thereby further improving the reliability and/or electrical properties of the electronic device including the packaging structure. Furthermore, the surface treatment device and the coating device used in the manufacturing method of the package structure provided by the present disclosure do not need to be connected. That is, independent surface treatment devices and coating devices can be used to perform the plasma treatment process and the film forming process respectively. This improves the process efficiency of manufacturing the packaging structure of the electronic device of the present disclosure.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present disclosure, but not to limit it. Although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments can still be modified, or some or all of the technical features can be equivalently replaced; and these modifications or substitutions do not deviate from the essence of the corresponding technical solutions from the technical solutions of the embodiments of the present disclosure. Scope. Features of various embodiments may be mixed and matched as long as they do not violate the spirit of the invention or conflict with each other.

10:Package structure 100:Micro-environment control device 110:Micro-environment control box 112: Upper bracket 114:Lower bracket 116:Pillar 118:Strut 120:Gas supply device 130:Gas transmission pipeline 140:Gas condition control device 142:Oxygen condition control element 144: Water and gas condition control element CP: carrier board IL1: first insulating layer IL2: Second insulation layer IL3: The third insulating layer IL4: The fourth insulating layer M1: first metal layer M2: Second metal layer M3: The third metal layer M4: The fourth metal layer M5: fifth metal layer OP1: First opening OP2: Second opening OP3: The third opening OP4: The fourth opening RDL: rewiring structure RL: release layer S100, S110, S120, S130, S140, S150: steps SEED1: The first seed layer SEED2: The second seed layer SEED3: The third seed layer SEED4: The fourth seed layer SEED5: The fifth seed layer W: Width

FIG. 1 is a flow chart of a method for manufacturing a packaging structure of an electronic device according to an embodiment of the present disclosure. FIG. 2 is a schematic cross-sectional view of a packaging structure of an electronic device according to an embodiment of the present disclosure. FIG. 3 is a partially enlarged cross-sectional view of the packaging structure of the electronic device according to FIG. 2 . FIG. 4 is a schematic diagram of a micro-environment control device according to an embodiment of the present disclosure.

S100, S110, S120, S130, S140, S150: Steps

Claims (8)

A method for manufacturing a packaging structure of an electronic device, including: forming a first seed layer on a carrier plate; forming a first metal layer on the first seed layer, wherein the first metal layer is a copper layer; A first insulating layer is formed on the first metal layer, wherein the first insulating layer exposes a portion of the first metal layer; the first insulating layer and the exposed portion of the third layer are A metal layer is subjected to a first plasma treatment; after the first plasma treatment, the carrier plate with the first seed layer, the first metal layer and the first insulating layer is placed. in the micro-environment control box; and after taking the carrier board out of the micro-environment control box, forming a second layer on the first insulating layer and the exposed portion of the first metal layer. Seed crystal layer, wherein the relative humidity in the micro-environment control box is less than 50%, and the air pressure in the micro-environment control box is greater than 1 atm. The manufacturing method of an electronic device packaging structure as claimed in claim 1, wherein the oxygen concentration in the microenvironment control box is less than 1000 ppm. The method for manufacturing a packaging structure of an electronic device according to claim 1, wherein the temperature in the micro-environment control box is greater than or equal to 25°C and less than or equal to 30°C. The method for manufacturing a packaging structure of an electronic device according to claim 1, wherein the gas in the micro-environment control box includes nitrogen or clean dry air. The method for manufacturing a packaging structure of an electronic device according to claim 1, wherein the carrier plate includes a glass carrier plate. The method for manufacturing a packaging structure of an electronic device according to claim 1, wherein a release layer is formed on the carrier board before forming the first seed layer on the carrier board. The method for manufacturing a packaging structure of an electronic device according to claim 1, wherein the gas used in the first plasma treatment includes oxygen, hydrogen, argon or a combination thereof. The method for manufacturing a packaging structure of an electronic device according to claim 1, wherein after forming the second seed layer on the first insulating layer and the exposed portion of the first metal layer, It also includes: forming a second metal layer on the second seed layer; forming a second insulating layer on the second metal layer, wherein the second insulating layer exposes part of the second metal layer; A second plasma treatment is performed on the second insulating layer and the exposed portion of the second metal layer; after the second plasma treatment, the first seed layer, The first metal layer, the first insulation layer, the second seed layer, the second metal layer and the carrier board of the second insulation layer are placed in the micro-environment control box; as well as After the carrier board is taken out from the micro-environment control box, a third seed layer is formed on the second insulating layer and the exposed portion of the second metal layer.

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