TWI817767B - Semiconductor device with fuse structure - Google Patents

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate, a fuse element, and a fuse medium. The fuse element is disposed within the substrate. The fuse medium surrounds a lateral surface of the fuse element.

Description

Semiconductor component with fuse structure

This application claims priority to U.S. Patent Application Nos. 17/839,796 and 17/840,097 (that is, the priority date is "June 14, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor device. In particular, it relates to a semiconductor element including a fuse structure embedded in a substrate.

Many integrated circuits (ICs) are composed of millions of interconnected components, such as transistors, resistors, capacitors, and diodes, on a single chip of a semiconductor substrate. It is generally hoped that the IC can operate as fast as possible and consume as little power as possible. Semiconductor ICs often include one or more types of memory, such as complementary metal-oxide semiconductor (CMOS) memory, antifuse (antifuse) memory, and electronic fuse (efuse) memory.

Electronic fuses are typically integrated into the semiconductor IC through a semiconductor material (eg, polycrystalline silicon) disposed on a dielectric layer (eg, silicon oxide). A programming current is applied to blow out the dielectric layer, thereby changing the resistivity of the electronic fuse. This is called "programming" the electronic fuse. However, this structure requires a relatively large breakdown voltage, which can adversely affect the performance of the semiconductor component.

The above description of "prior art" is only to provide background technology, and does not admit that the above description of "prior art" discloses the subject matter of the present disclosure. It does not constitute the prior art of the present disclosure, and any description of the above "prior art" They should not be used as any part of this case.

One aspect of the present disclosure provides a semiconductor device. The semiconductor element includes a substrate, a fuse element, and a fuse medium. The fuse element is arranged in the substrate. The fuse medium surrounds one side surface of the fuse element.

Another aspect of the present disclosure provides a semiconductor device. The semiconductor element includes a substrate, a fuse element, and a fuse medium. The fuse element is disposed in the substrate and extends from an upper surface of the substrate. The fuse medium is in contact with the fuse element. The fuse medium is spaced apart from the upper surface of the substrate.

Another aspect of the present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a substrate. The method also includes forming a fuse element in the substrate. The method further includes forming a fuse medium in the substrate, wherein the fuse medium surrounds the fuse element.

An embodiment of the present invention provides a fuse structure. The fuse structure can be embedded in a substrate. The fuse structure may include a fuse element and a fuse medium. The fuse dielectric is composed of a semiconductor material with dopants. The fuse structure may have a relatively small breakdown voltage.

The technical features and advantages of the present disclosure have been summarized rather broadly above so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages that constitute the subject matter of the patentable scope of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be readily modified Or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

1a: Semiconductor components

10:Substrate

10s1: Surface

11:Well area

20: Fuse structure

20h:Open your mouth

21: Fuse component

21’: Semiconductor layer

21s1: Surface

21s2: Surface

21s3: Surface

22: Fuse medium

31: Doped area

31s1:Border

32: Doped area

32s1:Border

33: Doped area

33s1:Border

34: Doped area

41: Dielectric layer

42:Dielectric layer

42h:Open your mouth

43:Dielectric layer

43h:Open your mouth

51: Conductive parts

52: Conductive parts

53: Conductive parts

54: Conductive parts

55: Conductive parts

61:Curtain

200:Method

201:Operation

202:Operation

203:Operation

204:Operation

205:Operation

206:Operation

207:Operation

208:Operation

209:Operation

210:Operation

211:Operation

212:Operation

A-A’: line

L1:Length

L2: length

X: axis

Z: axis

A more complete understanding of the present disclosure can be obtained by referring to the detailed description and claimed claims when considered in conjunction with the drawings, wherein like reference numerals represent similar elements throughout the drawings.

FIG. 1A is a top view of a semiconductor device according to some embodiments of the present disclosure.

FIG. 1B is a cross-sectional view drawn along line A-A’ of the semiconductor device shown in FIG. 1A according to some embodiments of the present disclosure.

FIGS. 2A and 2B are flow charts showing preparation of a semiconductor device according to some embodiments of the present disclosure.

FIG. 3A illustrates one or more stages of an exemplary method of fabricating a semiconductor device according to some embodiments of the present disclosure.

Figure 3B is a cross-sectional view drawn along line A-A' of Figure 3A showing some embodiments of the present disclosure.

FIG. 4A illustrates one or more stages of an exemplary method of fabricating a semiconductor device according to some embodiments of the present disclosure.

Figure 4B is a cross-sectional view drawn along line A-A' of Figure 4A showing some embodiments of the present disclosure.

FIG. 5A illustrates one or more stages of an exemplary method of fabricating a semiconductor device according to some embodiments of the present disclosure.

Figure 5B is a cross-sectional view drawn along line A-A' of Figure 5A showing some embodiments of the present disclosure.

FIG. 6A illustrates one or more stages of an exemplary method of fabricating a semiconductor device according to some embodiments of the present disclosure.

Figure 6B is a cross-sectional view drawn along line A-A' of Figure 6A showing some embodiments of the present disclosure.

FIG. 7A illustrates one or more stages of an exemplary method of fabricating a semiconductor device according to some embodiments of the present disclosure.

Figure 7B is a cross-sectional view drawn along line A-A' of Figure 7A showing some embodiments of the present disclosure.

8A illustrates one or more stages of an exemplary method of fabricating a semiconductor device according to some embodiments of the present disclosure.

Figure 8B is a cross-sectional view drawn along line A-A' of Figure 8A showing some embodiments of the present disclosure.

FIG. 9A illustrates one or more stages of an exemplary method of fabricating a semiconductor device according to some embodiments of the present disclosure.

Figure 9B is a cross-sectional view drawn along line A-A' of Figure 9A showing some embodiments of the present disclosure.

FIG. 10A illustrates one or more stages of an exemplary method of fabricating a semiconductor device according to some embodiments of the present disclosure.

10B is a cross-sectional view drawn along line A-A' of FIG. 10A showing some embodiments of the present disclosure.

FIG. 11A illustrates one or more stages of an exemplary method of fabricating a semiconductor device according to some embodiments of the present disclosure.

Figure 11B is a cross-sectional view drawn along line A-A' of Figure 11A showing some embodiments of the present disclosure.

FIG. 12A illustrates one or more stages of an exemplary method of fabricating a semiconductor device according to some embodiments of the present disclosure.

Figure 12B is a cross-sectional view drawn along line A-A' of Figure 12A showing some embodiments of the present disclosure.

FIG. 13A illustrates one or more stages of an exemplary method of fabricating a semiconductor device according to some embodiments of the present disclosure.

Figure 13B is a cross-sectional view drawn along line A-A' of Figure 13A showing some embodiments of the present disclosure.

FIG. 14A illustrates one or more stages of an exemplary method of fabricating a semiconductor device according to some embodiments of the present disclosure.

Figure 14B is a cross-sectional view drawn along line A-A' of Figure 14A showing some embodiments of the present disclosure.

Specific language will now be used to describe the embodiments or examples of the disclosure illustrated in the drawings. It should be understood that there is no intention to limit the scope of the present disclosure. Any changes or modifications to the embodiments described, as well as any further applications of the principles described herein, are deemed to be within the scope of those skilled in the art relevant to this disclosure. This disclosure may repeat reference symbols in different embodiments, but even if they share the same reference symbol, it does not necessarily mean that components of one embodiment are applicable to another embodiment.

It will be understood that when an element is referred to as being "connected" or "coupled" to another element, the initial element can be directly connected or coupled to the other element or intervening elements may be present.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not to be limited by these terms. limit. Rather, these terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the concepts of the present disclosure.

The terminology used herein is for the purpose of describing particular example embodiments only, and This disclosure is not intended to be limiting. As used herein, the singular forms "a/an" and "the" include the plural forms as well, unless the context clearly dictates otherwise. It should be understood that the use of the words "comprises" and "comprising" in this specification indicates the presence of the stated parts, integers, steps, operations, elements, or components, but does not exclude the presence or addition of One or more other parts, integers, steps, operations, elements, components, or combinations of the foregoing.

It should be noted that the term "about" when used to modify an amount of an ingredient, component, or reactant used in this disclosure refers to variations in quantities that may occur, for example, through typical measurements and liquid handling procedures for preparing concentrates or solutions. In addition, variations may occur due to inadvertent errors in measurement procedures, differences in the manufacture, source, or purity of ingredients used in the compositions or methods implemented, etc. On the one hand, the term "approximately" means within 10% of the reported value. On the other hand, the term "approximately" means within 5% of the reported value. Still, on the other hand, the term "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

1A and 1B illustrate a semiconductor device 1a according to some embodiments of the present disclosure. Fig. 1A is a top view, and Fig. 1B is a cross-sectional view taken along line A-A' in Fig. 1A. In some embodiments, semiconductor element la may include, for example, a memory element or other suitable element. Memory devices may include, for example, one-time programmable (OTP) memory devices, dynamic random access memory (DRAM) devices, static random access memory (static random access memory); SRAM) components, or other suitable memory components.

In some embodiments, the semiconductor device 1a may include a substrate 10, a fuse structure 20, doped regions 31, 32, 33, and 34, dielectric layers 41, 42, and 43, and conductive components 51, 52, 53, 54, and 55.

The substrate 10 may be a semiconductor substrate, such as a bulk semiconductor or an insulator upper half. Conductor (semiconductor-on-insulator; SOI) substrate, or the like. The substrate 10 may include elemental semiconductors including single crystal forms, polycrystalline forms, or amorphous forms of silicon or germanium; compound semiconductor materials including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and at least one of indium antimonide; alloy semiconductor materials, including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material; or a combination of the foregoing. In some embodiments, the alloy semiconductor substrate may be a SiGe alloy having a gradient Ge feature, wherein the Si and Ge compositions change from one ratio at one location of the gradient SiGe feature to another ratio at another location of the gradient SiGe feature . In another embodiment, a SiGe alloy is formed on a silicon substrate. In some embodiments, another material in contact with the SiGe alloy may mechanically strain the SiGe alloy. In some embodiments, the substrate 10 may have a multi-layer structure, or the substrate 10 may include a multi-layer compound semiconductor structure. The substrate 10 may have a surface 10s1. Surface 10s1 may also be called the upper surface.

The substrate 10 may include a well region 11 . The well region 11 may be located within the substrate 10 . In some embodiments, well region 11 may include a first conductivity type. In some embodiments, the first conductivity type is p-type. In some embodiments, p-type dopants include boron (B), other Group III elements, or combinations of any of the foregoing. In some embodiments, the first conductivity type is n-type. In some embodiments, n-type dopants include arsenic (As), phosphorus (P), other Group V elements, or combinations of any of the foregoing.

In some embodiments, the fuse structure 20 may be disposed within the substrate 10 . In some embodiments, a portion of the fuse structure 20 may be embedded in the substrate 10 . In some embodiments, a portion of fuse structure 20 may protrude from surface 10s1 of substrate 10 . In some embodiments, from a top view, the fuse structure 20 may include a circular outline, an elliptical outline, or other Fitted silhouette. In some embodiments, fuse structure 20 may have fuse element 21 and fuse medium 22 .

In some embodiments, the fuse element 21 may be disposed within the substrate 10 . In some embodiments, a portion of the fuse element 21 may be embedded in the substrate 10 . In some embodiments, a portion of fuse element 21 may protrude from surface 10s1 of substrate 10 . The fuse element 21 may have a surface 21s1, a surface 21s2 opposite the surface 21s1, and a surface 21s3 extending along the surfaces 21s1 and 21s2. Surface 21s1 may also be called a lower surface. Surface 21s2 may also be referred to as the upper surface. Surface 21s3 may also be called a side surface. In some embodiments, surface 21s2 of fuse element 21 and surface 10s1 of substrate 10 may be located at different levels. In some embodiments, the level of the surface 21s2 of the fuse element 21 may be higher than the level of the surface 10s1 of the substrate 10.

In some embodiments, fuse element 21 may include a semiconductor material, such as polycrystalline silicon, silicon germanium, and/or other suitable materials. In some embodiments, fuse element 21 may include a dopant having a second conductivity type that is different than the first conductivity type.

In some embodiments, the fuse element 21 may include a circular profile, an elliptical profile, or other suitable profile when viewed from a top view.

In some embodiments, fuse media 22 may be disposed within substrate 10 . In some embodiments, fuse media 22 may be spaced apart from surface 10s1 of substrate 10 . In some embodiments, fuse medium 22 may surround fuse element 21 . In some embodiments, fuse medium 22 may surround surface 21s3 of fuse element 21. In some embodiments, fuse medium 22 may be in contact with fuse element 21 . In some embodiments, fuse medium 22 may be in contact with surface 21s3 of fuse element 21. In some embodiments, fuse medium 22 may be in contact with the surface of fuse element 21 21s1 spaced. In some embodiments, fuse medium 22 may be spaced apart from surface 21s2 of fuse element 21.

In some embodiments, the doped region 31 may be disposed within the substrate 10 . In some embodiments, doped region 31 may have a first conductivity type. In some embodiments, doped region 31 may have a relatively large doping concentration. For example, the doping concentration of the doped region 31 may be on the order of 10 ²⁰ doping ions/cm ³ .

In some embodiments, doped region 31 may serve as fuse dielectric 22 . In some embodiments, doped region 31 may be spaced apart from surface 10s1 of substrate 10 . In some embodiments, doped region 31 may surround fuse element 21 . In some embodiments, doped region 31 may surround surface 21s3 of fuse element 21. In some embodiments, doped region 31 may be in contact with fuse element 21 . In some embodiments, doped region 31 may be in contact with surface 21s3 of fuse element 21. In some embodiments, doped region 31 may be spaced apart from surface 21s1 of fuse element 21 . In some embodiments, doped region 31 may be spaced apart from surface 21s2 of fuse element 21. In some embodiments, from a top view, the doped region 31 may include a circular outline, an elliptical outline, or other suitable outlines.

In some embodiments, the doped region 32 may be disposed within the substrate 10 . In some embodiments, doped region 32 may have a first conductivity type. In some embodiments, doped region 32 may have a relatively small doping concentration. For example, the doping concentration of doped region 32 may range from about 10 ¹⁸ doping ions/cm ³ to about 10 ¹⁹ doping ions/cm ³ .

In some embodiments, the doped region 32 may be disposed above the doped region 31 . In some embodiments, doped region 32 may extend from surface 10s1 of substrate 10 . The doped region 32 may be in contact with the surface 10s1 of the substrate 10 . In some embodiments, the doped region 31 may be spaced apart from the surface 10s1 of the substrate 10 through the doped region 32 . In some embodiments, doped region 32 may surround the melt Wire element 21. In some embodiments, doped region 32 may surround surface 21s3 of fuse element 21. In some embodiments, doped region 32 may be in contact with fuse element 21 . In some embodiments, doped region 32 may be in contact with surface 21s3 of fuse element 21. In some embodiments, doped region 32 may be spaced apart from surface 21s1 of fuse element 21 . In some embodiments, doped region 32 may be spaced apart from surface 21s2 of fuse element 21. In some embodiments, from a top view, the doped region 32 may include a circular profile, an elliptical profile, or other suitable profiles.

In some embodiments, the doped region 33 may be disposed within the substrate 10 . In some embodiments, doped region 33 may have a first conductivity type. In some embodiments, doped region 33 may have a relatively small doping concentration. For example, the doping concentration of the doped region 33 may range from about 10 ¹⁸ doping ions/cm ³ to about 10 ¹⁹ doping ions/cm ³ .

In some embodiments, the doped region 33 may be disposed under the doped region 31 . In some embodiments, doped region 33 may surround fuse element 21 . In some embodiments, doped region 33 may surround surface 21s3 of fuse element 21. In some embodiments, doped region 33 may be in contact with fuse element 21 . In some embodiments, doped region 33 may be in contact with surface 21s3 of fuse element 21. In some embodiments, doped region 33 may be in contact with surface 21s1 of fuse element 21 . In some embodiments, doped region 33 may cover the corner defined by surfaces 21s1 and 21s3 of fuse element 21 . In some embodiments, from a top view, the doped region 33 may include a circular outline, an elliptical outline, or other suitable outlines.

The boundary 31s1 may be located between the doped region 31 and the well region 11. The boundary 32s1 may be located between the doped region 32 and the well region 11 . The boundary 33s1 may be located between the doped region 33 and the well region 11. In some embodiments, boundary 31s1 may be substantially coplanar with boundary 32s1. In some embodiments, boundary 31s1 may be substantially coplanar with boundary 33s1. In some embodiments, boundary 32s1 may be substantially coplanar with boundary 33s1. In some embodiments, boundaries 31s1 and 32s1 may be Substantially continuous. In some embodiments, boundaries 31s1 and 33s1 may be substantially continuous. The doped region 31 may have a length L1 along the Z-axis. Doped region 32 may have a length L2 along the Z-axis. In some embodiments, length L2 may be greater than length L1.

Doped regions 31 and 33 may be configured to define a region (or boundary) of the fuse medium (eg, doped region 32). The doped region 33 may be configured to reduce signal noise when the fuse structure 20 is blown.

In some embodiments, the doped region 34 may be disposed within the substrate 10 . In some embodiments, doped region 34 may have a first conductivity type. In some embodiments, doped region 34 may have a relatively large doping concentration. For example, the doping concentration of doped region 34 may be on the order of 10 ²⁰ doping ions/cm ³ .

In some embodiments, the doped region 34 may be disposed above the doped region 31 . In some embodiments, doped region 34 may extend from surface 10s1 of substrate 10 . In some embodiments, doped region 34 may be spaced apart from fuse structure 20 . In some embodiments, doped region 34 may be spaced apart from fuse element 21 . In some embodiments, doped region 34 may be spaced apart from doped region 31 . In some embodiments, doped region 34 may be in contact with doped region 32 . In some embodiments, doped region 34 may be spaced apart from doped region 33 . In some embodiments, doped region 34 may vertically overlap doped region 31 . In some embodiments, doped region 34 may vertically overlap doped region 32 . In some embodiments, doped region 34 may vertically overlap doped region 33 . In some embodiments, the doped region 34 may have a rectangular profile, a square profile, or other suitable profile when viewed from a top view.

In some embodiments, the dielectric layer 41 may be disposed on the surface 10s1 of the substrate 10 . In some embodiments, the dielectric layer 41 may be disposed on the doped region 34 of the substrate 10 . In some embodiments, dielectric layer 41 may expose fuse element 21 . In some embodiments, dielectric layer 41 may include silicon oxide, silicon nitride, silicon oxynitride, other dielectric materials, or combinations thereof. In some embodiments, dielectric layer 41 may include a multilayer structure including an interface layer and a high-k (dielectric constant greater than 4) dielectric layer. The interface layer may include dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, other dielectric materials, or combinations thereof. The high-k dielectric layer may include high-k dielectric materials, such as HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, other suitable high-k dielectric materials, or combinations thereof.

In some embodiments, the dielectric layer 42 may be disposed on the surface 10s1 of the substrate 10 . In some embodiments, dielectric layer 42 may be disposed on dielectric layer 41 . In some embodiments, dielectric layer 42 may cover a portion of fuse structure 20 . In some embodiments, dielectric layer 42 may cover a portion of fuse element 21 . In some embodiments, dielectric layer 42 may cover a portion of dielectric layer 41 . Dielectric layer 42 may include silicon oxide, carbon-containing oxides such as silicon oxycarbide (SiOC), silicate glass, tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, Or doped silicon oxide such as borophosphosilicate glass (BPSG), fluorine-doped silica glass (FSG), phosphosilicate glass (PSG), boron Boron doped silicon glass (BSG), a combination of the above, and/or other suitable dielectric materials.

In some embodiments, the dielectric layer 43 may be disposed on the surface 10s1 of the substrate 10 . In some embodiments, dielectric layer 43 may be disposed on dielectric layer 42 . In some embodiments, dielectric layer 42 may cover a portion of fuse element 21 . Dielectric layer 43 may include silicon oxide, carbon-containing oxides such as silicon oxycarbide, silicate glass, tetraethoxysilane oxide, undoped silicate glass, or doped silicon oxide. Is boron phosphorus silicate glass, fluorine doped silicon glass glass, phosphosilicate glass, boron-doped silica glass, combinations of the foregoing, and/or other suitable dielectric materials.

In some embodiments, conductive component 51 may be disposed on fuse structure 20 . In some embodiments, the conductive component 51 may be disposed on the fuse element 21 . In some embodiments, conductive component 51 may be configured to electrically connect fuse element 21 . In some embodiments, conductive component 51 may be embedded in dielectric layer 42 . In some embodiments, the conductive component 51 may include conductive materials, such as tungsten (W), copper (Cu), aluminum (Al), tantalum (Ta), molybdenum (Mo), tantalum nitride (TaN), titanium, Titanium nitride (TiN), similar materials, and/or combinations of the foregoing.

In some embodiments, the conductive component 52 may be disposed on the surface 10s1 of the substrate 10 . In some embodiments, conductive features 52 may be disposed on doped regions 34 . In some embodiments, conductive component 52 may be configured to electrically connect doped region 34 . In some embodiments, conductive component 52 may be embedded in dielectric layer 41 . The material of conductive component 52 may be the same as or similar to the material of conductive component 51 .

In some embodiments, conductive component 53 may be disposed on fuse structure 20 . In some embodiments, conductive component 53 may be disposed on fuse element 21 . In some embodiments, conductive component 53 may be disposed on dielectric layer 42 . In some embodiments, the conductive component 53 may be disposed on the conductive component 51 . In some embodiments, conductive component 53 may be configured to electrically connect fuse element 21 and conductive component 51 . In some embodiments, conductive component 53 may be embedded in dielectric layer 43 . The material of the conductive component 53 may be the same as or similar to the material of the conductive component 51 .

In some embodiments, the conductive component 54 may be disposed on the surface 10s1 of the substrate 10 . In some embodiments, conductive features 54 may be disposed on doped regions 34 . in some In embodiments, the conductive component 54 may be disposed on the dielectric layer 42 . In some embodiments, conductive component 54 may be disposed on conductive component 52 . In some embodiments, conductive component 54 may be configured to electrically connect doped region 34 and conductive component 52 . In some embodiments, conductive component 52 may be embedded in dielectric layer 43 . The material of conductive component 54 may be the same as or similar to the material of conductive component 51 .

In some embodiments, conductive component 55 may be disposed on fuse structure 20 . In some embodiments, conductive component 55 may be disposed on fuse element 21 . In some embodiments, conductive component 55 may be disposed on conductive component 53 . In some embodiments, conductive component 55 may be disposed on dielectric layer 43 . In some embodiments, conductive component 55 may be configured to electrically connect fuse element 21 , conductive component 51 , and conductive component 53 . The material of conductive component 55 may be the same as or similar to the material of conductive component 51 .

In some embodiments, the fuse element 21 and the doped region 31 may form a PN junction. In some embodiments, the fuse element 21 and the doped region 32 may form a PN junction. In some embodiments, fuse element 21 and doped region 33 may form a PN junction. In some embodiments, the breakdown voltage between fuse element 21 and doped region 31 may be less than the breakdown voltage between fuse element 21 and doped region 32 . In some embodiments, the breakdown voltage between fuse element 21 and doped region 31 may be less than the breakdown voltage between fuse element 21 and doped region 33 .

In some embodiments, the breakdown voltage between fuse element 21 and doped region 31 may range from about 4V to about 5V, such as 4V, 4.2V, 4.4V, 4.6V, 4.8V, or 5V. In some embodiments, the breakdown voltage between fuse element 21 and doped region 32 may range from about 8V to about 10V, such as 8V, 8.4V, 8.8V, 9.2V, 9.6V, or 10V. In some embodiments, the breakdown voltage between fuse element 21 and doped region 33 may range from about 8V to about 10V, such as 8V, 8.4V, 8.8V, 9.2V, 9.6V, or 10V. For example, when When a voltage of 5V is applied to the fuse element 21, the fuse structure 20 can be turned on, thereby blowing the fuse structure 20. Signals (eg, electrical signals) may be transmitted to the doped region 34 through the fuse dielectric 22 and the boundaries 31s1 and 32s1.

In comparative semiconductor components, polycrystalline silicon and silicon oxide serve as fuse components and fuse media respectively. Comparative semiconductor components may have relatively large breakdown voltages, which may range from approximately 5V to approximately 6V or higher. In embodiments of the present disclosure, the semiconductor element 1a may have a relatively small breakdown voltage. The fuse structure (eg, 20) may be embedded in the substrate (eg, 10), thereby reducing the Z-dimension of the semiconductor element 1a. In addition, the process of forming the logic element can be applied to the fuse structure, which is beneficial to the formation cost of the semiconductor element 1a.

Referring to some embodiments of the present disclosure, FIG. 2A and FIG. 2B are flowcharts of a method 200 for preparing a semiconductor device.

Referring to FIG. 2A, method 200 begins with operation 201, where a substrate may be provided. The substrate may include well areas. The substrate may include an upper surface. The well region may include a first conductivity type. In some embodiments, the first conductivity type is p-type. In some embodiments, the first conductivity type is n-type.

The method 200 continues to operation 202, where a first doped region, a second doped region, and a third doped region may be formed in the substrate. Each of the first doped region, the second doped region, and the third doped region may have a first conductivity type. In some embodiments, the first doped region may be spaced apart from the upper surface of the substrate. In some embodiments, the third doped region may be spaced apart from the upper surface of the substrate. In some embodiments, the first doped region may be formed between the second doped region and the third doped region. In some embodiments, the doping concentration of the first doped region may be greater than the doping concentration of the second doped region. In some embodiments, the doping concentration of the first doping region may be greater than the doping concentration of the third doping region.

In some embodiments, the first boundary of the first doped region and the second boundary of the second doped region may be substantially continuous. In some embodiments, the first boundary of the first doped region and the third boundary of the third doped region may be substantially continuous. In some embodiments, the second doped region may extend from the upper surface of the substrate. In some embodiments, each of the first doped region, the second doped region, and the third doped region may have a circular profile, an elliptical profile, or other suitable profiles.

Method 200 continues to operation 203 where a first dielectric layer may be formed. The first dielectric layer may be formed on the upper surface of the substrate.

Method 200 continues to operation 204 where a first opening may be formed. In some embodiments, the first opening may pass through the substrate. In some embodiments, the first opening may pass through the first dielectric layer. In some embodiments, the first opening may pass through the first doped region. In some embodiments, the first opening may pass through the second doped region. In some embodiments, the first opening may expose the third doped region.

Method 200 continues with operation 205 where a semiconductor layer may be formed. In some embodiments, the semiconductor layer may fill the first opening. In some embodiments, the semiconductor layer may cover the upper surface of the substrate. In some embodiments, the semiconductor layer may include semiconductor materials such as polycrystalline silicon, silicon germanium, and/or other suitable materials. In some embodiments, the semiconductor layer may include a dopant having a second conductivity type.

Method 200 continues with operation 206 where a portion of the semiconductor layer may be removed to form a fuse element. In some embodiments, the fuse element is located within the first opening. In some embodiments, the fuse element may be in contact with the first dielectric layer. In some embodiments, the fuse element may be in contact with the first doped region. In some embodiments, the fuse element may be in contact with the second doped region. In some embodiments, the first doped region may be in contact with the third doped region. In some practical In embodiments, the fuse element may be surrounded by the first dielectric layer. In some embodiments, the fuse element may be surrounded by the first doped region. In some embodiments, the fuse element may be surrounded by a second doped region. In some embodiments, the fuse element may be surrounded by a third doped region. In some embodiments, the upper surface of the fuse element may be substantially coplanar with the upper surface of the first dielectric layer. In some embodiments, the upper surface of the fuse element may be higher than the upper surface of the substrate. In some embodiments, the first doped region may serve as a fuse medium. In some embodiments, the fuse element and the fuse medium may together serve as a fuse structure.

Referring to FIG. 2B , method 200 continues to operation 207 where a fourth doped region may be formed. In some embodiments, the fourth doped region may have the first conductivity type. In some embodiments, the fourth doped region may extend from the upper surface of the substrate. In some embodiments, the fourth doped region may be spaced apart from the fuse element. In some embodiments, a mask may be formed on the upper surface of the substrate. In some embodiments, the mask may be configured to define a pattern of fourth doped regions.

Method 200 continues to operation 208 where a second dielectric layer may be formed. In some embodiments, a second dielectric layer may be formed on the first dielectric layer. In some embodiments, the second dielectric layer may be patterned to form the second opening. In some embodiments, the second opening may expose the fuse element.

Method 200 continues with operation 209 where first, second, and third conductive features may be formed. In some embodiments, the first conductive component may be formed within the second opening. In some embodiments, a second conductive component may be formed within the second opening. In some embodiments, a first conductive component may be formed on the fuse element. In some embodiments, a second conductive component may be formed on the fourth doped region. In some embodiments, a third conductive component may be formed on the second conductive component. In some embodiments, a third conductive component may be formed on the second dielectric layer.

Method 200 continues to operation 210 where a third dielectric layer may be formed. In some embodiments, a third dielectric layer may be formed on the second dielectric layer. In some embodiments, the third dielectric layer may be patterned to form a third opening. In some embodiments, the third opening may expose the first conductive component.

The method 200 continues with operation 211 where a fourth conductive feature may be formed. In some embodiments, a fourth conductive component may be formed within the third opening. In some embodiments, a fourth conductive component may be formed on the first conductive component.

The method 200 continues to operation 212 where a fifth conductive feature may be formed, thereby creating a semiconductor element. In some embodiments, a fifth conductive component may be formed on the fourth conductive component.

Method 200 is an example only, and there is no intention to limit the disclosure beyond what is expressly stated in the claims. Additional operations may be provided before, during, or after each operation of method 200, and some operations described in additional embodiments of the method may be replaced, deleted, or reordered. In some embodiments, method 200 may include further operations not depicted in Figures 2A and 2B. In some embodiments, method 200 may include one or more operations depicted in Figures 2A and 2B.

3A to 14A and 3B to 14B illustrate one or more stages of an exemplary method of manufacturing a semiconductor device according to some embodiments of the present disclosure, wherein FIGS. 3A to 14A are top views, and FIGS. 3B to 14B are respectively This is a cross-sectional view drawn along line AA′ of FIGS. 3A to 14A . It should be noted that for the sake of brevity, there are some elements shown in the cross-sectional view but omitted in the top view.

As shown in Figures 3A and 3B, a substrate 10 may be provided. The substrate 10 may include a well region 11 . Substrate 10 may include surface 10s1. The well region 11 may comprise a first conductivity type. In a In some embodiments, the first conductivity type is p-type. In some embodiments, the first conductivity type is n-type.

As shown in FIGS. 4A and 4B, doped regions 31, 32, and 33 may be formed. Each of the doped regions 31, 32, and 33 may have the first conductivity type. In some embodiments, doped region 31 may be spaced apart from surface 10s1 of substrate 10 . In some embodiments, doped region 33 may be spaced apart from surface 10s1 of substrate 10 . In some embodiments, doped region 31 may be formed between doped regions 32 and 33 . In some embodiments, the doping concentration of the doping region 31 may be greater than the doping concentration of the doping region 32 . In some embodiments, the doping concentration of the doping region 31 may be greater than the doping concentration of the doping region 33 . In some embodiments, the boundary 31s1 of the doped region 31 and the boundary 32s1 of the doped region 32 may be substantially continuous. In some embodiments, the boundary 31s1 of the doped region 31 and the boundary 33s1 of the doped region 33 may be substantially continuous. In some embodiments, doped region 32 may extend from surface 10s1 of substrate 10 . In some embodiments, each of doped regions 31, 32, and 33 may have a circular profile, an elliptical profile, or other suitable profiles.

As shown in FIGS. 5A and 5B , dielectric layer 41 may be formed. The dielectric layer 41 may be formed on the surface 10s1 of the substrate 10. The manufacturing technology of the dielectric layer 41 may include chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low pressure chemical vapor deposition ( low-pressure chemical vapor deposition; LPCVD), or other suitable processes.

As shown in FIGS. 6A and 6B, the opening 20h may be formed. In some embodiments, opening 20h may pass through substrate 10 . In some embodiments, opening 20h may pass through dielectric layer 41 . In some embodiments, opening 20h may pass through doped region 31 . In some embodiments, opening 20h may pass through doped region 32 . In some embodiments, opening 20h may expose doped District 33. The manufacturing technology of the opening 20h may include a patterning process. Patterning processes may include photolithography processes, etching processes, and other suitable processes. The lithography process may include photoresist coating (e.g., spin coating), soft baking, mask aligning, exposure, post-exposure baking, photoresist development, and rinse and dry (e.g., hard roast). The etching process may include, for example, a dry etching process or a wet etching process.

As shown in FIGS. 7A and 7B, the semiconductor layer 21' may be formed. In some embodiments, semiconductor layer 21' may fill opening 20h. In some embodiments, the semiconductor layer 21' may cover the surface 10s1 of the substrate 10. In some embodiments, the semiconductor layer 21' may include semiconductor materials, such as polycrystalline silicon, silicon germanium, and/or other suitable materials. In some embodiments, semiconductor layer 21' may include a dopant having a second conductivity type. The manufacturing technology of the semiconductor layer 21' may include CVD, ALD, PVD, LPCVD, or other suitable processes.

As shown in FIGS. 8A and 8B , a portion of the semiconductor layer 21' may be removed, thereby forming the fuse element 21. In some embodiments, fuse element 21 is located within opening 2Oh. In some embodiments, fuse element 21 may be in contact with dielectric layer 41 . In some embodiments, fuse element 21 may be in contact with doped region 31 . In some embodiments, fuse element 21 may be in contact with doped region 32 . In some embodiments, doped region 31 may be in contact with doped region 33 . In some embodiments, fuse element 21 may be surrounded by dielectric layer 41 . In some embodiments, fuse element 21 may be surrounded by doped region 31 . In some embodiments, fuse element 21 may be surrounded by doped region 32 . In some embodiments, fuse element 21 may be surrounded by doped region 33 . In some embodiments, the surface 21s2 of the fuse element 21 may be substantially coplanar with the upper surface (not labeled in the figure) of the dielectric layer 41. In some embodiments, the surface 21s2 of the fuse element 21 may be higher than the surface 10s1 of the substrate 10. In some embodiments, doped region 32 may serve as fuse dielectric 22 . In some embodiments, fuse element 21 and fuse medium 22 may together serve as fuse structure 20.

As shown in FIGS. 9A and 9B , doped regions 34 may be formed. In some embodiments, doped region 34 may have a first conductivity type. In some embodiments, doped region 34 may extend from surface 10s1 of substrate 10 . In some embodiments, doped region 34 may be spaced apart from fuse element 21 . In some embodiments, the mask 61 may be formed on the surface 10s1 of the substrate 10 . In some embodiments, mask 61 may be configured to define a pattern of doped regions 34 . In some embodiments, mask 61 may include, for example, photoresist.

As shown in Figures 10A and 10B, dielectric layer 42 may be formed. In some embodiments, mask 61 may be removed. In some embodiments, dielectric layer 42 may be formed on dielectric layer 41 . In some embodiments, dielectric layers 41 and 42 may be patterned to form openings 42h. In some embodiments, opening 42h may expose fuse element 21. In some embodiments, opening 42h may expose doped region 34. The manufacturing technology of the dielectric layer 42 may include CVD, ALD, PVD, LPCVD, or other suitable processes.

As shown in FIGS. 11A and 11B, conductive members 51, 52, and 54 may be formed. In some embodiments, conductive component 51 may be formed within opening 42h. In some embodiments, conductive component 52 may be formed within opening 42h. In some embodiments, the conductive component 51 may be formed on the fuse element 21 . In some embodiments, conductive features 52 may be formed on doped regions 34 . In some embodiments, conductive feature 54 may be formed on conductive feature 52 . In some embodiments, conductive features 54 may be formed on dielectric layer 42 . The fabrication technique for each of conductive components 51, 52, and 54 may include sputtering, PVD, or other suitable processes.

As shown in FIGS. 12A and 12B, dielectric layer 43 may be formed. In some embodiments, dielectric layer 43 may be formed on dielectric layer 42 . In some embodiments, dielectric layer 43 may be patterned to form openings 43h. In some embodiments, opening 43h may expose conductive component 51. The manufacturing technology of the dielectric layer 43 may include CVD, ALD, PVD, LPCVD, or other His suitable process.

As shown in FIGS. 13A and 13B, the conductive member 53 may be formed. In some embodiments, conductive component 53 may be formed within opening 43h. In some embodiments, the conductive component 53 may be formed on the conductive component 51 . The manufacturing technology of the conductive component 53 may include sputtering, PVD, or other suitable processes.

As shown in FIGS. 14A and 14B, the conductive member 55 may be formed, thereby producing the semiconductor element 1a. In some embodiments, conductive component 55 may be formed on conductive component 53 . The manufacturing technology of the conductive component 55 may include sputtering, PVD, or other suitable processes.

One aspect of the present disclosure provides a semiconductor device. The semiconductor element includes a substrate, a fuse element, and a fuse medium. The fuse element is arranged in the substrate. The fuse medium surrounds one side surface of the fuse element.

Another aspect of the present disclosure provides a semiconductor device. The semiconductor element includes a substrate, a fuse element, and a fuse medium. The fuse element is disposed in the substrate and extends from an upper surface of the substrate. The fuse medium is in contact with the fuse element. The fuse medium is spaced apart from the upper surface of the substrate.

Another aspect of the present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a substrate. The method also includes forming a fuse element in the substrate. The method further includes forming a fuse medium in the substrate, wherein the fuse medium surrounds the fuse element.

An embodiment of the present invention provides a fuse structure. The fuse structure can be embedded in a substrate. The fuse structure may include a fuse element and a fuse medium. The fuse dielectric is composed of a semiconductor material with dopants. The fuse structure may have a relatively small breakdown voltage. In addition, the process of forming the logic element can be applied to the fuse structure, which is beneficial to the formation cost of the semiconductor element 1a.

Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the claimed claims. For example, many of the processes described above may be implemented in different ways and may be replaced with other processes or combinations of the foregoing.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machinery, manufacture, material compositions, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that the present disclosure can use existing or future development processes, machinery, manufacturing, and material compositions that have the same functions or achieve substantially the same results as the corresponding embodiments herein. object, means, method, or procedure. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patentable scope of this application.

1a: Semiconductor components

10:Substrate

10s1: Surface

11:Well area

20: Fuse structure

21: Fuse component

21s1: Surface

21s2: Surface

21s3: Surface

22: Fuse medium

31: Doped area

31s1:Border

32: Doped area

32s1:Border

33: Doped area

33s1:Border

34: Doped area

41: Dielectric layer

42:Dielectric layer

43:Dielectric layer

51: Conductive parts

52: Conductive parts

53: Conductive parts

54: Conductive parts

55: Conductive parts

A-A’: line

L1:Length

L2: length

X: axis

Z: axis

Claims (18)

A semiconductor element includes: a substrate; a fuse element disposed in the substrate; and a fuse medium surrounding one side surface of the fuse element; wherein the fuse element includes polycrystalline silicon, and the substrate includes a first A doped region serves as the fuse medium. The semiconductor device of claim 1, wherein the first doped region is spaced apart from an upper surface of the substrate. The semiconductor device according to claim 2, wherein the substrate includes a second doped region located between the upper surface of the substrate and the first doped region, and a first doped region of the first doped region The impurity concentration is different from a second doping concentration of the second doping region. The semiconductor device of claim 3, wherein the first doping concentration is greater than the second doping concentration. The semiconductor device of claim 3, wherein the second doped region surrounds the side surface of the fuse element. The semiconductor device according to claim 1, wherein the substrate includes a third doped region located Below the first doping region, a first doping concentration of the first doping region is different from a third doping concentration of the third doping region. The semiconductor device of claim 6, wherein the first doping concentration is greater than the third doping concentration, and the first doping region is spaced apart from the lower surface of the fuse element through the third doping region. The semiconductor device of claim 6, wherein the third doped region is in contact with the lower surface of the fuse element. The semiconductor device of claim 1, wherein the first doped region is in contact with the fuse element, and the substrate includes a fourth doped region spaced apart from the fuse element, and the fourth doped region extends from an upper surface of the substrate, and the first doped region overlaps the fourth doped region along a first direction perpendicular to the upper surface of the substrate. A semiconductor element, including: a substrate; a fuse element disposed in the substrate and extending from an upper surface of the substrate; and a fuse medium in contact with the fuse element, wherein the fuse medium is in contact with the substrate The upper surface is spaced apart; wherein the fuse element includes polycrystalline silicon, and the substrate includes a first doped region as the fuse medium. The semiconductor device according to claim 10, wherein the substrate includes a second doped region located between the upper surface of the substrate and the first doped region, and a first doped region of the first doped region The impurity concentration is different from a second doping concentration of the second doping region. The semiconductor device of claim 11, wherein the first doping concentration is greater than the second doping concentration, and the second doping region is in contact with the fuse element. The semiconductor device according to claim 10, wherein the substrate includes a third doping region located below the first doping region, and a first doping concentration of the first doping region is consistent with the third doping region. A third doping concentration of the impurity region is different. The semiconductor device of claim 13, wherein the first doping concentration is greater than the third doping concentration, and the first doping region is spaced apart from the lower surface of the fuse element through the third doping region. The semiconductor device of claim 13, wherein the third doped region is in contact with the lower surface of the fuse element. The semiconductor device of claim 10, wherein the substrate includes a fourth doped region spaced apart from the fuse element, and the fourth doped region extends from the upper surface of the substrate. The semiconductor device of claim 16, wherein the first doped region overlaps the fourth doped region along a first direction perpendicular to the upper surface of the substrate. The semiconductor device of claim 10, wherein a first boundary of the first doped region and a second boundary of the second doped region are substantially coplanar.