TWI817386B - Phase locked loop, voltage controlled oscillator and tuning method - Google Patents

Abstract

A tuning array selection circuit, together with a decoder and a voltage controlled oscillator (VCO), can be employed to overcome some disadvantages of previous methods of phase locked loops. For example, a VCO can include a coarse tuning array and a fine tuning array. A coarse tuning array can be used to tune a VCO to generate a signal within a wide frequency range. A fine tuning array can be used to tune a VCO to generate a signal within a narrow frequency range. In one embodiment, the narrow frequency range is within the wide frequency range. The tuning array selection circuit can coordinate selection of appropriate fine tuning devices and narrow tuning devices to reduce transition jitter and the risk of fail locking of phase locked loops.

Description

Phase locked loops, voltage controlled oscillators and tuning methods

This disclosure document relates to a phase locked loop, specifically a phase locked loop using an inductor/capacitor voltage controlled oscillator.

A phase locked loop (PLL) circuit is an electronic control circuit that generates an output clock signal, and the output clock signal has a phase locked to the phase of the input reference signal. For example, a phase locked loop can be used to adjust an oscillator so that the frequency and phase of the signal generated by the oscillator matches the frequency and phase of the reference input signal. Phase locked loop circuits are commonly used in communication devices, computers and other electronic devices. For advanced applications, high-performance phase-locked loops can use inductance-capacitance (LC) voltage-controlled oscillators. For example, LC voltage controlled oscillators can be used in fifth-generation mobile systems, radar and high-performance computing applications.

By using small voltage-controlled capacitors (varactors), the phase noise of LC voltage-controlled capacitors can be improved. However, small voltage-controlled capacitors can result in a very narrow frequency tuning range, a condition that can cause phase-locked loops to malfunction at temperature. High risk of losing lock during temperature or voltage changes. In addition, frequency adjustments within the voltage controlled oscillator may cause significant transition jitter. Solutions are needed to reduce the risk of losing lock and reduce transition jitter caused by frequency scaling.

This disclosure document provides a phase locked loop. The phase locked loop includes a voltage controlled oscillator. The voltage controlled oscillator includes a coarse adjustment array and a fine adjustment array. The coarse adjustment array includes a plurality of coarse adjustment devices, and the fine adjustment array includes a plurality of fine adjustment devices. Among them, according to the determination that the tuning signal of the voltage controlled oscillator is higher than the analog voltage range, the voltage controlled oscillator is used to select a trimming device from the trimming devices of the trimming array to increase the frequency of the voltage controlled oscillator output signal to a higher in a narrow frequency range. Among them, according to the determination that the tuning signal of the voltage controlled oscillator is lower than the analog voltage range, the voltage controlled oscillator is used to select a trimming device from the trimming devices of the trimming array to reduce the frequency of the output signal of the voltage controlled oscillator to a lower value. in the low and narrow frequency range. Among them, based on the determination that the tuning signal of the voltage controlled oscillator is higher than the analog voltage range and the narrow frequency range is at a high level within the wide frequency range, the voltage controlled oscillator is used to select the coarse adjustment device from the coarse adjustment devices of the coarse adjustment array , to increase the frequency of the voltage controlled oscillator output signal to a higher and wider frequency range. Among them, according to the determination that the tuning signal of the voltage controlled oscillator is lower than the analog voltage range and the narrow frequency range is at a low level within the wide frequency range, the voltage controlled oscillator is used to select a coarse adjustment device from the coarse adjustment device of the coarse adjustment array. Device to reduce the frequency of the voltage controlled oscillator output signal to a lower wide frequency range.

This disclosure document provides a voltage controlled oscillator. The voltage controlled oscillator includes Coarse array and fine array. The coarse adjustment array contains a plurality of coarse adjustment devices. The fine-tuning array includes a plurality of fine-tuning devices. Among them, according to the determination that the tuning signal of the voltage controlled oscillator is higher than the analog voltage range, the voltage controlled oscillator is used to select a trimming device from the trimming devices of the trimming array to increase the frequency of the voltage controlled oscillator output signal to a higher within a narrow frequency range. Among them, according to the determination that the tuning signal of the voltage controlled oscillator is lower than the analog voltage range, the voltage controlled oscillator is used to select a trimming device from the trimming devices of the trimming array to reduce the frequency of the output signal of the voltage controlled oscillator to a lower value. within a low and narrow frequency range. Among them, according to the determination that the tuning signal of the voltage controlled oscillator is higher than the analog voltage range and the narrow frequency range is at a high level within the wide frequency range, the voltage controlled oscillator is used to select a coarse adjustment device from the coarse adjustment device of the coarse adjustment array. Device to increase the frequency of the voltage controlled oscillator output signal to a higher and wider frequency range. Among them, according to the determination that the tuning signal of the voltage controlled oscillator is lower than the analog voltage range and the narrow frequency range is at a low level within the wide frequency range, the voltage controlled oscillator is used to select a coarse adjustment device from the coarse adjustment device of the coarse adjustment array. Device to reduce the frequency of the voltage controlled oscillator output signal to a lower wide frequency range.

This disclosure document provides a tuning method for a voltage controlled oscillator, which includes the following steps: receiving a voltage controlled oscillator tuning signal. Determine whether the voltage controlled oscillator tuning signal is higher than the analog voltage range, lower than the analog voltage range, or within the analog voltage range. When the voltage controlled oscillator tuning signal is higher than the analog voltage range, a trimming device is selected to generate a voltage controlled oscillator output signal within a higher narrow frequency range. When the voltage controlled oscillator tuning signal is lower than the analog voltage range, a trimming device is selected to generate a voltage controlled oscillator output signal within a lower narrow frequency range. Determine the narrow frequency range to be at a high level of the wide frequency range or low level.

100:Phase locked loop

101,V _TUNE : Voltage controlled oscillator tuning signal

102,F _REF : Reference input signal

103,band_bin_out[3:0]: Coarse binary code signal

104, fine_bin_out[2:0]: Fine-tune binary code signal

105,band_th[14:0]: Coarse adjustment selection signal

106, fine_th[6:0]: Fine-tuning selection signal

107: Tuning array selection circuit

108:Decoder

109, LC-VCO: Inductor/Capacitor Voltage Controlled Oscillator

110: Voltage controlled oscillator output signal

201: Analog Overflow and Underflow Detector

202: Fine-tuning counter circuit

203: Coarse adjustment counter circuit

204:Bounds checker

205:Frequency divider

206: Coarse array

207: Fine-tuning array

208,over_ana: overflow signal

209,under_ana: underflow signal

210, fine_ov: high frequency level boundary signal/fine adjustment range overflow signal

211, fine_ud: low frequency level boundary signal/fine adjustment range underflow signal

213: First reduced frequency signal

214: Second lower frequency signal

215,EN: Enable signal

216,ov_rt: Voltage controlled oscillator overflow tuning signal

217,ud_rt: Voltage controlled oscillator underflow tuning signal

218,band_bin[3:0]: Coarse/unsigned binary code input signal

401: wide frequency range

402: Narrow frequency range

501, fine_count[3:0]: Fine-tune counter variables

502,coar_count[3:0]: Coarse counter variable

503: first node

504: Second node

505: Third digital comparator

506: Fourth digital comparator

507: Fifth digital comparator

508: Sixth digital comparator

509: Seventh data latch

510: The fourth logic (and) gate

511: The fifth logic (and) gate

512: The sixth logic (and) gate

513: The seventh logic (or) gate

514: The eighth logic (and) gate

515: Logic (OR) gate

516:First multiplexer

517: First adder

518: First digital comparator

519: Second digital comparator

520: Third data latch

521: Fourth data latch

522: Fifth data latch

523: Second logic (and) gate

524: First logical (OR) gate

525: Signed to unsigned squares

526: Second multiplexer

527: Second adder

528: Sixth data latch

529: Ninth data latch

530: Third adder

531:Voltage divider

532: First data latch

533: Second data latch

534: Fine-tuning the adder signal

535:Output signal

536: Logic (and) gate

537:Tracking signal

801: Equation

802: Voltage controlled capacitor (varactor diode)

803:node

804: Fine adjustment device

805: Coarse adjustment device

901: High Quality Factor Inductor

902:Constant tutoring circuit

903:Varactor diode

904: Coarse adjustment capacitor

905:Trimmer capacitor

1001~1017: steps

1201:Analog-to-digital converter

1202:Digital comparator

1400:Method

1401~1405: Steps

The aspects of this disclosure can best be understood when the following detailed description is read in conjunction with the accompanying drawings.

Figure 1 is a block diagram of an exemplary tuned array selection circuit, decoder, and LC voltage controlled oscillator implemented in a phase locked loop; Figure 2 is a block diagram of an exemplary tuned array selection circuit, decoder, and LC voltage controlled oscillator Detailed block diagram; Figure 3 is a diagram of the detailed components of an exemplary tuning array selection circuit, decoder, and LC voltage controlled oscillator; Figure 4 is a schematic diagram of the voltage controlled oscillator adjusting the voltage controlled oscillator output signal; Figure 5 The figure shows the detailed diagram of the tuning array selection circuit; Figure 6 shows the timing diagram of various signals in the tuning array selection circuit during the condition when the voltage controlled oscillator tuning signal is slightly above the analog voltage range; Figure 7 shows the timing diagram of the various signals in the tuning array selection circuit. Timing diagram of various signals in the tuning array selection circuit during conditions where the oscillator tuning signal is significantly higher than the analog voltage range; Figure 8 is a detailed diagram of the LC voltage controlled oscillator; Figure 9 is the LC voltage controlled oscillator The layout plan of Diagrams of different embodiments of controlled oscillators; Figure 12 is a diagram of overflow and underflow detectors implemented using digital components; Figures 13A-13B are voltage controlled oscillator output signals used in previous methods and the present disclosure The waveform diagram of the output signal of the voltage controlled oscillator used in the method of the document; Figure 14 is a flow chart of the method of tuning the LC voltage controlled oscillator.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these components and configurations are examples only and do not limit this disclosure document. In addition, this disclosure may repeatedly refer to numbers and/or letters in each instance. This repetition is for simplicity and clarity and does not inherently indicate a relationship between the various embodiments and/or configurations discussed.

It should be noted that references such as “one embodiment”, “an embodiment”, “an exemplary embodiment”, “exemplary” and the like in this specification indicate that the described embodiment may include specific features, structures or characteristics, but each Embodiments do not necessarily include such specific features, structures or characteristics. Furthermore, such phrases are not necessarily referring to the same embodiment. Furthermore, when a particular feature, structure or characteristic is described in connection with an embodiment, whether or not explicitly described, it is within the knowledge of one skilled in the art to implement the feature, structure or characteristic in conjunction with other embodiments.

It should be understood that the wording or terminology used in this disclosure document is for description only. It is intended, without limitation, that the terms or expressions used in this disclosure should be interpreted in accordance with the explanation herein by a person skilled in the art.

A phase locked loop (PLL) can be used to adjust its oscillator so that the frequency and/or phase of the output signal produced by the oscillator is proportional to the frequency and/or phase of a reference input signal. The phase locked loop includes a phase and/or frequency detector that provides an error signal representing the difference in frequency and/or phase between the output signal and a reference input signal. This error signal can be measured to ensure that the frequency and/or phase of the output signal is proportional to the frequency and/or phase of the reference signal. For example, as the phase locked loop adjusts the oscillator, the frequency and/or phase of the output signal may gradually approach the frequency and/or phase of the reference input signal. When the frequency and phase of the output signal are proportional to the frequency and/or phase of the reference input signal, it means that the phase locked loop is locked to the reference input signal. In some applications, a phase locked loop can use an LC voltage controlled oscillator to generate this output signal in advanced computing and mobile applications.

Figure 1 is a block diagram of the phase locked loop 100. In this disclosure, the phase locked loop 100 includes a tuned array selection circuit 107, a decoder 108, and an LC voltage controlled oscillator 109. The tuning array selection circuit 107 is used to receive both the voltage controlled oscillator tuning signal 101 and the reference input signal 102 . The voltage controlled oscillator tuning signal 101 may originate from within the phase locked loop 100 . For example, the voltage controlled oscillator tuning signal 101 may be generated by a control loop within the phase locked loop 100 . The tuning array selection circuit 107 is used to use the voltage controlled oscillator tuning signal 101 and the reference input signal 102 to determine whether the voltage controlled oscillator tuning signal 101 is higher than the analog voltage range or lower than the analog voltage range. range is still within the analog voltage range. The tuning array selection circuit 107 is used to generate a fine-tuning binary code signal 104 and a coarse-tuning binary code signal 103 based on the determination result. These binary code signals (103, 104) may be received by the decoder 108 together with the reference input signal 102. The decoder 108 can convert these binary code signals (103, 104) into a fine adjustment selection signal 106 and a coarse adjustment selection signal 105. The fine selection signal 106 and the coarse selection signal 105 can be received at the LC voltage controlled oscillator 109, which can use these selection signals (105, 106) to select the appropriate fine and coarse devices. The LC voltage controlled oscillator 109 is also used to receive the voltage controlled oscillator tuning signal 101 and to generate a voltage controlled oscillator output signal 110 having a frequency proportional to the frequency of the reference input signal 102 .

Figure 2 is a detailed diagram of the tuning array selection circuit 107, the decoder 108 and the LC voltage controlled oscillator 109. In the example shown in FIG. 2 , the tuning array selection circuit 107 includes an analog overflow and underflow detector 201 , a fine-tuning counter circuit 202 , a coarse-tuning counter circuit 203 , a boundary checker 204 and a frequency divider 205 . The analog overflow and underflow detector 201 may receive the voltage controlled oscillator tuning signal 101 . According to the determination result that the voltage controlled oscillator tuning signal 101 is above the analog voltage range, below the analog voltage range, or within the analog voltage range, the analog overflow and underflow detector 201 can generate an overflow signal 208 or an underflow signal 209 . Both the overflow signal 208 and the underflow signal 209 may be received at the trim counter circuit 202 together with the first reduced frequency signal 213 and the second reduced frequency signal 214 . The fine-tuning counter circuit 202 can be used to adjust the counter according to the overflow signal 208 and the underflow signal. Signal 209 is used to determine whether it is appropriate to select different trimming devices in the trimming array 207 of the LC voltage controlled oscillator 109. The trimming counter circuit 202 can also be used to generate one or a plurality of frequency level boundary signals. The frequency level boundary signals include a high frequency level boundary signal 210 and a low frequency level boundary signal 211. As described below, the frequency level boundary signals are generated in a wide frequency range. The fine-tuning device corresponds to the frequency at the upper or lower boundary of the rate range. The trimming counter circuit 202 can also be used to generate a trimming binary code signal 104 that corresponds to an appropriate trimming device selected in the trimming array 207 of the LC voltage controlled oscillator 109 .

Tuned array selection circuit 107 may further include a coarse counter circuit 203 . In one example, the coarse counter circuit 203 is used to receive the frequency level boundary signals (210, 211), the second reduced frequency signal 214 and the coarse binary code input signal 218. In one example, the coarse binary code input signal 218 is the input signal and is used to select the initial coarse binary code signal. The coarse counter circuit 203 may be further used to generate the coarse binary code signal 103 . In one example, the coarse binary code signal 103 is determined based on the frequency level boundary signals (210, 211) and the coarse binary code input signal 218.

The boundary checker 204 is used to receive the coarse binary code signal 103 and the voltage controlled oscillator overflow tuning signal 216 and the voltage controlled oscillator underflow tuning signal 217 from the fine tuning counter circuit 202 . These signals may be used to determine whether enablement of tuning array selection circuit 107 is appropriate. The boundary checker 204 can generate an enable signal 215 based on this determination, and the enable signal 215 can be used to enable or disable the tuning array selection circuit 107 .

Tuned array selection circuit 107 may also include frequency divider 205. In an exemplary embodiment, the frequency divider 205 may be used to receive the input reference signal 102 . The frequency divider 205 may then divide the input reference signal 102 by a first predetermined constant and generate a first reduced frequency signal 213 . The first reduced frequency signal 213 may be received by the trim counter circuit 202 . The frequency divider 205 can also divide the input reference signal 102 by a second predetermined constant and generate a second reduced frequency signal 214. The second reduced frequency signal 214 can be generated from the fine adjustment counter circuit 202, the coarse adjustment counter circuit 203 and the boundary checker 204. One or more latches are received as a "clock" input, as understood by those skilled in the art.

Decoder 108 is also shown in Figure 2. The decoder 108 can be used to receive the coarse binary code signal 103 from the boundary checker 204, the fine binary code signal 104 from the fine adjustment counter circuit 202, and the reference input signal 102. The decoder 108 can convert the coarse adjustment binary code signal 103 and the fine adjustment binary code signal 104 into one or a plurality of fine adjustment selection signals 106 and one or a plurality of coarse adjustment selection signals 105 . The decoder 108 may convert the binary code signals (103, 104) into the selection signals (105, 106), for example, because the selection signals (105, 106) may be more easily adapted to the selection of individual devices than the binary code signals (103, 104).

Figure 2 also shows an LC voltage controlled oscillator 109. The LC voltage controlled oscillator 109 may include a coarse tuning array 206 and a fine tuning array 207 . For example, the coarse adjustment array 206 may include a plurality of coarse adjustment devices, and the fine adjustment array 207 may include a plurality of fine adjustment devices. Coarse adjustment array 206 may be used to adjust The LC voltage controlled oscillator 109 is tuned to produce a voltage controlled oscillator output signal 110 having a frequency over a wide frequency range. In contrast, the trim array 207 can be used to tune the LC voltage controlled oscillator 109 to produce a voltage controlled oscillator output signal 110 with a frequency within a narrow frequency range. In one example, this narrow frequency range is within a wide frequency range.

Figure 3 is a detailed diagram of the tuning array selection circuit 107, the decoder 108 and the LC voltage controlled oscillator 109. The details shown in Figure 3 are discussed further below.

Figure 4 is a diagram illustrating in detail the mechanism of the LC voltage controlled oscillator 109 to adjust the voltage controlled oscillator output signal 110 by selecting appropriate coarse adjustment and fine adjustment devices. According to the example shown in Figure 4, the trimmer may represent a narrow frequency range 402 of 50 MHz. However, the coarse adjustment device may represent a wide frequency range 401 of 200 MHz. The tuning array selection circuit 107, the decoder 108 and the LC voltage controlled oscillator 109 may cooperate with each other to adjust the frequency of the voltage controlled oscillator output signal 110 using steps equal to the frequency steps of the trimming device, further reducing the frequency change therefrom. Caused by transition jitter. For example, a fine-tuning device corresponding to a high frequency level whose frequency range is within the wide frequency range 401 may be selected. This operating state is represented by "Band@10,FINE@7" in Figure 4. In this example, 10 and 7 are variables indicating which coarse adjustment device and which fine adjustment device are selected respectively. If the selected device is a fine-tuning device corresponding to a frequency range located at a high frequency level within the wide frequency range 401, and the voltage controlled oscillator tuning signal 101 is above the analog voltage range, then a coarse-tuning device representing an increase in frequency will be selected. . This situation is shown in Figure 4 by rough adjustment. To illustrate, move the setting from "Band@10" to "Band@11". In the example shown in Figure 4, this situation corresponds to a 200 MHz increase in the frequency of the voltage controlled oscillator output signal 110. However, the trimming device corresponding to the low level located in the wide frequency range 401 is selected. This situation is illustrated in Figure 4 by moving the fine-tuning device from "FINE@7" to "FINE@4". Therefore, in this example, the frequency represented by the coarse adjustment device has been increased by 200MHz. However, the frequency represented by the trimmer has been reduced by 150MHz. Therefore, the frequency of the voltage controlled oscillator output signal 110 has a net increase of 50MHz. The switching jitter caused in the phase locked loop 100 is less than the switching jitter caused by a frequency increase greater than 50 MHz (eg, a frequency increase equal to the frequency of the coarse adjustment device).

Figure 5 shows a detailed implementation diagram of the tuned array selection circuit 107. In the exemplary embodiment shown in FIG. 5 , voltage controlled oscillator tuning signal V _TUNE 101 may be received as an input at the positive terminal of an amplifier in analog overflow and underflow detector 201 . The amplifier may be coupled to voltage divider 531 via its negative terminal. The first node 503 on the voltage divider 531 may represent a high predetermined value, while the second node 504 on the voltage divider may represent a low predetermined value. The high predetermined value 503 and the low predetermined value 504 may correspond to the limits of the analog voltage range. The voltage controlled oscillator tuning signal 101 may be compared with a high predetermined value 503 and a low predetermined value 504, and the amplifier may determine whether the voltage controlled oscillator tuning signal V _TUNE 101 is above the analog voltage range, below the analog voltage range, or within the analog voltage range. Within the range, the overflow signal over_ana 208 and the underflow signal under_ana 209 are generated. For example, when the voltage controlled oscillator tuning signal V _TUNE 101 is higher than the analog voltage range, the overflow signal over_ana 208 can be enabled, and when the voltage controlled oscillator tuning signal V _TUNE 101 is lower than the analog voltage range, the overflow signal over_ana 208 can be enabled. Can underflow signal under_ana 209.

The overflow signal 208 and the underflow signal 209 may be received as inputs by the trim counter circuit 202 . For example, the overflow signal over_ana 208 may be received as an input by the first data latch 532 and the underflow signal under_ana 209 may be received as an input to the second data latch 533 in the trim counter circuit 202 . The data latch (532,533) can also receive the first reduced frequency signal 213 from the frequency divider 205, and the same data latch (532,533) can generate the voltage controlled oscillator overflow tuning signal ov_rt 216 and the voltage controlled oscillator Underflow tuning signal ud_rt 217. The voltage controlled oscillator overflow tuning signal ov_rt 216 and the voltage controlled oscillator underflow tuning signal ud_rt 217 can be received at the first multiplexer 516 , and the first multiplexer 516 can utilize these signals to generate the fine-tuning adder signal 534 . Trim adder signal 534 may be received by first adder 517 . The output of the first adder 517 may be received by the second logic (AND) gate 523 , the first digital comparator 518 and the second digital comparator 519 . In an exemplary embodiment, when the output of the first adder 517 is equal to a predetermined value, the output of the first digital comparator 518 is enabled, and when the output of the first adder 517 is equal to a different predetermined value, the output of the first digital comparator 518 is enabled. The output of the second digital comparator 519 is enabled. The output of the first digital comparator 518 may correspond to a determination that the selected trim device in the trim array 207 corresponds to a frequency located at a high level within the wide frequency range 401 . Similarly, the output of the second digital comparator 519 may correspond to the A determination is made that the selected trimming device corresponds to a frequency located at a low level in the wide frequency range 401 .

The output of the second logic (AND) gate 523 may be received as an input to the third data latch 520 and the output of the first digital comparator 518 may be received as an input to the fourth data latch 521 . The output of the second digital comparator 519 may be received as an input to the fifth data latch 522 . The fourth data latch 521 coupled to the first digital comparator 518 can generate the fine-tuning range overflow signal fine_ov 210, and the fifth data latch 522 coupled to the second digital comparator 519 can generate the fine-tuning range underflow signal fine_ud 211. In one example, the fine-tuning range overflow and underflow signals (210, 211) may correspond to a determination that the narrow frequency range 402 is at a high level or a low level within the wide frequency range 401.

The trimming range overflow signal 210 and the trimming range underflow signal 211 can be received at the first logic (OR) gate 524 in the trimming counter circuit 202. When any signal (210, 211) is enabled, the first logic (OR) gate 524 is enabled. Logic (OR) gate 524. The output of the first logic (OR) gate 524 may be received at the inverting input node of the second logic (AND) gate 523 . As discussed previously, the output of the second logic (AND) gate 523 may be received at the data latch 520 . The output of data latch 520 may be the fine counter variable fine_count[3:0] 501 and is received at both the first adder 517 and the signed to unsigned block 525. In one example, the fine counter variable fine_count[3:0]501 is a signed binary number, which represents a positive or negative binary number. Signed to unsigned square 525 is OK This positive or negative binary number is converted into a positive binary number, and a fine-tuning binary code signal fine_bin_out[2:0]104 is generated. For example, the signed to unsigned block 525 receives the fine counter variable fine_count[3:0] 501 with the value "1101", which corresponds to -3 in the decimal number system, and produces the value "001" Fine-tune the binary code signal fine_bin_out[2:0]104. This value corresponds to 1 in the decimal number system. Similarly, the signed to unsigned block 525 can receive the fine counter variable fine_count[3:0] 501 with the value "0011", which corresponds to 3 in the decimal number system, and produce a fine with the value "111" Binary code signal fine_bin_out[2:0]104, this value corresponds to 7 in the decimal number system.

The fine adjustment range overflow signal fine_ov 210 and the fine adjustment range underflow signal fine_ud 211 may also be received as inputs to the second multiplexer 526 in the coarse adjustment counter circuit 203 . According to the fine-tuning range overflow signal fine_ov 210 and the fine-tuning range underflow signal fine_ud 211, the multiplexer 526 can be used to generate an output signal 535 according to whether different coarse-tuning devices should be selected. Output signal 535 may be received at second adder 527 . The output of the second adder 527 may be received as an input to the sixth data latch 528 . The output of the sixth latch 528 may be received at the third adder 530 along with the coarse binary code input signal band_bin[3:0] 218 . In one embodiment, the coarse binary code input signal band_bin[3:0]218 is used to set the initial value of the coarse binary code signal band_bin_out[3:0]103. The output of sixth latch 528 may also be coupled to second adder 527, and the sixth latch The output of 528 can be the coarse counter variable coar_count[3:0] 502. The output of the third adder 530 may be a coarse binary code signal band_bin_out[3:0] 103 that may be received by the decoder 108 .

The coarse binary code signal band_bin_out[3:0] 103 may be coupled to the third digital comparator 505 , the fourth digital comparator 506 , the fifth digital comparator 507 and the sixth digital comparator 508 in the boundary checker 204 . In the exemplary embodiment shown in FIG. 5 , the coarse binary code signal band_bin_out[3:0] 103 is limited between 0 and 15. The third, fourth, fifth and sixth digital comparators (505, 506, 507, 508) can assist the boundary checker 204 to prevent exhaustion of the coarse binary code signal band_bin_out[3:0] 103 and system crash. For example, in the embodiment shown in Figure 5, if the coarse adjustment binary code signal band_bin_out[3:0] 103 is greater than 1, the output of the third digital comparator 505 will be enabled, and if the coarse adjustment binary code signal band_bin_out[3:0]103 is greater than 1, the output of the third digital comparator 505 will be enabled. If the carry code signal band_bin_out[3:0]103 is less than 14, the output of the fourth digital comparator 506 will be enabled. If the outputs of both digital comparators (505, 506) are enabled, it will allow selection of the coarse adjustment device corresponding to a larger wide frequency range 401 or a lower wide frequency 401. Therefore, the outputs of the third and fourth digital comparators (505, 506) are coupled to separate inputs of the logic (AND) gate 536. The output of logic (AND) gate 536 is coupled to the input of seventh data latch 509 , and the output of seventh data latch 509 is coupled to fourth logic (AND) gate 510 . The other input of logic (AND) gate 510 is coupled to logic (OR) gate 515. Logic (OR) gate 515 receives the voltage controlled oscillator overflow tuning signal ov_rt 216 and the voltage controlled oscillator underflow tuning signal ov_rt from the trimming counter circuit 202. The harmonic signal ud_rt 217 is used as input. The output of the fourth logic (AND) gate 510 is one of the three inputs of the logic (OR) gate 513 . Each of the three inputs of logic (OR) gate 513 represents a condition that may enable tuning array selection circuit 107 . For example, when the coarse binary code signal band_bin_out[3:0] 103 is equal to 0, the output of the fifth digital comparator 507 is enabled. This output and the voltage controlled oscillator overflow tuning signal 216 are received as inputs at a fifth logic (AND) gate 511 . Similarly, when the coarse binary code signal band_bin_out[3:0] 103 is equal to 15, the output of the sixth digital comparator 508 is enabled. This output is received as an input at logic (AND) gate 512 along with voltage controlled oscillator underflow tuning signal ud_rt 217.

The output of the seventh logic (OR) gate 513 is received at the eighth logic (AND) gate 514 together with the tracking signal 537 . The output of the logic (AND) gate 514 is the enable signal EN 215, which is used to control the enable of the tuning array selection circuit 107. Therefore, when the fourth logic (AND) gate 510, the fifth logic (AND) gate 511, and the sixth logic (AND) gate 512 are all disabled, the tuning array selection circuit 107 will be disabled to prevent system collapse.

Figure 5 also shows frequency divider 205. In an exemplary embodiment, frequency divider 205 receives reference input signal 102 . The frequency divider 205 can also receive the enable signal EN 215 from the boundary checker 204. Reference input signal 102 may be received at ninth data latch 529 . The frequency divider 205 may be used to generate a first reduced frequency signal 213, wherein the first reduced frequency signal 213 is equal to the frequency of the reference input signal 102 divided by a first predetermined value. The frequency divider 205 can also be used to generate a different second reduced frequency signal. 214, wherein the second reduced frequency signal 214 is equal to the frequency of the reference input signal 102 divided by a second predetermined value. Signals of different frequencies can be received at different components according to their different frequency requirements.

Figure 6 is a timing diagram showing the selection changes of the trimming device. In an exemplary embodiment, the fine counter variable fine_count[3:0] 501 is limited between -4 and +4. In the example shown in FIG. 6 , the fine counter variable fine_count[3:0] 501 is received at the signed to unsigned block 525 and converted into the fine binary code signal fine_bin_out[2:0] 104. The coarse counter variable coar_count[3:0]502 can be combined with the unsigned binary code input signal band_bin[3:0]218 to generate a new coarse binary code signal band_bin_out[3:0]103. The coarse binary code signal band_bin_out[3:0] 103 is limited between 0 and 15.

The phase locked loop 100 may increase the voltage controlled oscillator tuning signal V _TUNE 101 to maintain the voltage controlled oscillator output signal 110 . However, the voltage controlled oscillator tuning signal 101 may exceed the high predetermined value in the analog overflow and underflow detector 201 , causing the overflow signal over_ana 208 to be enabled, and enabling the enable signal 215 to enable the divider 205 . If after 64 cycles of the second reduced frequency signal 214 (1024 cycles of the input reference signal F _REF 102 ), the voltage controlled oscillator tuning signal 101 still exceeds the high predetermined value in the analog overflow and underflow detector 201 , Then the fine-tuning counter variable fine_count[3:0]501 will increase by 1. The fine-tuning binary code signal fine_bin_out[2:0] 104 will increase (for example, from 4 to 5), which will slightly increase the frequency of the voltage controlled oscillator output signal 110. In the example shown in the timing diagram of FIG. 6 , the phase locked loop 100 will read: the frequency of the voltage controlled oscillator output signal 110 is fully locked to the frequency of the reference input signal 102 , and the voltage controlled oscillator tuning signal V _TUNE 101 is in the analog voltage range and operation of the tuned array selection circuit 107 will cease.

FIG. 7 is a timing diagram illustrating the operation of selecting another coarse adjustment device in the coarse adjustment array 206. As shown in FIG. In the example illustrated in Figure 7, the fine counter variable fine_count[3:0] 501 is increased to 3, and the overflow signal 208 is still enabled. This situation triggers the high frequency level boundary signal fine_ov 210 signal. In this case, the coarse adjustment counter variable coar_count[3:0]502 increases from 0 to 1, and the coarse adjustment binary code signal band_bin_out[3:0]103 increases from 5 to 6. At the same time, the fine-tuning counter variable fine_count[3:0]501 is reset to 0 to force the fine-tuning binary code signal fine_bin_out[2:0]104 to return to the value 4. Therefore, the frequency of the voltage controlled oscillator output signal 110 only increases by 50MHz in total. This situation is because the change in the value of the fine-tuning counter variable fine_count[3:0]501 causes the frequency to be reduced by 150MHz, and the change in the value of the coarse-tuning counter variable coar_count[3:0]502 causes the frequency to be increased by 200MHz.

Figure 8 is a detailed diagram of an embodiment of an LC voltage controlled oscillator 109. Voltage controlled oscillator tuning signal V _TUNE 101 may be received at node 803 of LC voltage controlled oscillator 109 , which is coupled to a voltage controlled capacitor (varactor) 802 on either side. The LC voltage controlled oscillator 109 may include a fine tuning array 207 and a coarse tuning array 206 . In the example shown in FIG. 8 , the fine-tuning array 207 includes a plurality of fine-tuning devices 804 , and the coarse-tuning array 206 includes a plurality of coarse-tuning devices 805 . In the embodiment shown in FIG. 8 , the coarse adjustment device 805 and the fine adjustment device 804 are capacitors. The coarse selection signal band_th[14:0] 105 may be received as an input to the coarse array 206 and the fine selection signal fine_th[6:0] 106 may be received as an input to the fine array 207 .

For example, the LC voltage controlled oscillator 109 may include two metal-oxide-metal (MOM) capacitor arrays, as understood by those skilled in the art. Coarse tuning array 206 can be designed to cover wide frequency tuning. In one example, the coarse tuning array 206 may include 15 steps, each step being 200 MHz. Therefore, the LC voltage controlled oscillator 109 can have a frequency tuning range of 3GHz. The trim array 207 can be designed to produce small steps. Trim array 207 may contain only 7 steps, each step being 50 MHz. In this example, the frequency step of the fine adjustment device 804 is one quarter of the step of the coarse adjustment device 805 . This situation is represented by equation 801 in Figure 8. However, the ratio of fine adjustment device steps to coarse adjustment device steps may be one eighth, one tenth, etc. This ratio can vary depending on different design requirements or different applications.

Figure 9 is a layout plan view 900 of the LC voltage controlled oscillator 109 from top to bottom. The layout plan 900 includes a high quality factor (Q) inductor 901, a constant guide (gm) circuit 902, a varactor diode 903, a trim capacitor 905, and a coarse capacitor 904, as understood by those skilled in the art.

Figure 10 shows a flow chart of the response of the phase locked loop of the present disclosure to unexpected interference. For example, phase locked loops may be affected by the test environment. Unexpected noise, temperature changes, or other factors may change the locking state of the phase-locked loop. First, unexpected noise or any voltage or temperature changes may occur. In this case, the voltage controlled oscillator tuning signal V _TUNE will increase or decrease to maintain the frequency of the voltage controlled oscillator output signal locked to the input reference signal. This step is represented by block 1001. When the voltage controlled oscillator tuning signal V _TUNE exceeds the upper limit value as shown by arrow 1002, the overflow signal is enabled and the underflow signal is disabled. Enable signal 215 will also enable the enable tuned array selection circuit. This step is shown in block 1005. After meeting this condition, the next thing to consider is whether the fine-tuning binary code signal is equal to the upper limit value, as indicated by arrow 1008. In the example shown in Figure 10, this value is 7. Therefore, if the fine binary signal is equal to 7, the coarse binary signal will be increased by 1 and the fine binary signal will change to a lower level, which is 4 in this example. This step is represented by block 1014. If the trimming binary code signal is not equal to 7, then the trimming binary code signal will only increase by 1, as shown in block 1015.

Next, the status of the overflow signal and the underflow signal must be considered. If both the overflow signal and the underflow signal are 0 as shown by arrow 1010, then the enable signal 215 will be set to "0" and the tuning array selection circuit and the LC voltage controlled oscillator will cease operation, as shown in block 1006 displayed. However, if the overflow signal is still enabled as shown by arrow 1009, then the tuning array selection circuit will be enabled and the process described in block 1005 will be followed again.

As shown by arrow 1004, the circuit will behave similarly when the voltage controlled oscillator tuning signal V _TUNE 101 is below the lower limit value. When the voltage controlled oscillator tuning signal V _TUNE 101 drops below the analog voltage range, the underflow signal will be enabled and the enable signal 215 will also be enabled, as shown at block 1007 . After meeting this condition, the next thing to consider is whether the fine-tuning binary code signal is equal to the lower limit value, as shown by arrow 1013. In the example shown in Figure 10, this value is 1. Therefore, if the fine binary signal is equal to 1, the coarse binary signal will be decreased by 1 and the fine binary signal will be changed to a higher level, in this example, the higher level is 4. This step is represented by block 1016. If the trimming binary signal is not equal to 1, then the trimming binary signal will only decrease by 1, as shown in block 1017.

The next thing to consider is the value of the overflow signal and the underflow signal. If both the overflow signal and the underflow signal are disabled, as shown by arrow 1011, the tuning array selection circuit will be disabled and cease operation. However, if the underflow signal is still enabled as shown by arrow 1012, then the tuning array selection circuit and the boundary checker will be enabled, and the enable signal 215 will be set to "1". Although there may be unexpected noise or voltage or temperature changes, there is still the possibility that the voltage controlled oscillator tuning signal V _TUNE is within the analog voltage range, as indicated by arrow 1003 . In this case, enable signal 215 will be set to "0" and no action will be taken, as shown by block 1006 .

Figures 11A, 11B, 11C, 11D, 11E, and 11F illustrate several different voltage controlled oscillator types that may utilize embodiments of the present disclosure. Figure 11A shows a complementary LC voltage controlled oscillator. Figure 11D shows an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) LC voltage-controlled oscillator. Book The voltage controlled oscillator disclosed in the document can be biased using an n-channel MOSFET. As an example, Figure 11B shows a complementary LC voltage controlled oscillator with a biased n-channel MOSFET. In addition, Figure 11E shows an LC voltage controlled oscillator with only n-channel MOSFETs. This LC voltage-controlled oscillator has an n-channel MOSFET biased. Voltage controlled oscillators utilizing embodiments of this disclosure may also employ current mirrors. Figure 11C shows a complementary LC voltage controlled oscillator with a current mirror. Similarly, Figure 11F shows an n-channel MOSFET-only LC voltage controlled oscillator with a current mirror. Additionally, other voltage controlled oscillators may be used within the spirit and scope of this disclosure.

Figure 12 shows a diagram of a digital implementation of an overflow and underflow detector. By using an analog-to-digital converter 1201 to convert the voltage controlled oscillator tuning signal V _TUNE 101 into a 16-bit digital code, the overflow and underflow detectors can be implemented in digital form. The 16 bits are represented in Figure 12 as A0 to A15 in the analog-to-digital converter 1201. The 16 individual bits B0 to B15 can be used to set the upper and lower limits of the voltage controlled oscillator tuning signal V _TUNE 101. For example, the first 8 bits B0~B7 can be used to set the lower limit of the voltage controlled oscillator tuning signal V _TUNE 101, and the next 8 bits B8~B15 can be used to set the upper limit of the voltage controlled oscillator tuning signal V _TUNE 101. The voltage controlled oscillator tuning signal V _TUNE 101 can be compared with these upper and lower limits through a digital comparator 1202 . In one example, if the supply voltage V _DD is 0.8V, 1 bit can cover 50mV. Therefore, when B0~B5 are set to 6'b111111, B6~B9 are set to 4'b0000 and B10~B15 are set to 6'b111111, the lower limit value is set to 300mV and the upper limit value is set to 500mV. If the voltage controlled oscillator tuning signal V _TUNE 101 is 400mV, the overflow signal 208 will be disabled, and the underflow signal 209 will also be disabled. If the voltage controlled oscillator tuning signal V _TUNE 101 is 550mV, the overflow signal will be enabled and the underflow signal will be disabled. However, if the voltage controlled oscillator tuning signal V _TUNE 101 is 250mV, the overflow signal 208 will be disabled and the underflow signal 209 will be enabled.

Figures 13A and 13B are diagrams illustrating the reduction in transition jitter and settling time caused by the effects of the LC voltage controlled oscillator embodiment of the present disclosure. Conversion jitter caused by embodiments of the present disclosure can be reduced by up to a factor of four compared to previous methods. Settling time can be reduced by a factor of six. The timing diagram of Figure 13A shows the waveform of the voltage controlled oscillator output signal using the previous tuning method. In the previous approach, transitions at a 3.5GHz output frequency could produce transition jitter of approximately 3.2 picoseconds and a settling time of approximately 0.3 microseconds. The timing diagram of Figure 13B shows the waveform of the output signal of the voltage controlled oscillator using the method of this disclosure document. Using the system and method used in this article, the conversion jitter can be reduced to 0.8 picoseconds and the settling time is less than 50 nanoseconds.

Figure 14 is a flow diagram of a method 1400 of tuning an LC voltage controlled oscillator. In one example, the first step 1401 is receiving a voltage controlled oscillator tuning signal. According to the example of this disclosure, the next step 1402 is to determine whether the voltage controlled oscillator tuning signal is above the analog voltage range, below the analog voltage range, or within the analog voltage range. If the VCO tuning signal is above the analog voltage range, the next step 1403 in the method is to select a trimming device to generate a VCO output signal in the higher narrow frequency range. No. However, if the VCO tuning signal is below the analog voltage range, the next step 1404 in the method is to select a trimming device to generate a VCO output signal in a lower narrow frequency range. Regardless of whether the trimming device is selected to generate a voltage controlled oscillator output signal in a higher narrow frequency range or a voltage controlled oscillator output signal in a lower narrow frequency range, the next step 1405 is to determine whether the narrow frequency range is in a wide frequency range high level or low level.

The previous article reveals a phase-locked loop. In some embodiments of the phase locked loop, the phase locked loop of the present disclosure includes a voltage controlled oscillator, the voltage controlled oscillator includes a coarse adjustment array and a fine adjustment array, the coarse adjustment array includes a plurality of coarse adjustment devices, and the fine adjustment array includes a plurality of coarse adjustment devices. Fine adjustment device. The phase locked loop of the present disclosure can be used to select a trimming device from a plurality of trimming devices in the trimming array to increase the frequency of the voltage controlled oscillator output signal to a higher level within a narrow frequency range. This selection can be based on the determination that the voltage controlled oscillator tuning signal is above the analog voltage range.

In some embodiments of the phase locked loop, the voltage controlled oscillator can also be used to select a trimming device from a plurality of trimming devices in the trimming array to reduce the frequency of the output signal of the voltage controlled oscillator to a lower narrow frequency range. level. This selection may be based on the determination that the voltage controlled oscillator tuning signal is below the analog voltage range. Based on the determination that the tuning signal of the voltage controlled oscillator is higher than the analog voltage range and the narrow frequency range is at a high level within the wide frequency range, the voltage controlled oscillator can be further used to select one of the plurality of coarse adjustment devices of the coarse adjustment array. A coarse adjustment device is used to increase the frequency of the voltage controlled oscillator output signal to a higher level within a wide frequency range.

In some phase-locked loop embodiments, the voltage-controlled oscillator may further be used to adjust the voltage-controlled oscillator from a coarse-tuned array based on a determination that the voltage-controlled oscillator tuning signal is below the analog voltage range and that the narrow frequency range is at a low level within the wide frequency range. A coarse adjustment device is selected among a plurality of coarse adjustment devices to reduce the frequency of the output signal of the voltage controlled oscillator to a level within a lower frequency range.

In some phase locked loop embodiments, the voltage controlled oscillator of the present disclosure may be further used to receive one or a plurality of coarse adjustment selection signals for selecting a coarse adjustment device from a plurality of coarse adjustment devices in the coarse adjustment array. adjustment device. In addition, the voltage controlled oscillator can be used to receive one or a plurality of trimming selection signals for selecting a trimming device from a plurality of trimming devices in the trimming array. Each of a plurality of coarse tuning devices may be selected to tune the voltage controlled oscillator output signal to a different wide frequency range. Each of the plurality of fine tuning devices may be selected to tune the voltage controlled oscillator output signal to a different narrow frequency range within the wide frequency range of the selected coarse tuning device.

In some phase locked loop embodiments, the voltage controlled oscillator can be further used when the frequency of the voltage controlled oscillator output signal generated by the trimming array is at a higher frequency level within a wide frequency range and the voltage controlled oscillator tuning signal is high. In the analog voltage range, select a trimmer corresponding to the lower frequency level within the wide frequency range. In this manner, the voltage controlled oscillator can be tuned to produce a voltage controlled oscillator output signal with a net increase in frequency.

In some phase locked loop embodiments, the voltage controlled oscillator can also be further used when the frequency of the voltage controlled oscillator output signal generated by the trimming array is at a lower frequency level within a wide frequency range and the voltage controlled oscillator tuning signal Below the analog voltage range, select the phase phase with a higher frequency level within a wide frequency range. Corresponding fine-tuning device. In this manner, the voltage controlled oscillator can be tuned to produce a voltage controlled oscillator output signal with a net reduction in frequency. The amplitude of the net increase in frequency and the net decrease in frequency of the voltage controlled oscillator output signal may be smaller than the wide frequency range. The net increase in frequency and the net decrease in frequency of the voltage controlled oscillator output signal cause switching jitter in the phase locked loop, which switching jitter is smaller than the switching jitter caused by the frequency increase of the voltage controlled oscillator output signal equal to a wide frequency range.

In some phase locked loop embodiments, the phase locked loop of this disclosure may also include a tuned array selection circuit. The tuning array selection circuit can be used to receive the voltage controlled oscillator tuning signal, and generate a coarse binary bit code selection signal according to whether the voltage controlled oscillator tuning signal is higher than the analog voltage range, lower than the analog voltage range, or within the analog voltage range. and fine-tuning the binary code selection signal.

In some embodiments of the phase locked loop, the trimming binary code signal is generated when the voltage controlled oscillator tuning signal is higher than the analog voltage range to indicate that the frequency of the voltage controlled oscillator output signal is increased to a higher level within the narrow frequency range. bit, and when the voltage controlled oscillator tuning signal is lower than the analog voltage range, it indicates that the frequency of the voltage controlled oscillator output signal is reduced to a level within a lower narrow frequency range.

In some phase locked loop embodiments, a coarse binary code signal is generated when the voltage controlled oscillator tuning signal is above the analog voltage range and the narrow frequency range is at a high level within the wide frequency range to indicate the voltage controlled oscillator The frequency of the output signal increases to a higher level within the wide frequency range and indicates the voltage controlled oscillator output when the voltage controlled oscillator tuning signal is below the analog voltage range and the narrow frequency range is at a low level within the wide frequency range The frequency of the signal is reduced to level over a lower frequency range.

In some phase locked loop embodiments, the phase locked loop of the present disclosure may further include a decoder. The decoder can be used to receive the fine-tuning binary code signal and the coarse-tuning binary code signal, convert the coarse-tuning binary code signal into one or more coarse-tuning selection signals, and convert the fine-tuning binary code signal into one or more fine-tuning selection signals. .

In some phase-locked loop embodiments, the phase-locked loop of the present disclosure may also include analog overflow and underflow detectors, fine-tuning counter circuits, and coarse-tuning counter circuits. The analog overflow and underflow detector can be used to receive the voltage controlled oscillator tuning signal and generate an overflow signal when the voltage controlled oscillator tuning signal is higher than the analog voltage range. Analog overflow and underflow detectors can also be used to generate an underflow signal when the voltage controlled oscillator tuning signal falls below the analog voltage range.

In some phase locked loop embodiments, the trimming counter circuit may be used to receive overflow signals and underflow signals. The trimming counter circuit can also be used to determine whether the voltage controlled oscillator can use the selected trimming device to generate a voltage controlled oscillator output signal proportional to the reference input signal based on the enablement of the overflow signal and the underflow signal. The fine-tuning counter circuit can also be used to determine whether the narrow frequency range of the selected fine-tuning device is at a high level or a low level within the wide frequency range, and when the narrow frequency range is at a high level within the wide frequency range, a high frequency is generated Level boundary signal. The trimming counter circuit can also be used to generate a low frequency level boundary signal when the narrow frequency range is at a low level within the wide frequency range. In addition, the trimming counter circuit can generate a trimming binary code signal corresponding to a higher narrow frequency range when the overflow signal is enabled, and generate a trimming binary code signal corresponding to a lower narrow frequency range when the underflow signal is enabled. signal.

In some embodiments of the phase locked loop, the coarse counter circuit of the phase locked loop of the present disclosure can be used to receive one or more frequency level boundary signals and binary code input signals to determine whether the voltage controlled oscillator can The selected coarse adjustment device is used to produce a voltage controlled oscillator output signal proportional to the reference input signal. The coarse counter circuit generates a signal corresponding to a higher bandwidth when a high frequency level boundary signal is enabled and the VCO is unable to produce a VCO output signal proportional to the reference input signal using the selected coarse device. Coarse binary code signal in the rate range. The coarse adjustment device can also generate a VCO output signal proportional to the reference input signal when the low frequency level boundary signal is enabled and the VCO is unable to produce a VCO output signal proportional to the reference input signal using the selected coarse adjustment device. Coarse binary code signal in the rate range.

In some embodiments of the phase locked loop, the tuning array selection circuit of the present disclosure may further include a boundary checker. The boundary checker is used to receive the coarse binary code signal and determine the coarse adjustment device according to the coarse binary code signal. Whether it corresponds to the upper or lower boundary of the frequency range of the voltage controlled oscillator output signal. The tuning array selection circuit can also be used to generate an enable signal when the coarse adjustment device corresponds to the upper or lower boundary of the frequency range of the voltage controlled oscillator output signal. The enable signal can be used to disable the tuning array selection circuit.

In some phase locked loop embodiments, the tuned array selection circuit of the present disclosure may also include a frequency divider for receiving a reference input signal and calculating the frequency of the reduced frequency signal based on the reference input signal. The frequency divider can also be used to calculate the frequency of the down-frequency signal based on the reference input signal. and generates a reduced frequency signal. The reduced frequency signal may be equal to the frequency of the reference input signal divided by a predetermined constant.

In an exemplary embodiment of the present disclosure, the coarse adjustment device and the fine adjustment device of the present disclosure are capacitors.

This disclosure document also discloses a voltage-controlled oscillator, which may include a coarse-tuning array and a fine-tuning array. The coarse adjustment array includes a plurality of coarse adjustment devices, and the fine adjustment array includes a plurality of fine adjustment devices. In an exemplary embodiment of the present disclosure, the voltage controlled oscillator may be an inductor-capacitor voltage controlled oscillator.

In some embodiments of the voltage controlled oscillator, based on the determination that the tuning signal of the voltage controlled oscillator is higher than the analog voltage range, the voltage controlled oscillator is used to select a trimming device from the trimming devices of the trimming array to adjust the voltage controlled oscillator. The frequency of the device output signal increases to a higher narrow frequency range. In some embodiments of the voltage controlled oscillator, based on the determination that the tuning signal of the voltage controlled oscillator is lower than the analog voltage range, the voltage controlled oscillator is used to select a trimming device from the trimming devices of the trimming array to adjust the voltage controlled oscillator. The frequency of the output signal of the converter is reduced to a lower narrow frequency range.

In some embodiments of the voltage controlled oscillator, the voltage controlled oscillator is used to adjust the voltage controlled oscillator from the coarse tuning array based on a determination that the voltage controlled oscillator tuning signal is above the analog voltage range and that the narrow frequency range is at a high level within the wide frequency range. A coarse adjustment device is selected among the coarse adjustment devices to increase the frequency of the output signal of the voltage controlled oscillator to a higher and wider frequency range. In some embodiments of the voltage controlled oscillator, based on a determination that the voltage controlled oscillator tuning signal is below the analog voltage range and that the narrow frequency range is at a low level within the wide frequency range, the voltage controlled oscillator is used to start the coarse frequency range. A coarse adjustment device is selected among the coarse adjustment devices of the modulation array to reduce the frequency of the output signal of the voltage controlled oscillator to a lower wide frequency range.

In some embodiments of the voltage controlled oscillator, the voltage controlled oscillator is further used when the frequency of the voltage controlled oscillator output signal generated by the trimming array is at a high frequency level within a wide frequency range and the voltage controlled oscillator tuning signal is higher than In the analog voltage range, a trimmer corresponding to a low frequency level within a wide frequency range is selected such that the voltage controlled oscillator is tuned to produce a voltage controlled oscillator output signal with a net increase in frequency. When the frequency of the voltage-controlled oscillator output signal generated by the trimming array is at a lower frequency level in the wide frequency range and the voltage-controlled oscillator tuning signal is lower than the analog voltage range, the phase with the higher frequency level in the wide frequency range is selected. The corresponding trimming device causes the voltage controlled oscillator to be tuned to generate a voltage controlled oscillator output signal with a net reduction in frequency.

In some embodiments of the voltage controlled oscillator, the net increase in frequency and the net decrease in frequency of the voltage controlled oscillator output signal are smaller than the wide frequency range.

In some voltage controlled oscillator embodiments, a net increase in frequency and a net decrease in frequency of the voltage controlled oscillator output signal cause switching jitter in the phase locked loop that is less than the frequency increase of the voltage controlled oscillator output signal equal to Conversion jitter caused by wide frequency range.

The foregoing detailed description also discloses a tuning method for tuning a voltage controlled oscillator. In one example, the tuning method may include the first step of receiving a voltage controlled oscillator tuning signal. The tuning method may further include the step of determining whether the voltage controlled oscillator tuning signal is above the analog voltage range, below the analog voltage range, or within the analog voltage range. Another step in this tuning method may include selecting trim when the voltage controlled oscillator tuning signal is above the analog voltage range device to generate a voltage controlled oscillator output signal within a higher narrow frequency range. Another step of the tuning method may be to select a trimming device to generate a VCO output signal in a lower narrow frequency range when the VCO tuning signal is below the analog voltage range. The tuning method may also involve the step of determining whether the narrow frequency range is at the high or low level of the broad frequency range.

In some embodiments of the tuning method, the tuning method of tuning the voltage controlled oscillator may also include the steps of selecting a coarse tuning device corresponding to a higher broad frequency range and selecting a fine tuning device corresponding to a low level within the broad frequency range. This coarse adjustment device and fine adjustment device can be selected when the voltage controlled oscillator tuning signal is higher than the analog voltage range and the narrow frequency range is at a high level within the wide frequency range. In this way, the frequency variation amplitude of the voltage controlled oscillator output signal can be smaller than the wide frequency range.

In some embodiments of the tuning method, the tuning method of tuning the voltage controlled oscillator may also include the steps of selecting a coarse tuning device corresponding to a lower broad frequency range and selecting a fine tuning device corresponding to a higher level within the broad frequency range. . This coarse adjustment device and fine adjustment device can be selected when the voltage controlled oscillator tuning signal is higher than the analog voltage range and the narrow frequency range is at a lower level within the wide frequency range.

The foregoing summary summarizes the features of several embodiments so that those skilled in the art may better understand the aspects of this disclosure. Those skilled in the art should appreciate that they may readily use this disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and they may Various changes, substitutions and alterations may be made herein without departing from the spirit and scope of this disclosure document.

101: Voltage controlled oscillator tuning signal

102: Reference input signal

103: Coarse adjustment of binary code signal

104: Fine-tuning the binary code signal

105: Coarse adjustment selection signal

106: Fine-tuning the selection signal

107: Tuning array selection circuit

108:Decoder

109, LC VCO: Inductor/Capacitor Voltage Controlled Oscillator

110: Voltage controlled oscillator output signal

201: Analog Overflow and Underflow Detector

202: Fine-tuning counter circuit

203: Coarse adjustment counter circuit

204:Bounds checker

205:Frequency divider

206: Coarse array

207: Fine-tuning array

208: Overflow signal

209: Underflow signal

210: High frequency level boundary signal/fine-tuning range overflow signal

211: Low frequency level boundary signal/fine-tuning range underflow signal

213: First reduced frequency signal

214: Second lower frequency signal

215: Enable signal

216: Voltage controlled oscillator overflow tuning signal

217: Voltage controlled oscillator underflow tuning signal

218: Coarse adjustment of binary code input signal

Claims (10)

A phase locked loop includes: a voltage controlled oscillator, the voltage controlled oscillator includes a coarse adjustment array and a fine adjustment array, the coarse adjustment array includes a plurality of coarse adjustment devices, and the fine adjustment array includes a plurality of fine adjustment devices, wherein, Based on the determination that the tuning signal of a voltage controlled oscillator is higher than an analog voltage range, the voltage controlled oscillator is used to select a trimming device from among the trimming devices of the trimming array to adjust the output signal of a voltage controlled oscillator. The frequency is increased to a higher narrow frequency range, wherein the voltage controlled oscillator is used to select one of the trimming devices of the trimming array based on a determination that the voltage controlled oscillator tuning signal is lower than the analog voltage range. Trimming device to reduce the frequency of the voltage controlled oscillator output signal to a lower narrow frequency range, wherein the voltage controlled oscillator tuning signal is higher than the analog voltage range and a narrow frequency range is within a wide frequency range The voltage controlled oscillator is used to select a coarse adjustment device from among the coarse adjustment devices of the coarse adjustment array to increase the frequency of the output signal of the voltage controlled oscillator to a higher level. In a high and wide frequency range, and wherein, based on the determination that the voltage controlled oscillator tuning signal is lower than the analog voltage range and the narrow frequency range is at a low level within the wide frequency range, the voltage controlled oscillator is used to obtain the signal from the voltage controlled oscillator. A coarse adjustment device is selected among the coarse adjustment devices of the coarse adjustment array to reduce the frequency of the output signal of the voltage controlled oscillator to a lower wide frequency range. The phase locked loop of claim 1, wherein the voltage controlled oscillator is further used to receive one or a plurality of coarse adjustment selection signals for selecting a coarse adjustment from among the coarse adjustment devices in the coarse adjustment array. device, and receiving one or more fine-tuning selection signals for selecting a fine-tuning device from among the fine-tuning devices in the fine-tuning array, wherein each of the coarse-tuning devices can be selected to control the voltage-controlled oscillation. The output signal of the voltage controlled oscillator is tuned to a different wide frequency range, and each of the fine-tuning devices can be selected to tune the voltage-controlled oscillator output signal to a different narrow one of the wide frequency range of a selected coarse-tuning device. frequency range. The phase locked loop of claim 2, wherein the voltage controlled oscillator is further used to operate when the frequency of the voltage controlled oscillator output signal generated by the trimming array is at a high level within the wide frequency range and the voltage controlled oscillation When the oscillator tuning signal is higher than the analog voltage range, a trimming device corresponding to a low frequency level in the wide frequency range is selected, so that the voltage controlled oscillator is tuned to generate the voltage controlled oscillation with a net increase in frequency. The output signal of the oscillator, and when the frequency of the voltage-controlled oscillator output signal generated by the fine-tuning array is at a low level within the wide frequency range and the voltage-controlled oscillator tuning signal is lower than the analog voltage range, the wide-frequency A trimming device corresponding to a higher frequency level within the frequency range causes the voltage controlled oscillator to be tuned to produce an output signal of the voltage controlled oscillator with a net reduction in frequency. The phase locked loop as described in claim 2, wherein the phase locked loop The circuit further includes: a tuning array selection circuit, the tuning array selection circuit is used to receive the voltage controlled oscillator tuning signal, and according to the voltage controlled oscillator tuning signal is higher than an analog voltage range, lower than the analog voltage range, or Within the analog voltage range, a coarse-tuned binary code selection signal and a fine-tuned binary code selection signal are generated, wherein the fine-tuned binary code signal is generated when the voltage-controlled oscillator tuning signal is higher than the analog voltage range It is used to indicate that the frequency of the output signal of the voltage controlled oscillator increases to a level within a higher narrow frequency range, and is used to indicate the voltage controlled oscillation when the tuning signal of the voltage controlled oscillator is lower than the analog voltage range. The frequency of the output signal of the oscillator is reduced to a level within a lower narrow frequency range, wherein the coarse-tuned binary code signal is generated when the voltage-controlled oscillator tuning signal is higher than the analog voltage range and the narrow frequency The frequency of the voltage controlled oscillator output signal is generated when the frequency range is at a high level within the wide frequency range to increase to a higher level within the wide frequency range, and when the voltage controlled oscillator tuning signal is lower than When the analog voltage range and the narrow frequency range are at a low level within the wide frequency range, they are used to indicate that the frequency of the output signal of the voltage controlled oscillator is reduced to a lower level within the wide frequency range; and a decoding The decoder is used to receive the fine-tuning binary code signal and the coarse-tuning binary code signal, convert the coarse-tuning binary code signal into one or more coarse-tuning selection signals, and convert the fine-tuning binary code signal into The one or plurality of trim selection signals. The phase locked loop of claim 4, wherein the tuning array selection circuit includes: an analog overflow and underflow detector, the analog overflow and underflow detector is used to receive the voltage controlled oscillator tuning signal, and in the An overflow signal is generated when the voltage controlled oscillator tuning signal is higher than the analog voltage range, and an underflow signal is generated when the voltage controlled oscillator tuning signal is lower than the analog voltage range; a fine-tuning counter circuit, the fine-tuning counter circuit uses To receive the overflow signal and the underflow signal, and to determine whether the voltage controlled oscillator can use the selected trimming device to generate a signal proportional to a reference input signal based on the enabling of the overflow signal and the underflow signal. The output signal of the voltage controlled oscillator is used to determine whether the narrow frequency range of the selected fine-tuning device is at a high level or a low level within the wide frequency range, and is used to determine whether the narrow frequency range is at a high level or a low level within the wide frequency range. When the narrow frequency range is at a low level within the wide frequency range, a high frequency level boundary signal is generated to generate a low frequency level boundary signal when the overflow signal is Generating a trimming binary code signal corresponding to a higher narrow frequency range when enabled, and for generating a trimming binary code signal corresponding to a lower narrow frequency range when the underflow signal is enabled; and A coarse adjustment counter circuit, the coarse adjustment counter circuit is used to receive the one or plurality of frequency level boundary signals and a binary code input signal, and is used to operate according to the one or plurality of frequency level boundary signals and the binary code. The input signal determines whether the voltage controlled oscillator can produce the voltage controlled oscillator output signal proportional to the reference input signal using the selected coarse adjustment device, for generating a comparison signal corresponding to the voltage controlled oscillator when the high frequency level boundary signal is enabled and the voltage controlled oscillator cannot use the selected coarse adjustment device to generate an output signal of the voltage controlled oscillator that is proportional to the reference input signal. A coarse-tuned binary code signal over a wide frequency range, such that at the low frequency level boundary the signal is enabled and the voltage controlled oscillator is unable to use the selected coarse-tuning device to produce a signal proportional to the reference input signal The output signal of the voltage controlled oscillator generates a coarse-tuned binary code signal corresponding to a lower wide frequency range. A voltage controlled oscillator, the voltage controlled oscillator includes: a coarse adjustment array, the coarse adjustment array includes a plurality of coarse adjustment devices; and a fine adjustment array, the fine adjustment array includes a plurality of fine adjustment devices, wherein, according to a voltage controlled oscillation Determining that the oscillator tuning signal is higher than an analog voltage range, the voltage controlled oscillator is used to select a trimming device from among the trimming devices of the trimming array to increase the frequency of a voltage controlled oscillator output signal to a relatively Within a high and narrow frequency range, wherein, based on the determination that the tuning signal of the voltage controlled oscillator is lower than the analog voltage range, the voltage controlled oscillator is used to select a trimming device from among the trimming devices of the trimming array to adjust The frequency of the voltage controlled oscillator output signal is reduced to a lower narrow frequency range, wherein the voltage controlled oscillator tuning signal is higher than the analog voltage range and a narrow frequency range is within a high accuracy of a wide frequency range. bit determination, the voltage controlled oscillator is used to select a coarse adjustment device from among the coarse adjustment devices of the coarse adjustment array to increase the frequency of the output signal of the voltage controlled oscillator to a higher and wider frequency range ,and Wherein, based on the determination that the voltage controlled oscillator tuning signal is lower than the analog voltage range and the narrow frequency range is at a low level within the wide frequency range, the voltage controlled oscillator is used to obtain the coarse tuning signals from the coarse tuning array. A coarse adjustment device is selected among the adjustment devices to reduce the frequency of the output signal of the voltage controlled oscillator to a lower wide frequency range. The voltage controlled oscillator as described in claim 6, wherein the voltage controlled oscillator is further used when the frequency of the voltage controlled oscillator output signal generated by the trimming array is at a high level within the wide frequency range and the voltage controlled oscillator When the oscillator tuning signal is higher than the analog voltage range, a trimming device corresponding to a low frequency level in the wide frequency range is selected, so that the voltage controlled oscillator is tuned to produce the voltage controlled oscillator with a net increase in frequency. The oscillator output signal, and when the frequency of the voltage-controlled oscillator output signal generated by the fine-tuning array is at a low level within the wide frequency range and the voltage-controlled oscillator tuning signal is lower than the analog voltage range, is selected to match the A trimming device corresponding to a higher frequency level within a wide frequency range causes the voltage controlled oscillator to be tuned to produce an output signal of the voltage controlled oscillator with a net reduction in frequency. A tuning method for a voltage controlled oscillator, including the following steps: receiving a voltage controlled oscillator tuning signal; determining whether the voltage controlled oscillator tuning signal is higher than an analog voltage range, lower than the analog voltage range, or within the analog voltage range within; when the voltage controlled oscillator tuning signal is higher than the analog voltage range, select a a trimming device to generate a voltage controlled oscillator output signal within a higher narrow frequency range; when the voltage controlled oscillator tuning signal is lower than the analog voltage range, a trimming device is selected to generate a lower narrow frequency The voltage controlled oscillator output signal within the range; and determining whether a narrow frequency range is at a high level or a low level of a wide frequency range. The tuning method described in claim 8 further includes the following steps: when the voltage controlled oscillator tuning signal is higher than the analog voltage range and the narrow frequency range is at a high level within the wide frequency range, select a corresponding A coarse adjustment device for a higher wide frequency range and a fine adjustment device corresponding to a lower level within the wide frequency range are selected. The tuning method of claim 8 further includes the following steps: when the voltage controlled oscillator tuning signal is lower than the analog voltage range and the narrow frequency range is at a low level within the wide frequency range, select a signal corresponding to A coarse adjustment device for a lower wide frequency range and a fine adjustment device corresponding to a higher level within the wide frequency range are selected.

Images