TWI817374B - Semiconductor structure having a fin structure and method for preparing the same - Google Patents

Abstract

A semiconductor structure is provided. The semiconductor substrate has an active region defined by an isolation structure. A trench passes through the active region and the isolation structure. The active region of the semiconductor substrate includes a fin structure in the trench. The fin structure includes a first protrusion extending upwards along a first sidewall of the trench.

Description

Semiconductor structure with fin structure and preparation method thereof

This application claims priority to U.S. Patent Application Nos. 17/554,813 and 17/554,102 (that is, the priority date is "December 17, 2021"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor structure, and particularly to a semiconductor structure having a fin structure.

With the rapid growth of the electronics industry, the development of semiconductor components has achieved high performance and miniaturization. Due to the shrinkage of semiconductor devices, such as dynamic random access memory (DRAM) devices, a short channel effect may occur. In order to deal with such problems, a buried-channel array transistor (BCAT) element is proposed.

However, although the recessed channel of BCAT components improves the short channel effect, BCAT components have other problems, such as threshold voltage (Vth) reduction and current leakage, which adversely affect the performance and stability of semiconductor components.

The above "prior art" description is merely to provide background technology, and does not admit that the above "prior art" description reveals the subject matter of the present disclosure, and does not constitute prior art for the present disclosure, and Any description of the "prior art" above shall not constitute any part of this case.

An embodiment of the present disclosure provides a semiconductor structure including a semiconductor substrate. The semiconductor substrate has an active region defined by an isolation structure. A trench passes through the active region and the isolation structure. The active region of the semiconductor substrate includes a fin structure in the trench. The fin structure includes a first protrusion extending upward along a first side wall of the trench.

Another embodiment of the present disclosure provides a semiconductor structure including a semiconductor substrate and a conductive element. The semiconductor substrate has an active region including a fin structure. The fin structure includes a main body part and a first tapered part. The first tapered portion protrudes from an upper surface of the main body portion. The conductive element is provided on the body portion and the first tapered portion of the fin structure.

Another embodiment of the present disclosure provides a method of manufacturing a semiconductor structure. The preparation method includes providing a semiconductor substrate with an active region. The preparation method also includes removing a portion of the active region of the semiconductor substrate to form a trench and an initial fin structure. The preparation method also includes removing a portion of the initial fin structure to form a fin structure, the fin structure including a first protrusion extending upward along a first side wall of the trench.

When designing a fin structure that includes a protrusion extending upwardly along the trench sidewalls, the protrusion can provide an extension of the fin structure that can be further covered by a conductive element. Since the electric field is relatively high near the trench sidewalls (i.e., the doped region or the source/drain region of the unit transistor), the protrusions covered by the conductive element can increase the coverage of the conductive element (i.e., the gate control region) area. Thus, additional gate control areas can be created and gate control of the semiconductor structure (ie, transistor) channel can be improved.

The technical features and advantages of the present disclosure have been summarized rather broadly in order to facilitate the following This article reveals detailed descriptions to gain a better understanding. Other technical features and advantages that constitute the subject matter of the patentable scope of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purposes of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

1: Semiconductor structure

1B-1B': line

1D: Part

2B-2B': line

3B-3B': line

4B-4B': line

5B-5B': line

6B-6B': line

7B-7B': line

10:Semiconductor substrate

10A: Active area

20:Isolation structure

30:Trench

30A: Groove

40:Conductive components

50:Dielectric layer

90:Preparation method

100: Fin structure

100A: Initial fin structure

100A1: Upper surface

100A2: Side

110:Protrusion

111: Incline

112: Incline

113: Incline

120: Main part

121: Upper surface

122: Incline

123: Incline

124: Bottom

130:Protrusion

131: Incline

132: Incline

133: Incline

201: Upper surface

301:Side wall

302:Side wall

303: Bottom surface

PR: Patterned photoresist layer

S91: Operation

S92: Operation

S93: Operation

T1: Depth

T2: distance

T3:Thickness

T4:Thickness

T5:Thickness

T6: distance

W1: Width

W2: Width

W3: length

W4: length

X: direction

Y: direction

Z: direction

The disclosure content of this application can be more fully understood by referring to the embodiments and the patent scope combined with the drawings. The same element symbols in the drawings refer to the same elements.

FIG. 1A is a top view illustrating a semiconductor structure according to some embodiments of the present disclosure.

FIG. 1B is a cross-sectional view illustrating a semiconductor structure according to some embodiments of the present disclosure.

1C is a three-dimensional view illustrating a semiconductor structure of some embodiments of the present disclosure.

FIG. 1D is a perspective view illustrating a portion of a semiconductor structure according to some embodiments of the present disclosure.

2A and 2B illustrate one stage of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.

3A and 3B illustrate one stage of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.

4A and 4B illustrate one stage of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.

5A and 5B illustrate one stage of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.

6A and 6B illustrate one stage of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.

7A and 7B illustrate one stage of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.

8A and 8B illustrate one stage of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.

FIG. 9 is a flow chart illustrating a method of manufacturing a semiconductor structure according to some embodiments of the present disclosure.

Specific language will now be used to describe the embodiments, or examples, of the present disclosure illustrated in the drawings. It should be understood that there is no intention to limit the scope of the present disclosure. Any changes or modifications to the described embodiments, and any further applications of the principles described herein, are deemed to be commonly made by one of ordinary skill in the art to which this disclosure relates. Reference numerals may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment apply to another embodiment even if they share the same reference numerals.

It will be understood that the terms first, second, third, etc. may be used to describe various elements, components, regions, layers or sections. May be used to describe various elements, components, regions, layers or sections but these elements, components, regions, layers or sections are not limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the inventive concept.

The terminology used herein is for describing particular embodiments only and is not intended to be limiting of the concepts of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should be further understood that the terms "comprising" and "comprising" when used in this specification indicate stated features, integers, steps, operations, elements or the presence of an element, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, elements or groups thereof.

1A is a top view illustrating the semiconductor structure 1 of some embodiments of the present disclosure, FIG. 1B is a cross-sectional view illustrating the semiconductor structure 1 of some embodiments of the present disclosure, FIG. 1C is a three-dimensional view illustrating the semiconductor structure 1 of some embodiments of the present disclosure, and FIG. 1D is a perspective view illustrating a portion 1D of a semiconductor structure 1 according to some embodiments of the present disclosure. The semiconductor structure 1 includes a semiconductor substrate 10 , an isolation structure 20 , one or more trenches 30 , one or more conductive elements 40 , and one or more dielectric layers 50 .

FIG. 1B is a cross-sectional view along line 1B-1B' in FIG. 1A. In some embodiments, FIG. 1B is a cross-sectional view along line 1B-1B' in FIG. 1C. It should be noted that some elements (eg, conductive element 40 and dielectric layer 50) are omitted from Figure ID for clarity.

Semiconductor substrate 10 may include one or more active regions 10A defined by isolation structures 20 . In some embodiments, active region 10A of semiconductor substrate 10 is adjacent to and defined by isolation structure 20 . The fabrication technology of semiconductor substrate 10 may be or include, for example, silicon, doped silicon, silicon germanium, silicon on insulator, silicon on sapphire, silicon germanium on insulator, silicon carbide, germanium, gallium arsenide, gallium phosphide , gallium arsenide phosphide, indium phosphide, gallium indium phosphide or any other Group IV-IV, Group III-V or Group I-VI semiconductor material.

The manufacturing technology of the isolation structure 20 may be or include an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

Trench 30 may pass through active region 10A and isolation structure 20 . In some embodiments, the trench 30 extends along an extension direction of the Y axis (or Y direction), and the trench 30 has a width W1 along the X axis (or X direction). In some embodiments, trench 30 has sidewall 301 and sidewall 302 opposite sidewall 301 . Width W1 is the distance between side wall 301 and side wall 302 . In some embodiments , the width W1 of the trench 30 is about 20 nanometers (nm) to about 30 nanometers. In some embodiments, trench 30 has a depth T1. In some embodiments, trench 30 has a depth T1 of about 20 nanometers to about 150 nanometers.

In some embodiments, trench 30 includes one or more trench portions in one or more active regions 10A, and one or more trench portions in isolation structure 20 . In some embodiments, trench portions in active region 10A are connected to trench portions in isolation structure 20 . In some embodiments, the trench portion in active region 10A has a length W4 along the extension direction of trench 30 (eg, Y-axis). In some embodiments, the length W4 of the trench portion of trench 30 in active region 10A is from about 5 nanometers to about 30 nanometers.

In some embodiments, the active region 10A of the semiconductor substrate 10 may further include a doped region adjacent to the sidewalls 301 and 302 of the trench 30 . The doped region may be adjacent to a trench portion of trench 30 in active region 10A. The doped region may be a source/drain region.

In some embodiments, active region 10A of semiconductor substrate 10 includes one or more fin structures 100 in trench 30 . In some embodiments, fin structure 100 includes body portion 120 and protrusions 110 and 130 . In some embodiments, body portion 120 is connected to protrusions 110 and 130 .

Referring to FIGS. 1B to 1D , the main body portion 120 of the fin structure 100 may have an upper surface 121 , a bottom surface 124 opposite to the upper surface 121 , and inclined surfaces 122 and 123 . In some embodiments, the area of upper surface 121 is smaller than the area of bottom surface 124 . In some embodiments, the slope 122 of the body portion 120 extends from the upper surface 121 to the bottom surface 124 . In some embodiments, bevel 123 of body portion 120 extends from upper surface 121 to bottom surface 124 . In some embodiments, the slope 122 of the body portion 120 extends from the upper surface 121 to the bottom surface 303 of the trench 30 . In some embodiments, bevel 123 of body portion 120 extends from upper surface 121 to bottom surface 303 of trench 30 .

In some embodiments, upper surface 121 of body portion 120 has a width W2 along the X-axis. In some embodiments, the ratio of the width W2 of the upper surface 121 of the body portion 120 to the width W1 of the trench 30 (W2/W1) is equal to or exceeds about 0.5. In some embodiments, the ratio of the width W2 of the upper surface 121 of the body portion 120 to the width W1 of the trench 30 (W2/W1) is equal to or exceeds about 0.6. In some embodiments, the ratio of the width W2 of the upper surface 121 of the body portion 120 to the width W1 of the trench 30 (W2/W1) is equal to or exceeds about 0.7. In some embodiments, the ratio of the width W2 of the upper surface 121 of the body portion 120 to the width W1 of the trench 30 (W2/W1) is equal to or exceeds about 0.8.

In some embodiments, the upper surface 121 of the body portion 120 has a length W3 along the extension direction of the trench 30 (eg, the Y-axis). In some embodiments, length W3 may extend in a direction (eg, Y-axis) that is substantially perpendicular to the direction in which width W2 extends (eg, X-axis). In some embodiments, the ratio (W3/W4) of the length W3 of the upper surface 121 of the body portion 120 to the length W4 of the trench portion of the trench 30 in the active region 10A is equal to or exceeds about 0.5. In some embodiments, the ratio (W3/W4) of the length W3 of the upper surface 121 of the body portion 120 to the length W4 of the trench portion of the trench 30 in the active region 10A is equal to or exceeds about 0.6. In some embodiments, the ratio (W3/W4) of the length W3 of the upper surface 121 of the body portion 120 to the length W4 of the trench portion of the trench 30 in the active region 10A is equal to or exceeds about 0.7. In some embodiments, the ratio (W3/W4) of the length W3 of the upper surface 121 of the body portion 120 to the length W4 of the trench portion of the trench 30 in the active region 10A is equal to or exceeds about 0.8.

In some embodiments, body portion 120 has a thickness T4. The thickness T4 of the body portion 120 may be defined by the vertical distance between the upper surface 121 and the bottom surface 124 of the body portion 120 . In some embodiments, thickness T4 is from about 10 nanometers to about 100 nanometers. In some embodiments, the ratio of the thickness T4 of the body portion 120 to the depth T1 of the trench 30 (T4/T1) is equal to or less than About 0.5. In some embodiments, the ratio of thickness T4 of body portion 120 to depth T1 of trench 30 (T4/T1) is equal to or less than about 0.4. In some embodiments, the ratio of thickness T4 of body portion 120 to depth T1 of trench 30 (T4/T1) is equal to or less than about 0.3.

In some embodiments, the opening of the groove 30 may be spaced a certain distance T2 from the upper surface 121 of the body portion 120 . In some embodiments, distance T2 is from about 10 nanometers to about 100 nanometers.

In some embodiments, a portion of the isolation structure 20 is in the trench 30 and has an upper surface 201 , and the slope 122 of the body portion 120 extends from the upper surface 121 of the body portion 120 to the upper surface of the isolation structure 20 in the trench 30 201. In some embodiments, the bevel 123 of the body portion 120 extends from the upper surface 121 of the body portion 120 to the upper surface 201 of the isolation structure 20 in the trench 30 .

In some embodiments, the protrusions 110 of the fin structure 100 protrude from the upper surface 121 of the body portion 120 . In some embodiments, protrusions 110 extend upwardly along sidewalls 301 of trench 30 . In some embodiments, protrusion 110 includes a plurality of bevels (eg, bevels 111, 112, and 113). In some embodiments, the slope 111 of the protrusion 110 is connected to the upper surface 121 of the body portion 120 . In some embodiments, the bevel 112 of the protrusion 110 is connected to the bevel 122 of the body portion 120 . In some embodiments, the bevel 113 of the protrusion 110 is connected to the bevel 123 of the body portion 120 . In some embodiments, protrusion 110 may be tapered, or may include a tapered portion. In some embodiments, protrusion 110 is tapered or has a tapered shape.

In some embodiments, protrusion 110 has thickness T3. The thickness T3 of the protrusion 110 may be defined by the vertical distance between the bottommost surface and the topmost surface or endpoints of the protrusion 110 . The bottommost surface of the protrusion 110 may be at the same height as the upper surface 121 of the body portion 120 . In some embodiments, the thickness T3 of the protrusion 110 is from about 5 nanometers to about 50 nanometers. In some embodiments, the sudden A ratio (T3/T2) of the thickness T3 of the groove 30 to the distance T2 between the opening of the trench 30 and the upper surface 121 of the body portion 120 is equal to or less than about 0.5. In some embodiments, the ratio of the thickness T3 of the protrusion 110 to the distance T2 between the opening of the trench 30 and the upper surface 121 of the body portion 120 (T3/T2) is equal to or less than about 0.4. In some embodiments, the ratio of the thickness T3 of the protrusion 110 to the distance T2 between the opening of the trench 30 and the upper surface 121 of the body portion 120 (T3/T2) is equal to or less than about 0.3.

In some embodiments, the protrusions 130 of the fin structure 100 protrude from the upper surface 121 of the body portion 120 . In some embodiments, protrusions 130 extend upwardly along sidewalls 302 of trench 30 . In some embodiments, protrusion 130 includes a plurality of bevels (eg, bevels 131, 132, and 133). In some embodiments, the bevel 131 of the protrusion 130 faces the bevel 111 of the protrusion 110 . In some embodiments, the slope 131 of the protrusion 130 is connected to the upper surface 121 of the body portion 120 . In some embodiments, the bevel 132 of the protrusion 130 is connected to the bevel 122 of the body portion 120 . In some embodiments, the bevel 133 of the protrusion 130 is connected to the bevel 123 of the body portion 120 . In some embodiments, protrusion 130 may be tapered, or may include a tapered portion. In some embodiments, protrusion 130 is tapered or has a tapered shape.

In some embodiments, protrusion 130 has thickness T5. The thickness T5 of the protrusion 130 may be defined by the vertical distance between the bottommost surface and the topmost surface or endpoints of the protrusion 130 . The bottommost surface of the protrusion 130 may be at the same height as the upper surface 121 of the main body portion 120 . In some embodiments, the thickness T5 of the protrusions 130 is from about 5 nanometers to about 50 nanometers. In some embodiments, the ratio of the thickness T5 of the protrusion 130 to the distance T2 between the opening of the trench 30 and the upper surface 121 of the body portion 120 (T5/T2) is equal to or less than about 0.5. In some embodiments, the ratio of the thickness T5 of the protrusion 130 to the distance T2 between the opening of the trench 30 and the upper surface 121 of the body portion 120 (T5/T2) is equal to or less than about 0.4. In some embodiments, the thickness T5 of the protrusion 130 is consistent with the opening of the trench 30 The ratio (T5/T2) of the distance T2 to the upper surface 121 of the main body portion 120 is equal to or less than about 0.3.

In some embodiments, protrusions 110 and 130 are located on opposite sides of upper surface 121 of body portion 120 . In some embodiments, protrusions 110 and 130 protrude in the same direction or orientation (eg, Z-axis). In some embodiments, the bevel 112 of the protrusion 110, the bevel 132 of the protrusion 130, and the bevel 122 of the body portion 120 form a continuous plane or surface. In some embodiments, the bevel 113 of the protrusion 110, the bevel 133 of the protrusion 130, and the bevel 123 of the body portion 120 form a continuous plane or surface.

The conductive element 40 may be disposed on the protrusion 110 of the fin structure 100 in the trench 30 . In some embodiments, conductive elements 40 are disposed on protrusions 110 and 130 of fin structure 100 in trench 30 . In some embodiments, conductive element 40 is disposed on body portion 120 and protrusions 110 and 130 of fin structure 100 in trench 30 . In some embodiments, conductive elements 40 are conformally formed on bevels of protrusion 110 (eg, bevels 111, 112, and 113). In some embodiments, conductive element 40 completely covers the bevels of protrusion 110 (eg, bevels 111, 112, and 113). In some embodiments, conductive elements 40 are conformally formed on bevels of protrusion 130 (eg, bevels 131, 132, and 133). In some embodiments, conductive element 40 completely covers the bevels of protrusion 130 (eg, bevels 131, 132, and 133). In some embodiments, conductive elements 40 are conformally formed on slopes of body portion 120 (eg, slopes 122 and 123). In some embodiments, conductive element 40 includes a conductive material, such as doped polysilicon, a metal, or a metal silicide. The metal may be, for example, aluminum, copper, tungsten, cobalt or alloys thereof. The metal silicide may be, for example, nickel silicide, platinum silicide, titanium silicide, molybdenum silicide, cobalt silicide, tantalum silicide, tungsten silicide, or the like. In some embodiments, conductive element 40 may be or include a word line.

The dielectric layer 50 may be disposed on the conductive element 40 and the protrusion 110 of the fin structure 100 between. In some embodiments, dielectric layer 50 is disposed between conductive element 40 in trench 30 and protrusions 110 and 130 of fin structure 100 . In some embodiments, dielectric layer 50 is disposed between conductive element 40 in trench 30 and body portion 120 and protrusions 110 and 130 of fin structure 100 . In some embodiments, dielectric layer 50 is conformally formed on the slopes of protrusion 110 (eg, slopes 111, 112, and 113). In some embodiments, dielectric layer 50 completely covers the bevels of protrusion 110 (eg, bevels 111, 112, and 113). In some embodiments, dielectric layer 50 is conformally formed on bevels of protrusion 130 (eg, bevels 131, 132, and 133). In some embodiments, dielectric layer 50 completely covers the bevels of protrusion 130 (eg, bevels 131, 132, and 133). In some embodiments, dielectric layer 50 is conformally formed on bevels of body portion 120 (eg, bevels 122 and 123). In some embodiments, the fabrication technology of the dielectric layer 50 may be or include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, fluorine-doped silicate, or a high K material etc. In some embodiments, the manufacturing technology of the dielectric layer 50 may be or include barium strontium titanate, lead zirconate titanate, titanium oxide, aluminum oxide, hafnium oxide, yttrium oxide, zirconium oxide, etc. In some embodiments, dielectric layer 50 may be or include a word line insulation layer.

In some embodiments, in the design of the fin structure 100 , the subthreshold swing of the cell transistor in the semiconductor structure 1 can be reduced by about 10 mV/dec to about 20 mV/dec. In some embodiments, in the design of the fin structure 100 , the subcritical swing of the unit transistor in the semiconductor structure 1 can be reduced by about 10% to about 20%. In some embodiments, in the design of the fin structure 100 , the threshold voltage of the unit transistor in the semiconductor structure 1 can be reduced by about 20 millivolts (mV). Therefore, the gate control of the unit transistor in the semiconductor structure 1 can be increased, the channel formation time can be reduced, and therefore the switching speed of the unit transistor in the semiconductor structure 1 can be increased. Furthermore, current leakage can be reduced or prevented, and therefore the electrical performance of the semiconductor structure 1 can be improved.

According to some embodiments of the present disclosure, in the design of the fin structure 100 , a protrusion 110 extending upward along the sidewall 301 of the trench 30 is included. The protrusion 110 can provide an extension of the fin structure 100 , which can be further covered by the conductive element 40 . Since the electric field is relatively high near the sidewall 301 of the trench 30 (ie, the location of the doped region or the source/drain region of the unit transistor), the protrusion 110 covered by the conductive element 40 can increase the area covered by the conductive element 40 (i.e. gate control area). Thus, additional gate control areas can be created and gate control of the semiconductor structure (ie, transistor) channel can be improved.

In addition, if the upper surface 121 of the main body portion 120 of the fin structure 100 is too small, the space for filling the conductive element 40 in the trench 30 and contacting the fin structure 100 may be relatively insufficient, and therefore the resistance of the conductive element 40 may not be sufficient. increase predictably. In contrast, according to some embodiments of the present disclosure, at the above-mentioned ratio (W2/W1) of the width W2 of the upper surface 121 of the body portion 120 to the width W1 of the trench 30, for example, at least equal to or exceeding about 0.5, the formed conductive Element 40 may be of sufficient volume and width. Therefore, the resistance of the conductive element 40 does not increase unintentionally, and the conductivity of the conductive element 40 can be protected from adverse effects.

2A, 2B, 3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7A, 7B, 7A and 8B illustrate semiconductor structures according to some embodiments of the present disclosure. Various stages of the preparation method of 1.

2A and 2B illustrate one stage of a method of manufacturing the semiconductor structure 1 according to some embodiments of the present disclosure. In some embodiments, Figure 2B is a cross-sectional view along line 2B-2B' in Figure 2A.

A semiconductor substrate 10 having an active region 10A may be provided. The fabrication technology of semiconductor substrate 10 may be, for example, silicon, doped silicon, silicon germanium, silicon on insulator, silicon on sapphire, silicon germanium on insulator, silicon carbide, germanium, gallium arsenide, gallium phosphide, arsenic Gallium Phosphide, Indium phosphide, gallium indium phosphide, or any other Group IV-IV, Group III-V or Group I-VI semiconductor material.

A photolithography process may be performed to pattern the semiconductor substrate 10 to define the positions of a plurality of active regions 10A. After the lithography process, an etching process may be performed to form a plurality of trenches in the semiconductor substrate 10 .

3A and 3B illustrate one stage of a method of manufacturing the semiconductor structure 1 according to some embodiments of the present disclosure. In some embodiments, Figure 3B is a cross-sectional view along line 3B-3B' in Figure 3A.

An isolation structure 20 may be formed in the semiconductor substrate 10 , and the plurality of active regions 10A of the semiconductor substrate 10 may be defined by the isolation structure 20 .

After etching to form a plurality of trenches in the semiconductor substrate 10 , an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or fluorine-doped silicate, may be used to fill the portions of the semiconductor substrate 10 through a deposition process. Plural grooves. After the deposition process, a planarization process, such as chemical mechanical polishing, may be performed to remove excess material and provide a substantially planar surface for subsequent process steps, and to conformally form the isolation structure 20 and the plurality of active regions. 10A.

4A and 4B illustrate one stage of a method of manufacturing the semiconductor structure 1 according to some embodiments of the present disclosure. In some embodiments, Figure 4B is a cross-sectional view along line 4B-4B' in Figure 4A.

A patterned photoresist layer PR may be provided on the isolation structure 20 and the active region 10A of the semiconductor substrate 10 . A photoresist layer may be coated on the isolation structure 20 and the active area 10A of the semiconductor substrate 10 , and then the photoresist layer may be exposed and developed to form a patterned photoresist layer PR having a plurality of openings to expose the semiconductor substrate 10 part of the isolation structure 20 and the active area 10A. The patterned photoresist layer PR may have a predetermined pattern for forming trenches (eg, trenches 30 discussed below) through the active region 10A and the isolation structure 20 . Opening of patterned photoresist layer PR The ports correspond to locations where trenches (eg, trench 30 discussed below) are subsequently formed through active region 10A and isolation structure 20 .

5A and 5B illustrate one stage of a method of manufacturing the semiconductor structure 1 according to some embodiments of the present disclosure. In some embodiments, Figure 5B is a cross-sectional view along line 5B-5B' in Figure 5A. It should be noted that the patterned photoresist layer PR is omitted from Figure 5A for clarity.

In some embodiments, a portion of active region 10A of semiconductor substrate 10 is removed to form trench 30A and initial fin structure 100A in trench 30A. In some embodiments, the active region 10A and the isolation structure 20 are etched through the openings of the patterned photoresist layer PR to form one or more trenches 30A penetrating the active region 10A and the isolation structure 20 . In some embodiments, an anisotropic etching operation may be performed to form trench 30A and initial fin structure 100A therein. In some embodiments, a reactive ion etching (RIE) process is used to perform anisotropic dry etching on the active region 10A of the semiconductor substrate 10 to form the trench 30A and the initial fin structure 100A in the trench 30A.

In some embodiments, initial fin structure 100A has a planar upper surface 100A1. In some embodiments, initial fin structure 100A has one or more sides (eg, side 100A2) that are substantially perpendicular to upper surface 100A1 of initial fin structure 100A.

In some embodiments, trench 30A further passes through isolation structure 20 . In some embodiments, the opening of the trench 30A is spaced apart from the upper surface 100A1 of the initial fin structure 100A by a certain distance T6. In some embodiments, the distance T6 is about 5 nanometers to about 50 nanometers.

6A and 6B illustrate one stage of a method of manufacturing the semiconductor structure 1 according to some embodiments of the present disclosure. In some embodiments, Figure 6B is a cross-sectional view along line 6B-6B' in Figure 6A. It should be noted that the patterned photoresist layer PR is omitted from FIG. 6A for clarity.

In some embodiments, a portion of initial fin structure 100A is removed to form fin structure 100 in trench 30 . In some embodiments, shaped fin structure 100 includes body portion 120 and protrusions 110 and 130 . In some embodiments, an isotropic etching operation may be performed to form the fin structure 100 .

In some embodiments, a dry etching process or a wet etching process is used to perform an isotropic etching on the initial fin structure 100A to form the fin structure 100 in the trench 30 . In some embodiments, the isotropic etching operation has a relatively high etching selectivity between the semiconductor substrate 10 and the isolation structure 20 , so the isolation structure 20 is only slightly etched during the isotropic etching operation or Not etched at all.

In some embodiments, trench 30A, initial fin structure 100A in trench 30A, and fin structure 100 in trench 30 may be formed by etching from the same patterned photoresist layer PR. In some embodiments, the isotropic etching operation is performed after an anisotropic etching operation is performed on the active region of the semiconductor substrate.

In some embodiments, fin structure 100 includes body portion 120 and protrusions 110 and 130 . In some embodiments, body portion 120 is connected to protrusions 110 and 130 .

In some embodiments, the body portion 120 of the fin structure 100 may have an upper surface 121 , a bottom surface 124 opposite the upper surface 121 , and inclined surfaces 122 , 123 . In some embodiments, the area of upper surface 121 is smaller than the area of bottom surface 124 . In some embodiments, bevel 122 of body portion 120 extends from upper surface 121 to bottom surface 124 . In some embodiments, bevel 123 of body portion 120 extends from upper surface 121 to bottom surface 124 . In some embodiments, bevel 122 of body portion 120 extends from upper surface 121 to bottom surface 303 of trench 30 . In some embodiments, bevel 123 of body portion 120 extends from upper surface 121 to bottom surface 303 of trench 30 .

In some embodiments, trench 30 further passes through isolation structure 20 . In some implementations In this example, a portion of the isolation structure 20 is in the trench 30 and has an upper surface 201 , and the slope 122 of the main body portion 120 extends from the upper surface 121 of the main body portion 120 to the upper surface 201 of the isolation structure 20 in the trench 30 . In some embodiments, the bevel 123 of the body portion 120 extends from the upper surface 121 of the body portion 120 to the upper surface 201 of the isolation structure 20 in the trench 30 .

In some embodiments, the protrusions 110 of the fin structure 100 protrude from the upper surface 121 of the body portion 120 . In some embodiments, protrusions 110 extend upwardly along sidewalls 301 of trench 30 . In some embodiments, protrusion 110 includes a plurality of bevels (eg, bevels 111, 112, and 113). In some embodiments, the slope 111 of the protrusion 110 is connected to the upper surface 121 of the body portion 120 . In some embodiments, the bevel 112 of the protrusion 110 is connected to the bevel 122 of the body portion 120 . In some embodiments, the bevel 113 of the protrusion 110 is connected to the bevel 123 of the body portion 120 . In some embodiments, protrusion 110 may be tapered, or may include a tapered portion. In some embodiments, protrusion 110 has a tapered shape.

In some embodiments, the protrusions 130 of the fin structure 100 protrude from the upper surface 121 of the body portion 120 . In some embodiments, protrusions 130 extend upwardly along sidewalls 302 of trench 30 . In some embodiments, protrusion 130 includes a plurality of bevels (eg, bevels 131, 132, and 133). In some embodiments, the bevel 131 of the protrusion 130 faces the bevel 111 of the protrusion 110 . In some embodiments, the slope 131 of the protrusion 130 is connected to the upper surface 121 of the body portion 120 . In some embodiments, the bevel 132 of the protrusion 130 is connected to the bevel 122 of the body portion 120 . In some embodiments, the bevel 133 of the protrusion 130 is connected to the bevel 123 of the body portion 120 . In some embodiments, protrusion 130 may be tapered, or may include a tapered portion. In some embodiments, protrusion 130 has a tapered shape.

In some embodiments, protrusions 110 and 130 are located on opposite sides of upper surface 121 of body portion 120 . In some embodiments, protrusions 110 and 130 are in the same direction or Orientation (e.g. Z-axis) protrudes. In some embodiments, the bevel 112 of the protrusion 110, the bevel 132 of the protrusion 130, and the bevel 122 of the body portion 120 form a continuous plane or surface. In some embodiments, the bevel 113 of the protrusion 110, the bevel 133 of the protrusion 130, and the bevel 123 of the body portion 120 form a continuous plane or surface.

7A and 7B illustrate one stage of a method of manufacturing the semiconductor structure 1 according to some embodiments of the present disclosure. In some embodiments, Figure 7B is a cross-sectional view along line 7B-7B' in Figure 7A. It should be noted that the patterned photoresist layer PR is omitted from Figure 7A for clarity.

In some embodiments, dielectric layer 50 is conformally formed on fin structure 100 and sidewalls 301 and 302 of trench 30 .

In some embodiments, dielectric layer 50 is deposited on fin structure 100 . In some embodiments, dielectric layer 50 is deposited on fin structure 100 using a CVD process, an ALD process, or a similar process. In some embodiments, the dielectric layer 50 deposited on the topmost surface of the patterned photoresist layer PR can be removed using, for example, an etching process, while the dielectric layer 50 deposited on the sidewalls 301 and 302 of the trench 30 is removed. Stay where you are. In some other embodiments, a thermal oxidation process may be used to grow the dielectric layer 50 on the exposed portions of the substrate 10 (ie, the sidewalls 301 and 302 of the trench 30).

In some embodiments, the manufacturing technology of the dielectric layer 50 may be or include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, fluorine-doped silicate, or a high-K material. In some embodiments, the manufacturing technology of the dielectric layer 50 may be or include barium strontium titanate, lead zirconate titanate, titanium oxide, aluminum oxide, hafnium oxide, yttrium oxide, zirconium oxide, etc.

8A and 8B illustrate one stage of a method of manufacturing the semiconductor structure 1 according to some embodiments of the present disclosure. In some embodiments, Figure 8B is a cross-sectional view along line 8B-8B' in Figure 8A.

In some embodiments, conductive elements 40 are conformally formed on fin structure 100 on the body portion 120 and the protrusions 110 and 130 as well as the side walls 301 and 302 of the groove 30 . In some embodiments, conductive element 40 is conformally formed on dielectric layer 50 of trench 30 .

In some embodiments, conductive element 40 is deposited on dielectric layer 50 . In some embodiments, conductive element 40 is formed on dielectric layer 50 using CVD, PVD, or ALD. In some embodiments, the patterned photoresist layer PR is removed. In some embodiments, the patterned photoresist layer PR is removed by an ashing or stripping process.

In some embodiments, conductive element 40 includes a conductive material, such as doped polysilicon, a metal, or a metal silicide. The metal may be, for example, aluminum, copper, tungsten, cobalt or alloys thereof. The metal silicide may be, for example, nickel silicide, platinum silicide, titanium silicide, molybdenum silicide, cobalt silicide, tantalum silicide, tungsten silicide, or similar materials.

FIG. 9 is a flowchart illustrating a method 90 for fabricating a semiconductor structure according to some embodiments of the present disclosure.

The preparation method 90 begins with operation S91, in which a semiconductor substrate having an active region is provided.

The preparation method 90 continues with operation S92, in which a portion of the active region of the semiconductor substrate is removed to form a trench and an initial fin structure in the trench.

The manufacturing method 90 continues with operation S93, where a portion of the initial fin structure is removed to form a fin structure. The fin structure includes a first protrusion extending upward along a first side wall of the trench.

The preparation method 90 is only an example and is not intended to limit the content of the present disclosure beyond the scope explicitly mentioned in the patent application. Additional operations may be provided before, during, or after each operation of the preparation method 90, and some of the operations described may be replaced, eliminated, or moved for additional embodiments of the preparation method. In some embodiments, preparation methods 90 may also include operations not depicted in FIG. 9 . In some embodiments, the preparation method may 90 include one or more of the operations depicted in FIG. 9 .

An embodiment of the present disclosure provides a semiconductor structure including a semiconductor substrate. The semiconductor substrate has an active region defined by an isolation structure. A trench passes through the active region and the isolation structure. The active region of the semiconductor substrate includes a fin structure in the trench. The fin structure includes a first protrusion extending upward along a first side wall of the trench.

Another embodiment of the present disclosure provides a semiconductor structure including a semiconductor substrate and a conductive element. The semiconductor substrate has an active region including a fin structure. The fin structure includes a main body part and a first tapered part. The first tapered portion protrudes from an upper surface of the main body portion. The conductive element is provided on the body portion and the first tapered portion of the fin structure.

Another embodiment of the present disclosure provides a method of manufacturing a semiconductor structure. The preparation method includes providing a semiconductor substrate with an active region. The preparation method also includes removing a portion of the active region of the semiconductor substrate to form a trench and an initial fin structure. The preparation method also includes removing a portion of the initial fin structure to form a fin structure, the fin structure including a first protrusion extending upward along a first side wall of the trench.

When designing a fin structure that includes a protrusion extending upwardly along the trench sidewalls, the protrusion can provide an extension of the fin structure that can be further covered by a conductive element. Since the electric field is relatively high near the trench sidewalls (i.e., the doped region or the source/drain region of the unit transistor), the protrusions covered by the conductive element can increase the coverage of the conductive element (i.e., the gate control region) area. Thus, additional gate control areas can be created and gate control of the semiconductor structure (ie, transistor) channel can be improved.

Although the present disclosure and its advantages have been described in detail, it should be understood that other variations may be made transformation, replacement and substitution without departing from the spirit and scope of the present disclosure as defined by the scope of the disclosure patent. For example, many of the processes described above may be implemented in different ways and replaced with other processes or combinations thereof.

Furthermore, the scope of the present disclosure is not limited to the specific embodiments of the process, machinery, manufacture, compositions of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure of this disclosure that they can use existing or future processes, machinery, manufacturing, etc. that have the same functions or achieve substantially the same results as the corresponding embodiments described herein in accordance with the present disclosure. A material composition, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patent scope of the present disclosure.

1D: Part

10A: Active area

30:Trench

100: Fin structure

110:Protrusion

111: Incline

112: Incline

113: Incline

120: Main part

121: Upper surface

122: Incline

123: Incline

124: Bottom

130:Protrusion

131: Incline

132: Incline

133: Incline

201: Upper surface

301:Side wall

302:Side wall

T1: Depth

T2: distance

T3:Thickness

T4:Thickness

T5:Thickness

W1: Width

W2: Width

W3: length

W4: length

X: direction

Y: direction

Z: direction

Claims (20)

A semiconductor structure, including: a semiconductor substrate having an active region defined by an isolation structure, and a trench passing through the active region and the isolation structure; wherein the active region of the semiconductor substrate includes in the trench A fin structure, and the fin structure includes a first protrusion extending upward along a first side wall of the trench. The semiconductor structure of claim 1, wherein the fin structure further includes: a main body portion connected to the first protrusion, and the first protrusion protrudes from an upper surface of the main body portion. The semiconductor structure of claim 2, wherein the main body portion has a bottom surface opposite to the upper surface, and an area of the upper surface is smaller than an area of the bottom surface. The semiconductor structure of claim 2, wherein the body portion has a slope extending from the upper surface to a bottom surface of the trench. The semiconductor structure of claim 4, wherein the first protrusion has a first slope connected to the upper surface of the body part, and a second slope connected to the slope of the body part. The semiconductor structure of claim 2, wherein the trench has a first width, the upper surface of the main body portion has a second width along the first direction, and a ratio of the second width to the first width is equal to or exceeds about 0.5. The semiconductor structure of claim 1, wherein the first protrusion of the fin structure has a tapered shape. The semiconductor structure of claim 1, wherein the fin structure further includes: a second protrusion extending along a second sidewall opposite to the first sidewall of the trench. The semiconductor structure of claim 1, further comprising: a conductive element disposed on the first protrusion of the fin structure in the trench. The semiconductor structure of claim 9, further comprising: a dielectric layer disposed between the conductive element and the first protrusion of the fin structure. A method for preparing a semiconductor structure, including: providing a semiconductor substrate having an active region; removing a portion of the active region of the semiconductor substrate to form a trench and an initial fin structure in the trench; and removing the A portion of the initial fin structure is formed to form a fin structure including a first protrusion extending upward along a first side wall of the trench. The preparation method according to claim 11, wherein the trench and the initial The fin structure and the formation of the fin structure are performed by etching from the same patterned photoresist layer. The preparation method of claim 11, wherein forming the trench and the initial fin structure in the trench is performed by an anisotropic etching operation. The manufacturing method of claim 13, further comprising: forming an isolation structure defining the active region, wherein the trench further passes through the isolation structure. The preparation method of claim 11, wherein forming the fin structure including the first protrusion extending upward along the first side wall of the trench is performed by an isotropic etching operation. . The preparation method of claim 15, further comprising: forming an isolation structure defining the active region, wherein the trench further passes through the isolation structure, and the fin structure has a slope extending from an upper surface to the An upper surface of the isolation structure in the trench. The preparation method of claim 11, wherein forming the initial fin structure includes performing an anisotropic etching operation on the active region of the semiconductor substrate, and forming the fin structure includes performing the anisotropic etching operation. After the etching operation, an isotropic etching operation is performed on the active region of the semiconductor substrate. The manufacturing method of claim 11, further comprising: conformally forming a conductive element on the first protrusion of the fin structure and the first side wall of the trench. The preparation method of claim 11, further comprising: conformally forming a dielectric layer on the fin structure and the first sidewall of the trench. The preparation method of claim 19, further comprising: conformally forming a conductive element on the dielectric layer in the trench.