TWI817243B - Arrayed switch circuitry and switching circuit - Google Patents

Abstract

An arrayed switch circuitry includes contact units each of which includes a pad, a first row channel, a first column channel, a connecting channel, a second row channel and a second column channel. The first row channel is provided with a first switching element. The first column channel is connected to the first row channel, and provided with a second switching element. The connecting channel connects the pad to the first row channel or the first column channel. The second row channel is connected with the pad through a third switching element. The second column channel is connected with the pad through a fourth switching element. The first row channels of the contact units with the same row position are connected to each other, and the second row channels of the contact units with the same row position are connected to each other. The first column channels of the contact units with the same column position are connected to each other, and the second column channels of the contact units with the same column position are connected to each other.

Description

Array switching circuit system and switching circuit

The present invention relates to an array switch circuit system, and in particular to an array switch circuit system that can be applied to system packaging.

System packaging is to package multiple chips together into an integrated circuit (IC). In today's system packaging, the connection between chips and the connection of the input/output pins of the package are wound through the wire redistribution layer (RDL). When the RDL winding design is completed, It is handed over to the packaging factory for manufacturing and packaging. After packaging, it is handed over to the testing factory for integrated circuit testing. Since all wire redistribution layers are customized by the packaging factory, it is only after the packaged integrated circuit is tested by the test factory that it is discovered that the winding of the wire redistribution layer needs to be modified, or the chip in the integrated circuit needs to be replaced. , the wire redistribution layer must be redesigned, which increases product development time and cost. In addition, if there are products with low production demand, packaging factories will be less willing to accept orders.

In view of the above, the present invention provides an array switch circuit system and a switch circuit, which can be applied to system packaging. By controlling the switching elements in the array switch circuit system, different winding combinations can be formed with the wire redistribution layer, so that the wire redistribution layer Customization is no longer required, and the need to redesign the wire redistribution layer during the R&D process can be avoided, thereby shortening product R&D time and reducing R&D costs.

An array switch circuit system according to an embodiment of the present invention includes a plurality of contact units arranged in an array, wherein each contact unit includes a conductive pad, a first column channel, a first row channel, a connecting channel, and a second column channel. and the second row of passages. The first column of channels is provided with first switching elements. The first row channel is connected to the first column channel and is provided with a second switching element. The connecting channel connects the conductive pad to the first column channel or the first row channel. The second column of channels is connected to the conductive pad through the third switching element. The second row of channels is connected to the conductive pad through the fourth switching element. wherein the first column channels of each of the plurality of contact units having the same column position are connected to each other, and the second column channels of each of the plurality of contact units having the same column position are connected to each other, The first row channels of each of the plurality of contact units having the same row position are connected to each other, and the second row channels of each of the plurality of contact units having the same row position are connected to each other.

A switch circuit according to an embodiment of the present invention includes a transmission gate and a base voltage control subcircuit. The transmission gate has an input end, an output end, a two-gate control end and a two-base control end, and is used to make the input end and the output end conductive or cut off each other according to the voltage of the two gate control ends. The base voltage control subcircuit is connected to the input terminal and the base control terminal of the transmission gate, and is used to adjust the voltage of the base control terminal according to the voltage of the input terminal when the input terminal and the output terminal are turned on, so that the input terminal and the base terminal are connected. The voltage difference between the pole control terminals is less than a preset value.

Through the above structure, the array switch circuit system disclosed by the present invention integrates two architectures, the checkerboard type and the high-speed channel type, and can select a better signal transmission path according to the signal characteristics, and can be equipped with a single wire circuit design in the system package. The wire redistribution layer provides a variety of winding combinations, thereby shortening product development time and reducing research and development costs. In addition, the switch circuit disclosed in the present invention has a sub-circuit that dynamically tracks the input signal voltage to control the base voltage, and can have a wider channel bandwidth than the traditional transmission gate switch.

The above description of the present disclosure and the following description of the embodiments are used to demonstrate and explain the spirit and principles of the present invention, and to provide further explanation of the patent application scope of the present invention.

A: System packaging

A1: Wire redistribution layer

A2: Straight through mold hole layer

A3: Silicon through hole layer

C1: First chip

C2: Second chip

C3: Connect chip

C11, C12, C21, C22: Pins

P: position

TMV: through die hole

TSV: Through silicon

SB: solder ball

1, 1’, 1”, 3: Array switch circuit system

11, 11’, 11”: contact unit

111, 111a~111d: conductive pad

131: The first column of channels

133: First switching element

135:Connection channel

151: First row of channels

153: Second switching element

171:Second column channel

173: The third switching element

191:Second row channel

193: The fourth switching element

132:The third column channel

134:Fifth switching element

137: Connect switch components

152:Third row channel

154:Sixth switching element

172:The fourth column channel

174:Seventh switching element

192:Fourth row channel

194: The eighth switching element

133a, 134a, 137a, 193a, 193c, 137d, 154d: switching elements

10:Array area

20a~20d: extended pin area

31: Switch array

33: Switch control circuit

35:Memory

37:Microcontroller

39: Pre-write circuit

6: Some areas

211:Extended conductive pad

213:Switch group

500: switch circuit

501: First transmission gate

503: Base voltage control subcircuit

P1: first input terminal

P2: first output terminal

P3, P4: first gate control terminal

P5, P6: base control terminal

SW:Control terminal

M1~M8: Transistor

Vdd: working voltage

FIG. 1 is a schematic structural diagram of a system package according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of an array switch circuit system according to an embodiment of the present invention.

FIG. 3A is a schematic diagram of a contact unit in an array switch circuit system according to another embodiment of the present invention.

FIG. 3B is a schematic diagram of a contact unit in an array switch circuit system according to another embodiment of the present invention.

FIG. 4 is a schematic diagram of an array switch circuit system formed by the contact units shown in FIG. 3B.

FIG. 5 is a schematic diagram of an array switch circuit system according to yet another embodiment of the present invention.

FIG. 6 is a schematic diagram of a partial area of the array switch circuit system shown in FIG. 5 .

FIG. 7 is a functional block diagram of an array switch circuit system according to another embodiment of the present invention.

FIG. 8 is a schematic diagram of a switching circuit according to an embodiment of the present invention.

FIG. 9 is a circuit diagram of a switch circuit according to an embodiment of the present invention.

The detailed features and advantages of the present invention are described in detail below in the implementation mode. The content is sufficient to enable anyone skilled in the relevant art to understand the technical content of the present invention and implement it according to the content disclosed in this specification, the patent scope and the drawings. , anyone familiar with the relevant art can easily understand the present invention Explain the relevant purposes and advantages. The following examples further illustrate the aspects of the present invention in detail, but do not limit the scope of the present invention in any way.

Please refer to FIG. 1 , which is a schematic structural diagram of a system package A according to an embodiment of the present invention. As shown in Figure 1, system package A includes a first chip C1, a second chip C2, a wire redistribution layer (RDL) A1, a connection chip C3, a through-die hole layer A2, a silicon through-hole layer A3 and a plurality of solder joints. A ball grid array (BGA) package formed by balls SB, in which the connection chip C3 and the through-hole layer A2 are disposed between the wire redistribution layer A1 and the silicon through hole layer A3, the first chip C1 and the second The chip C2 is disposed on the opposite surface of the surface where the wire redistribution layer A1 connects the chip C3 and the through-die hole layer A2, and the solder ball SB is disposed on the opposite surface of the silicon via layer A3 where the chip C3 and the through-die hole layer A2 are arranged. .

The first chip C1 has a plurality of pins C11 and C12, and the second chip C2 has a plurality of pins C21 and C22. The conductor redistribution layer A1 may include multiple conductor lines that are not connected to each other. The connection chip C3 includes an array switch circuit system. The array switch circuit system includes a plurality of conductive pads and a plurality of switching elements. The switching elements can be controlled to conduct channels between different conductive pad combinations. That is to say, the connection chip C3 can The program connects to the chip. The detailed architecture of the array switch circuit system connected to chip C3 will be described later. The through-die hole layer A2 includes a plurality of through-die holes TMV. The silicon via layer A3 includes a plurality of silicon via TSVs. The pins C11 and C12 of the first chip C1 and the pins C21 and C22 of the second chip C2 can be respectively connected to the conductive pads connecting different positions P of the chip C3 through a plurality of wire lines of the wire redistribution layer A1. The switching element connected to the chip C3 is controlled to connect the conductive pad connected to the pin C11 and the conductive pad connected to the pin C21, and to connect the conductive pad connected to the pin C12 to another wire connected to the wire redistribution layer A1. The conductive pad of the circuit (the first conductor circuit) is electrically connected to the conductive pad connected to the pin C22 and the conductive pad connected to another conductor circuit (the second conductor circuit) in the conductor redistribution layer A1. The first and second conductive lines are respectively connected to the solder balls SB through the through-die holes TMV in the through-die hole layer A2 and the silicon through-holes TSV in the silicon through-hole layer A3.

The conductive path shown in Figure 1 is only an example. The switching elements in the connection chip C3 can also be controlled to conduct channels between different conductive pads, and can be used with the wire redistribution layer A1 to provide other winding combinations. In other words, the wire redistribution layer of a single circuit design and the connection chip can provide a variety of winding combinations. In this way, for different chip system packages, there is no need to design wire redistribution layers with different wire lines, thereby shortening product development time and reducing research and development costs. In addition, the number of chip pins, the number of wire lines, and the number of through holes shown in FIG. 1 are only examples and are not limited by the present invention.

Various embodiments of the architecture of the array switch circuit system connected to chip C3 will be described below. Please refer to FIG. 2 , which is a schematic diagram of an array switch circuit system 1 according to an embodiment of the present invention. As shown in Figure 2, the array switch circuit system 1 includes a plurality of contact units 11 arranged in an array. Each contact unit 11 includes a conductive pad 111, a first column channel 131, a first row channel 151, a connecting channel 135, The second column channel 171 and the second row channel 191, wherein the plurality of channels can be implemented by wires.

The first column channel 131 is provided with a first switching element 133 . The first row channel 151 is connected to the first column channel 131 and is provided with a second switch element 153 . The connecting channel 135 connects the conductive pad 111 to the first column channel 131 or the first row channel 151. FIG. 2 takes the connection to the first column channel 131 as an example. The second column channel 171 is connected to the conductive pad 111 through the third switch element 173 . The second row channel 191 is connected to the conductive pad 111 through the fourth switch element 193 . In the array, each contact unit 11 has a column position and a row position, wherein the first column channels 131 of the contact units 11 with the same column position are connected to each other, and the second column of the contact units 11 with the same column position are connected to each other. The channels 171 are connected to each other, the first row channels 151 of the contact units 11 with the same row position are connected to each other, and the second row channels 191 of the contact units 11 with the same row position are connected to each other.

In particular, the first column channel 131, the first switching element 133, the first row channel 151, the second switching element 153 and the connecting channel 135 of the contact unit 11 can jointly form a chessboard structure, and the third The two column channels 171, the third switching element 173, the second row channel 191 and the fourth switching element 193 can jointly form a high-speed channel structure. Among them, the checkerboard architecture is suitable for the transmission of general signals, while the high-speed channel architecture is suitable for signal transmission between contact units 11 that are far apart (for example, contact units 11 separated by more than 5) or where high-speed transmission is required. transmission of signals. In other words, the array switch circuit system 1 integrates two architectures, the checkerboard type and the high-speed channel type, and can be optimized according to the signal characteristics.

Please refer to Figures 3A and 3B. Figure 3A is a schematic diagram of the contact unit 11' in the array switch circuit system according to another embodiment of the present invention. Figure 3B is a schematic diagram of the contact unit 11' in the array switch circuit system according to another embodiment of the present invention. A schematic diagram of the contact unit 11" in the array switch circuit system. As shown in Figures 3A and 3B, the contact unit 11'/11" except the conductive pad 111, the first column channel 131, the first row shown in Figure 2 In addition to the channel 151, the connecting channel 135, the second column channel 171 and the second row channel 191, it also includes a third column channel 132, a third row channel 152, a fourth column channel 172 and a fourth row channel 192, wherein the Multiple channels can be implemented via wires. The third column channel 132 is provided with a fifth switching element 134 . The third row channels 152 are respectively connected to the third column channels 132, and each is provided with a sixth switching element 154. The fourth column channel 172 is connected to the conductive pad 111 through the seventh switching element 174 . The fourth row channel 192 is connected to the conductive pad 111 through the eighth switching element 194 .

3A and 3B illustrate that the first channel in the third column 132 is connected to the first column channel 131 through the connection switch element 137, and the other third column channels 132 are connected in sequence through the connection switch element 137, and in In other embodiments, the connection switch element 137 may be disposed between the third row of channels 152 and the first row of channels 151 , that is, the first channel in the third row of channels 152 is connected to the first row of channels through the connection switch element 137 channel 151, and other third row channels 152 are connected in sequence through the connecting switch element 137. In addition, it should be noted that the third column channel 132, the third row channel 152, the fourth column channel 172, the fourth row channel 192, the fifth switching element 134, and the sixth switching element 154 shown in Figures 3A and 3B , the seventh switch The number of the element 174, the eighth switching element 194 and the connecting switching element 137 is only an example, and the invention is not limited thereto.

In an array formed by a plurality of contact units 11'/11", each contact unit 11'/11" has one column position and one row position. For the contact units 11'/11" with the same column position, their first column channels 131 are connected to each other, the second column channels 171 are connected to each other, the third column channels 132 are connected to each other, and the fourth column channels 172 are connected to each other. connection. For the contact units 11'/11" with the same row position, their first row channels 151 are connected to each other, the second row channels 191 are connected to each other, the third row channels 152 are connected to each other, and the fourth row channels 192 are connected to each other.

Specifically, in the array formed by the contact units 11' in FIG. 3A, the first column channel 131, the first switching element 133, the first row channel 151, and the second switching element 153 of the contact unit 11' , the third column channel 132, the fifth switching element 134, the third row channel 152, the sixth switching element 154, the connecting channel 135 and the connecting switching element 137 can jointly form a checkerboard structure, while the second column channel 171, the third switch The element 173, the second row channel 191, the fourth switching element 193, the fourth column channel 172, the seventh switching element 174, the fourth row channel 192 and the eighth switching element 194 can jointly form a high-speed channel architecture; as shown in FIG. 3B In the array formed by the contact units 11' arranged, the composition of the checkerboard structure is the same as that of the array formed by the contact units 11' arranged in Figure 3A, while the high-speed channel structure except for the contacts in Figure 3A The high-speed channel structure of the array formed by the units 11' further includes a first column channel 131 and a connecting channel 135. The connecting channel 135 not only connects the conductive pad 111 and the first column channel 131, but also connects the first column channel. 131 and the third and seventh switching elements 173 and 174.

As mentioned above, the checkerboard structure is suitable for the transmission of general signals, while the high-speed channel structure is suitable for contact units 11'/11" that are widely spaced (for example, contact units 11'/11" spaced more than 5 times apart) The transmission of signals between devices or the transmission of signals requiring high-speed transmission. Through both the chessboard type and the high-speed channel type Through the integration of this architecture, the array switch circuit system can control the connections between contact units in any combination of signals, and can make optimal selections based on signal characteristics. In addition, the signal transmission speeds of the checkerboard architecture and the high-speed channel architecture proposed in the aforementioned embodiments of the present invention have excellent performance. Experiments were conducted with 20 contact units as the transmission distance, and experimental results were obtained that the transmission speed of the checkerboard architecture can reach 100Mb/s, while the transmission speed of the high-speed channel architecture can reach 2Gb/s.

The operation of the array switch circuit system is illustrated below. Please refer to Figure 4, which is a schematic diagram of the array switch circuit system 1' formed by the contact unit 11" shown in Figure 3B. For the array switch circuit system 1' shown in Figure 4, when the circuit design requires When the conductive pad 111a is electrically connected to the conductive pad 111b, the switching element 133a can be controlled to be turned on to conduct the channel between the conductive pad 111a and the conductive pad 111b; when the circuit design requirement is that the conductive pad 111a is electrically connected to the conductive pad 111c , the switching elements 193a and 193c can be controlled to be turned on to conduct the channel between the conductive pad 111a and the conductive pad 111c; when the circuit design requirement is that the conductive pad 111a is electrically connected to the conductive pad 111d, the switching elements 137a, 134a, 154d can be controlled and 137d are turned on to connect the channel between the conductive pad 111a and the conductive pad 111d.

Please refer to Figure 5, which is a schematic diagram of an array switch circuit system 1" according to yet another embodiment of the present invention. As shown in Figure 5, the array switch circuit system 1" includes an array area 10 and an array area 10 respectively connected to the array. The expansion pin areas 20a, 20b, 20c and 20d on the four sides of the area 10 are provided with an array of contact units, and the expansion pin areas 20a, 20b, 20c and 20d are each provided with an array of contact units. A plurality of expansion conductive pads are respectively connected to the contact unit located on the side of the array through a plurality of wires and a plurality of expansion switch elements. It should be noted here that FIG. 5 exemplarily shows that the four sides of the array area 10 are provided with extended pin areas 20a, 20b, 20c and 20d. However, in other embodiments, only one of them may be provided. Three. Further, please refer to Figure 5 and Figure 6 together. Figure 6 is a schematic diagram of a partial area 6 of the array switch circuit system 1" shown in Figure 5. As shown in Figure 6, the array area 10 is provided with the components shown in Figure 3B. indicated However, this is only an example. The array area 10 may be provided with an array composed of the contact units 11 shown in FIG. 2 or the contact units 11' shown in FIG. 3A. The extended pin area 20a and 20b are each provided with a plurality of expansion conductive pads 211 and a switch group 213 including a plurality of expansion switching elements. The expansion conductive pads 211 are connected to respective channel groups of the contact units 11" located on the sides of the array through the switch groups 213.

Taking the expansion pin area 20a as an example, the channel group is composed of column channels of the contact unit 11", that is, the aforementioned first column channel, second column channel, third column channel and fourth column channel. To expand For the pin area 20b, the channel group is composed of row channels of the contact unit 11", that is, the first row channel, the second row channel, the third row channel and the fourth row channel. The structures of the extended pin areas 20c and 20d are symmetrical to the structures of the extended pin areas 20a and 20b respectively, and will not be described again here. As mentioned above, the contact unit provided in the array area 10 can also be the contact unit 11 shown in FIG. 2. In this embodiment, the channel group connected to the expansion pin areas 20a and 20c is formed by the first column. The channel group connected to the expansion pin areas 20b and 20d is composed of a first row channel and a second row channel. That is to say, the number of extended conductive pads 211 and the number of extended switching elements in the extended pin areas 20a and 20c is the same as the number of column channels in the array area 10, and the number of extended conductive pads 211 in the extended pin areas 20b and 20d is the same as the number of column channels in the array area 10. The number and expansion switching elements are the same as the number of row channels in the array area 10 . In this way, each signal path has its own expansion pin and can be connected independently.

By extending the structure of one or more of the pin areas 20a to 20d, multiple connection chips each provided with the array switch circuit system 1" can be connected to each other to realize input/output (I/O) connections across the chips. For example, the conductive pads 211 in the extended pin area 20a of an array switch circuit system 1" can be connected to the conductive pads 211 in the extended pin area 20c of another array switch circuit system 1"; an array switch circuit system The conductive pads 211 in the extended pin area 20b of 1" can be connected to the conductive pads 211 in the extended pin area 20d of another array switch circuit system 1". In addition, through the switches in the extended pin areas 20a~20d With the setting of group 213, the combination of multiple array switch circuit systems 1" can control whether to turn on the cross-chip signal transmission function according to the needs, which has great design flexibility.

In particular, the switching elements in the array switch circuit system of any of the above embodiments can be controlled by an external control device (such as a microcontroller), or the array switch circuit system can further include a memory. Connect to the control end of each switching element. The memory is, for example, a non-volatile memory such as a read-only memory or a flash memory, which can store control signals written by an external control device (such as a microcontroller) to control the switching state of each switching element, and can Read the switching status of each switching element and record it. In one embodiment, the external control device may be included in the array switch circuit system.

Please refer to FIG. 7 , which is a functional block diagram of an array switch circuit system according to another embodiment of the present invention. As shown in Figure 7, the array switch circuit system 3 includes a switch array 31, a switch control circuit 33, a memory 35, a microcontroller 37 and a pre-writing circuit 39. The switch control circuit 33 is connected to the switch array 31, and the memory 35 It is connected to the switch control circuit 33 and the microcontroller 37, and the microcontroller 37 is not only connected to the switch control circuit 33 through the memory 35, but also connected to the switch control circuit 33 through the pre-writing circuit 39 (not through the memory 35). Furthermore, the memory 35 can be connected to the control terminals of the switching elements in the switch array 31 through the switch control circuit 33 , and the microcontroller 37 can be connected to the control terminals of the switching elements in the switch array 31 through the switch control circuit 33 . It should be noted here that FIG. 7 exemplarily uses a single line to represent the connection relationship between the elements/circuit of the array switch circuit system 3, and is not intended to limit the number of connection lines between the elements/circuit.

The switch array 31 may be an array composed of any one or more contact units described in the foregoing embodiments, or may include an array region and an extended pin region as described in the embodiment of FIG. 5 . The switch control circuit 33 can receive a control signal from the memory 35 or the microcontroller 37 and control the switch accordingly. Turn off the switching elements in array 31. For example, the switch control circuit 33 may include control components such as a D flip-flop, a decoder, and an SR flip-flop. Its circuit configuration can be designed by those with ordinary knowledge in the field of this case as required, and is not limited by the present invention. . The memory 35 may be a one-time programmable (OTP) memory or a multiple-times programmable (MTP) memory. The microcontroller 37 is used to write instructions (such as program codes) for controlling the switch array 31 into the memory 35 so that the memory 35 can control the switching state of the switching elements in the switch array 31 through the switch control circuit 33 according to the instructions. Prewrite circuit 39 may include one or more lines. In one implementation, the microcontroller 37 can use the instructions to control the switch array 31 through the pre-writing circuit 39 and the switch control circuit 33 before writing the instructions to the memory 35 and execute the communication. Test (AC testing), and after the AC test passes, the instructions are written into the memory 35 . Furthermore, the above-mentioned pre-writing operation and communication test can be executed by the operator controlling the microcontroller 37 .

In this way, for the array switch circuit system 3 using the OTP memory as the memory 35, it is possible to avoid the problem of directly writing the control instructions into the memory 35 and only discovering the error in the subsequent testing stage, so the entire system needs to be discarded. Reduce testing costs. In particular, the microcontroller 37 and the pre-writing circuit 39 can be removed from the array switch circuit system 3 after the control instructions are written into the memory 35 .

The present invention also provides a switching circuit, which has a circuit capable of controlling the base voltage, and can be applied to any switching element in the foregoing embodiments. That is to say, any switching element in the foregoing embodiments can be implemented by this switching circuit. An embodiment of this switching circuit will be described below. Please refer to FIG. 8 , which is a schematic diagram of a switching circuit according to an embodiment of the present invention. As shown in FIG. 8 , the switch circuit 500 includes a first transmission gate 501 and a base voltage control sub-circuit 503 . The first transmission gate 501 has a first input terminal P1, a first output terminal P2, two first gate control terminals P3 and P4, and two base control terminals P5 and P6, and the first transmission gate 501 is used according to the first gate control terminal. The voltage of extremely control terminals P3 and P4 makes The first input terminal P1 and the first output terminal P2 are on or off with each other. The base voltage control sub-circuit 503 is connected to the first input terminal P1 and the base control terminals P5 and P6, and is used to adjust according to the voltage of the first input terminal P1 when the first input terminal P1 and the first output terminal P2 are turned on. The voltages of the base control terminals P5 and P6 are such that the voltage difference between the first input terminal P1 and any one of the two base control terminals P5 and P6 is less than a preset value, specifically equal to 0.

To further describe the circuit architecture of the switch circuit 500, please refer to FIG. 9. FIG. 9 is a circuit diagram of an embodiment of the switch circuit 500. As shown in FIG. 9 , the switch circuit 500 includes transistors M1 ~ M8 , where the transistors M1 and M2 form a first transmission gate 501 , and the transistors M3 ~ M8 form a base voltage control sub-circuit 503 . The drain electrode of the transistor M1 and the source electrode of the transistor M2 are connected to each other to serve as the first input terminal P1. The source electrode of the transistor M1 and the drain electrode of the transistor M2 are connected to each other to serve as the first output terminal P2. The transistor M1 and The gates of M2 serve as first gate control terminals P3 and P4 respectively, and the bases of transistors M1 and M2 serve as base control terminals P5 and P6 respectively. The first gate control terminals P3 and P4 of the first transmission gate 501 can be connected to an external control circuit to be controlled by the external control circuit to control/store the switching states of the transistors M1 and M2. The external control circuit may include an inverter as shown in FIG. 9 and the aforementioned memory. The memory may be connected to the control terminal SW of the switch circuit 500 (ie, the first gate control terminal of the first transmission gate 501 P3) is used to perform writing/reading operations, that is, to control/store the switching state of the switch circuit 500, but the present invention is not limited to this. For example, when the voltage of the first gate control terminal P3 is 1.5V and the voltage of the first gate control terminal P4 is 0V, the switch circuit 500 is in the ON state; when the voltage of the first gate control terminal P3 When the voltage is 0V and the voltage of the first gate control terminal P4 is 1.5V, the switch circuit 500 is in a closed (OFF) state.

The base voltage control sub-circuit 503 includes a second transmission gate composed of transistors M3 and M4, a third transmission gate composed of transistors M5 and M6, a first transistor M7 and a second transistor M8. The second transmission gate has a second input terminal, a second output terminal and two second gate control terminals. That , the drain electrode of the transistor M3 and the source electrode of the transistor M4 are connected to each other as the second input terminal, connected to the first input terminal P1 of the first transmission gate 501; The gates of the transistors M3 and M4 are respectively used as the two second gate control terminals and are respectively connected to the first gate control terminals P3 and P4. The third transmission gate has a third input terminal, a third output terminal and two third gate control terminals. Among them, the drain electrode of the transistor M5 and the source electrode of the transistor M6 are connected to each other as the third input terminal, connected to the first input terminal P1 of the first transmission gate 501; the source electrode of the transistor M5 and the drain electrode of the transistor M6 The gates of the transistors M5 and M6 are respectively used as the two third gate control terminals and are respectively connected to the first gate control terminals P3 and P4.

The first transistor M7 has a fourth input terminal, a fourth output terminal and a fourth control terminal. Among them, the fourth input terminal is the drain of the first transistor M7, which is connected to the second output terminal of the second transmission gate and the base control terminal P5 of the first transmission gate 501; the fourth output terminal is the first transistor M7 The source electrode is used to connect to the lowest potential (ground voltage); the fourth control terminal is the gate electrode of the first transistor M7 and is connected to the first gate control terminal P4 of the first transmission gate 501 . The second transistor M8 has a fifth input terminal, a fifth output terminal and a fifth control terminal, wherein the fifth input terminal is the source of the second transistor M8 and is used to receive the highest potential (operating voltage Vdd); The output terminal is the drain of the second transistor M8, which is connected to the third output terminal of the third transmission gate and the base control terminal P6 of the first transmission gate 501; the fifth control terminal is the gate of the second transistor M8, Connected to the first gate control terminal P3 of the first transmission gate 501 .

It should be noted here that the embodiment of FIG. 9 uses an N-channel metal-oxide-semiconductor field-effect transistor (MOSFET) to implement the transistor in the base voltage control sub-circuit 503. M3, M5 and M7, and the transistors M4, M6 and M8 are implemented with P-channel MOSFETs for illustration, but the invention is not limited thereto.

Through the above circuit structure, the base voltage control sub-circuit 503 can dynamically adjust the base voltages of the two transistors of the first transmission gate 501 according to the switching state of the first transmission gate 501 . Furthermore, when the first transmission gate 501 is in the ON state, the base voltage control sub-circuit 503 synchronizes the base voltages of the transistors M1 and M2 of the first transmission gate 501 with the voltage of the input signal (less than one The default value is even equal to 0). As shown in the following transistor critical voltage formula (1), when the source voltage is higher than the base voltage and the voltage difference V _sb is a positive number, the critical voltage V _th will rise; as shown in the following transistor current formula (2) , when the critical voltage V _th rises, the drain current I _d will decrease. At this time, the drain voltage V _d remains unchanged, and the switch on-resistance R _on will rise. In other words, when a traditional transmission gate switch is turned on, due to the difference between the base voltage and the input signal voltage, there will be a problem of increased switch on-resistance.

In comparison, the switch circuit 500 of this embodiment can reduce the increase in the threshold voltage V _th or prevent the increase in the threshold voltage V _th through the above-mentioned structure of synchronizing the substrate voltage with the input signal voltage, and therefore can have a lower switch On-resistance R _on , and from the following time constant formula (3), it can be seen that when the switch on-resistance decreases, the charging and discharging speed of the transistor will speed up, thereby increasing the channel bandwidth. That is to say, the switch circuit proposed by the present invention can solve the problem of increased switch on-resistance caused by the difference between the base voltage and the input signal voltage when the traditional transmission gate switch is turned on. Therefore, it has a lower switch on-resistance, and thus Has a wider channel bandwidth.

τ= RC (3)

In addition, when the first transmission gate 501 is in the closed (OFF) state, the base voltage control sub-circuit 503 adjusts the base voltages of the transistors M1 and M2 of the first transmission gate 501 to the operating voltage and the ground voltage respectively, thereby The problem of base terminal leakage can be avoided. In addition, the area occupied by the switching circuit 500 on the circuit wiring can be similar to that of a conventional transmission gate switch. That is to say, the switch circuit 500 is superior in characteristics to the traditional transmission gate switch and has a similar area, which is advantageous in comparison.

With the above structure, the array switch circuit system disclosed by the present invention integrates two architectures: checkerboard type and high-speed channel type. It can select a better signal transmission path according to the signal characteristics, and can be applied to system packaging. By controlling the switching elements The switching status can form different winding combinations with the wire redistribution layer, so that the wire redistribution layer no longer needs to be customized, and can avoid the need to redesign the wire redistribution layer during the development process, thereby shortening product development time and Reduce R&D costs. In addition, the switch circuit disclosed in the present invention has a sub-circuit that dynamically tracks the input signal voltage to control the base voltage, and can have a wider channel bandwidth than the traditional transmission gate switch.

Although the present invention is disclosed in the foregoing embodiments, they are not intended to limit the present invention. All changes and modifications made without departing from the spirit and scope of the present invention shall fall within the scope of patent protection of the present invention. Regarding the protection scope defined by the present invention, please refer to the attached patent application scope.

1: Array switch circuit system

11:Contact unit

111:Conductive pad

131: The first column of channels

133: First switching element

135:Connection channel

151: First row of channels

153: Second switching element

171:Second column channel

173: The third switching element

191:Second row channel

193: The fourth switching element

Claims (12)

An array switch circuit system includes a plurality of contact units arranged in an array, wherein each of the contact units includes: a conductive pad; a first column channel provided with a first switching element; a first row channel, Connected to the first column channel and provided with a second switching element; a connecting channel connecting the conductive pad to the first column channel or the first row channel; a second column channel connected through a third switching element on the conductive pad; and a second row channel connected to the conductive pad through a fourth switching element; wherein the first column channels of each of the contact units having the same column position are connected to each other, and the The second column channels of each of the contact units having the same column position are connected to each other, the first row channels of each of the contact units having the same row position are connected to each other, and the contact units The second row channels in each with the same row position are connected to each other. The array switch circuit system as claimed in claim 1, wherein each of the contact units further includes: a third column channel provided with a fifth switching element; a third row channel connected to the third column channel, And there is a sixth switching element; a fourth column channel connected to the conductive pad through a seventh switching element; and a fourth row channel connected to the conductive pad through an eighth switching element; wherein the third column The channel is connected to the first row of channels through a connection switch element, or the third row of channels is connected to the first row of channels through the connection switch element; The third column channels of each of the contact units with the same column position are connected to each other, and the fourth column channels of each of the contact units with the same column position are connected to each other. The third row channels of each of the point units having the same row position are connected to each other, and the fourth row channels of each of the contact units having the same row position are connected to each other. The array switch circuit system as described in claim 1 further includes: a plurality of extended conductive pads, respectively connected to each of the plurality of contact units located on one side of the array through a plurality of extended switch elements. A channel group; wherein the channel group consists of the first column of channels and the second column of channels, or the first row of channels and the second row of channels. The array switch circuit system as described in claim 2 further includes: a plurality of extended conductive pads, respectively connected to each of the plurality of contact units located on one side of the array through a plurality of extended switch elements. A channel group; wherein the channel group consists of the first column of channels, the second column of channels, the third column of channels and the fourth column of channels, or the first row of channels, the second row of channels, the It consists of the third row of channels and the fourth row of channels. The array switching circuit system of claim 1, wherein at least one of the first switching element, the second switching element, the third switching element and the fourth switching element includes: a transmission gate including an input terminal, an output terminal, a two-gate control terminal and a two-base control terminal, and are used to cause the input terminal and the output terminal to conduct or cut off each other according to the voltage of the two-gate control terminal; and A base voltage control subcircuit is connected to the input terminal and the two base control terminals, and is used to adjust the voltage of the two base control terminals according to the voltage of the input terminal when the input terminal and the output terminal are turned on, so as to The voltage difference between the input terminal and the two base control terminals is smaller than a preset value. The array switch circuit system as described in claim 5, wherein the transmission gate is a first transmission gate, the input terminal is a first input terminal, the output terminal is a first output terminal, and the two gate control terminals are Two first gate control terminals, and the base voltage control sub-circuit includes: a second transmission gate having a second input terminal, a second output terminal and two second gate control terminals, wherein the second input terminal The terminal is connected to the first input terminal, the second output terminal is connected to a first of the two base control terminals, and the two second gate control terminals are respectively connected to the two first gate control terminals; A third transmission gate has a third input terminal, a third output terminal and two third gate control terminals, wherein the third input terminal is connected to the first input terminal, and the third output terminal is connected to the two a second one of the base control terminals, and the two third gate control terminals are respectively connected to the two first gate control terminals; a first transistor having a fourth input terminal and a fourth output terminal and a fourth control terminal, wherein the fourth input terminal is connected to the second output terminal, the fourth output terminal is used for grounding, and the fourth control terminal is connected to a first of the two first gate control terminals. and a second transistor having a fifth input terminal, a fifth output terminal and a fifth control terminal, wherein the fifth input terminal is used to receive the operating voltage, and the fifth output terminal is connected to the third output terminal, and the fifth control terminal is connected to a second one of the two first gate control terminals. The array switching circuit system of claim 6, wherein the first transmission gate, the second transmission gate and the third transmission gate respectively include a plurality of N-channel metal oxide semiconductor field effect transistors (MOSFETs) and a plurality of P-channel MOSFETs, the gates of the N-channel MOSFETs are connected to each other, the gates of the P-channel MOSFETs are connected to each other, and the base of the N-channel MOSFET belonging to the first transmission gate among the N-channel MOSFETs serves as the two bases The first one of the control terminals, the gate of the N-channel MOSFET of the first transmission gate serves as the second one of the two first gate control terminals, and the gate of the P-channel MOSFET belonging to the first transmission gate The base of the P-channel MOSFET serves as the second of the two base control terminals, and the gate of the P-channel MOSFET of the first transmission gate serves as the first of the two first gate control terminals. . The array switching circuit system of claim 1 further includes a memory connected to a plurality of control terminals in the first switching element, the second switching element, the third switching element and the fourth switching element, wherein The memory is used to control and record the switching states of the first switching element, the second switching element, the third switching element and the fourth switching element. The array switching circuit system of claim 1 further includes: a memory connected to a plurality of control terminals of the first switching element, the second switching element, the third switching element and the fourth switching element; and A microcontroller is connected to the memory and the control terminals. The microcontroller is used to control the control terminals according to a control command and perform an AC test, and after the AC test passes, write the control command into the memory. A switching circuit containing: A transmission gate has an input terminal, an output terminal, two gate control terminals and two base control terminals, and is used to conduct or cut off the input terminal and the output terminal with each other according to the voltage of the two gate control terminals; and A base voltage control subcircuit is connected to the input terminal and the two base control terminals, and is used to adjust the voltage of the two base control terminals according to the voltage of the input terminal when the input terminal and the output terminal are turned on, so as to The voltage difference between the input terminal and the two base control terminals is smaller than a preset value. The switching circuit of claim 10, wherein the transmission gate is a first transmission gate, the input terminal is a first input terminal, the output terminal is a first output terminal, and the two gate control terminals are two A gate control terminal, and the base voltage control sub-circuit includes: a second transmission gate having a second input terminal, a second output terminal and two second gate control terminals, wherein the second input terminal is connected to At the first input terminal, the second output terminal is connected to a first of the two base control terminals, and the two second gate control terminals are respectively connected to the two first gate control terminals; a first A three-transmission gate has a third input terminal, a third output terminal and two third gate control terminals, wherein the third input terminal is connected to the first input terminal, and the third output terminal is connected to the two bases. A second one of the control terminals, and the two third gate control terminals are respectively connected to the two first gate control terminals; a first transistor has a fourth input terminal, a fourth output terminal and a A fourth control terminal, wherein the fourth input terminal is connected to the second output terminal, the fourth output terminal is used for grounding, and the fourth control terminal is connected to a first of the two first gate control terminals; as well as a second transistor having a fifth input terminal, a fifth output terminal and a fifth control terminal, wherein the fifth input terminal is used to receive an operating voltage, the fifth output terminal is connected to the third output terminal, and The fifth control terminal is connected to a second one of the two first gate control terminals. The switch circuit of claim 11, wherein the first transmission gate, the second transmission gate and the third transmission gate respectively include a plurality of N-channel metal oxide semiconductor field effect transistors (MOSFETs) and a plurality of P channel MOSFET, the gates of the N-channel MOSFETs are connected to each other, the gates of the P-channel MOSFETs are connected to each other, and the base of the N-channel MOSFET belonging to the first transmission gate among the N-channel MOSFETs serves as the two base control terminals The first one of them, the gate of the N-channel MOSFET of the first transmission gate serves as the second one of the two first gate control terminals, and the P of the P-channel MOSFETs belonging to the first transmission gate The base of the channel MOSFET serves as the second of the two base control terminals, and the gate of the P-channel MOSFET of the first transmission gate serves as the first of the two first gate control terminals.

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