TWI814578B - Thin-film transistor and manufacturing method thereof - Google Patents

Abstract

A thin-film transistor and manufacturing method thereof are disclosed in the present invention, the thin-film transistor can be bottom-gate or top-gate transistor. The thin-film transistor includes a substrate, a first insulative film, a second insulative film, a semiconductive film and a conductive film. A source electrode, a drain electrode and a gate electrode can be obtained after patterning the conductive film. The second insulative film includes multiple contact windows which are used to expose the source electrode, the drain electrode and the gate electrode. The films of the transistor can be all oxide films deposited in non-vacuum environment so as to reduce manufacture cost of large-sized display.

Description

Thin film transistor and manufacturing method thereof

The present invention relates to a transistor and a manufacturing method thereof, in particular to a thin film transistor and a manufacturing method thereof.

Most display drive circuits are composed of thin film transistors. Vacuum coating technology is generally used to manufacture thin film transistors. However, large-size displays are the mainstream development nowadays. In order to perform large-area coating, the size of the vacuum chamber needs to be increased, which in turn leads to equipment costs and manufacturing processes. The time, process cost and power consumption have increased significantly, which is not conducive to reducing the manufacturing cost of large-size displays. In addition, if the transmittance of the thin film transistor for visible light is poor, the backlight light will be absorbed by the thin film transistor and affect the brightness of the display.

The purpose of the present invention is to provide a thin film transistor and a manufacturing method thereof. The thin film transistor can be a lower gate type or an upper gate type all-oxide thin film transistor. Oxide films with different resistivities are selected as electrodes and channel layers. , insulation layer and surface passivation layer, and different oxide films can be deposited separately in a non-vacuum environment, which helps to reduce the complexity and cost of the process. The oxide film has good transmittance of visible light, which can reduce the backlight light being blocked by the film. Transistor absorption occurs.

The invention discloses a thin film transistor, which includes a substrate, a gate electrode, a first insulating film, a semiconductor film, a source electrode, a drain electrode and a second insulating film. The gate electrode is located on the A surface of the substrate has a first part and a second part, the first insulating film covers the surface of the substrate and the first part of the gate electrode, and exposes the second part of the gate electrode, The semiconductor film covers the first insulating film, and a surface of the semiconductor film defines a source region and a drain region, the source electrode is located in the source region, the drain electrode is located in the drain region, and the third Two insulating films cover the surface of the substrate, the source electrode, the drain electrode and the second part of the gate electrode. The second insulating film has a plurality of contact windows, and the contact windows respectively expose the source electrode. electrode, the drain electrode and the second part of the gate electrode, wherein the second insulating film is made of polysilazane, polysiloxane or polysiloxane.

The invention discloses another thin film transistor, which includes a substrate, a semiconductor film, a first insulating film, a source electrode, a drain electrode, a gate electrode and a second insulating film. The semiconductor film is located on the A surface of the substrate, and a surface of the semiconductor film defines a source region and a drain region, the first insulating film covers the surface of the substrate and the semiconductor film and has a first opening and a second opening, The first opening exposes the source region, the second opening exposes the drain region, the source electrode is located in the source region, the drain electrode is located in the drain region, the gate electrode is located in the source electrode and On the first insulating film between the drain electrodes, the second insulating film is located on the first insulating film. The second insulating film has a plurality of contact windows, and the contact windows respectively expose the source electrode, the The drain electrode and the gate electrode, wherein the second insulating film is made of polysilazane, polysiloxane or polysiloxane.

The invention discloses a method for manufacturing a thin film transistor, which includes the following steps: depositing a first conductive film on a surface of a substrate; patterning the first conductive film to form a gate electrode, the gate electrode having a A first part and a second part; deposit a first insulating film on the surface of the substrate and the gate electrode; deposit a semiconductor film on the first insulating film, one surface of the semiconductor film defines a source electrode region and a drain region; deposit a second conductive film on the semiconductor film; pattern the second conductive film to form a source electrode and a drain electrode, the source electrode is located in the source region, the The drain electrode is located in the drain area; patterning the semiconductor film and the first insulating film to remove the semiconductor film and the first insulating film outside an active area to expose the surface of the substrate and the gate The second part of the electrode, the source electrode and the drain electrode are located in the active area; deposit a second insulating film on the surface of the substrate, the source electrode, the drain electrode and the gate electrode The second part, the second insulating film has a plurality of contact windows, and the contact windows respectively expose the second part of the source electrode, the drain electrode and the gate electrode. The second insulating film is made of polysilicon. Made of azane, polysiloxane or polysiloxane.

The present invention discloses another method for manufacturing a thin film transistor, which includes the following steps: depositing a semiconductor film on a surface of a substrate, the surface of the semiconductor film defining a source region and a drain region; patterning the semiconductor film , to remove the semiconductor film outside an active region, the source region and the drain region are located in the active region; deposit a first insulating film on the surface of the substrate and the semiconductor film; pattern the first insulating film An insulating film to form a first opening and a second opening, the first opening exposing the source region, the second opening exposing the drain region; depositing a conductive film on the first insulating film, the source region and the drain region; patterning the conductive film to form a source electrode, a drain electrode and a gate electrode, the source electrode is located in the source region, and the drain electrode is located in the drain region, The gate electrode is located on the first insulating film between the source electrode and the drain electrode; a second insulating film is deposited on the first insulating film, the second insulating film has a plurality of contact windows, the The contact windows respectively expose the source electrode, the drain electrode and the gate electrode, wherein the second insulating film is made of polysilazane, polysiloxane or polysiloxane.

Figures 1 to 10 are schematic diagrams of a manufacturing method of a thin film transistor (first embodiment). Please refer to Figure 1. After cleaning a substrate 110, a first conductive film 120 is deposited on one surface 111 of the substrate 110. Preferably, the resistance value of the first conductive film 120 is less than 10 ^-2 Ω-cm. More preferably, the first conductive film 120 is a metal oxide film with a resistance value less than 10 ^-2 Ω-cm. In this embodiment In an example, the first conductive film 120 is an indium tin oxide (ITO, Indium Tin Oxide) film.

Please refer to Figures 2a and 2b, which are cross-sectional views and top views respectively. After depositing the first conductive film 120, the first conductive film 120 is patterned to form a gate electrode 121 on the substrate 110. The gate electrode 121 has a first part 121a and a second part 121b. The first part 121a is connected to the second part 121b. The resistance value of the gate electrode 121 is less than 10 ^-2 Ω-cm. In this embodiment, it is passed through Conventional lithography technology defines a gate area and uses a wet etching method to pattern the first conductive film 120 to form the gate electrode 121 .

Please refer to Figure 3. After patterning the first conductive film 120, a first insulating film 130 is deposited on the surface 111 of the substrate 110 and the gate electrode 121. Preferably, the first insulating film 130 is The resistance value is greater than 10 ² Ω-cm and can be made of metal oxide, polysilazane, polysiloxane or polysiloxane. In this embodiment, the first insulating film 130 is an aluminum oxide ( AlO _x ) film.

Please refer to Figure 4. After depositing the first insulating film 130, a semiconductor film 140 is then deposited on the first insulating film 130. A surface 141 of the semiconductor film 140 defines a source region 141a and a drain region. 141b. The source region 141a and the drain region 141b are respectively located on both sides of the first portion 121a of the gate electrode 121. Preferably, the resistance value of the semiconductor film 140 is greater than 10 ^-2 Ω-cm. Here, In an embodiment, the semiconductor film 140 is an indium gallium zinc oxide (InGaZnO _x ) film.

Please refer to Figure 5. After depositing the semiconductor film 140, a second conductive film 150 is deposited on the surface 141 of the semiconductor film 140. Preferably, the resistance value of the second conductive film 150 is less than 10 ^-2 Ω-cm , more preferably, the second conductive film 150 is a metal oxide film with a resistance value less than 10 ^-2 Ω-cm. In this embodiment, the second conductive film 150 is an indium tin oxide (ITO, Indium Tin Oxide film and the first conductive film 120 are made of the same material, but the invention is not limited thereto. In other embodiments, the first conductive film 120 and the second conductive film 150 can be different oxide films. .

Please refer to Figures 6a and 6b. After depositing the second conductive film 150, the second conductive film 150 is patterned to form a source electrode 151 and a drain electrode 152. The source electrode 151 is located in the source region. 141a, the drain electrode 152 is located in the drain region 141b, there is a space between the source electrode 151 and the drain electrode 152, the space exposes the surface 141 of the semiconductor film 140, and the gate electrode 121 The first part 121a is located between the source electrode 151 and the drain electrode 152, and the second part 121b of the gate electrode 121 is located outside the source electrode 151 and the drain electrode 152. Preferably, the source The resistance values of the electrode electrode 151 and the drain electrode 152 are less than 10 ^-2 Ω-cm. In this embodiment, the source region 141a and the drain region 141b are defined by photolithography technology, and then patterned by wet etching. The second conductive film 150 is formed to form the source electrode 151 and the drain electrode 152. The wet etching rate of the second conductive film 150 is more than 5 times the wet etching rate of the semiconductor film 140. By controlling the etching selection This is to avoid etching the semiconductor film 140 under the second conductive film 150 .

Please refer to Figures 7a and 7b. After patterning the second conductive film 150, the semiconductor film 140 and the first insulating film 130 are patterned to remove the semiconductor film 140 and the first insulating film outside an active area A. The insulating film 130, therefore the surface 111 of the substrate 110 outside the active area A and the second portion 121b of the gate electrode 121 are exposed, and the source electrode 151, the drain electrode 152 and the gate The first portion 121a of the electrode 121 is located in the active area A. In this embodiment, the semiconductor film 140 and the first insulating film 130 are patterned through photolithography technology and wet etching to define the active area. A.

Please refer to Figures 8a and 8b. After removing the semiconductor film 140 and the first insulating film 130 outside the active area A, a photoresist 160 is formed on the source electrode 151, the drain electrode 152 and the gate. On the second part 121b of the electrode 121, the area of the photoresist 160 is smaller than the area of the source electrode 151, the drain electrode 152 and the second part 121b. Please refer to Figures 9a and 9b, and then a second The insulating film 170 is exposed between the surface 111 of the substrate 110, the source electrode 151 and the drain electrode 152, the semiconductor film 140, the source electrode 151 not covered by the photoresist 160, and the drain electrode. 152 and the second portion 121b of the gate electrode 121, preferably, the resistance value of the second insulating film 170 is greater than 10 ² Ω-cm, and can be made of metal oxide (such as aluminum oxide), polysilazane, Made of polysiloxane or polysiloxane.

Referring to Figures 10a and 10b, after depositing the second insulating film 170, the photoresist 160 is removed by a lift-off method, and a plurality of contact windows 171 are formed in the second insulating film 170. The contact windows 171 respectively expose the source electrode 151, the drain electrode 152 and the second portion 121b of the gate electrode 121. After forming the contact windows 171, the gate type thin film transistor 100 can be obtained. The invention does not limit the formation method of the contact windows 171. In other embodiments, the second insulating film 170 can be deposited first, and then the second insulating film 170 can be patterned through photolithography technology and wet etching to form the contact windows 171. Contact window 171.

Preferably, the first conductive film 120, the first insulating film 130, the semiconductor film 140, the second conductive film 150 and the second insulating film 170 are respectively deposited in a non-vacuum environment. More preferably, It is deposited by mist chemical vapor deposition, spin coating, spray coating, inkjet printing or dip coating. The first conductive film 120, the first insulating film 130, the semiconductor film 140, the second conductive film 150 and the second insulating film 170. In this embodiment, the first conductive film 120, the first insulating film 130. The semiconductor film 140, the second conductive film 150 and the second insulating film 170 are all oxide films, and are obtained by atomizing chemical vapor deposition in a non-vacuum environment. In other embodiments, The first conductive film 120, the first insulating film 130, the semiconductor film 140, the second conductive film 150 and the second insulating film 170 can be deposited using different deposition methods.

Please refer to Figures 10a and 10b. The thin film transistor 100 has the substrate 110, the gate electrode 121, the first insulating film 130, the semiconductor film 140, the source electrode 151, the drain electrode 152 and the third Two insulating films 170, the gate electrode 121 is located on the surface 111 of the substrate 110, the first insulating film 130 is the insulating layer of the gate electrode 121, covering the surface 111 of the substrate 110 and the gate electrode 121 The first portion 121a exposes the second portion 121b of the gate electrode 121. The semiconductor film 140 is the channel layer of the thin film transistor 100, covering the first insulating film 130, and the semiconductor film 140, the third An insulating film 130, the source electrode 151, the drain electrode 152 and the first portion 121a of the gate electrode 121 are located in the active area A. The second insulating film 170 is a surface passivation of the thin film transistor 100. layer, which covers the surface 111 of the substrate 110, the source electrode 151, the drain electrode 152 and the second portion 121b of the gate electrode 121, the second insulating film 170 has the contact windows 171, The contact windows 171 respectively expose the source electrode 151, the drain electrode 152 and the second portion 121b of the gate electrode 121. Preferably, the area of the contact windows 171 is smaller than that of the source electrode 151, the drain electrode 152 and the second portion 121b of the gate electrode 121. The area of the source electrode 152 and the second portion 121b of the gate electrode 121 only partially exposes the source electrode 151, the drain electrode 152 and the second portion 121a of the gate electrode 121.

In this embodiment, the first conductive film 120 , the first insulating film 130 , the semiconductor film 140 , the second conductive film 150 and the second conductive film 150 are respectively deposited using an atomized chemical vapor deposition method in a non-vacuum environment. The second insulating film 170 can be coated on a large area, which is beneficial to reducing process complexity and cost, and the first conductive film 120 (the gate electrode 121), the first insulating film 130, the semiconductor film 140, the third The two conductive films 150 (the source electrode 151 and the drain electrode 152) and the second insulating film 170 are both oxide films, so the thin film transistor 100 is a bottom gate all-oxide thin film transistor. Due to oxidation The thin film transistor 100 has a very good transmittance in the visible light wavelength range. When the thin film transistor 100 is applied to a large-size display, it can prevent the backlight light from being absorbed.

Figures 11 to 19 are schematic diagrams of another method of manufacturing a thin film transistor (second embodiment). Please refer to Figure 11. After cleaning a substrate 210, a semiconductor film 220 is deposited on a surface 211 of the substrate 210. The semiconductor One surface 221 of the film 220 defines a source region 221a and a drain region 221b. Preferably, the resistance value of the semiconductor film 220 is greater than 10 ^-2 Ω-cm. In this embodiment, the semiconductor film 220 is a Indium gallium zinc oxide (InGaZnO _x ) thin film.

Referring to Figure 12, the semiconductor film 220 is then patterned to remove the semiconductor film 220 outside an active region A, and the source region 221a and the drain region 221b are located in the active region A, preferably , the active area A is defined through photolithography technology, and the semiconductor film 220 is patterned by wet etching to remove the semiconductor film 220 outside the active area A.

Please refer to Figure 13. After patterning the semiconductor film 220, a first insulating film 230 is deposited on the surface 211 of the substrate 210 and the surface 221 of the semiconductor film 220. Preferably, the first insulating film 230 The resistance value is greater than 10 ² Ω-cm and can be made of metal oxide, polysilazane, polysiloxane or polysiloxane. In this embodiment, the first insulating film 230 is an aluminum oxide (AlO _x ) films.

Referring to Figure 14, after depositing the first insulating film 230, the first insulating film 230 is patterned to form a first opening 231 and a second opening 232. The first opening 231 exposes the source region 221a. The second opening 232 exposes the drain region 221b. In this embodiment, the source region 221a and the drain region 221b are defined through photolithography technology, and then the first insulating film 230 is patterned by wet etching. The first opening 231 and the second opening 232 are formed, and the wet etching rate of the first insulating film 230 is more than 5 times the wet etching rate of the semiconductor film 220. Patterning of the first insulating film can be avoided by controlling the etching selectivity ratio. When the film 230 is removed, the semiconductor film 220 under the first insulating film 230 is affected.

Referring to Figure 15, after patterning the first insulating film 230, a conductive film 240 is deposited on the first insulating film 230, the source region 221a exposed by the first opening 231, and the source region 221a exposed by the second opening 232. In the drain region 221b, preferably, the resistance value of the conductive film 240 is less than 10 ^-2 Ω-cm, and can be a metal oxide film. In this embodiment, the conductive film 240 is an indium tin oxide (ITO). , Indium Tin Oxide) film.

Referring to Figure 16, the conductive film 240 is then patterned to form a source electrode 241, a drain electrode 242 and a gate electrode 243. The source electrode 241 is located in the source region 221a. The drain electrode 242 is located in the drain region 221b, and the gate electrode 243 is located on the first insulating film 230 between the source electrode 241 and the drain electrode 242. Preferably, the source electrode 241 and the drain electrode 242 and the resistance value of the gate electrode 243 is less than 10 ^-2 Ω-cm. In this embodiment, the conductive film 240 is patterned by photolithography technology and wet etching method, and the wet etching rate of the conductive film 240 is The wet etching rate of the first insulating film 230 is more than 5 times to avoid over-etching and damaging the first insulating film 230 when etching the conductive film 240 .

Please refer to Figure 17. After patterning the conductive film 240, a photoresist 250 is formed on the source electrode 241, the drain electrode 242 and the gate electrode 243. Preferably, the photoresist 250 completely covers the source electrode 241, the drain electrode 242 and the gate electrode 243. The source electrode 241, the drain electrode 242 and the gate electrode 243, please refer to Figure 18, and then a second insulating film 260 is deposited on the first insulating film 230. Preferably, the second insulating film 260 The resistance value is greater than 10 ² Ω-cm and can be made of metal oxide (such as aluminum oxide), polysilazane, polysiloxane or polysiloxane. Please refer to Figure 19. Finally, use the lift-off method The photoresist 250 is removed by (lift-off), so that the second insulating film 260 forms a plurality of contact windows 261. The contact windows 261 respectively expose the source electrode 241, the drain electrode 242 and the gate electrode. 243, whereby an upper gate thin film transistor 200 can be obtained. The present invention does not limit the formation method of the contact windows 261. In other embodiments, the second insulating film 260 can be deposited first, and then the photolithography technology is used. The second insulating film 260 is patterned by a wet etching method to form the contact windows 261 .

Preferably, the semiconductor film 220, the first insulating film 230, the conductive film 240 and the second insulating film 260 are respectively deposited in a non-vacuum environment. More preferably, the atomized chemical vapor deposition method is used. The semiconductor film 220 and the first insulating film are deposited by mist chemical vapor deposition, spin coating, spray coating, inkjet printing or dip coating. 230. The conductive film 240 and the second insulating film 260. In this embodiment, the semiconductor film 220, the first insulating film 230, the conductive film 240 and the second insulating film 260 are all oxide films, and They are all obtained by atomizing chemical vapor deposition in a non-vacuum environment. In other embodiments, different deposition methods can be used to deposit the semiconductor film 220, the first insulating film 230, the conductive film 240 and the second Insulating film 260.

Please refer to Figure 19. The thin film transistor 200 has the substrate 210, the semiconductor film 220, the first insulating film 230, the source electrode 241, the drain electrode 242, the gate electrode 243 and the second insulating film. Thin film 260, the semiconductor film 220 is located on the surface 211 of the substrate 210, and is the channel layer of the thin film transistor 200. The first insulating film 230 covers the surface 211 of the substrate 210 and the semiconductor film 220. The gate electrode 243 is located on the first insulating film 230 between the source electrode 241 and the drain electrode 242. The second insulating film 260 is located on the first insulating film 230 and is a surface passivation layer of the thin film transistor 200. The second insulating film 260 has contact windows 261 , and the contact windows 261 respectively expose the source electrode 241 , the drain electrode 242 and the gate electrode 243 .

In this embodiment, the semiconductor film 220, the first insulating film 230, the conductive film 240 and the second insulating film 260 are deposited by atomization chemical vapor deposition in a non-vacuum environment, so there is no limitation. Due to the size of the vacuum equipment, large-area coating can be performed to effectively reduce process complexity and cost, and the semiconductor film 220, the first insulating film 230, the conductive film 240 (the source electrode 241, the drain electrode 242 and the The gate electrode 243) and the second insulating film 260 are both oxide films. Therefore, the thin film transistor 200 is an upper-gate all-oxide thin film transistor, which can be used in large-size displays, and the oxide film is effective in visible light. It has good transmittance within the range, so it can avoid the absorption of backlight light.

The protection scope of the present invention shall be determined by the appended patent application scope. Any changes and modifications made by anyone familiar with this art without departing from the spirit and scope of the present invention shall fall within the protection scope of the present invention. .

100:Thin film transistor 110:Substrate 111: Surface 120: First conductive film 121: Gate electrode 121a: first part 121b: Part 2 130: First insulating film 140: Semiconductor thin film 141: Surface 141a: Source region 141b: Drain region 150: Second conductive film 151: Source electrode 152: Drain electrode 160: Photoresist 170: Second insulating film 171: Contact window 200:Thin film transistor 210:Substrate 211:Surface 220:Semiconductor thin film 221: Surface 221a: Source region 221b: drain region 230: first insulating film 231: First opening 232: Second opening 240: Conductive film 241: Source electrode 242: Drain electrode 243: Gate electrode 250: Photoresist 260: Second insulating film 261: Contact window A: Active area

Figures 1 to 10 are schematic diagrams of a method for manufacturing a thin film transistor according to an embodiment of the present invention. Figures 11 to 19 are schematic diagrams of a method for manufacturing a thin film transistor according to another embodiment of the present invention.

100:Thin film transistor

110:Substrate

111:Surface

121a:Part 1

130:First insulating film

140:Semiconductor thin film

141:Surface

151: Source electrode

152: Drain electrode

170: Second insulation film

171:Contact window

Claims (16)

A thin film transistor, which includes: a substrate; a gate electrode located on a surface of the substrate, the gate electrode having a first part and a second part; a first insulating film covering the surface of the substrate and the first part of the gate electrode, the first insulating film exposing the second part of the gate electrode; a semiconductor film covering the first insulating film, a surface of the semiconductor film defining a source region and a drain region; a source electrode located in the source region; a drain electrode located in the drain region; and a second insulating film covering the surface of the substrate, the source electrode, and the drain electrode and the second part of the gate electrode, the second insulating film has a plurality of contact windows, the contact windows respectively expose the source electrode, the drain electrode and the second part of the gate electrode, wherein the The second insulating film is made of polysilazane, polysiloxane or polysiloxane. The semiconductor film, the first insulating film, the second insulating film, the source electrode, the drain electrode and The gate electrodes are each an oxide film. A thin film transistor, which includes: a substrate; a semiconductor film located on a surface of the substrate; a surface of the semiconductor film defines a source region and a drain region; a first insulating film covering the surface of the substrate surface and the semiconductor film, the first insulating film has a first opening and a second opening, the first opening exposes the source region, and the second opening exposes the drain region; a source electrode located in the source region; a drain electrode located in the drain region; a gate electrode located on the first insulating film between the source electrode and the drain electrode; and a first Two insulating films, located on the first insulating film, the second insulating film has a plurality of contact windows, the contact windows respectively expose the source electrode, the drain electrode and the gate electrode, wherein the second insulating film Made of polysilazane, polysiloxane or polysiloxane, the semiconductor film, the first insulating film, the second insulating film, the source electrode, the drain electrode and the gate electrode are an oxide film respectively. The thin film transistor of claim 1 or 2, wherein the resistance value of the semiconductor thin film is greater than 10 ^-2 Ω-cm. The thin film transistor of claim 1 or 2, wherein the resistance value of the first insulating film is greater than 10 ² Ω-cm. The thin film transistor of claim 1 or 2, wherein the resistance values of the source electrode, the drain electrode and the gate electrode are less than 10 ^-2 Ω-cm. The thin film transistor of claim 1, wherein the areas of the contact windows are smaller than the areas of the source electrode and the drain electrode. A method of manufacturing a thin film transistor, which includes: depositing a first conductive film on a surface of a substrate; patterning the first conductive film to form a gate electrode, the gate electrode having a first portion and a Part 2: Deposit a first insulating film on the surface of the substrate and the gate electrode; deposit a semiconductor film on the first insulating film, one surface of the semiconductor film defines a source region and a drain region; deposit a second conductive film on the semiconductor film; pattern the second conductive film to form a source electrode and a drain electrode, the source electrode is located in the source region , the drain electrode is located in the drain region; pattern the semiconductor film and the first insulating film to remove the semiconductor film and the first insulating film outside an active area, and expose the surface of the substrate and the The second part of the gate electrode, the source electrode, the drain electrode and the first part of the gate electrode are located in the active area; and depositing a second insulating film on the surface of the substrate, the source The second part of the source electrode, the drain electrode and the gate electrode, the second insulating film has a plurality of contact windows, and the contact windows respectively expose the source electrode, the drain electrode and the gate electrode. The second part, the second insulating film is made of polysilazane, polysiloxane or polysiloxane, wherein the semiconductor film, the first insulating film, the second insulating film, the source The electrode, the drain electrode and the gate electrode are respectively an oxide film. A method of manufacturing a thin film transistor, which includes: depositing a semiconductor film on a surface of a substrate, the surface of the semiconductor film defining a source region and a drain region; patterning the semiconductor film to remove an active The source region and the drain region are located outside the active region of the semiconductor film; deposit a first insulating film on the surface of the substrate and the semiconductor film; pattern the first insulating film to form A first opening and a second opening, the first opening exposing the source region, and the second opening exposing the drain region; depositing a conductive film on the first insulating film, the source region and the drain region ;Pattern the conductive film to form a source electrode, a drain electrode and a gate electrode, the source electrode The electrode is located in the source region, the drain electrode is located in the drain region, the gate electrode is located on the first insulating film between the source electrode and the drain electrode; and a second insulating film is deposited on the On the first insulating film, the second insulating film has a plurality of contact windows, and the contact windows respectively expose the source electrode, the drain electrode and the gate electrode, wherein the second insulating film is made of polysilazane, Made of polysiloxane or polysiloxazane, wherein the semiconductor film, the first insulating film, the second insulating film, the source electrode, the drain electrode and the gate electrode are each an oxide film. The method for manufacturing a thin film transistor according to claim 7, wherein the second conductive film is patterned by a wet etching method, and the wet etching rate of the second conductive film is more than 5 times the wet etching rate of the semiconductor film. The method for manufacturing a thin film transistor according to claim 7, wherein the first conductive film, the first insulating film, the semiconductor film, the second conductive film and the second insulating film are respectively deposited in a non-vacuum environment. For example, the method for manufacturing a thin film transistor according to claim 7 or 10, wherein the first conductive film and the first conductive film are deposited by an atomized chemical vapor deposition method, a spin coating method, a spray coating method, an inkjet printing method or a dip coating method. An insulating film, the semiconductor film, the second conductive film and the second insulating film. The method of manufacturing a thin film transistor according to claim 8, wherein the first insulating film is patterned by a wet etching method, and the wet etching rate of the first insulating film is more than 5 times the wet etching rate of the semiconductor film. The method for manufacturing a thin film transistor according to claim 8, wherein the conductive film is patterned by a wet etching method, and the wet etching rate of the conductive film is more than 5 times the wet etching rate of the first insulating film. The method for manufacturing a thin film transistor according to claim 8, wherein the semiconductor film, the first insulating film, the conductive film and the second insulating film are respectively deposited in a non-vacuum environment. The method for manufacturing a thin film transistor according to claim 8 or 14, wherein the semiconductor film and the first insulating film are deposited by atomized chemical vapor deposition, spin coating, spray coating, inkjet printing or dip coating. film, the conductive film and the second insulating film. The method for manufacturing a thin film transistor according to claim 7 or 8, wherein the contact windows are formed on the second insulating film by a lift-off method.

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