TWI814546B - Memory device and method of fabricating the same - Google Patents

Abstract

A memory device includes: a stack structure disposed above a substrate. The stack structure includes a plurality of stacks and a plurality of isolation layers that alternate with each other. Each stack includes: a first source and drain electrode layer, an insulating layer disposed on the first source and drain layer; and a second source and drain layer disposed on the insulating layer; and a channel layer disposed on sidewalls of the insulating layer. The lower surface of the channel layer is connected to the first source and drain layer, and the upper surface of the channel layer is connected to the second source and drain layer. The memory device further includes a gate pillar extends through the stacked structure, and a charge storage structure disposed between the channel layer and the gate pillar.

Description

Memory device and method of manufacturing same

Embodiments of the present invention relate to a semiconductor element and a manufacturing method thereof, and in particular, to a memory element and a manufacturing method thereof.

Non-volatile memory components (such as flash memory) have become a memory component widely used in personal computers and other electronic devices because they have the advantage that stored data will not disappear even after a power outage. NOR flash memory is a flash memory array that is commonly used in the industry. In order to further improve the integration of memory components, a three-dimensional NOR flash memory was developed. However, when depositing stacked film layers in a three-dimensional NOR flash memory, it is easy to cause dopant diffusion in the source and drain layers due to high temperatures, making it impossible to control the dopant concentration and resistance of the source and drain layers.

An embodiment of the present invention provides a memory element, including: a stacked structure disposed above a substrate, wherein the stacked structure includes a plurality of alternating stacks and a plurality of isolation layers, and each stack includes: a first source and drain layer; insulation layer, set placed on the first source and drain layers; a second source and drain layer disposed on the insulating layer; and a channel layer disposed on the sidewalls of the insulating layer, and the channel layer The lower surface is connected to the first source and drain layers, the upper surface of the channel layer is connected to the second source and drain layers; the gate pillar passes through the stacked structure; and the charge storage structure, Disposed between the channel layer and the gate pillar.

An embodiment of the present invention provides a method for manufacturing a memory element, including forming a stacked structure above a substrate, wherein the stacked structure includes a plurality of alternating stacked layers and a plurality of isolation layers, and each stacked layer includes sequentially stacked A first semiconductor layer, an insulating layer and a second semiconductor layer; patterning the stacked structure to form a first opening; removing the exposed portion of the first semiconductor layer and the portion of the sidewall of the first opening. a second semiconductor layer to form a first groove and a second groove respectively; a third semiconductor layer and a fourth semiconductor layer are respectively formed in the first groove and the second groove, wherein the third semiconductor layer The doping concentration of the third semiconductor layer and the fourth semiconductor layer is greater than the doping concentration of the first semiconductor layer and the second semiconductor layer; a tempering process is performed to make the third semiconductor layer and the second semiconductor layer Dopants of the fourth semiconductor layer are driven into the first semiconductor layer and the second semiconductor layer to form first source and drain layers and second source and drain layers; the third semiconductor layer is removed. The insulating layer exposes the sidewall of an opening to form a third groove; forming a channel layer in the third groove; forming an insulating filling layer in the first opening; in the insulating filling layer forming a second opening in the second opening; and forming a charge storage structure and a gate pillar in the second opening.

Based on the above, the memory device and its manufacturing method according to the embodiment of the present invention, After the stacked film layers are formed, the dopants of the source and drain layers can be adjusted so that the source and drain layers have appropriate concentrations to reduce the resistance.

100:Base

102:Component layer

104:Dielectric layer

105: Metal interconnection

106:Plug

108:Wire

110: Metal interconnect structure

112, 128: Stop layer

114:Laminate

120:Isolation layer

122, 122a, 126, 126a, 130L, 130U, 138: semiconductor layer

122R, 124R, 126R: Groove

122S: Side wall

124, 124a: Insulating layer

130: Semiconductor material layer

132, 136, 232, 236: source and drain layers

132I, 136I: interface

134: Block the gap wall

138a: Channel layer

140: Insulating filling layer

140S: Insulating filling layer

142:Hard curtain layer

144:Charge storage structure

146: Gate post

230L, 230U: epitaxial layer

OP1, OP2: Open your mouth

OP3: hole

PR: mask layer

SK1, SK2, SK3: stacked structure

W1, W2, W3: Width

X, Y, Z: direction

I-I’: Tangent line

1A to 1G are schematic three-dimensional views of a method for manufacturing a three-dimensional memory device according to an embodiment of the present invention.

2A to 2O are schematic cross-sectional views of a manufacturing process of a three-dimensional memory device according to an embodiment of the present invention. Figures 2A, 2B, 2C to 2K, 2L, 2M, 2N and 2O are tangent lines I-I of Figures 1A, 1B, 1C, 1D, 1E, 1F and 1G respectively. 'A partial cross-section diagram.

3A to 3C are schematic cross-sectional views of a manufacturing process of a three-dimensional memory device according to another embodiment of the present invention.

Referring to FIGS. 1A and 2A , a substrate 100 is provided. Base 100. The substrate 100 may be a semiconductor substrate, such as a silicon-containing substrate. Device layers 102 are sequentially formed on the substrate 100 . The component layer 102 may include active components or passive components. Active components are, for example, transistors, diodes, etc. Passive components are, for example, capacitors, inductors, etc. The transistor may be an N-type metal oxide half (NMOS) transistor, a P-type metal oxide half (PMOS) transistor, or a complementary metal oxide half element (CMOS), etc.

A metal interconnect structure 110 is formed on the device layer 102 . The metal interconnect structure 110 may include a multi-layer dielectric layer 104 and a multi-layer dielectric layer 104 formed in the multi-layer dielectric layer 104 Metal interconnection 105. The metal interconnect 105 includes a plurality of plugs 106 and a plurality of wires 108. Dielectric layer 104 separates adjacent conductors 108 . The wires 108 can be connected to each other through plugs 106, and the wires 108 can be connected to the component layer 102 through the plugs 106. In some embodiments, metal interconnect structure 110 also includes a stop layer (not shown). The stop layer may be disposed between the dielectric layers 104 and/or above the topmost dielectric layer 104 . The stop layer and the dielectric layer 104 are made of different materials, such as silicon nitride, silicon oxynitride, silicon carbide, aluminum oxide or combinations thereof.

A stacked structure SK1 is formed on the metal interconnect structure 110 . The stacked structure SK1 includes a plurality of stacked layers 114 and isolation layers 120 stacked alternately with each other. The number of stacked layers 114 and isolation layers 120 is not limited to those shown in the figure.

Each stack 114 includes a semiconductor layer 122 , an insulating layer 124 and a semiconductor layer 126 . Semiconductor layers 122 and 126 include polysilicon. The insulating layer 124 is, for example, silicon oxide. Isolation layer 120 separates stacks 114 from each other. The isolation layer 120 can be a single layer or multiple layers, and its material is, for example, silicon carbide or silicon nitride. In the example of FIG. 1A , the isolation layer 120 may include a layer 120a, a layer 120b, and a layer 120c, and the materials thereof are, for example, silicon carbide, silicon nitride, and silicon carbide respectively.

The stack structure SK1 also includes stop layers 112 and 128, respectively located below the bottom stack 114 and above the top stack 114. Stop layers 112 and 128 include silicon nitride, silicon oxynitride, or silicon carbide. The semiconductor layers 122 and 126, the insulating layer 124, the isolation layer 120, and the stop layers 112 and 128 of the stacked structure SK1 can be formed in situ on the same machine. Since the semiconductor layers 122 and 126 can be formed in-situ on the same machine as other layers of the stacked structure SK1, in order to take into account the overall deposition rate of the stacked structure SK1, the doping concentration of the deposited semiconductor layers 122 and 126 cannot be determined. Too high, therefore, the doping concentration of the semiconductor layers 122 and 126 will be lower than the doping concentration of the subsequently formed semiconductor material layer 130 (shown in FIG. 2D ). The dopants of the semiconductor layers 122 and 126 are, for example, arsenic (As), boron (B), phosphorus (P), antimony (Sb), boron fluoride (BF ₂ ) or indium (In), and the doping concentration may be lower than E17 atoms/cm ³ , for example, E12 atoms/cm ³ to E17 atoms/cm ³ .

Referring to FIG. 1B and FIG. 2B , the stacked structure SK1 is patterned to form a stacked structure SK2 and a plurality of openings OP1 . In some embodiments, the stacked structure SK2 is a plurality of strips extending along the Y direction. The opening OP1 is, for example, a trench extending in the Y direction. In other embodiments, the stacking structure SK2 is in a grid shape, and the opening OP1 is surrounded by the stacking structure SK2 (not shown).

2C to 2K are partial cross-sectional schematic views of the tangent line I-I' in FIG. 1C.

Referring to FIG. 2C , a pullback process is performed on the semiconductor layers 122 and 126 to form the semiconductor layers 122 a and 126 a and a plurality of grooves 122R and 126R. The pullback process is, for example, an etching process. The semiconductor layer 122a and the semiconductor layer 126a expose incomplete crystal grains, and the sidewalls 122S and 126S formed by the semiconductor layer 122a and the semiconductor layer 126a have higher undulations (roughness) than the crystal grains in the semiconductor layer 122a or 126a. The degree of fluctuation (roughness) of boundaries 122B and 126B.

2D and 2E, the semiconductor material layer 130 is deposited in the opening OP1, and the semiconductor material layer 130 fills the grooves 122R and 126R, and is in contact with the semiconductor layers 122a and 126a, and the semiconductor material layer 130 is in contact with the semiconductor layer 130. There is an interface 132I between 122a and an interface 136I between the semiconductor material layer 130 and the semiconductor layer 126a. The semiconductor material layer 130 is, for example, a doped polycrystalline silicon layer formed by chemical vapor deposition. In some embodiments, the semiconductor material layer 130 and the semiconductor layers 122a and 126a are all doped semiconductor layers, and the doping concentration of the semiconductor material layer 130 is greater than the doping concentration of the semiconductor layers 122a and 126a. The dopant of the semiconductor material layer 130 is, for example, As, B, P, Sb, BF ₂ or In, and the doping concentration may be greater than E12 atoms/cm ³ , for example, E12 atoms/cm ³ to E21 atoms/cm ³ .

Afterwards, a partial removal process is performed to remove the semiconductor material layer 130 outside the grooves 122R and 126R, so as to form the semiconductor layers 130L and 130U respectively in the grooves 122R and 126R. The semiconductor layer 130L and the semiconductor layer 122a have an interface 132I, and the semiconductor layer 130U and the semiconductor layer 126a have an interface 136I.

Referring to FIG. 2F , a blocking spacer 134 is formed on the side wall of the opening OP1. The material of the barrier spacer 134 is, for example, silicon nitride, silicon oxynitride or a combination thereof. The barrier spacer 134 is formed by, for example, first forming a barrier layer to cover the sidewalls and bottom surface of the opening OP1, and then performing an anisotropic etching process to remove the barrier layer covering the top surface of the stop layer 128 and the bottom surface of the opening OP1. barrier layer.

Referring to FIG. 2G, a tempering process is performed to drive the dopants of the semiconductor layers 130L and 130U into the semiconductor layers 122a and 126a. During the tempering process, the barrier spacer 134 can prevent the dopants of the semiconductor layers 130L and 130U from diffusing to other areas, so that the dopants of the semiconductor layers 130L and 130U diffuse toward the semiconductor layers 122a and 126a to form the source and drain electrodes. Layers 132 and 136. The temperature of the tempering process is, for example, 400 degrees Celsius to 1200 degrees Celsius. The doping concentration of the source and drain layers 132 and 136 is, for example, E12 atoms/cm ³ to E21 atoms/cm ³ . In some embodiments, interfaces 132I and 136I also exist in source and drain layers 132 and 136 .

Referring to FIGS. 2H and 2I , the blocking spacer 134 is removed. Afterwards, a pull back process, such as an anisotropic etching process, is performed on the insulating layer 124 of the stack 114 to form the insulating layer 124a and the groove 124R.

Referring to FIGS. 2J and 2K , the semiconductor layer 138 is formed in the opening OP1 and filled in the groove 124R. The semiconductor layer 138 is, for example, a plurality of Crystalline silicon layer. Afterwards, a partial removal process is performed on the semiconductor layer 138 to form the channel layer 138a in the groove 124R. The channel layer 138a is located on the sidewall of the insulating layer 124a. The upper surface and lower surface of the channel layer 138a are connected and contact the source and drain layers 132 and 136 respectively. In some embodiments, the sidewalls of channel layer 138a are flush with contact source and drain layers 132 and 136. At this point, the stacked structure SK3 is formed, as shown in FIG. 1C and FIG. 2K .

1D and 2L, an insulating filling layer 140 is formed on the substrate 100, and the insulating filling layer 140 is filled into the opening OP1. The material of the insulating filling layer 140 is, for example, silicon oxide.

Referring to FIGS. 1E and 2M , a multilayer 142 and a mask layer PR are formed on the insulating filling layer 140 . Multilayer 142 may include anti-reflective layers, hard mask layers, and the like. The mask layer PR is, for example, a patterned photoresist layer and has a plurality of openings OP2.

Referring to FIG. 1F and FIG. 2N, a patterning process is performed to transfer the mask layer PR to the insulating filling layer 140 and the stacked structure SK3 to form the hole OP3. In some embodiments, holes OP3 are arranged in an array. Afterwards, the mask layer PR and the hard mask layer 142 are removed.

Referring to FIG. 1G and FIG. 2O , a charge storage structure 144 and a gate post 146 are formed in the hole OP3. The charge storage structure 144 and the gate pillar 146 are formed by, for example, forming a charge storage material layer on the upper surface of the insulating filling layer 140 and in the hole OP3, and then removing the charge storage material layer on the bottom of the hole OP3 through an etch-back process. After that, a gate material layer is formed above the upper surface of the insulating filling layer 140 and in the hole OP3, and then a planarization process is performed using a chemical mechanical polishing method to remove the excess gate material layer on the upper surface of the insulating filling layer 140. . The electrical charge storage material layer is, for example, an oxide/nitride/oxide (ONO) composite layer. The gate material layer is, for example, a conductor layer. conductor layer Including barrier layer and metal layer. The material of the barrier layer includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof, and the material of the metal layer includes tungsten (W). In some embodiments, gate posts 146 are arranged in an array. Gate posts 146 in two adjacent rows may be staggered or aligned. The insulating filling layer 140S located between two adjacent rows of gate posts 146 may serve as a slit.

The gate post 146 extends continuously in the Z direction and is electrically connected to the metal interconnect 105 below. The charge storage structure 144 extends continuously in the Z direction and surrounds the sidewalls of the gate pillars 146 . The charge storage structure 144 is sandwiched between the sidewalls of each channel layer 138a and the sidewalls of the gate pillars 146. The source and drain layers 132, the insulating layer 124a and the source and drain layers 136 are stacked in the Z direction. The width W1 of the insulating layer 124a in the X direction is smaller than the widths W2 and W3 of the source and drain layers 132 and 136. The channel layer 138a is disposed on the sidewall of the insulating layer 124a. The lower surface of each channel layer 138a is connected to the source and drain layers 132, and the upper surface of each channel layer 138a is connected to the source and drain layers 136. In addition, the plurality of channel layers 138a in the Z direction are separated from each other.

The method of forming the source and drain layers 132 and 136 of the present invention is not limited to the above embodiment. In other embodiments, source and drain layers 132 and 136 are formed as follows. Referring to FIG. 3A, the semiconductor layers 122a and 126a and the plurality of grooves 122R and 126R are formed according to the aforementioned method. Afterwards, an epitaxial growth process is performed to form epitaxial layers 230L and 230U in the grooves 122R and 126R, as shown in FIG. 3B . The epitaxial layers 230L and 230U are also called semiconductor layers. Thereafter, the source and drain layers 232 and 236, the charge storage structure 144, the gate pillar gate 146, etc. are formed according to the above-mentioned process of FIGS. 2F to 2H, as shown in FIG. 3C.

In embodiments of the present invention, the source and drain layers are formed in multiple stages. First, a semiconductor layer with a lower concentration is formed according to the process, and then the sidewall portion of the semiconductor layer is removed, and then a high-concentration semiconductor layer (epitaxial layer) is formed in the formed groove. Thereafter, through a tempering process, the high-concentration dopant is diffused and driven into the lower-concentration semiconductor layer to form source and drain layers with suitable doping concentration. In this way, a stacked structure with stacked layers and insulating layers can be formed in situ on the same machine, and after the stacked structure is formed, the concentrations of the source and drain layers can be adjusted so that the source and drain layers have Appropriate concentration to reduce resistance.

128: Stop layer

120:Isolation layer

122a, 126a, 130L, 130U: semiconductor layer

124:Insulation layer

132I, 136I: interface

134: Block the gap wall

OP1: Open your mouth

X, Y, Z: direction

Claims (10)

A memory element includes: a stacked structure disposed above a substrate, wherein the stacked structure includes a plurality of alternating stacked layers and a plurality of isolation layers, and each stacked layer includes: a first source electrode and a drain electrode layer; An insulating layer is disposed on the first source and drain layers; a second source and drain layer is disposed on the insulating layer; and a channel layer is disposed on the sidewall of the insulating layer, and the The lower surface of the channel layer is connected to the first source and drain layers, and the upper surface of the channel layer is connected to the second source and drain layers; gate pillars pass through the stacked structure; and charges A storage structure is disposed between the channel layer and the gate pillar, wherein the first source and drain layer and the second source and drain layer have interfaces. The memory device of claim 1, wherein side walls of the first source and drain layer and the second source and drain layer are flush with side walls of the channel layer. The memory device of claim 1, further comprising: a metal interconnect structure disposed between the stacked structure and the substrate, wherein the gate post is electrically connected to the metal interconnect structure. Metal interconnections. A method for manufacturing a memory element, including: forming a stacked structure above a substrate, wherein the stacked structure includes alternating A plurality of stacked layers and a plurality of isolation layers, and each stacked layer includes a first semiconductor layer, an insulating layer and a second semiconductor layer stacked in sequence; patterning the stacked structure to form a first opening; removing all The exposed portion of the first semiconductor layer and the portion of the second semiconductor layer on the sidewall of the first opening form a first groove and a second groove respectively; A third semiconductor layer and a fourth semiconductor layer are respectively formed in the two grooves, wherein the doping concentrations of the third semiconductor layer and the fourth semiconductor layer are greater than those of the first semiconductor layer and the second semiconductor layer. Doping concentration; perform a tempering process so that the dopants of the third semiconductor layer and the fourth semiconductor layer are driven into the first semiconductor layer and the second semiconductor layer to form the first source and drain layers and second source and drain layers; remove the insulating layer at the exposed portion of the sidewall of the first opening to form a third groove; form in the third groove a channel layer; forming an insulating filling layer in the first opening; forming a second opening in the insulating filling layer; and forming a charge storage structure and a gate pillar in the second opening. The manufacturing method of a memory element according to claim 4, wherein the forming method of the third semiconductor layer and the fourth semiconductor layer includes: depositing a semiconductor material layer on the substrate and filling the first the opening and the first groove and the second groove; and A local removal process is performed to remove the semiconductor material layer outside the first groove and the second groove. The method of manufacturing a memory element according to claim 4, wherein the forming method of the third semiconductor layer and the fourth semiconductor layer includes performing an epitaxial growth process to form a gap between the first groove and the second semiconductor layer. The grooves respectively form a first epitaxial layer and a second epitaxial layer. The method of manufacturing a memory element according to claim 4, wherein the first semiconductor layer, the insulating layer, the second semiconductor layer and the isolation layer are formed in situ on the same machine. The method of manufacturing a memory device according to claim 4, further comprising: forming a metal interconnect structure on the substrate before forming the stacked structure on the substrate, wherein the gate posts are electrically connected Metal interconnects of the metal interconnect structure. The method of manufacturing a memory element according to claim 4, further comprising: before performing the tempering process, forming a blocking spacer on the side wall of the first opening; and after performing the tempering process. , remove the blocking spacer wall. The method of manufacturing a memory element according to claim 9, wherein the material of the blocking spacer includes silicon nitride, silicon oxynitride or a combination thereof.

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