TWI813024B - Method of forming three-dimensional memory device - Google Patents

Abstract

Provided is a method of forming a three-dimensional (3D) memory device including: forming a discharging layer and a stack structure on a buffer layer; forming vertical channel structures in the stack structure; forming an opening in the stack structure, wherein the opening includes two first trenches extending along a X direction and two second trenches extending along a Y direction, and the two first trenches and the two second trenches are separated from each other; forming an insulating layer on a sidewall of the opening; removing the discharging layer exposed by the insulating layer to form a cavity connecting the two first trenches and the two second trenches, thereby forming a ring-shaped opening; performing a gate replacement process to replace sacrificial layers of the stack structure by conductive layers; and filling an isolating material in the ring-shaped opening to form an isolating ring structure.

Description

Methods of forming three-dimensional memory devices

The present invention relates to a method of forming a semiconductor element, and in particular to a method of forming a three-dimensional memory element.

Non-volatile memory (such as flash memory) has become a type of memory widely used in personal computers and other electronic devices because it has the advantage that stored data will not disappear even after a power outage.

Currently, three-dimensional flash memories commonly used in the industry include NOR flash memory and NAND flash memory. In addition, another type of three-dimensional flash memory is AND flash memory, which can be used in multi-dimensional flash memory arrays to have high integration and high area utilization, and has fast operation speed. advantages. Therefore, the development of three-dimensional flash memory has gradually become the current trend.

The invention provides a method for forming a three-dimensional memory element, which includes the following steps. A buffer layer having a first area and a second area is provided. The second area surrounds the first area. A stop layer and a stack structure including a plurality of alternately stacked dielectric layers and a plurality of sacrificial layers are formed on the buffer layer. The stacked structure includes at least one vertical channel structure penetrating the stacked structure in the first region. A first opening is formed in the stacked structure of the first region, and a second opening is formed in the stacked structure of the second region. The width of the second opening is greater than the width of the first opening. A dielectric material is formed to fill the first opening and the second opening. Perform a first etching process to remove at least part of the dielectric material on the bottom surface of the second opening to expose a part of the stop layer, and then form a first dielectric layer in the first opening and on the sidewall of the second opening. second dielectric layer. A second etching process is performed to remove the stop layer exposed at the bottom surface of the second opening, thereby forming a cavity. The cavity extends laterally below the stacked structure such that the cavity connects to the second opening to form a closed ring.

The invention provides a method for forming a three-dimensional memory element, which includes the following steps. A discharge layer (discharging layer) and a stacked structure including a plurality of alternately stacked dielectric layers and a plurality of sacrificial layers are formed on the buffer layer. Multiple vertical channel structures are formed in the stacked structure. Openings are formed in the stacked structure. The opening includes two first slits extending along the X direction and two second slits extending along the Y direction, and the two first slits and the two second slits are separated from each other. An insulating layer is formed on the sidewall of the opening. The insulating layer exposes the discharge layer at the bottom surface of the opening. The discharge layer exposed at the bottom surface of the opening is removed to form a cavity. The cavity extends below the stacked structure to connect the two first slits and the two second slits to form an annular opening. A gate replacement process is performed to replace multiple sacrificial layers in the stacked structure with multiple conductor layers. A plurality of conductor layers respectively surround a plurality of vertical channel structures to form a plurality of memory cells. Fill the annular opening with isolation material to form an isolation ring structure.

Based on the above, in this embodiment, a first opening and a second opening are simultaneously formed in the array region and the isolation ring region, so that the gate replacement process can be performed through the first opening and the second opening. The second opening may include an unclosed slit ring structure to prevent the discharge layer from being cut off by the second opening, thereby preventing arcing effects. In addition, this embodiment can perform a subsequent etching process to remove the discharge layer exposed at the bottom surface of the second opening, thereby forming a cavity. The cavity can laterally penetrate the unsealed slit ring structure to form a ring-shaped opening, thereby electrically or physically separating the discharge layer in the array region and the discharge layer in the outer region. In this case, this embodiment can avoid the arc effect when cutting the discharge layer, thereby improving the reliability of the three-dimensional memory element.

The present invention will be described more fully with reference to the drawings of this embodiment. However, the present invention may also be embodied in various forms and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings are exaggerated for clarity. The same or similar component numbers represent the same or similar components, which will not be described one by one in the following paragraphs.

FIG. 1 is a schematic cross-sectional view of a three-dimensional memory device according to an embodiment of the present invention.

Referring to FIG. 1 , the three-dimensional memory device according to the embodiment of the present invention may include a buffer layer 100 , a stop layer 102 , a stacked structure 110 , a capping layer 116 and a vertical channel structure 130 . In one embodiment, buffer layer 100 includes a dielectric substrate. The dielectric substrate may be a dielectric layer formed on a silicon substrate, such as a silicon oxide layer. In other words, there may be peripheral circuits underneath the buffer layer 100 . In addition, the buffer layer 100 may include a first region R1 and a second region R2. In an embodiment, the first region R1 may be an array region, and the second region R2 may be an isolation ring region.

The stop layer 102 may be formed on the buffer layer 100 . In one embodiment, the material of the stop layer 102 includes a conductive material. The conductor material may include semiconductor materials including polycrystalline silicon, III-V compound semiconductors, or combinations thereof. When the three-dimensional memory device is an embodiment of a three-dimensional NAND flash memory, the stop layer 102 can be used as a source line. When the three-dimensional memory device is an embodiment of a three-dimensional NOR flash memory, the stop layer 102 can be used as a dummy word line. Although the stop layer 102 shown in FIG. 1 has a single-layer structure, the present invention is not limited thereto. In alternative embodiments, stop layer 102 may also be a multi-layer structure. The multi-layer structure may include alternately stacked dielectric layers (eg, silicon oxide layers) and conductor layers (eg, polycrystalline silicon layers).

The stack structure 110 may be formed on the stop layer 102 such that the stop layer 102 is disposed between the buffer layer 100 and the stack structure 110 . In one embodiment, the stacked structure 110 may include a plurality of dielectric layers 112 and a plurality of sacrificial layers 114 stacked alternately. In one embodiment, the dielectric layer 112 and the sacrificial layer 114 may be made of different materials, or materials with different etching rates. For example, the dielectric layer 112 may be a silicon oxide layer; the sacrificial layer 114 may be a silicon nitride layer, a polycrystalline silicon layer or a metallic tungsten layer. The number of the dielectric layer 112 and the sacrificial layer 114 can be adjusted according to requirements, and the present invention is not limited thereto.

The capping layer 116 may be formed on the stacked structure 110 such that the stacked structure 110 is disposed between the stop layer 102 and the capping layer 116 . In one embodiment, the material of the capping layer 116 may include a dielectric material, such as silicon oxide.

The vertical channel structure 130 may be formed in the stack structure 110 and the stop layer 102 in the first region R1. As shown in FIG. 1 , the vertical channel structure 130 may penetrate the stack structure 110 , the stop layer 102 and partially extend into the buffer layer 100 . It is worth noting that when forming the opening 115 that can accommodate the vertical channel structure 130, the stop layer 102 can not only be used as an etching stop layer, but can also be used to prevent the arcing effect generated during plasma etching, and thus Improve component reliability. In this embodiment, the stop layer 102 can be regarded as a discharging layer, which is usually grounded to the silicon substrate to reduce the charge accumulated by the above-mentioned plasma etching, thereby avoiding damage to the component. Therefore, when performing a high aspect ratio etching process, the stop layer 102 is usually grounded to the silicon substrate to avoid arc discharge.

Basically, according to different forms of the three-dimensional memory device, the vertical channel structure 130 can have different aspects, as detailed below.

2A, 3A and 4A are schematic cross-sectional views of vertical channel structures according to various embodiments of the present invention. Figures 2B, 3B and 4B are schematic plan views of Figures 2A, 3A and 4A respectively.

Please refer to FIG. 2A and FIG. 2B. When the three-dimensional memory device is a three-dimensional AND flash memory, the vertical channel structure 130A may include a charge storage structure 132, a channel layer 134, a dielectric material 136, and a first source electrode. /Drain post 133 and the second source/Drain post 135. As shown in FIG. 2A , the first source/drain pillar 133 and the second source/drain pillar 135 can penetrate the cap layer 116 , the stack structure 110 and the stop layer 102 , and partially extend into the buffer layer 100 . In one embodiment, the first source/drain pillar 133 and the second source/drain pillar 135 may have the same conductor material, such as N-type doped (N+) polycrystalline silicon material. The dielectric material 136 may be disposed between the first source/drain post 133 and the second source/drain post 135 to separate the first source/drain post 133 and the second source/drain post 135 . In addition, as shown in FIG. 2B , the channel layer 134 may laterally surround the dielectric material 136 , the first source/drain pillar 133 and the second source/drain pillar 135 . The first source/drain pillar 133 and the second source/drain pillar 135 respectively physically contact a portion of the channel layer 134 . Charge storage structure 132 may laterally surround channel layer 134 . In one embodiment, the charge storage structure 132 may be a composite layer composed of a tunneling layer, a charge storage layer and a blocking layer. The tunneling layer, charge storage layer and blocking layer can be considered as oxide/nitride/oxide (ONO) respectively. In another embodiment, the tunneling layer may be a composite layer of oxide/nitride/oxide (ONO). In other embodiments, the barrier layer may be a composite layer of oxide/nitride/oxide (ONO) or other suitable materials. The channel layer 134 may include a doped polysilicon layer or an undoped polysilicon layer. Dielectric material 136 may include silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

Referring to FIGS. 3A and 3B , when the three-dimensional memory device is a first type of three-dimensional NAND flash memory, the vertical channel structure 130B may include a charge storage structure 132 , a channel structure 234 and a dielectric pillar 236 . As shown in FIG. 3A , the dielectric pillar 236 may penetrate the cap layer 116 , the stack structure 110 and the stop layer 102 , and partially extend into the buffer layer 100 . Channel structure 234 may include liner 234A and plug 234B. The liner 234A may cover the sidewalls and bottom surfaces of the dielectric pillars 236 , and the plugs 234B may seal the top surfaces of the dielectric pillars 236 . In this case, the channel structure 234 may completely cover all surfaces of the dielectric pillar 236 . The charge storage structure 132 may be disposed between the channel structure 234 and the cap layer 116 , and between the channel structure 234 and the stack structure 110 . The charge storage structure 132 between the channel structure 234 and the stop layer 102 is removed. From the perspective of cross-section Figure 3B, the charge storage structure 132 may laterally surround the channel structure 234. The materials of the charge storage structure 132, the channel structure 234, and the dielectric pillar 236 are the same as the materials of the charge storage structure 132, the channel layer 134, and the dielectric material 136 respectively, and have been described in detail in the above paragraphs, and will not be described again here.

Referring to FIGS. 4A and 4B , when the three-dimensional memory device is a second type of three-dimensional NAND flash memory, the vertical channel structure 130C may include a charge storage structure 132 and a channel column 334 . As shown in FIG. 4A , the channel pillars 334 can penetrate the cap layer 116 , the stack structure 110 and the stop layer 102 , and partially extend into the buffer layer 100 . The charge storage structure 132 may be disposed between the channel pillar 334 and the capping layer 116 , between the channel pillar 334 and the stacked structure 110 , and between the channel pillar 334 and the stop layer 102 . From the perspective of cross-section FIG. 4B , the charge storage structure 132 may laterally surround the channel pillar 334 . The charge storage structure 132 between the channel pillar 334 and the stop layer 102 is removed. Channel post 334 directly contacts stop layer 102 . The materials of the charge storage structure 132 and the channel pillar 334 are the same as the materials of the charge storage structure 132 and the channel layer 134 respectively, and have been described in detail in the above paragraphs, and will not be described again here.

FIG. 5 is a schematic plan view of a three-dimensional memory device according to an embodiment of the present invention. 6A, 7A, 8A, 9A, 10A, 11A, 12A, and 13A are schematic cross-sectional views of the manufacturing process along the line A-A in FIG. 5 . 6B, 7B, 8B, 9B, 10B, 11B, 12B, and 13B are schematic cross-sectional views of the manufacturing process along the line B-B in FIG. 5 . FIG. 14 is a schematic plan view of a three-dimensional memory device according to another embodiment of the present invention. Figure 15 is a schematic plan view of a three-dimensional memory device according to an alternative embodiment of the present invention.

After the vertical channel structure 130 of FIG. 1 is formed, a gate replacement process may be performed to replace the sacrificial layer 114 in the stacked structure 110 with the conductor layer 154, as shown in FIGS. 5 to 14 .

First, please refer to FIG. 5 . The buffer layer 100 may include a first region R1 , a second region R2 and a third region R3 . The second region R2 may surround the first region R1, and the third region R3 may be disposed between the first region R1 and the second region R2. In an embodiment, the first region R1 may be an array region, the second region R2 may be an isolation ring region, and the third region R3 may be a step region. For the sake of clarity, the subsequent cross-sectional figures 6A to 13A only show the A-A tangent line in the first area R1, and the subsequent cross-sectional figures 6B to 13B only show the B-B tangent line in the second area R2, and omit the Vertical channel structure 130.

As shown in FIGS. 6A and 6B , after the vertical channel structure 130 is formed, the first opening 10 may be formed in the stacked structure 100 in the first region R1 , and the second opening 20 may be formed in the stacked structure 100 in the second region R2 . The method of forming the first opening 10 and the second opening 20 includes: forming a mask pattern 118 on the top cover layer 116; using the mask pattern 118 as a mask, performing a plasma etching process to remove part of the top cover layer 116 and part of the cover layer 116. The stacked structure 110 exposes a portion of the surface of the stop layer 102 . In one embodiment, the width W2 of the second opening 20 is greater than the width W1 of the first opening 10 . The ratio of the width W2 of the second opening 20 to the width W1 of the first opening 10 is greater than or equal to 2. For example, the width W1 of the first opening 10 is approximately 100 nm, and the width W2 of the second opening 20 is approximately 300 nm.

Specifically, as shown in FIG. 5 , the second opening 20 may include two first trenches 22 (which may be referred to as first slits) extending along the X direction and two second trenches 24 extending along the Y direction. (Can be called the second slit). The first trench 22 and the second trench 24 are separated from each other and not connected, thereby forming an unclosed slit ring structure. That is to say, there is a break 23 between the adjacent first trench 22 and the second trench 24 . It is worth noting that after the first opening 10 and the second opening 20 are formed, the stop layer 102 can still extend continuously between the array regions R1. Specifically, the stop layer 102 is located below the stacked structure 110 , and the first opening 10 and the second opening 20 only expose part of the surface of the stop layer 102 and do not extend into the buffer layer 100 . In other words, the stop layer 102 has not been cut off by the first opening 10 and/or the second opening 20 . Therefore, the stop layer 102 can be grounded to the silicon substrate in the subsequent high aspect ratio etching process to avoid arc effects. On the other hand, the first opening 10 may include a plurality of third trenches 12 (which may be referred to as third slits) extending along the X direction to separate the plurality of vertical channel structures 130 into a plurality of vertical channel structures 130 arranged along the Y direction. Memory cell area MR.

Although the first trench 22 and the second trench 24 shown in FIG. 5 are continuous trench structures or continuous slit structures, the present invention is not limited thereto. In other embodiments, the first trench 22 and the second trench 24 may also be a discontinuous trench structure or not a continuous slit structure, as shown in FIG. 15 .

Next, referring to FIGS. 7A and 7B , a dielectric material 120 is formed to fill the first opening 10 and the second opening 20 . Specifically, the dielectric material 120 includes a first material 120a and a second material 120b. The first material 120a conformally covers the surface of the first opening 10 and extends to cover the top surface of the top cover layer 116, and the second material 120b conformally covers the first material 120a, as shown in FIG. 7A. The first material 120a also conformally covers the surface of the second opening 20 and extends to cover the top surface of the top cover layer 116, and the second material 120b conformally covers the first material 120a, as shown in FIG. 7B. In one embodiment, the first material 120a and the sacrificial layer 114 are made of the same material, while the first material 120a and the second material 120b are different. For example, the first material 120a and the sacrificial layer 114 may be made of silicon nitride, and the second material 120b may be silicon oxide. In this embodiment, the dielectric material 120 is formed by a deposition method with high sidewall step coverage, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or a combination thereof.

It is worth noting that in this embodiment, the width W1 of the first opening 10 is smaller than the width W2 of the second opening 20 . Therefore, after the dielectric material 120 is formed, the dielectric material 120 fills the first opening 10 but does not fill the second opening 20 . In this case, the dielectric material 120 on the second opening 20 forms a recessed opening 25 .

Please refer to FIGS. 7A to 8A and 7A to 8B to perform a first etching process to remove part of the dielectric on the top surface of the top cover layer 116 (or the stacked structure 110 ) and the bottom surface 20bt of the second opening 20 Material 120 to form a first dielectric layer 140 in the first opening 10 and a second dielectric layer 150 (which may be called an insulating layer) on the sidewall of the second opening 20 . Specifically, the first dielectric layer 140 may include a first material layer 140a and a second material layer 140b. The second material layer 140b can penetrate the top cover layer 116 and the stacked structure 110, and the first material layer 140a covers the second material layer 140b and is in contact with the stacked structure 110 and the stop layer 102, as shown in FIG. 8A. In addition, the second dielectric layer 150 may include a first material layer 150a and a second material layer 150b. The first material layer 150a covers the sidewalls of the top cover layer 116 and the sidewalls of the stacked structure 110, while the second material layer 150b is disposed on the first material layer 150a, as shown in FIG. 8B. It is worth noting that in this embodiment, while the first dielectric layer 140 seals the first opening 10 , the second dielectric layer 150 exposes part of the stop layer 102 at the bottom surface 20bt of the second opening 20 . In one embodiment, the first etching process includes a comprehensive etching process. In alternative embodiments, the first etching process includes a dry etching process, a wet etching process, an isotropic etching process, an anisotropic etching process, or a combination thereof.

Referring to FIGS. 8A to 9A and 8B to 9B , the first dielectric layer 140 and the second dielectric layer 150 are used as masks to perform a second etching process to remove the bottom surface 20bt of the second opening 20 . stop layer 102, thereby forming a cavity 30. As shown in FIG. 9B , the cavity 30 extends laterally below the stacked structure 110 so that the width W3 of the cavity 30 is greater than the width W2 of the second opening 20 . In one embodiment, the second etching process includes: a dry etching process, a wet etching process, a chemical dry etching (CDE) process, or a combination of an oxidation process and a wet cleaning process. For example, the first material layers 140a and 150a (such as silicon nitride) can be used as the etching stop layer to perform a wet etching process of the HNA system (which includes an etchant of HNO ₃ /HF/H ₂ O ₂ ), and remove the The second material layers 140b, 150b (eg, silicon oxide) and the partial stop layer 102 (eg, polycrystalline silicon). On the other hand, the second material layer 140b, 150b (such as silicon oxide) or the first material layer 140a, 150a (such as silicon nitride) can also be used as an etching stop layer to perform an alkali metal hydroxide (Alkali Hydroxide) system. A wet etching process (which includes NaOH or KOH etchant) removes part of the stop layer 102 (eg, polycrystalline silicon). In this embodiment, the second material layers 140b and 150b still remain in the first opening 10 and the second opening 20, as shown in FIGS. 9A and 9B. In addition, a highly selective chemical dry etching (CDE) process may also be used to remove part of the stop layer 102 .

It is worth noting that after the second etching process is performed, the cavity 30 can connect the two first trenches 22 and the two second trenches 24 to form an annular opening (or closed ring) 40, as shown in the upper view 9C. In other words, the cavity 30 may extend from the end points of the first trench 22 and/or the second trench 24 to the fracture 23 (as shown in FIG. 5 ) to connect the first trench 22 and the second trench 24 . In this case, the stop layer 102 will be cut off by the annular opening 40 so that the stop layer 102 in the first region R1 is electrically isolated from the external stop layer 102 . In this embodiment, after the first opening 10 and the second opening 20 are formed, there is no high aspect ratio etching process that requires the stop layer 102 to be grounded to avoid the arc effect. Therefore, the stop layer 102 can be removed in this step. Truncated or divided to prevent adjacent stop layers 102 between adjacent areas from being electrically connected to each other, thereby affecting the operation of the memory device. In addition, since the cavity 30 extends from the end points of the first trench 22 and/or the second trench 24, the connection point 26 of the first trench 22 and the second trench 24 may have an arcuate outline, as shown in FIG. 9C Show.

Next, filling material 160 is formed. As shown in FIG. 10A , the filling material 160 covers the capping layer 116 and the first dielectric layer 140 . On the other hand, as shown in FIG. 10B , the filling material 160 extends from the top surface of the top cover layer 116 into the second opening 20 and fills the cavity 30 . In one embodiment, the filling material 160 includes silicon oxide, silicon nitride, silicon oxynitride and other similar dielectric materials, which are used to replace the hollowed stop layer 102 and thereby support the entire stack structure 110 .

Referring to FIGS. 10A to 11A and 10B to 11B, a wet etching process is performed to remove part of the filling material 160 and the second material layers 140b and 150b. In this case, as shown in FIG. 11A , the first material layer 140a still covers the sidewalls and bottom surface of the first opening 10, and the outer surface of the first material layer 140a is exposed. On the other hand, as shown in FIG. 11B , the second opening 20 extends downward into the filling material 160 a, and the outer surfaces of the first material layer 150 a and the filling material 160 a are exposed.

Referring to FIGS. 11A to 12A and 11B to 12B , an etching process is performed through the first opening 10 and the second opening 20 to remove the first material layers 140 a and 150 a and the sacrificial layer 114 to form a gap between the dielectric layer 112 Multiple voids (not shown) are formed. In one embodiment, the etching process may be a wet etching process. For example, when the first material layers 140a, 150a and the sacrificial layer 114 are silicon nitride, the etching process may be to use an etching solution containing phosphoric acid, and pour the etching solution into the first opening 10 and the second opening. in the opening 20, thereby removing the first material layers 140a, 150a and the sacrificial layer 114. Since the etching liquid has high etching selectivity for the first material layers 140a, 150a and the sacrificial layer 114, the first material layers 140a, 150a and the sacrificial layer 114 can be completely removed, while the dielectric layer 112, the stop layer 112 and the sacrificial layer 114 can be completely removed. 102 and the capping layer 116 are not removed or only slightly removed.

Then, the conductor layer 154 is formed in the above-mentioned gap, thereby completing the three-dimensional memory element of the present invention. In one embodiment, the material of the conductor layer 154 is, for example, polycrystalline silicon, amorphous silicon, tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide ( _WSix ) or cobalt silicide ( _CoSix ). In addition, before forming the conductor layer 154, a buffer layer and a barrier layer may be formed sequentially between the dielectric layer 112 and the conductor layer 154. The material of the buffer layer is, for example, a high dielectric constant material with a dielectric constant greater than 7, such as aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), lanthanum oxide (La ₂ O ₅ ), transition metal oxide, Lanthanide oxides or combinations thereof. The material of the barrier layer is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof.

In this embodiment, the three-dimensional memory device has a plurality of memory cells (not shown). The number of memory cells can be adjusted with the number of conductor layers 154 in the stacked structure 210, and the present invention is not limited thereto.

Referring to FIGS. 13A and 13B , after performing the gate replacement process, an isolation material 170 can be formed in the first opening 10 and the second opening 20 (or the annular opening 40 ). In one embodiment, the isolation material 170 may be the same as the filling material 160a, such as silicon oxide. In this case, the isolation material 170 may contact the filling material 160a to form an isolation ring structure 180, as shown in FIGS. 14 and 13B.

In an alternative embodiment, the formation method of the isolation ring structure 180 may also include: forming a liner (such as silicon oxide) to conformally cover the surfaces of the first opening 10 and the second opening 20 (or the annular opening 40 ); Remove part of the lining layer at the bottom surfaces of the first opening 10 and the second opening 20 ; and form a metal layer (eg, W) in the first opening 10 and the second opening 20 so that the metal layer contacts the stop layer 102 .

To sum up, in this embodiment, the first opening and the second opening are simultaneously formed in the array area and the isolation ring area, so that the gate replacement process can be performed through the first opening and the second opening. The second opening may include an unclosed slit ring structure to prevent the discharge layer from being cut off by the second opening, thereby preventing arcing effects. In addition, this embodiment can perform a subsequent etching process to remove the discharge layer exposed at the bottom surface of the second opening, thereby forming a cavity. The cavity can laterally penetrate the unsealed slit ring structure to form a ring-shaped opening, thereby electrically or physically separating the discharge layer in the array region and the discharge layer in the outer region. In this case, this embodiment can avoid the arc effect when cutting the discharge layer, thereby improving the reliability of the three-dimensional memory element.

10:First opening 12:Third ditch 20:Second opening 20bt: Bottom 22:First ditch 23: Fracture 24:Second ditch 25: concave opening 26:Connection point 30:Cavity 40: Annular opening 100:Buffer layer 102: Stop layer 110, 210: stacked structure 112: Dielectric layer 114:Sacrificial layer 115:Open your mouth 116:Cover 120:Dielectric materials 120a: First material 120b: Second material 130, 130A, 130B, 130C: vertical channel structure 132:Charge storage structure 133: First source/drain column 134: Channel layer 135: Second source/drain column 136:Dielectric materials 140: First dielectric layer 140a, 150a: first material layer 140b, 150b: second material layer 150: Second dielectric layer 154: Conductor layer 160, 160a: filling material 170:Isolation materials 180:Isolation ring structure 234:Channel structure 234A: Lining 234B:Plug 236:Dielectric pillar 334:Channel column MR: memory cell area R1: The first area R2:Second area R3: The third area W1, W2, W3: Width X, Y: direction

FIG. 1 is a schematic cross-sectional view of a three-dimensional memory device according to an embodiment of the present invention. 2A, 3A and 4A are schematic cross-sectional views of vertical channel structures according to various embodiments of the present invention. Figures 2B, 3B and 4B are schematic plan views of Figures 2A, 3A and 4A respectively. FIG. 5 is a schematic plan view of a three-dimensional memory device according to an embodiment of the present invention. 6A, 7A, 8A, 9A, 10A, 11A, 12A, and 13A are schematic cross-sectional views of the manufacturing process along the line A-A in FIG. 5 . 6B, 7B, 8B, 9B, 10B, 11B, 12B, and 13B are schematic cross-sectional views of the manufacturing process along the line B-B in FIG. 5 . Figure 9C is a schematic plan view of the structure of Figures 9A and 9B. FIG. 14 is a schematic plan view of a three-dimensional memory device according to another embodiment of the present invention. Figure 15 is a schematic plan view of a three-dimensional memory device according to an alternative embodiment of the present invention.

10:First opening

12:Third ditch

20:Second opening

22:First ditch

23: Fracture

24:Second ditch

100:Buffer layer

130: Vertical channel structure

MR: memory cell area

R1: The first area

R2:Second area

R3: The third area

X, Y: direction

Claims (10)

A method for forming a three-dimensional memory element, including: providing a buffer layer having a first region and a second region, wherein the second region surrounds the first region; A stop layer and a stacked structure including a plurality of alternately stacked dielectric layers and a plurality of sacrificial layers are formed on the buffer layer, wherein the stacked structure includes at least one vertical channel structure to penetrate all the elements in the first region. The stacking structure; A first opening is formed in the stacked structure of the first region, and a second opening is formed in the stacked structure of the second region, wherein the width of the second opening is greater than the width of the first opening. width; forming a dielectric material to fill the first opening and the second opening; Perform a first etching process to remove at least a portion of the dielectric material on the bottom surface of the second opening to expose a portion of the stop layer, thereby forming a first dielectric layer in the first opening and forming a second dielectric layer on the sidewall of the second opening; and A second etching process is performed to remove the stop layer exposed at the bottom surface of the second opening, thereby forming a cavity, wherein the cavity extends laterally below the stacked structure such that the The cavity connects the second opening to form a closed ring. The method of forming a three-dimensional memory element according to claim 1, wherein the first region includes an array region, and the second region includes an isolation ring region. The method of forming a three-dimensional memory element according to claim 2, wherein the second opening includes two first trenches extending along the X direction and two second trenches extending along the Y direction, and the two first trenches extend along the Y direction. The first trench and the two second trenches are separated from each other. The method of forming a three-dimensional memory element according to claim 3, wherein after performing the second etching process, the cavity connects the two first trenches and the two second trenches to form the Said closed loop. The method of forming a three-dimensional memory element according to claim 1, wherein after forming the closed ring, the forming method further includes: forming a filling material to fill the cavity. The method of forming a three-dimensional memory element according to claim 1, wherein the material of the stop layer includes a conductor material. A method for forming a three-dimensional memory element, including: Forming a discharge layer and a stacked structure on the buffer layer, wherein the stacked structure includes a plurality of alternately stacked dielectric layers and a plurality of sacrificial layers; forming a plurality of vertical channel structures in the stacked structure; An opening is formed in the stacked structure, wherein the opening includes two first slits extending along the X direction and two second slits extending along the Y direction, and the two first slits and The two second slits are separated from each other; forming an insulating layer on the sidewall of the opening, wherein the insulating layer exposes the discharge layer at the bottom surface of the opening; The discharge layer exposed at the bottom surface of the opening is removed to form a cavity, wherein the cavity extends below the stacked structure to connect the two first slits and the two second slits, thus forming an annular opening; Performing a gate replacement process to replace the plurality of sacrificial layers in the stacked structure with a plurality of conductor layers, wherein the plurality of conductor layers respectively surround the plurality of vertical channel structures to form a plurality of memory cells; as well as Isolation material is filled into the annular opening to form an isolation ring structure. The method of forming a three-dimensional memory element as claimed in claim 7, wherein each first slit includes a continuous slit structure or a discontinuous slit structure. The method of forming a three-dimensional memory element as claimed in claim 7, wherein each second slit includes a continuous slit structure or a discontinuous slit structure. The method of forming a three-dimensional memory element according to claim 7, wherein the material of the discharge layer includes a conductor material, and the conductor material includes a semiconductor material including polycrystalline silicon, a III-V compound semiconductor, or a combination thereof.