TWI813010B - Integrated circuits and method for manufacturing the same - Google Patents

Abstract

An integrated circuit includes a first-type active-region structure, a second-type active-region structure on a substrate, and a plurality of gate-conductors. The integrated circuit also includes a backside horizontal conducting line in a backside first conducting layer below the substrate, a backside vertical conducting line in a backside second conducting layer below the backside first conducting layer, and a pin-connector for a circuit cell. The pin-connector is directly connected between the backside horizontal conducting line and the backside vertical conducting line. The backside horizontal conducting line extends across a vertical boundary of the circuit cell.

Description

Integrated circuits and manufacturing methods

Embodiments of the present disclosure relate to an integrated circuit, and in particular, to a backside conductor in an integrated circuit.

The recent trend in the miniaturization of integrated circuits (ICs) has resulted in devices that are smaller and consume less power, but can provide more functionality at faster speeds. The miniaturization process also leads to tighter design and manufacturing specifications and reliability challenges. Various electronic design automation (EDA) tools generate, optimize and verify standard cell layout designs for integrated circuits, while ensuring that standard cell layout design and manufacturing specifications are met.

The purpose of the embodiments of the present disclosure is to provide an integrated circuit including a first type active area structure, a second type active area structure, a first layer of front conductors, a plurality of gate conductors, a circuit unit, a back side horizontal conductor, a back side Side vertical wires and pin connectors. Type 1 active area structure and a Type 2 active area The zone structure extends along the first direction on the substrate. The first layer of wires on the front side is in the first connection layer above the substrate. A plurality of gate conductors extend along the second direction below the first connection layer, and two adjacent gate conductors are spaced apart by a distance equal to a contact poly pitch (CPP). The circuit unit has a first vertical boundary and a second vertical boundary extending along a second direction perpendicular to the first direction. Each of the first vertical boundary and the second vertical boundary spans at least one boundary isolation area along the first The distance between the first vertical boundary and the second vertical boundary of the direction is less than or equal to three times the contact poly pitch (CPP). The backside horizontal conductive line extends along the first direction in the backside first conductive layer under the substrate, and the backside horizontal conductive line extends across the first vertical boundary of the circuit unit. The backside vertical conductive lines extend along the second direction in the backside second conductive layer below the backside first conductive layer, and the backside vertical conductors are aligned with the first vertical boundary. Pin connectors are used in circuit units. The pin connector is directly connected between the backside horizontal conductor and the backside vertical conductor.

The purpose of the embodiments of the present disclosure is to provide an integrated circuit that includes a first-type active area structure, a second-type active area structure, a first layer of front-side conductors, a plurality of gate conductors, circuit units, and back-side horizontal conductors. Vertical wire and pin connectors on the back. The first type active area structure and a second type active area structure extend along the first direction on the substrate. The first layer of wires on the front side is in the first connection layer above the substrate. A plurality of gate conductors extend along the second direction below the first connection layer, and two adjacent gate conductors are spaced apart by a distance equal to a contact poly pitch (CPP). The circuit unit has a second direction along a direction perpendicular to the first The first vertical boundary and the second vertical boundary extend in a direction, and each of the first vertical boundary and the second vertical boundary spans at least one boundary isolation area. The backside horizontal wire extends along the first direction in the backside first conductive layer below the substrate. The backside vertical conductive lines extend along the second direction in the backside second conductive layer below the backside first conductive layer. Pin connectors are used in circuit units. The pin connector is directly connected between the backside horizontal conductor and the backside vertical conductor at an overlap region between the backside horizontal conductor and the backside vertical conductor. The backside horizontal conductor has a first portion covering the overlapping area and the backside horizontal conductor has a second portion outside the overlapping area, and a first width of the first portion along the first direction is greater than a second width of the second portion along the first direction.

The purpose of embodiments of the present disclosure is to provide a method for manufacturing an integrated circuit, which includes: manufacturing a first-type active area structure and a second-type active area structure extending along a first direction on a substrate; manufacturing a first-type active area structure and a second-type active area structure extending along a first direction; A plurality of gate conductors extending in a second direction in the first direction, each gate conductor intersecting with the first type active region structure and/or the second type active region structure above the substrate, two of the plurality of gate conductors are adjacent They are spaced apart by a spacing distance and the spacing distance is equal to the contact poly pitch (CPP); a backside horizontal conductor extending along the first direction is manufactured in the backside first conductive layer under the substrate; a backside connection is made pin connectors for horizontal conductors; and manufacturing backside vertical conductors extending along the second direction in the backside second conductive layer below the backside first conductive layer, wherein the backside vertical conductors are aligned with the first side of the circuit unit a vertical boundary, wherein the pin connector is directly connected between the backside horizontal conductor and the backside vertical conductor at an overlap region between the backside horizontal conductor and the backside vertical conductor; wherein manufacturing the backside horizontal conductor includes placing the backside horizontal conductor The side horizontal conductors are fabricated as extension conductors that extend across the first vertical boundary of the circuit cell at a distance less than the contact poly pitch (CPP).

20,40:Power rail

50:Substrate

52:Insulation layer

54,56: Backside interlayer dielectric

80n: n-type active area structure

80p: p-type active area structure

100,400: Inverse OR gate circuit

110:Unit boundary

111,119: Vertical cell boundary

122,124,126,522,524,526,622,624,626,722,724,726: The first layer of wires on the front side

132n,132p,135n,135p,138,532n,532p,535n,535p,538,632,635n,635p,638,735n,735p,738: Terminal conductor

151,159: Dummy gate conductor

152,158,552,558,652,658,758: Gate conductor

151i,159i:Border quarantine area

172,175,178,572,575,578,672,675,678,775,778,972,975,978: Backside vertical wire

178A,805,978A:Part 1

178B,978B:Part 2

181,182,184,186,581,582,584,586,681,682,684,686,782,784,786,981,982,984,986: Dorsal horizontal wire

500: Anti-AND gate circuit

600,700:Inverter circuit

800:Process

810,820,832,834,836,838: Operation

895:Remainder

900: unit

902:original position

908:Alternate position

1000:Method

1010,1022,1024,1030,1040,1050,1060,1070,1080: Operation

1100:EDA system

1102: Processor

1104:Storage media

1106:Instruction

1107:Standard cell library

1108:Bus

1109:Layout drawing

1110: Input/output (I/O)

1112:Network interface

1114:Internet

1142: User interface (UI)

1200:IC manufacturing system

1220:Design room

1222:IC design layout diagram

1230:Mask room

1232: Data preparation

1244:Mask manufacturing

1245:mask

1250:IC Manufacturer/Manufacturer

1252: Manufacturing tools

1253:wafer

1260:IC device

1BV0A,1BV0B,1BV0C,1BVD1,1BVG1,1BVG2,1VD1,1VD2,1VDdd,1VDss,5BV0A,5BV0B,5BV0C,5BVD1,5BVG1,5BVG2,5VD1,5VD2,5VDdd,5VDss,6BV0A,6 BV0B,6BV0C,6BVD1,6BVG1, 6BVG2,6VD1,6VD2,6VDdd,6VDss,7BV0A,7BV0B,7BVD1,7BVG1,7VDdd,7VDss, 9BV0A: Through hole connector

A-A’, B-B’, C-C’, D-D’, E-E’, P-P’, Q-Q’, R-R’: cutting plane

A1,A2,IN: input signal/input node

CPP: contact polycrystalline spacing

nA1, nA2: n-type transistor

pA1, pA2: p-type transistor

W: Width

Wa: first width

Wb: second width

X,Y,Z: direction

ZN: Output signal/output node

Δ: distance

Aspects of the present disclosure are best understood from the following detailed description, taken in conjunction with the accompanying drawings. Note that in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for the sake of clarity of discussion.

Figures 1A to 1B are layout diagrams of an inverse-OR gate circuit according to some embodiments.

Figure 1C is an equivalent circuit diagram of the inverse-OR gate circuit specified by the layout diagrams of Figures 1A-1B, according to some embodiments.

Figures 2A-2E are cross-sectional views along cutting planes of the inverter circuit specified by the layout diagrams of Figures 1A-1B, according to some embodiments.

Figures 3A-3C are cross-sectional views along cutting planes of the inverter circuit specified by the layout diagrams of Figures 1A-1B, according to some embodiments.

Figures 4A to 4E are layout diagrams of an inverse-OR gate circuit according to some embodiments.

Figures 5A to 5B are layout diagrams of an NAND gate circuit according to some embodiments.

Figures 6A-6B are layout diagrams of inverter circuits according to some embodiments.

Figures 7A-7B are layout diagrams of inverter circuits according to some embodiments.

Figure 8 is a flowchart of a process for designing integrated circuits according to some embodiments.

Figures 9A-9C are layout diagrams of cells according to some embodiments.

Figure 10 is a flow diagram of a method of manufacturing an integrated circuit in accordance with some embodiments.

Figure 11 is a block diagram of an electronic design automation system in accordance with some embodiments.

Figure 12 is a block diagram of an integrated circuit (IC) manufacturing system and an IC manufacturing process associated therewith, in accordance with some embodiments.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to limit the disclosure. For example, in the description, a first feature is formed on or over a second feature. This may include embodiments in which the first feature is formed in direct contact with the second feature. This may also include embodiments in which additional features may be formed on the second feature. Embodiments between one feature and a second feature such that the first feature and the second feature may not be in direct contact. In addition, this disclosure may repeat reference numbers and/or text in various examples. This repetition is for the purposes of brevity and clarity, but is not intended per se to designate the various embodiments and/or architectures discussed. relationship between structures.

Furthermore, spatial relative terms may be used here, such as "beneath", "below", "lower", "above", "upper", etc. etc., to facilitate explanation of the relationship between one element or feature and another (other) elements or features as shown in the drawings. These spatially relative terms are intended to encompass, in addition to the directions depicted in the drawings, different orientations of the device in use or operation. The device may be oriented differently (for example, rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

In some embodiments, the integrated circuit includes a plurality of gate-conductors and a plurality of terminal-conductors at the front side of the substrate. The integrated circuit also includes a plurality of backside horizontal conductors in the backside first conductive layer and a plurality of backside vertical conductors in the backside second conductive layer at the backside of the substrate. The backside vertical conductor of interest is aligned with the first vertical boundary of the circuit unit, and the backside vertical conductor of interest is connected to the backside horizontal conductor of interest through the pin connector. In some embodiments, the backside horizontal conductor of interest is an extension conductor that extends across the first vertical boundary of the circuit cell. In some embodiments, the backside vertical conductor of interest is a local two-dimensional conductor having a first portion and a second portion, the first portion having a first width, and the second portion having a different width. The second width of the first width. In some embodiments, greater flexibility in positioning of the pin connector is provided due to the extended conductors and/or the area 2D conductors without Design rule violations will occur.

Figures 1A to 1B are layout diagrams of a NOR gate circuit 100 according to some embodiments. The layout diagrams of FIGS. 1A to 1B include a plurality of layout patterns for specifying a p-type active region structure 80p and an n-type active region structure 80n extending in the X direction, and a plurality of layout patterns extending in the Y direction. gate conductors (152 and 158), terminal conductors (132p, 132n, 135p, 135n and 138) extending in the Y direction, and dummy gate conductors (151 and 159) extending in the Y direction. The NOR gate circuit 100 is located in a cell bounded by a cell boundary 110, and the cell width along the X direction is bounded by two vertical cell boundaries 111 and 119 extending in the Y direction. The layout diagram of Figure 1A also includes a plurality of layout patterns for specifying the power rails (40 and 20) extending in the X direction, the front first layer conductors (122, 124 and 126), and various via-connectors. The layout diagram of Figure 1B also includes a plurality of layout patterns for specifying backside horizontal conductors (181, 182, 184, and 186) extending in the X direction, and backside vertical conductors extending in the Y direction. (172, 175 and 178), and various through-hole connectors. In the X-Y coordinate, the X direction and the Y direction are perpendicular to each other.

In the inverse-OR gate circuit 100 specified in the layout diagrams of Figures 1A-1B, two adjacent gate conductors (eg, gate conductors 152 and 158) are separated by a separation distance equal to the contact poly Pitch (contacted poly pitch, CPP). In the inverse-OR gate circuit 100, the relationship between the vertical cell boundary 111 and the vertical cell boundary 119 along the The distance between them is three times the contact polycrystalline spacing (CPP).

Figure 1C is an equivalent circuit diagram of the inverter circuit 100 specified by the layout diagrams of Figures 1A-1B, according to some embodiments. Figures 2A to 2E and Figures 3A to 3C are cross-sectional views of the inverter circuit 100 specified by the layout diagram of Figures 1A to 1B according to some embodiments.

In the inverter circuit 100 specified in the layout diagrams of Figures 1A-1B and in the inverter circuit 100 shown in the equivalent circuit diagram of Figure 1C, the gate conductor 152 is in the p-type transistor. The channel region of pA1 intersects with the p-type active region structure 80p, and intersects with the n-type active region structure 80n at the channel region of the n-type transistor nA1. Gate conductor 158 intersects p-type active region structure 80p at the channel region of p-type transistor pA2 and intersects n-type active region structure 80n at the channel region of n-type transistor nA2. Terminal conductors 132p and 135p intersect p-type active region structure 80p at respective source/drain regions of p-type transistors pA2 and pA1. Terminal conductors 132n and 135n intersect n-type active region structure 80n at respective source/drain regions of n-type transistors nA2 and nA1. The terminal conductor 138 intersects the p-type active region structure 80p and the n-type active region structure 80n at the drain region of the p-type transistor pA1 and the drain region of the n-type transistor nA1, respectively. Non-limiting examples of p-type transistors (pA1 and pA2) and n-type transistors (nA1 and nA2) include fin field effect transistors (FinFETs), nano-sheet transistors, and nanowires -wire) transistor. The layout patterns used for dummy gate conductors 151 and 159 in FIGS. 1A-1B designate multiple active regions in the NOR gate circuit 100 (e.g., source region, drain region and channel region), the plurality of active regions are isolated from active regions in adjacent cells.

In the inverter circuit 100 specified in the layout diagrams of Figures 1A-1B and in the inverter circuit 100 shown in the equivalent circuit diagram of Figure 1C, the front side first layer conductors (122, 124 and 126) and the power rails (40 and 20) are located in the first connection layer above the substrate. In some embodiments, the first connection layer is a first metal layer (MO) above the top insulating layer fabricated in a front-end-of-line (FEOL) process. In the NOR circuit 100, the terminal conductor 132p is electrically connected to the power rail 40 through the through-hole connector 1VDdd, and the power rail 40 is configured to provide the first supply voltage VDD. The terminal conductor 135n is electrically connected to the power rail 20 through the through-hole connector 1VDss, and the power rail 20 is configured to provide the second supply voltage VSS. The front first layer wire 126 is electrically connected to the terminal conductor 132n through the through-hole connector 1VD1, and is electrically connected to the terminal conductor 138 through the through-hole connector 1VD2.

In the NOR circuit 100, the terminal conductor 138 (in FIG. 1A) is also conductively connected to the backside horizontal conductor 182 (in FIG. 1B) through the through-substrate through-hole connector 1BVD1. Additionally, gate conductor 152 (in FIG. 1A ) is electrically connected to the backside horizontal conductor 184 (in FIG. 1B ) through through-hole connector 1BVG1 and gate conductor 158 (in FIG. 1A ) through the through-hole Connector 1BVG2 is electrically connected to the backside horizontal conductor 186 (in Figure 1B).

In the NOR gate circuit 100, the backside horizontal conductor 182 is electrically connected to the backside vertical conductor 178 through the through-hole connector 1BV0A. dorsal water The flat conductor 184 is electrically connected to the backside vertical conductor 172 through the through-hole connector 1BV0B. The backside horizontal conductor 186 is electrically connected to the backside vertical conductor 175 through the through-hole connector 1BV0C.

In the NOR gate circuit 100, the backside horizontal conductors 181, 182, 184 and 186 are located in the backside first conductive layer below the substrate. Backside vertical conductors 172, 175, and 178 are located in the backside second conductive layer below the backside first conductive layer. In some embodiments, the first backside conductive layer is a first backside metal layer (BM0) fabricated at the backside of the substrate, and the backside second conductive layer is a second backside metal layer (BM0) fabricated at the backside of the substrate. Side metal layer (BM1). The first backside metal layer (BM0) is sandwiched between the substrate and the second backside metal layer (BM1). Each of through-hole connectors 1BV0A, 1BV0B, and 1BV0C is a through-hole connector BV0 through an interlayer dielectric (ILD) material that connects the second backside metal layer (BM1) and the first backside metal layer (BM0) are separated.

In the inverse-OR gate circuit 100, the backside vertical conductor 172, the through-hole connector 1BV0B and the backside horizontal conductor 184 are conductively connected together to carry the input signal “A1” of the inverse-OR gate circuit 100. The backside vertical conductor 175, the through-hole connector 1BV0C and the backside horizontal conductor 186 are conductively connected together to carry the input signal "A2" of the inverter circuit 100. The backside vertical conductor 178 , the through-hole connector 1BV0A and the backside horizontal conductor 182 are electrically connected together to carry the output signal “ZN” of the inverter circuit 100 .

In the NOR circuit 100, the through-hole connector 1BV0A (shown in FIG. 1C) is used as a pin-connector extending along the Z direction for connecting the backside vertical conductor 178 to the socket. The backside horizontal conductor 182 carries the output signal "ZN" of the inverter circuit 100 . In some embodiments, as shown in Figure 1B, when the backside horizontal conductors 182 extend across the vertical cell boundary 119, greater flexibility is provided for the positioning of the pin connector (ie, through-hole connector 1BV0A) , without generating design rule violations. In FIG. 1B , the backside horizontal conductor 182 extends along the X direction across the vertical cell boundary 119 at a distance "Δ". In some embodiments, the backside horizontal conductor 182 extends across the vertical cell boundary 119 a distance "Δ" that is less than one contact poly pitch (CPP) but greater than one-eighth of the contact poly pitch (CPP). In some embodiments, the backside horizontal conductor 182 extends across the vertical cell boundary 119 a distance "Δ" that is less than one contact poly pitch (CPP) but greater than one quarter of the contact poly pitch (CPP). In some embodiments, the backside horizontal conductor 182 extends across the vertical cell boundary 119 by a distance "Δ" that is less than one contact poly pitch (CPP) but greater than half the contact poly pitch (CPP). In some embodiments, distance "Δ" is selected to be large enough to mitigate design rule violations associated with pin connector connections between backside vertical conductors 178 and backside horizontal conductors 182 . In some embodiments, distance "Δ" is selected to be less than one contact poly pitch (CPP) such that the horizontal gap distance from vertical cell boundary 119 to the vertical cell boundary of an adjacent cell is reduced to a minimum distance of Mitigates design rule violations associated with pin connector connections.

In Figure 1B, the backside vertical conductor 178 has a width "W" extending in the X direction. In some embodiments, the width “W” is selected to reduce IR drops in the backside vertical conductors 178 . In some embodiments, the width "W" of the backside vertical conductor 178 is greater than the contact width half of the intercrystalline spacing (CPP). In some embodiments, the width "W" of the backside vertical conductors 178 is greater than three-quarters of the contact poly pitch (CPP). Generally speaking, the larger the width "W", the smaller the voltage drop (IR drops) in the backside vertical conductor 178. However, if the number of backside vertical conductor tracks in the unit is fixed, the spacing requirements between two adjacent backside vertical conductors limit the maximum value of the width "W". Reducing the number of tracks increases the maximum width "W" but also reduces the routing flexibility of the unit design. In some embodiments, a compromise between routing flexibility and IR drops requirements determines the maximum value of the width "W".

Figure 2A is a cross-sectional view of the inverter circuit 100 along cutting plane A-A' as specified in the layout diagram of Figures 1A-1B, according to some embodiments. As shown in FIG. 2A, the p-type active region structure 80p is located on the substrate 50. Each of terminal conductors 132p, 135p, and 138 intersects p-type active region structure 80p. Each of gate conductors 152 and 158 also intersects p-type active region structure 80p. In some embodiments, the active region (eg, source region, channel region, or drain region) in the p-type active region structure 80p passes through the boundary isolation region 151i under the dummy gate conductor 151 and the dummy gate conductor 151 A boundary isolation area 159i below 159 is separated from the active areas in adjacent cells. The first layer of wires 122 on the front side is covered with the insulating layer 52, and the insulating layer 52 covers the gate conductors (152 and 158) and the terminal conductors (132p, 135p and 138). Backside vertical conductors 172 , 175 , and 178 are located on backside interlayer dielectric 56 covering backside interlayer dielectric 54 at the backside of substrate 50 .

FIG. 2B is a cross-sectional view of the inverter circuit 100 specified in the layout diagram of FIGS. 1A-1B along cutting plane B-B, according to some embodiments. As shown in Figure 2B, the n-type active region structure 80n is located on the substrate 50. Each of terminal conductors 132n, 135n, and 138 intersects n-type active region structure 80n. Each of gate conductors 152 and 158 also intersects n-type active region structure 80n. In some embodiments, the active region (eg, source region, channel region, or drain region) in the n-type active region structure 80n is isolated 151i by a boundary isolation region under the dummy gate conductor 151 and the dummy gate A boundary isolation region 159i beneath conductor 159 is separated from active regions in adjacent cells. The first layer of wires 126 on the front side covers the insulating layer 52, and the insulating layer 52 covers the gate conductors (152 and 158) and the terminal conductors (132n, 135n and 138). Backside vertical conductors 172 , 175 , and 178 are located on backside interlayer dielectric 56 covering backside interlayer dielectric 54 at the backside of substrate 50 .

Figure 2C is a cross-sectional view of the inverter circuit 100 along cutting plane C-C' as specified in the layout diagram of Figures 1A-1B, according to some embodiments. As shown in Figure 2C, the insulating layer 52 covers the gate conductors (152 and 158), the terminal conductors (132p, 135p and 138) and the dummy gate conductors (151 and 159). Backside horizontal conductors 181 and 182 are located at the backside of the substrate 50 . Portions of backside interlayer dielectric 54 separate backside horizontal conductors 181 and backside horizontal conductors 182 . The backside vertical conductors 172, 175, and 178 are located on the backside interlayer dielectric 56, and the backside interlayer dielectric 56 covers the backside interlayer dielectric 54 and the backside horizontal conductors 181 and 182. Through-hole connector 1BVD1 passes through substrate 50 and connects terminal conductors 138 to the backside Horizontal wires 182 are electrically connected. Through-hole connector 1BV0A passes through the backside interlayer dielectric 56 and electrically connects the backside horizontal conductor 182 to the backside vertical conductor 178 .

Figure 2D is a cross-sectional view of the inverter circuit 100 along cutting plane D-D' as specified in the layout diagram of Figures 1A-1B, according to some embodiments. As shown in Figure 2D, the insulating layer 52 covers the gate conductors (152 and 158), the terminal conductor 138 and the dummy gate conductors (151 and 159). Backside horizontal conductors 184 are located at the backside of substrate 50 . The backside vertical conductors 172, 175, and 178 are located on the backside interlayer dielectric 56, and the backside interlayer dielectric 56 covers the backside interlayer dielectric 54 and the backside horizontal conductors 184. Through-hole connector 1BVG1 passes through substrate 50 and electrically connects gate conductor 152 to backside horizontal conductor 184 . The through-hole connector 1BV0B passes through the backside interlayer dielectric 56 and conductively connects the backside horizontal conductor 184 and the backside vertical conductor 172 .

Figure 2E is a cross-sectional view of the inverter circuit 100 along cutting plane E-E' as specified in the layout diagram of Figures 1A-1B, according to some embodiments. As shown in Figure 2E, the insulating layer 52 covers the gate conductors (152 and 158), the terminal conductors (132n, 135n and 138) and the dummy gate conductors (151 and 159). Backside horizontal conductors 186 are located at the backside of substrate 50 . Backside vertical conductors 172, 175, and 178 are located on backside interlayer dielectric 56, which covers backside interlayer dielectric 54 and backside horizontal conductors 186. Through-hole connector 1BVG2 passes through substrate 50 and electrically connects gate conductor 158 to backside horizontal conductor 186 . Through-hole connector 1BV0C passes through the backside interlayer dielectric 56 and connects the backside horizontal conductors 186 It is electrically connected to the backside vertical wire 175 .

Figure 3A is a cross-sectional view of the inverter circuit 100 along the cutting plane P-P' as specified in the layout diagram of Figures 1A-1B, according to some embodiments. As shown in FIG. 3A , the terminal conductor 132n intersects the n-type active region structure 80n on the substrate 50, and the terminal conductor 132p intersects the p-type active region structure 80p on the substrate 50. Insulating layer 52 covers terminal conductors 132n and 132p. The power rails (40 and 20) and the front first layer conductors 122 and 126 are located in the first connection layer above the insulating layer 52. The through-hole connector 1VDdd passes through the insulating layer 52 and electrically connects the terminal conductor 132p to the power rail 40. Backside horizontal conductors 181 , 184 and 186 are located at the backside of substrate 50 . The backside interlayer dielectric 54 and the backside horizontal conductors 181 , 184 and 186 are covered by the backside interlayer dielectric 56 . Backside vertical conductors 172 cover the backside interlayer dielectric 56 . The through-hole connector 1BV0B passes through the backside interlayer dielectric 56 and conductively connects the backside horizontal conductor 184 and the backside vertical conductor 172 .

Figure 3B is a cross-sectional view of the inverter circuit 100 along cutting plane Q-Q' as specified in the layout diagram of Figures 1A-1B, according to some embodiments. As shown in FIG. 3B , the terminal conductor 135n intersects the n-type active region structure 80n on the substrate 50 , and the terminal conductor 135p intersects the p-type active region structure 80p on the substrate 50 . The insulating layer 52 covers the terminal conductors 135n and 135p. The power rails (20 and 40) and the front first layer conductors 122, 124 and 126 are located in the first connection layer above the insulating layer 52. The through-hole connector 1VDss passes through the insulating layer 52 and electrically connects the terminal conductor 135n to the power rail 20 . Backside horizontal conductors 184 and 186 are located on the backside of substrate 50 side. Backside interlayer dielectric 54 and backside horizontal conductors 184 and 186 are covered by backside interlayer dielectric 56 . Backside vertical conductors 175 cover the backside interlayer dielectric 56 . The through-hole connector 1BVOC passes through the backside interlayer dielectric 56 and conductively connects the backside horizontal conductor 186 and the backside vertical conductor 175 .

Figure 3C is a cross-sectional view of the inverter circuit 100 along cutting plane R-R' as specified in the layout diagram of Figures 1A-1B, according to some embodiments. As shown in FIG. 3C , the terminal conductor 138 intersects the n-type active region structure 80n and the p-type active region structure 80p on the substrate 50 . Insulating layer 52 covers terminal conductors 138 . The power rails (20 and 40) and the front first layer conductors 124 and 126 are located in the first connection layer above the insulating layer 52. Backside horizontal conductors 182 , 184 and 186 are located at the backside of substrate 50 . The through-hole connector 1BVD1 passes through the substrate 50 and electrically connects the terminal conductor 138 to the backside horizontal conductor 182 . The backside interlayer dielectric 54 and the backside horizontal conductors 182 , 184 and 186 are covered by the backside interlayer dielectric 56 . Backside vertical conductors 178 cover the backside interlayer dielectric 56 . The through-hole connector 1BV0A passes through the backside interlayer dielectric 56 and conductively connects the backside horizontal conductor 182 and the backside vertical conductor 178 .

In the NOR circuit 100 specified by the layout diagrams of FIGS. 1A-1B , the backside vertical conductors 178 have a uniform width "W" at the backside of the substrate 50 . In some alternative embodiments, at least one backside vertical conductor includes a first portion having a first width and a second portion having a second width, and the first width of the first portion is greater than the second width of the second portion. As an example, in the inverter circuit specified by the layout diagrams of Figures 4A through 4E (which are described in more detail below), the backside vertical conductors The first portion of backside vertical conductor 178 has a first width "Wa" and the second portion of backside vertical conductor 178 has a second width "Wb", where the first width "Wa" is greater than the second width "Wb".

Figures 4A to 4E are layout diagrams of an inverter circuit 400 according to some embodiments. Each of the layout diagrams in FIGS. 4A-4E includes a plurality of layout patterns for specifying backside horizontal conductors (181, 182, 184, and 186) and backside vertical conductors (172, 175, and 178). The layout of the multiple components of the inverse-OR circuit 400 on the back side of the substrate (as shown in FIGS. 4A to 4E ) is different from the layout of the multiple components of the inverse-OR circuit 100 on the back side of the substrate (as shown in FIGS. 4A to 4E ). (shown in Figure 1B). However, the layout of the components of the NOR circuit 400 at the front side of the substrate is the same as the layout of the components of the NOR circuit 100 at the front side of the substrate (as shown in FIG. 1A ). Therefore, for the inverse-OR gate circuit 400, the layout of the multiple components on the back side of the substrate is described in detail only with reference to the layout diagrams of FIGS. 4A to 4E, and the layout of the multiple components on the front side is no longer referred to. The front layout diagram explains.

As specified in the layout diagrams of Figures 4A-4E, the inverter circuit 400 includes backside horizontal conductors 181, 182, 184, and 186 in the backside first conductive layer beneath the substrate. The inverter circuit 400 also includes backside vertical conductors 172, 175, and 178 in the backside second conductive layer below the backside first conductive layer. The gate conductor 152 is electrically connected to the backside horizontal conductor 184 through the through-hole connector 1BVG1, and the backside horizontal conductor 184 is electrically connected to the backside vertical conductor 172 through the through-hole connector 1BV0B. Gate conductor 158 is connected to the backside horizontal conductor through through hole connector 1BVG2 The line 186 is electrically connected, and the backside horizontal wire 186 is electrically connected to the backside vertical wire 175 through the through-hole connector 1BV0C. Terminal conductor 138 (in FIG. 1A ) is electrically connected to backside horizontal conductor 182 through through-hole connector 1BVD1, and backside horizontal conductor 182 is electrically conductively connected to backside vertical conductor 178 through through-hole connector 1BV0A.

As specified in the layout diagrams of Figures 4A-4E, in the inverter circuit 400, the backside vertical conductor 178 includes a first portion 178A and a second portion 178B. The first portion 178A covers the overlap area between the backside horizontal conductor 182 and the backside vertical conductor 178, while the second portion 178B is outside the overlap area. The first portion 178A has a first width "Wa" and the second portion has a second width "Wb." The first width "Wa" is greater than the second width "Wb". In some embodiments, the first width "Wa" is greater than the second width "Wb" by more than one eighth of a contact poly pitch (CPP). In some embodiments, the first width "Wa" is greater than the second width "Wb" by more than one quarter of a contact poly pitch (CPP). In some embodiments, the first width "Wa" is sufficiently larger than the second width "Wb" to allow positioning of pin connector 1BV0A without creating a design rule violation. In some embodiments, flexibility in locating pin connectors for circuit cells having a cell width less than or equal to three times the contact poly pitch (CPP) improves layout area in integrated circuit designs. Coverage (layout area coverages).

In some embodiments, such as in the NOR circuit 400 of FIG. 4A , the backside horizontal conductor 182 extends along the X direction across the vertical cell boundary 119 at a distance "Δ". In some embodiments, the dorsal level The distance "[Delta]" that the wires 182 extend across the vertical cell boundary 119 is less than one contact poly pitch (CPP) but greater than one-eighth of the contact poly pitch (CPP). In some embodiments, the backside horizontal conductor 182 extends across the vertical cell boundary 119 a distance "Δ" that is less than one contact poly pitch (CPP) but greater than one quarter of the contact poly pitch (CPP). In some embodiments, the backside horizontal conductor 182 extends across the vertical cell boundary 119 by a distance "Δ" that is less than one contact poly pitch (CPP) but greater than half the contact poly pitch (CPP). In some embodiments, distance "Δ" is selected to be large enough to mitigate design rule violations associated with pin connector connections between backside vertical conductors 178 and backside horizontal conductors 182 . In some embodiments, distance "Δ" is selected to be less than one contact poly pitch (CPP) such that the horizontal gap distance from vertical cell boundary 119 to the vertical cell boundary of an adjacent cell is reduced to a minimum distance of Mitigates design rule violations associated with pin connector connections.

In some embodiments, such as in the inverter circuit 400 of Figure 4B, the backside horizontal conductors 182 extend across the vertical cell boundary 119. In some embodiments, such as in the NOR circuit 400 of FIG. 4C , the first portion 178A of the backside vertical conductor 178 extends across the vertical cell boundary 119 while the second portion 178B of the backside vertical conductor 178 does not extend across the vertical cell boundary 119 . Cell boundary 119. In some embodiments, such as in the inverter circuit 400 of FIG. 4D , both the first portion 178A and the second portion 178B of the backside vertical conductor 178 extend across the vertical cell boundary 119 .

In some embodiments, such as in the inverter circuit 400 of Figure 4E, although the backside vertical conductors 178 do not extend across vertical cell boundaries 119, but the first width "Wa" of first portion 178A is increased to provide greater flexibility in positioning the pin connector (ie, through-hole connector 1BV0A) onto the backside horizontal conductor 182. Additionally, backside vertical conductor 175 (adjacent to backside vertical conductor 178) is also modified to avoid design rule violations.

Figures 5A to 5B are layout diagrams of a NAND gate circuit 500 according to some embodiments. The layout diagrams of Figures 5A to 5B include a plurality of layout patterns for specifying a p-type active region structure 80p, an n-type active region structure 80n, a plurality of gate conductors (552 and 558), Terminal conductors (532p, 532n, 535p, 535n and 538), and dummy gate conductors (151 and 159). The NAND gate circuit 500 is located in a cell bounded by a cell boundary 110, and the cell width is bounded by two vertical cell boundaries 111 and 119. The layout diagram of Figure 5A also includes multiple layout patterns that designate power rails (40 and 20), front side first layer conductors (522, 524, and 526), and various through-hole connectors. The layout diagram of Figure 5B also includes a plurality of layout patterns for specifying backside horizontal conductors (581, 582, 584, and 586), backside vertical conductors (572, 575, and 578), and various Through hole connector.

In the NAND gate circuit 500 specified in the layout diagrams of Figures 5A-5B, the gate conductor 552 intersects the p-type active region structure 80p at the channel region of the p-type transistor pA1, and at the n-type transistor pA1 The channel region of crystal nA1 intersects with the n-type active region structure 80n. Gate conductor 558 intersects p-type active region structure 80p at the channel region of p-type transistor pA2 and intersects n-type active region structure 80n at the channel region of n-type transistor nA2 intersect. Terminal conductors 532p and 535p intersect p-type active region structure 80p at respective source/drain regions of p-type transistors pA2 and pA1. Terminal conductors 532n and 535n intersect n-type active region structure 80n at respective source/drain regions of n-type transistors nA2 and nA1. The terminal conductor 538 intersects the p-type active region structure 80p and the n-type active region structure 80n at the drain region of the p-type transistor pA1 and the drain region of the n-type transistor nA1, respectively.

In the NAND gate circuit 500 specified in the layout diagram of Figures 5A-5B, the first layer of front-side conductors (522, 524 and 526) and the power rails (40 and 20) are located on the first connection layer above the substrate middle. In the NAND gate circuit 500, the terminal conductor 535p is electrically connected to the power rail 40 through the through-hole connector 5VDdd, and the power rail 40 is configured to provide the first supply voltage VDD. The terminal conductor 532n is electrically connected to the power rail 20 through the through-hole connector 5VDss, and the power rail 20 is configured to provide the second supply voltage VSS. The front first layer wire 522 is electrically connected to the terminal conductor 532p through the through-hole connector 5VD1, and is electrically connected to the terminal conductor 538 through the through-hole connector 5VD2.

In the NAND gate circuit 500, the terminal conductor 538 (in FIG. 5A) is also conductively connected to the backside horizontal conductor 582 (in FIG. 5B) through the through-substrate through-hole connector 5BVD1. Additionally, gate conductor 552 (in Figure 5A) is electrically connected to backside horizontal conductor 584 (in Figure 5B) through through-hole connector 5BVG1, and gate conductor 558 (in Figure 5A) through the through-hole Connector 5BVG2 is electrically connected to backside horizontal conductor 586 (in Figure 5B).

In the NAND gate circuit 500, the backside horizontal conductor 582 is electrically connected to the backside vertical conductor 578 through the through-hole connector 5BV0A. The backside horizontal wire 584 is electrically connected to the backside vertical wire 572 through the through-hole connector 5BV0B. The backside horizontal wire 586 is electrically connected to the backside vertical wire 575 through the through-hole connector 5BV0C. In the NAND gate circuit 500, the backside horizontal conductors 581, 582, 584 and 586 are located in the backside first conductive layer under the substrate. The backside vertical conductors 572 , 575 and 578 are located in the backside first conductive layer and the backside second conductive layer below the substrate 50 .

In the NAND gate circuit 500 , the backside vertical conductor 572 , the through-hole connector 5BV0B and the backside horizontal conductor 584 are conductively connected together to carry the input signal “A1” of the NAND gate circuit 500 . The backside vertical conductor 575, the through-hole connector 5BV0C and the backside horizontal conductor 586 are conductively connected together to carry the input signal "A2" of the NAND gate circuit 500. The backside vertical conductor 578, the through-hole connector 5BV0A and the backside horizontal conductor 582 are conductively connected together to carry the output signal "ZN" of the NAND gate circuit 500.

In the NAND gate circuit 500, the through-hole connector 5BV0A is used as a pin connector extending along the Z direction for connecting the backside vertical conductor 578 to the backside carrying the output signal "ZN" of the NAND gate circuit 500. Side horizontal wire 582. In some embodiments, when backside horizontal conductors 582 extend across vertical cell boundaries 119, greater flexibility is provided for the positioning of pin connectors (ie, through-hole connectors 5BV0A) without incurring design rules Violation. In Figure 5B, the backside horizontal conductor 582 extends along the X direction across the vertical cell boundary 119 at a distance "Δ". In some embodiments, backside horizontal conductors 582 extend across vertical cell boundaries 119 The distance "Δ" is less than one Contact Poly Pitch (CPP). In some embodiments, the backside horizontal conductor 582 extends across the vertical cell boundary 119 a distance "Δ" that is greater than one-eighth of the contact poly pitch (CPP), one-quarter of the contact poly pitch (CPP), or Contact half the polycrystalline spacing (CPP). In some embodiments, distance "Δ" is selected to be large enough to mitigate design rule violations associated with pin connector connections between backside vertical conductors 578 and backside horizontal conductors 582 . In some embodiments, distance "Δ" is selected to be less than one contact poly pitch (CPP) such that the horizontal gap distance from vertical cell boundary 119 to the vertical cell boundary of an adjacent cell is reduced to a minimum distance of Mitigates design rule violations associated with pin connector connections.

Figures 6A-6B are layout diagrams of an inverter circuit 600 according to some embodiments. The layout diagrams of FIGS. 6A to 6B include multiple layout patterns for specifying the p-type active region structure 80p, the n-type active region structure 80n, a plurality of gate conductors (652 and 658), A plurality of terminal conductors (632, 635p, 635n, and 638), and dummy gate conductors (151 and 159). The inverter circuit 600 is located in a cell bounded by cell boundary 110, and the cell width is bounded by two vertical cell boundaries 111 and 119. The layout diagram of Figure 6A also includes multiple layout patterns for specifying power rails (40 and 20), front side first layer conductors (622, 624, and 626), and various through-hole connectors. The layout diagram of Figure 6B also includes a plurality of layout patterns for specifying the backside horizontal conductors (681, 682, 684, and 686), the backside vertical conductors (672, 675, and 678), and various Through hole connector.

In the inverter circuit 600 specified in the layout diagram of Figures 6A-6B, the gate conductor 652 intersects the p-type active region structure 80p at the channel region of the p-type transistor pA1, and at the n-type transistor pA1 The channel region of crystal nA1 intersects with the n-type active region structure 80n. Gate conductor 658 intersects p-type active region structure 80p at the channel region of p-type transistor pA2 and intersects n-type active region structure 80n at the channel region of n-type transistor nA2. Terminal conductor 635p intersects p-type active region structure 80p at the source regions of p-type transistors pA2 and pA1. Terminal conductor 635n intersects n-type active region structure 80n at the source regions of n-type transistors nA2 and nA1. The terminal conductor 632 intersects the p-type active region structure 80p and the n-type active region structure 80n at the drain region of the p-type transistor pA1 and the drain region of the n-type transistor nA1, respectively. Terminal conductor 638 intersects p-type active region structure 80p and n-type active region structure 80n at the drain region of p-type transistor pA2 and the drain region of n-type transistor nA2, respectively.

In the inverter circuit 600 specified in the layout diagram of Figures 6A-6B, the first layer of front-side conductors (622, 624, and 626) and the power rails (40 and 20) are located on the first connection layer above the substrate middle. In the inverter circuit 600, the terminal conductor 635p is electrically connected to the power rail 40 through the through-hole connector 6VDdd, and the power rail 40 is configured to provide the first supply voltage VDD. The terminal conductor 635n is electrically connected to the power rail 20 through the through-hole connector 6VDss, and the power rail 20 is configured to provide the second supply voltage VSS. The front first layer wire 626 is electrically connected to the terminal conductor 632 through the through-hole connector 6VD1, and is electrically connected to the terminal conductor 638 through the through-hole connector 6VD2.

In inverter circuit 600, terminal conductor 638 (in Figure 6A) is also conductively connected to backside horizontal conductor 682 (in Figure 6B) through through-substrate through-hole connector 6BVD1. Additionally, backside horizontal conductor 684 (in Figure 6B) is electrically connected to gate conductor 652 through via connector 6BVG1 and to gate conductor 658 through via connector 6BVG2.

In the inverter circuit 600, the backside horizontal conductor 682 is electrically connected to the backside vertical conductor 678 through the through-hole connector 6BV0A. The backside horizontal conductor 684 is electrically connected to the backside vertical conductor 672 through the through-hole connector 6BV0B. In inverter circuit 600, backside horizontal conductors 681, 682, 684, and 686 are located in the backside first conductive layer beneath the substrate. Backside vertical conductors 672, 675, and 678 are located in the backside second conductive layer below the backside first conductive layer. In the inverter circuit 600 , the backside vertical conductor 672 serves as the input node “IN” of the inverter circuit 600 and the backside vertical conductor 678 serves as the output node “ZN” of the inverter circuit 600 .

In the inverter circuit 600, the through-hole connector 6BV0A serves as a pin connector extending along the Z direction for connecting the backside vertical conductor 678 to the backside carrying the output signal "ZN" of the inverter circuit 600. Side horizontal wire 682. In some embodiments, when backside horizontal conductors 682 extend across vertical cell boundary 119, greater flexibility is provided for the positioning of pin connectors (i.e., through-hole connectors 6BV0A) without incurring design rules Violation. In Figure 6B, the backside horizontal conductor 682 extends along the X direction across the vertical cell boundary 119 at a distance "Δ". In some embodiments, backside horizontal conductors 682 extend across vertical cell boundaries 119 The distance "Δ" is less than one Contact Poly Pitch (CPP). In some embodiments, the backside horizontal conductor 682 extends across the vertical cell boundary 119 by a distance "Δ" that is greater than one-eighth of the contact poly pitch (CPP), one-quarter of the contact poly pitch (CPP), or Contact half the polycrystalline spacing (CPP). In some embodiments, distance "Δ" is selected to be large enough to mitigate design rule violations associated with pin connector connections between backside vertical conductors 678 and backside horizontal conductors 682 . In some embodiments, distance "Δ" is selected to be less than one contact poly pitch (CPP) such that the horizontal gap distance from vertical cell boundary 119 to the vertical cell boundary of an adjacent cell is reduced to a minimum distance of Mitigates design rule violations associated with pin connector connections.

Figures 7A-7B are layout diagrams of an inverter circuit 700 according to some embodiments. The layout diagrams of Figures 7A-7B include a plurality of layout patterns for specifying a p-type active region structure 80p, an n-type active region structure 80n, a gate conductor 758, a plurality of terminal conductors (735p , 735n and 738), and dummy gate conductors (151 and 159). Inverter circuit 700 is located in a cell bounded by cell boundary 110, and the cell width is bounded by two vertical cell boundaries 111 and 119. The layout diagram of Figure 7A also includes multiple layout patterns that designate power rails (40 and 20), front side first layer conductors (722, 724, and 726), and various through-hole connectors. The layout diagram of Figure 7B also includes multiple layout patterns for specifying backside horizontal conductors (782, 784, and 786), backside vertical conductors (775 and 778), and various through-hole connectors .

In the inverter circuit 700 specified in the layout diagram of Figures 7A-7B, the gate conductor 758 intersects the p-type active region structure 80p at the channel region of the p-type transistor Tp, and at the n-type transistor Tp The channel region of crystal Tn intersects with the n-type active region structure 80n. Terminal conductor 735p intersects p-type active region structure 80p at the source region of p-type transistor Tp. Terminal conductor 735n intersects n-type active region structure 80n at the source region of n-type transistor Tn. Terminal conductor 738 intersects p-type active region structure 80p and n-type active region structure 80n at the drain region of p-type transistor Tp and the drain region of n-type transistor Tn, respectively.

In the inverter circuit 700 specified in the layout diagram of Figures 7A-7B, the first layer of front-side conductors (722, 724, and 726) and the power rails (40 and 20) are located on the first connection layer above the substrate middle. In the inverter circuit 700, the terminal conductor 735p is electrically connected to the power rail 40 through the through-hole connector 7VDdd, and the power rail 40 is configured to provide the first supply voltage VDD. The terminal conductor 735n is electrically connected to the power rail 20 through the through-hole connector 7VDss, and the power rail 20 is configured to provide the second supply voltage VSS.

In inverter circuit 700, terminal conductor 738 (in Figure 7A) is also conductively connected to backside horizontal conductor 782 (in Figure 7B) through through-substrate through-hole connector 7BVD1. In addition, the gate conductor 758 is electrically connected to the backside horizontal conductor 784 through the through-hole connector 7BVG1.

In the inverter circuit 700, the backside horizontal conductor 782 is electrically connected to the backside vertical conductor 778 through the through-hole connector 7BV0A. The backside horizontal conductor 784 passes through the through-hole connector 7BV0B and the backside vertical conductor 775 Conductive connection. In inverter circuit 700, backside horizontal conductors 782, 784, and 786 are located in the backside first conductive layer beneath the substrate. Backside vertical conductors 772, 775, and 778 are located in the backside second conductive layer below the backside first conductive layer. In the inverter circuit 700, the backside vertical conductor 775 serves as the input node "IN" of the inverter circuit 700, and the backside vertical conductor 778 serves as the output node "ZN" of the inverter circuit 700.

In the inverter circuit 700, the through-hole connector 7BV0A is used as a pin connector extending along the Z direction for connecting the backside vertical conductor 778 to the backside carrying the output signal "ZN" of the inverter circuit 700. Side horizontal wire 782. In some embodiments, when backside horizontal conductors 782 extend across vertical cell boundaries 119, greater flexibility is provided for the positioning of pin connectors (i.e., through-hole connectors 7BV0A) without incurring design rules. Violation. In some embodiments, flexibility in locating pin connectors for circuit cells having a cell width less than or equal to twice the contact poly pitch (CPP) improves layout area in integrated circuit designs. Coverage. In Figure 7B, the backside horizontal conductor 782 extends along the X direction across the vertical cell boundary 119 at a distance "Δ". In some embodiments, the backside horizontal conductor 782 extends a distance "Δ" across the vertical cell boundary 119 that is less than one contact poly pitch (CPP). In some embodiments, the backside horizontal conductor 782 extends across the vertical cell boundary 119 a distance "Δ" that is greater than one-eighth of the contact poly pitch (CPP), one-fourth of the contact poly pitch (CPP), or Contact half the polycrystalline spacing (CPP). In some embodiments, the distance "Δ" is selected to be large enough to ease the connection between the backside vertical conductors 778 and the backside horizontal conductors 782. associated design rule violation. In some embodiments, distance "Δ" is selected to be less than one contact poly pitch (CPP) such that the horizontal gap distance from vertical cell boundary 119 to the vertical cell boundary of an adjacent cell is reduced to a minimum distance of Mitigates design rule violations associated with pin connector connections.

Figure 8 is a flow diagram of a process 800 for designing an integrated circuit according to some embodiments. The process 800 in FIG. 8 is explained with reference to the layout diagrams of FIGS. 9A to 9C as an example. Figures 9A-9C are layout diagrams of unit 900 according to some embodiments. As shown in Figures 9A-9C, cell 900 includes backside horizontal conductors (981, 982, 984, and 986) in a first backside metal layer (BM0) and a second backside metal layer (BM1) dorsal vertical wires (972, 975 and 978) in . Through-hole connector 9BV0A (acting as a pin connector) connects the backside vertical conductor 978 to the backside horizontal conductor 982 .

In Figure 8, process 800 begins with the first part 805 of the design flow. The first part 805 includes design operations prior to placement and routing of backside conductors. Example operations in the first part of the design flow 805 include floor planning, partitioning, power planning, and placement and routing of various components at the front side of the substrate. After the process 800 completes the first part 805 of the design flow, the process 800 proceeds to operation 810, which performs automatic placement and routing (APR) of various backside conductors. Then, after operation 810, process 800 proceeds Go to operation 820, which performs a design rule check (DRC) on the layout design of the backside conductors. The design rules of layout design are geometric constraints imposed on the layout design to ensure that the corresponding circuit based on the layout design can operate normally and reliably, and that the corresponding circuit can also be produced with an acceptable yield. Design rule checks are performed to ensure that the layout design does not violate design rules. If the layout design of the backside conductors passes the design rule check, the process 800 proceeds to the remainder of the design flow 895 . On the other hand, if the layout design of the backside conductors fails the design rule check, the process 800 proceeds to operation 832 . An example of a Design Rule Check (DRC) failure is when the separation between two backside wires becomes too small. Another example of a Design Rule Check (DRC) failure is when the pin connector is positioned too close to the edge of the backside conductor.

At operation 832 , a layout area in the vicinity of unit 900 that was found to have at least one design rule violation at operation 820 is analyzed to determine whether the location of unit 900 is moveable. If the location of unit 900 is moveable, process 800 proceeds to operation 838 to repair the design rule violation and the location of unit 900 is moved from the original location to the alternate location in the modified layout design. For example, in the modified layout design shown in Figure 9A, unit 900 is moved from an original position 902 to an alternate position 908. On the other hand, in operation 832, if the location of the unit 900 cannot be moved, the process 800 proceeds to operation 834.

At operation 834, the layout area near unit 900 (which was found to have at least one design rule violation at operation 820) is analyzed to determine whether backside horizontal conductors supporting pin access can be extended. If the backside horizontal wire can be extended, process 800 proceeds to operation 838 to fix the design rule violation and the backside horizontal wire is redesigned as an extension wire that extends across the vertical cell boundary in the modified layout design. For example, in the modified layout design shown in Figure 9B, the backside horizontal conductor 982 (as an extension conductor) extends across to the vertical cell boundary 119 at a distance "Δ". On the other hand, in operation 834, if the backside horizontal wires used to support pin access cannot be extended, the process 800 proceeds to operation 836.

At operation 836 , the backside vertical conductors used to access the circuit nodes through the pin connectors are redesigned as local two-dimensional conductors in the modified layout design, and the process 800 proceeds to operation 838 . The area two-dimensional conductor has a first part and a second part, the first part has a first width, and the second part has a second width different from the first width. For example, in the modified layout design shown in Figure 9C, the backside vertical conductor 978 has a first portion 978A and a second portion 978B. The first portion 978A has a first width "Wa" and the second portion 978B has a second width "Wb" that is less than the first width "Wa". Additionally, in the modified layout design shown in Figure 9C, the backside vertical conductors 975 are also modified. In some embodiments, backside vertical conductors 975 are modified to avoid design rule violations caused by the increased first width "Wa" of first portion 978A. In some alternative embodiments, the backside vertical conductors 975 are not modified and the first portion 978A is designed with an increased first width "Wa". At operation 836, when the backside vertical conductors (eg, 978 in FIG. 9C) used to access the circuit nodes are redesigned as regional 2D conductors, the regional 2D conductors The wire has the potential to cause a design rule violation and two adjacent backside vertical wires (eg, 975 in Figure 9C) may need to be modified to mitigate the design rule violation. For example, when the backside vertical conductor 978 is changed to the area two-dimensional conductor in FIG. 9C, the backside vertical conductor 975 in FIG. 9C is shortened from the backside vertical conductor 975 in FIG. 9A. In the example flow diagram of FIG. 8, operation 836 is in the process flow after operations 832 and 834 due to the possibility of modifying adjacent backside vertical conductors.

In Figure 8, after process 800 completes operation 838, process 800 returns to operation 810 and performs auto placement and routing (APR) on various backside conductors. The process 800 then proceeds to operation 820 to check the modified layout design again for design rule violations. The iterations including operations 838, 810, and 820 are repeated until the layout design passes the design rule check, and then the process 800 proceeds to the remainder of the design flow 895. Example operations in the remainder of the design flow 895 include clock tree synthesis, RC extraction, timing analysis, signal integrity analysis, verifications )wait.

Figure 10 is a flowchart of a method 1000 of manufacturing an integrated circuit in accordance with some embodiments. The sequence of operations of method 1000 illustrated in FIG. 10 is for illustration only; the operations of method 1000 can be performed in a different order than the sequence of operations illustrated in FIG. 10 . It should be understood that additional operations may be performed before, during, and/or after the method 1000 illustrated in Figure 10, and some other processes may be only briefly described herein.

In operation 1010 of method 1000, a first type active area structure and a second type active area structure are fabricated. In some embodiments, the first type active region structure is a p-type active region structure, and the second type active region structure is an n-type active region structure. In some embodiments, the first type active region structure is an n-type active region structure, and the second type active region structure is a p-type active region structure. In the exemplary embodiments shown in FIGS. 2A to 2E and 3A to 3C, a p-type active region structure 80p and an n-type active region structure 80n are fabricated on top of the substrate 50. Examples of active region structures fabricated in operation 1010 include fin structures, nanosheet structures, and nanowire structures.

In operations 1022 and 1024 of method 1000, gate conductors and terminal conductors are fabricated. Each of the gate conductor and the terminal conductor intersects the first type active region structure and/or the second type active region structure above the substrate. In the example embodiments shown in FIGS. 2A-2E and 3A-3C, the gate conductor fabricated at operation 1022 includes a gate intersecting the p-type active region structure 80p and the n-type active region structure 80n. pole conductors 152 and 158. In the example embodiment, the terminal conductors fabricated at operation 1022 include terminal conductors 132p, 135p, and 138 intersecting p-type active region structure 80p and terminal conductors 132n, 135n, and 138 intersecting n-type active region structure 80n. After operations 1022 and 1024, method 1000 proceeds to operation 1030.

In operation 1030 of method 1000, front side first layer conductors are fabricated. In the example embodiments shown in FIGS. 2A to 2E and 3A to 3C, after the top insulating layer is fabricated in a front-end-of-line (FEOL) process, in operation 1030 , on top of covering The front-side first layer conductors 122, 124 and 126 are fabricated in the first connecting layer of the partial insulating layer, such as the first metal layer (M0).

After operations 1010, 1022, and 1030, the wafer including the substrate is flipped at operation 1040. Method 1000 then proceeds to operation 1050. In operation 1050 of method 1000, a through-hole connector is fabricated through the substrate. One example of a through-hole connector fabricated at operation 1050 is a through-hole connector used to connect gate conductors at the front side of the substrate to wires at the back side of the substrate. Another example of a through-hole connector fabricated at operation 1050 is a through-hole connector used to connect terminal conductors at the front side of the substrate to wires at the back side of the substrate. In the example embodiments shown in FIGS. 2A-2E and 3A-3C , through-hole connectors 1BVG1 , 1BVG2 , and 1BVD1 are fabricated through the substrate 50 at operation 1050 . After operation 1050, method 1000 proceeds to operation 1060.

In operation 1060 of method 1000, backside horizontal conductors are fabricated at the backside of the substrate. In some embodiments, one of the backside horizontal conductors is fabricated as an extension conductor that extends across the vertical boundary of the circuit cell at a distance less than the contact poly pitch (CPP). In the example embodiments shown in FIGS. 2A-2E and 3A-3C, in the backside first conductive layer at the backside of the substrate 50 (eg, in the first backside metal layer (BM0) )) to manufacture the backside horizontal conductors 181, 182, 184 and 186. In the example embodiment, the backside horizontal conductive lines 182 extend across the vertical cell boundary 119 at a distance "Δ" that is less than the contact poly pitch (CPP). After operation 1060, method 1000 proceeds to operation 1070.

In operation 1070 of method 1000, a through-hole connector is fabricated. One example of a through-hole connector fabricated at operation 1070 is a through-hole connector used to connect a backside horizontal conductor to a backside vertical conductor. In the example embodiments shown in FIGS. 2A-2E and 3A-3C , through-hole connectors 1BV0A, 1BV0B, and 1BV0C are fabricated through the backside interlayer dielectric 56 in operation 1070 . After operation 1070, method 1000 proceeds to operation 1080.

In operation 1080 of method 1000, backside vertical conductors are fabricated. In some embodiments, one of the backside vertical conductors is aligned with a vertical boundary of the circuit cell and is connected directly to one of the backside horizontal conductors through a pin connector. In some embodiments, the backside vertical conductor aligned with the vertical boundary of the circuit cell is a regional two-dimensional conductor having a first portion and a second portion, the first portion having a first width and the second portion having a width different from that of the first portion. One width to a second width. In the example embodiments shown in Figures 2A-2E and 3A-3C, the backside vertical Wires 172, 175 and 178. In the example embodiment, backside vertical conductors 178 are aligned with vertical cell boundaries 119 . Backside vertical conductor 178 is conductively connected to backside horizontal conductor 182 through through-hole connector 1BV0A (used as a pin connector). In the example embodiment shown in FIGS. 4A-4E , the backside vertical conductor 178 includes a first portion 178A having a first width “Wa” and a second portion 178B having a second width “Wb”.

In the example embodiments shown in Figures 2A-2E and 3A-3C, the contact poly node of the backside vertical conductor (in the second backside metal layer (BM1)) to the gate conductor Gear ratio between pitch (CPP) (gear ratio) is one to one (i.e. 1:1). In some alternative embodiments, the gear ratio between the backside vertical conductors (in the second backside metal layer (BM1)) and the contact poly pitch (CPP) of the gate conductors is two to three (i.e., 2 :3). In yet other alternative embodiments, the gear ratio between the backside vertical conductors (in the second backside metal layer (BM1)) and the contact poly pitch (CPP) of the gate conductors is one to two (i.e., 1:2). Other choices for gear ratios are also contemplated by this disclosure.

Figure 11 is a block diagram of an electronic design automation (EDA) system 1100 according to some embodiments.

In some embodiments, EDA system 1100 includes an automatic placement and routing (APR) system. The methods of designing floorplans described herein represent routing arrangements in accordance with one or more embodiments, such as may be implemented using EDA system 1100 in accordance with some embodiments.

In some embodiments, EDA system 1100 is a general-purpose computing device including a hardware processor 1102 and a non-transitory computer-readable storage medium 1104. Storage medium 1104 is, among other things, encoded with (i.e., stores) computer program code 1106, which is a set of executable instructions. Execution of instructions 1106 by hardware processor 1102 represents (at least in part) an EDA tool that implements a portion of the methods described herein or all.

The processor 1102 is electrically coupled to the computer-readable storage medium 1104 through the bus 1108 . Processor 1102 also provides electrical power via bus 1108 is coupled to an input/output (I/O) interface 1110. The network interface 1112 is also electrically connected to the processor 1102 through the bus 1108 . The network interface 1112 is connected to the network 1114, allowing the processor 1102 and the computer-readable storage medium 1104 to connect to external components through the network 1114. Processor 1102 is configured to execute computer program code 1106 encoded in computer-readable storage medium 1104 to enable system 1100 to perform some or all of the described processes and/or methods. In one or more embodiments, the processor 1102 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit circuit, ASIC) and/or suitable processing unit.

In one or more embodiments, computer readable storage medium 1104 is an electronic, magnetic, optical, electromagnetic, infrared, and/or semiconductor system (or device or device). For example, the computer-readable storage media 1104 includes semiconductor or solid-state memory, magnetic tape, portable computer disk, random access memory (RAM), and read-only memory (ROM). , rigid magnetic discs and/or optical discs. In one or more embodiments using optical disks, the computer-readable storage medium 1104 includes compact disk-read only memory (CD-ROM), compact disk-read/write (CD-ROM), and compact disk-read/write (CD-ROM). -R/W) and/or digital video disc (DVD).

In one or more embodiments, storage media 1104 stores computer programs Computer program code 1106 is configured such that system 1100 (in which such execution represents (at least in part) an EDA tool) may be used to execute some or all of the processes and/or methods. In one or more embodiments, storage medium 1104 also stores information that facilitates performing some or all of the processes and/or methods. In one or more embodiments, storage medium 1104 stores a standard cell library 1107 including such standard cells as disclosed herein. In one or more embodiments, storage medium 1104 stores one or more layout diagrams 1109 corresponding to one or more layouts as disclosed herein.

EDA system 1100 includes I/O interface 1110 . I/O interface 1110 is coupled to external circuitry. In one or more embodiments, I/O interface 1110 includes a keyboard, numeric keypad, mouse, trackball, trackpad, touch screen, and/or cursor direction keys for communicating information and commands with processor 1102 .

EDA system 1100 also includes a network interface 1112 coupled to processor 1102 . Network interface 1112 allows system 1100 to communicate with network 1114 to which one or more other computer systems are connected. The network interface 1112 includes a wireless network interface, such as BLUETOOTH, WIFI, WIMAX, GPRS or WCDMA; or a wired network interface, such as ETHERNET, USB or IEEE-1364. In one or more embodiments, some or all of the processes and/or methods are implemented in two or more systems 1100 .

System 1100 is configured to receive information via I/O interface 1110 . Information received via I/O interface 1110 includes instructions, data, design rules, standard cell libraries, and/or other parameters processed by processor 1102 one or more of. Information is passed to processor 1102 via bus 1108 . EDA system 1100 is configured to receive user interface (UI) related information via I/O interface 1110 . The information is stored in computer-readable media 1104 as user interface (UI) 1142 .

In some embodiments, some or all of the processes and/or methods are implemented as stand-alone software applications executed by a processor. In some embodiments, part or all of the process and/or method is implemented as a software application that is part of an additional software application. In some embodiments, part or all of the process and/or method is implemented as a plug-in for a software application. In some embodiments, at least one implementation of the process and/or method is a software application that is part of an EDA tool. In some embodiments, some or all of the processes and/or methods are implemented as software applications used by EDA system 1100 . In some embodiments, a layout drawing including standard cells is generated using a tool such as VIRTUOSO®, available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generation tool.

In some embodiments, a process is implemented as a function of a program stored on a non-transitory computer-readable medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external/portable and/or interlayer/embedded storage or memory units, for example, optical disks such as DVDs, magnetic disks such as hard drives. One or more chips, semiconductor memories such as ROM, RAM, memory cards, etc.

Figure 12 illustrates an integrated circuit according to some embodiments A block diagram of an integrated circuit (IC) manufacturing system 1200 and its associated IC manufacturing process. In some embodiments, fabrication system 1200 is used to fabricate at least one of (A) one or more semiconductor masks or (B) at least one component of a layer of a semiconductor integrated circuit based on the layout diagram.

In Figure 12, IC manufacturing system 1200 includes entities such as a design house 1220, a mask house 1230, and an IC fabricator/fab 1250, which are involved in manufacturing IC devices 1260 Related design, development and manufacturing cycles and/or services interact with each other. Entities in system 1200 are connected by communications networks. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as intranets and the Internet. Communication networks include wired and/or wireless communication channels. Each entity interacts with and provides services to and/or receives services from one or more other entities. In some embodiments, two or more of design room 1220, mask room 1230, and IC fab 1250 are owned by a single larger company. In some embodiments, two or more of the design room 1220, the mask room 1230, and the IC fab 1250 co-exist in a shared facility and use shared resources.

The design office (or design group) 1220 generates an IC design layout 1222. IC design layout 1222 includes various geometric patterns designed for IC device 1260 . The geometric pattern corresponds to the pattern of metal, oxide, or semiconductor layers that make up the various components of the IC device 1260 to be fabricated. Various layers combine to form various IC features. For example, portions of IC design layout diagram 1222 include various IC features such as active regions, gate electrodes, source and drain These IC features are formed in a semiconductor substrate, such as a silicon wafer, and in various material layers disposed on the semiconductor substrate, such as electrodes, metal lines or vias for inter-layer interconnection, and openings for bonding pads. Design room 1220 implements appropriate design procedures to form IC design layout 1222 . The design process includes one or more of logical design, physical design, and/or placement and layout. IC design layout 1222 exists in one or more data files with geometric pattern information. For example, the IC design layout diagram 1222 can be represented in GDSII file format or DFII file format.

Mask room 1230 includes data preparation 1232 and mask manufacturing 1244. Mask chamber 1230 uses IC design layout 1222 to fabricate one or more masks 1245 that are to be used to fabricate various layers of IC device 1260 based on IC design layout 1222 . The mask room 1230 performs mask data preparation 1232, in which the IC design layout diagram 1222 is converted into a representative data file (RDF). Mask data preparation 1232 provides RDF to mask fabrication 1244 . Mask fabrication 1244 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 1245 or a semiconductor wafer 1253. The design layout 1222 is manipulated by the mask data preparation 1232 to conform to the specific characteristics of the mask writer and/or the requirements of the IC fab 1250 . In Figure 12, mask data preparation 1232 and mask manufacturing 1244 are shown as separate components. In some embodiments, mask data preparation 1232 and mask manufacturing 1244 may be collectively referred to as mask data preparation.

In some embodiments, mask data preparation 1232 includes optical proximity correction (OPC), which Use lithography enhancement techniques to compensate for aberrations, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjustment IC design layout diagram 1222. In some embodiments, mask data preparation 1232 includes additional resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase Phase-shifting masks, other suitable techniques, etc. or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

In some embodiments, mask data preparation 1232 includes a mask rule checker (MRC) that checks the IC design layout 1222 that has undergone processing in OPC using a set of mask generation rules. Certain geometric and/or connectivity constraints are included to ensure sufficient margin to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 1222 to compensate for constraints during mask fabrication 1244, which may cancel portions of the modifications performed by OPC to satisfy mask generation rules.

In some embodiments, mask data preparation 1232 includes lithography process checking (LPC), which simulates the processes to be performed by IC fab 1250 to fabricate IC device 1260 . LPC simulates this process based on IC design layout 1222 to create a simulated manufacturing device, such as IC device 1260 . Processing parameters in LPC simulations may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with the processes used to manufacture the IC. parameters associated with the tool, and/or other aspects of the manufacturing process. LPC considers various factors, such as aerial image contrast (aerial image contrast), depth of focus (DOF), mask error enhancement factor (MEEF), other appropriate factors, etc. or a combination thereof. In some embodiments, after the simulated device has been created by LPC, if the simulated device is not close enough to the shape to satisfy the design rules, OPC and/or MRC are repeated to further refine the IC design layout 1222.

It should be understood that the above description of mask data preparation 1232 has been simplified for the sake of simplicity. In some embodiments, data preparation 1232 includes additional features such as logic operations (LOPs) to alter the IC design layout 1222 according to manufacturing rules. Additionally, the processes applied to the IC design layout 1222 during data preparation 1232 may be performed in various orders.

After mask data preparation 1232 and during mask fabrication 1244 , a mask 1245 or mask group 1245 is fabricated based on the modified IC design layout 1222 . In some embodiments, mask fabrication 1244 includes performing one or more lithography exposures based on the IC design layout 1222 . In some embodiments, an electron-beam (e-beam) or mechanism of multiple e-beams is used to create a photomask or reticle based on a modified IC design layout 1222 )1245 to form a pattern. Mask 1245 can be formed using various techniques. In some embodiments, mask 1245 is formed using binary techniques. In some embodiments, the mask pattern includes opaque areas and transparent areas. Used to expose image-sensitive materials that have been coated on the wafer Radiation beams from the material layer (eg, photoresist), such as ultraviolet (UV) beams, are blocked by the opaque regions and transmitted through the transparent regions. In one example, a binary mask version of mask 1245 includes a transparent substrate (eg, fused quartz), and an opaque material (eg, chromium) coated in the opaque regions of the binary mask. In another example, mask 1245 is formed using phase shift technology. In the phase shift mask (PSM) version of mask 1245, various features in the pattern formed on the phase shift mask are configured to have appropriate phase differences to improve resolution and imaging quality. In various examples, the phase shift mask may be a decaying PSM or an alternating PSM. The masks produced by mask fabrication 1244 are used in various processes. For example, such a mask is used in an ion implantation process to form various doped regions in the semiconductor wafer 1253, and this kind of mask is used in an etching process to form various etched regions in the semiconductor wafer 1253. , and/or such masks are used in other appropriate processes.

An IC fab 1250 is an IC manufacturing company that includes one or more manufacturing facilities used to manufacture a variety of different IC products. In some embodiments, IC fab 1250 is a semiconductor fabrication fab. For example, there may be a manufacturing facility used for front-end-of-line (FEOL) manufacturing of multiple IC products, while a second manufacturing facility may provide back-end manufacturing for interconnection and packaging of the IC products. (back-end-of-line (BEOL)), and the third manufacturing facility can provide other services to the manufacturing company.

IC fab 1250 includes components for executing on semiconductor wafer 1253 Various fabrication operations enable fabrication tool 1252 to fabricate IC device 1260 according to a mask (eg, mask 1245). In various embodiments, the manufacturing tool 1252 includes one or more of the following: a wafer stepper, an ion implanter, a photoresist coater, a process chamber chamber (such as a CVD chamber or LPCVD furnace), CMP system, plasma etch system, wafer cleaning system, or other manufacturing equipment capable of performing one or more manufacturing processes as described herein.

IC fab 1250 uses masks 1245 produced by mask chamber 1230 to fabricate IC devices 1260 . Thus, IC fab 1250 uses IC design layout 1222 , at least indirectly, to fabricate IC device 1260 . In some embodiments, IC fab 1250 uses mask 1245 to form IC device 1260 to fabricate semiconductor wafer 1253 . In some embodiments, IC fabrication includes performing one or more lithographic exposures based at least indirectly on IC design layout 1222 . Semiconductor wafer 1253 includes a silicon substrate or other suitable substrate with layers of materials formed thereon. Semiconductor wafer 1253 further includes one or more of various doped regions, dielectric features, multi-level interconnects, etc. (formed in subsequent fabrication steps).

Details regarding integrated circuit (IC) manufacturing systems (e.g., system 1200 of FIG. 12) and their associated IC manufacturing processes are found in: e.g., U.S. Patent No. 9,256,709, issued February 9, 2016; U.S. Pre-Authorization Publication No. 20150278429, published on October 1, 2015; U.S. Pre-Authorization Publication No. 20140040838, published on February 6, 2014; and Authorized on August 21, 2007 No. 7,260,442, the contents of each of which are incorporated herein by reference in their entirety.

One aspect of the present disclosure relates to integrated circuits. The integrated circuit includes a first-type active area structure, a second-type active area structure, a first-layer wire on the front side, a plurality of gate conductors, a circuit unit, a back-side horizontal wire, a back-side vertical wire and a pin connector. The first type active area structure and a second type active area structure extend along the first direction on the substrate. The first layer of wires on the front side is in the first connection layer above the substrate. A plurality of gate conductors extend along the second direction below the first connection layer, and two adjacent gate conductors are spaced apart by a distance equal to a contact poly pitch (CPP). The circuit unit has a first vertical boundary and a second vertical boundary extending along a second direction perpendicular to the first direction. Each of the first vertical boundary and the second vertical boundary spans at least one boundary isolation area along the first The distance between the first vertical boundary and the second vertical boundary of the direction is less than or equal to three times the contact poly pitch (CPP). The backside horizontal conductive line extends along the first direction in the backside first conductive layer under the substrate, and the backside horizontal conductive line extends across the first vertical boundary of the circuit unit. The backside vertical conductive lines extend along the second direction in the backside second conductive layer below the backside first conductive layer, and the backside vertical conductors are aligned with the first vertical boundary. Pin connectors are used in circuit units. The pin connector is directly connected between the backside horizontal conductor and the backside vertical conductor. In some embodiments, the backside horizontal conductors extend across the first vertical boundary of the circuit cell at a distance less than one-eighth of the contact poly pitch (CPP) but greater than one-eighth of the contact poly pitch (CPP). In some embodiments, the backside horizontal conductors are formed with a spacing less than the contact poly pitch (CPP) but greater than the contact poly pitch (CPP). One quarter of the distance extends across the first vertical boundary of the circuit cell. In some embodiments, the backside horizontal conductors extend across the first vertical boundary of the circuit cell at a distance less than one-half but greater than the contact poly pitch (CPP). In some embodiments, the width of the backside vertical conductors along the first direction is greater than three-quarters of the contact poly pitch (CPP). In some embodiments, the width of the backside vertical conductors along the first direction is greater than one-half the contact poly pitch (CPP). In some embodiments, the distance between the first vertical boundary and the second vertical boundary along the first direction is less than or equal to twice the contact poly pitch (CPP).

Another aspect of the disclosure still involves integrated circuits. The integrated circuit includes a first-type active area structure, a second-type active area structure, a first-layer wire on the front side, a plurality of gate conductors, a circuit unit, a back-side horizontal wire, a back-side vertical wire and a pin connector. The first type active area structure and a second type active area structure extend along the first direction on the substrate. The first layer of wires on the front side is in the first connection layer above the substrate. A plurality of gate conductors extend along the second direction below the first connection layer, and two adjacent gate conductors are spaced apart by a distance equal to a contact poly pitch (CPP). The circuit unit has a first vertical boundary and a second vertical boundary extending along a second direction perpendicular to the first direction, and each of the first vertical boundary and the second vertical boundary spans at least one boundary isolation region. The backside horizontal wire extends along the first direction in the backside first conductive layer below the substrate. The backside vertical conductive lines extend along the second direction in the backside second conductive layer below the backside first conductive layer. Pin connectors are used in circuit units. Pin connectors are directly located at the overlap area between the backside horizontal conductors and the backside vertical conductors The ground is connected between the horizontal conductor on the back side and the vertical conductor on the back side. The backside horizontal conductor has a first portion covering the overlapping area and the backside horizontal conductor has a second portion outside the overlapping area, and a first width of the first portion along the first direction is greater than a second width of the second portion along the first direction. In some embodiments, the first width is greater than the second width by more than one-eighth of the contact poly pitch (CPP). In some embodiments, the first width is greater than the second width by more than one quarter of the contact poly pitch (CPP). In some embodiments, the first vertical boundary and the second vertical boundary are separated by a distance along the first direction, and the distance is less than or equal to three times the contact poly pitch (CPP). In some embodiments, the first vertical boundary and the second vertical boundary are separated by a distance along the first direction, and the distance is less than or equal to twice the contact poly pitch (CPP). In some embodiments, the backside horizontal conductors extend across the first vertical boundary of the circuit cell at a distance less than one-eighth of the contact poly pitch (CPP) but greater than one-eighth of the contact poly pitch (CPP). In some embodiments, the backside horizontal conductors extend across the first vertical boundary of the circuit cell at a distance less than one-quarter of the contact poly pitch (CPP) but greater than one-quarter of the contact poly pitch (CPP).

Yet another aspect of the present disclosure involves methods. The method includes: manufacturing a first-type active region structure and a second-type active region structure extending along a first direction on a substrate; manufacturing a plurality of gate conductors extending along a second direction perpendicular to the first direction, each The gate conductor intersects the first-type active region structure and/or the second-type active region structure above the substrate. Two adjacent gate conductors are spaced apart by a spacing distance, and the spacing distance is equal to the contact poly spacing. pitch, CPP); manufacturing backside horizontal conductors extending along the first direction in the backside first conductive layer below the substrate; manufacturing Pin connectors connecting the backside horizontal conductors; and manufacturing backside vertical conductors extending along the second direction in the backside second conductive layer below the backside first conductive layer, wherein the backside vertical conductors are aligned with the circuit unit a first vertical boundary, wherein the pin connector is directly connected between the backside horizontal conductor and the backside vertical conductor at an overlap region between the backside horizontal conductor and the backside vertical conductor; wherein manufacturing the backside horizontal conductor includes The backside horizontal conductors are fabricated as extension conductors that extend across the first vertical boundary of the circuit cell at a distance less than the contact poly pitch (CPP). In some embodiments, the method further includes: fabricating the backside vertical conductive lines to form a first portion covering the overlapping area and forming a second portion outside the overlapping area, the first portion having a first width along the first direction greater than the second portion. A second width of the portion along the first direction. In some embodiments, the method further includes fabricating a front-side first layer of wires in a first connection layer above the substrate and above the plurality of gate conductors. In some embodiments, fabricating the backside horizontal conductor includes fabricating the backside horizontal conductor as an extension conductor that is less than one-eighth of the contact poly pitch (CPP) but greater than one-eighth of the contact poly pitch (CPP). The distance extends across a first vertical boundary of the circuit cell. In some embodiments, fabricating the backside horizontal conductor includes fabricating the backside horizontal conductor as an extension conductor with a conductor that is less than a contact poly pitch (CPP) but greater than one-quarter of the contact poly pitch (CPP). The distance extends across a first vertical boundary of the circuit cell. In some embodiments, fabricating the backside horizontal conductor includes fabricating the backside horizontal conductor as a conductor having a uniform width greater than half the contact poly pitch (CPP).

The above has summarized the features of several embodiments, so that those skilled in the art You can learn more about this disclosure. Those skilled in the art should appreciate that they can easily use this disclosure as a basis to design or modify other processes and structures to achieve the same goals and/or achieve the same advantages as the embodiments introduced herein. . Those skilled in this art should also understand that these equivalent constructions do not deviate from the spirit and scope of the disclosure, and they can make various changes, substitutions and changes without departing from the spirit and scope of the disclosure.

20,40:Power rail

80n: n-type active area structure

80p: p-type active area structure

100: Inverse OR gate circuit

110:Unit boundary

111,119: Vertical cell boundary

122,124,126: First layer of wires on the front side

132n, 132p, 135n, 135p, 138: terminal conductor

151,159: Dummy gate conductor

152,158: Gate conductor

1BVD1, 1BVG1, 1BVG2, 1VD1, 1VD2, 1VDdd, 1VDss: through hole connector

A-A’, B-B’, C-C’, D-D’, E-E’, P-P’, Q-Q’, R-R’: cutting plane

CPP: contact polycrystalline spacing

X,Y: direction

Claims (10)

An integrated circuit includes: a first-type active area structure and a second-type active area structure extending along a first direction on a substrate; a first-layer conductor on the front side, a first layer above the substrate In the connection layer; a plurality of gate conductors extend along a second direction below the first connection layer, wherein two adjacent gate conductors are spaced apart by a spacing distance and the spacing distance is equal to a contact polycrystalline spacing ; A circuit unit having a first vertical boundary and a second vertical boundary extending along the second direction perpendicular to the first direction, wherein each of the first vertical boundary and the second vertical boundary spans At least one boundary isolation region, wherein a distance between the first vertical boundary and the second vertical boundary along the first direction is less than or equal to three times the contact poly pitch; a backside horizontal conductor on the A backside first conductive layer below the substrate extends along the first direction, wherein the backside horizontal conductor extends across the first vertical boundary of the circuit unit; a backside vertical conductor, in the backside first conductive a backside second conductive layer below the layer extending along the second direction, wherein the backside vertical conductors are aligned with the first vertical boundary; and a pin connector for the circuit unit directly connected to between the backside horizontal wire and the backside vertical wire. The integrated circuit as claimed in claim 1, wherein the backside horizontal conductor has an eight-dimensional conductor that is smaller than the contact polycrystal pitch but larger than the contact polycrystalline pitch. One-half of the distance extends across the first vertical boundary of the circuit unit. The integrated circuit of claim 1, wherein the backside horizontal conductor extends across the first vertical boundary of the circuit unit at a distance smaller than the contact poly pitch but greater than a quarter of the contact poly pitch. The integrated circuit of claim 1, wherein the backside horizontal conductor extends across the first vertical boundary of the circuit unit at a distance smaller than the contact poly pitch but greater than half of the contact poly pitch. An integrated circuit includes: a first-type active area structure and a second-type active area structure extending along a first direction on a substrate; a first-layer conductor on the front side, a first layer above the substrate In the connection layer; a plurality of gate conductors extend along a second direction below the first connection layer, wherein two adjacent gate conductors are spaced apart by a spacing distance and the spacing distance is equal to a contact polycrystalline spacing ; A circuit unit having a first vertical boundary and a second vertical boundary extending along the second direction perpendicular to the first direction, wherein each of the first vertical boundary and the second vertical boundary spans At least one boundary isolation area; a backside horizontal conductor extending along the first direction in a backside first conductive layer below the substrate; a backside vertical conductor in a backside first conductive layer below the substrate dorsal Two conductive layers extend along the second direction; and a pin connector for the circuit unit is directly connected to the back at an overlap area between the back horizontal conductor and the back vertical conductor. between the side horizontal conductor and the backside vertical conductor; wherein the backside horizontal conductor has a first portion covering the overlapping area and the backside horizontal conductor has a second portion outside the overlapping area, wherein the first portion is along A first width in the first direction is greater than a second width of the second portion along the first direction. The integrated circuit of claim 5, wherein the first width is greater than the second width by more than one-eighth of the contact poly pitch. The integrated circuit of claim 5, wherein the first width is larger than the second width by more than a quarter of the contact poly pitch. The integrated circuit of claim 5, wherein the first vertical boundary and the second vertical boundary are separated by a distance along the first direction, and the distance is less than or equal to three times the contact poly pitch. A method of manufacturing an integrated circuit, including: manufacturing a first type active area structure and a second type active area structure extending along a first direction on a substrate; manufacturing a first type active area structure extending along a first direction; A plurality of gate conductors extending in the second direction, wherein each of the gate conductors is connected to the first conductor above the substrate Type active region structure and/or the second type active region structure intersects, wherein two adjacent ones of the gate conductors are spaced apart by a spacing distance and the spacing distance is equal to a contact poly pitch; on a back side under the substrate A backside horizontal conductor extending along the first direction is fabricated in the first conductive layer; a pin connector connected to the backside horizontal conductor is fabricated; and a backside second conductive layer is formed under the backside first conductive layer. A backside vertical conductor extending along the second direction is fabricated in the conductive layer, wherein the backside vertical conductor is aligned with a first vertical boundary of a circuit unit, wherein the pin connector has a connection between the backside horizontal conductor and the An overlapping area between the backside vertical conductors is directly connected between the backside horizontal conductor and the backside vertical conductor; wherein manufacturing the backside horizontal conductor includes manufacturing the backside horizontal conductor as an extended conductor, the Extension wires extend across the first vertical boundary of the circuit cell at a distance less than the contact poly pitch. The method of claim 9, further comprising: manufacturing the backside vertical conductor to form a first portion covering the overlapping area and a second portion formed outside the overlapping area, wherein the first portion is along the first A first width in a direction is greater than a second width of the second portion along the first direction.

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