TWI812572B - Semiconductor device - Google Patents

Abstract

A semiconductor device including a substrate including a first and second wells with a first interface therebetween and in contact with each other, an isolation structure in the first well, a control gate on the isolation structure, a first gate on the second well, a first charge storage structure on a region of the substrate between the control gate and the first gate and including the first interface, and source/drain regions in the substrate. The isolation structure spaces apart from the first interface by a first distance. The isolation structure is located between the source/drain regions in a top view. The first charge storage structure is disposed on a first sidewall of the control gate that faces the first gate and on a first sidewall of the first gate that faces the control gate.

Description

Semiconductor device

The present invention relates to a semiconductor device, and in particular to a memory device.

Flash memory is a widely used non-volatile memory (NVM). Silicon-oxide-nitride-oxide-silicon (SONOS) memory, metal-oxide-nitride-oxide-silicon (metal-oxide-nitride-oxide-silicon) , MONOS) and floating gate memories are some common non-volatile memories. Among the above-mentioned volatile memories, SONOS memories and MONOS memories have lower operating voltages compared to floating gate memories. However, in terms of manufacturing processes, SONOS memory and MONOS memory require additional photolithography processes, so they are not easily integrated into complementary metal oxide semiconductor (CMOS) logic processes.

The present invention provides a semiconductor device that is compatible with CMOS logic processes.

The present invention provides a semiconductor device, which includes a substrate, an isolation structure, a control gate, a first gate, a first charge storage structure and a plurality of source/drain regions. The substrate includes a first well region and a second well region. The first well region has a first conductivity type. The second well region has a second conductivity type that is different from the first conductivity type. The first well area and the second well area have a first interface in contact with each other. The isolation structure is disposed in the first well region of the substrate and is spaced a first distance from the first interface. The control gate is disposed on the isolation structure and includes first sidewalls and second sidewalls opposite to each other. The first gate is disposed on the second well region of the substrate and includes first sidewalls and second sidewalls opposite to each other, wherein the first sidewall of the first gate and the first sidewall of the control gate face each other. The first charge storage structure is disposed on the first sidewall of the control gate, the first sidewall of the first gate, and a region of the substrate between the control gate and the first gate and including the first interface. A plurality of source/drain regions are respectively disposed in the substrate. From a top view, the isolation structure is disposed between the plurality of source/drain regions, and the first gate is disposed between the isolation structure and one of the plurality of source/drain regions.

In an embodiment of the invention, the first charge storage structure includes a first dielectric layer and a first charge storage layer. The first dielectric layer is disposed on the first sidewall of the control gate, the first sidewall of the first gate and the above-mentioned area of the substrate. The first charge storage layer is disposed on the first dielectric layer.

In an embodiment of the present invention, the top of the first dielectric layer is higher than the top of the first charge storage layer.

In an embodiment of the present invention, the semiconductor device further includes a plurality of dummy charge storage structures, which are respectively disposed on the second sidewall of the first gate and the second sidewall of the control gate.

In an embodiment of the invention, the substrate includes a doped region having a first conductivity type. The doped region is in contact with the first charge storage structure, the first well region, and the second well region.

In an embodiment of the invention, the substrate includes a third well region having a second conductivity type, the first well region is between the second well region and the third well region, and the first well region is between the first well region and the third well region. There is a second interface in contact with each other, the isolation structure is spaced a second distance from the second interface, and the semiconductor device further includes a second gate and a second charge storage structure. The second gate is disposed on the third well region of the substrate and includes first sidewalls and second sidewalls opposite to each other. The first sidewall of the second gate faces the second sidewall of the control gate. The second charge storage structure is disposed on the second sidewall of the control gate, the first sidewall of the second gate, and a region of the substrate between the control gate and the second gate and including the second interface.

In one embodiment of the present invention, the second gate is disposed between the isolation structure and another one of the plurality of source/drain regions.

In one embodiment of the invention, the second gate and the second charge storage structure are aligned with the first gate and the first charge storage structure on an axis passing through the first well region of the substrate, the isolation structure and the control gate. Mirror symmetry.

In an embodiment of the invention, the substrate includes a plurality of doped regions having a first conductivity type. One of the plurality of doped regions is in contact with the first charge storage structure, the first well region, and the second well region. Another of the plurality of doped regions is in contact with the second charge storage structure, the first well region, and the third well region.

In an embodiment of the present invention, the top surface of the first gate or the top surface of the second gate is higher than the top surface of the control gate.

The present invention further provides a semiconductor device, which includes a substrate, an isolation structure, a conductive plug, a first gate, a first spacer, a dielectric liner and a plurality of source/drain regions. The substrate includes a first well region and a second well region. The first well region has a first conductivity type. The second well region has a second conductivity type that is different from the first conductivity type. The first well area and the second well area have a first interface in contact with each other. The isolation structure is disposed in the first well region of the substrate and is spaced a first distance from the first interface. The conductive plug is provided on the isolation structure. The first gate is disposed on the second well region of the substrate and includes a first sidewall facing the conductive plug and a second sidewall opposite to the first sidewall. The first spacer is disposed on the first sidewall of the first gate and includes a first tunnel dielectric layer and a first charge storage layer disposed on the first tunnel dielectric layer. The first tunneling dielectric layer is disposed on the first sidewall of the first gate and on a region of the substrate between the conductive plug and the first gate and including the first interface. A dielectric liner is disposed between the conductive plug and the first spacer to space the first charge storage layer from the conductive plug. A plurality of source/drain regions are respectively disposed in the substrate. From a top view, the isolation structure is between the plurality of source/drain regions, and the first gate is disposed between the isolation structure and one of the plurality of source/drain regions.

In an embodiment of the present invention, the top of the first tunneling dielectric layer is higher than the top of the first charge storage layer.

In an embodiment of the invention, the substrate includes a doped region having a first conductivity type. The doped region is in contact with the first spacer, the first well region and the second well region.

In an embodiment of the invention, the substrate includes a third well region having a second conductivity type. The first well area is between the second well area and the third well area, and the first well area and the third well area have a second interface in contact with each other. The isolation structure is spaced a second distance from the second interface. The semiconductor device further includes a second gate and a second spacer. The second gate is disposed on the third well region of the substrate and includes a first sidewall facing the conductive plug and a second sidewall opposite to the first sidewall. The second spacer is disposed on the first sidewall of the second gate and includes a second tunnel dielectric layer and a second charge storage layer disposed on the second tunnel dielectric layer. The second tunneling dielectric layer is disposed on the first sidewall of the second gate and on a region of the substrate between the conductive plug and the second gate and including the second interface.

In an embodiment of the present invention, from a top view, the second gate is disposed between the isolation structure and another one of the plurality of source/drain regions.

In one embodiment of the invention, the second gate and the second spacer are mirror images of the first gate and the first spacer on an axis passing through the first well region of the substrate, the isolation structure and the conductive plug. Symmetry.

In an embodiment of the invention, the substrate includes a plurality of doped regions having a first conductivity type. One of the plurality of doped regions is in contact with the first spacer, the first well region, and the second well region. Another one of the plurality of doped regions is in contact with the second spacer, the first well region, and the third well region.

In an embodiment of the present invention, the top surface of the conductive plug is higher than the top surface of the first gate or the top surface of the second gate.

In an embodiment of the present invention, the semiconductor device further includes a third spacer disposed on the second side wall of the first gate or the second side wall of the second gate. The third spacer includes a dummy charge storage layer and a dummy tunneling dielectric layer. The dummy tunneling dielectric layer is disposed between the first gate and the dummy charge storage layer or between the second gate and the dummy charge storage layer.

Based on the above, in the embodiment of the present invention, since the control gate is designed on the isolation structure and the first charge storage structure is designed on the first side wall of the control gate, the first side wall of the first gate and the substrate The position is on the area between the control gate and the first gate and including the first interface, so that the semiconductor device according to the embodiment of the present invention can be easily integrated into the CMOS logic process. In another embodiment of the present invention, since the conductive plug is designed on the isolation structure and the first spacer including the first tunneling dielectric layer and the first charge storage layer is designed on the first gate of the first On the sidewall, this allows the semiconductor device according to another embodiment of the present invention to be easily integrated into a CMOS logic process.

The present invention will be described more fully with reference to the drawings of this embodiment. However, the present invention may also be embodied in various forms and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings are exaggerated for clarity. The same or similar reference numbers indicate the same or similar components, and will not be repeated one by one in the following paragraphs.

It will be understood that when an element is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. When an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connection" may refer to a physical and/or electrical connection, and "electrical connection" or "coupling" may refer to the presence of other components between two components. "Electrical connection" as used herein may include physical connections (such as wired connections) and physical disconnections (such as wireless connections).

As used herein, "about," "approximately" or "substantially" includes the recited value and the average within an acceptable range of deviations from the specific value that a person with ordinary skill in the art can determine, taking into account the Discuss the measurement and the specific amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" may mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, "about", "approximately" or "substantially" used in this article can be used to select a more acceptable deviation range or standard deviation based on optical properties, etching properties or other properties, and one standard deviation does not apply to all properties. .

The terminology used herein is used only to describe illustrative embodiments and does not limit the disclosure. In such cases, the singular form includes the plural form unless the context dictates otherwise.

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention.

Referring to FIG. 1 , the semiconductor device 10 includes a substrate 100 , an isolation structure STI1 , a control gate 110 , a first gate 120 , a first charge storage structure 130 and a plurality of source/drain regions SD1 and SD2 .

The substrate 100 may include a deep well region 101 and a first well region 103 having a first conductivity type and a second well region 104 having a second conductivity type. The substrate 100 may be, for example, a substrate having the second conductivity type. Deep well region 101 may be formed in an active region of substrate 100 defined by isolation structure STI2. The first well area 103 and the second well area 104 may be formed in the deep well area 101 with a first interface 103a in contact with each other. In some embodiments, the isolation structure STI2 may be shallow trench isolation, but is not limited thereto. The first conductivity type is different from the second conductivity type. For example, the first conductivity type may be N-type; and the second conductivity type may be P-type, but is not limited thereto. The first conductivity type may also be P type; and the second conductivity type may also be N type.

The isolation structure STI1 is disposed in the first well region 103 of the substrate 100 and is spaced apart from the first interface 103a by a first distance d1. In some embodiments, the first distance d1 can be adjusted as needed but the first interface 103a must be located between the isolation structure STI1 and the first gate 120 . In some embodiments, the isolation structure STI1 may be a shallow trench isolation.

The control gate 110 is disposed on the isolation structure STI1 and includes a first sidewall 110a and a second sidewall 110b opposite to each other. In some embodiments, the control gate 110 may be directly disposed on the isolation structure STI1 to contact the isolation structure STI1. In some embodiments, the width of the control gate 110 in the first direction D1 is smaller than the width of the isolation structure STI1 in the first direction D1. For example, from a top view, the isolation structure STI1 may include a portion that is not covered by the control gate 110 . As shown in FIG. 1 , the isolation structure STI1 may include a first part and a second part that are not covered by the control gate 110 , wherein the first part is located on one side of the control gate 110 (for example, the side adjacent to the first side wall 110 a ). ; and the second part is located on the other side of the control gate 110 (for example, the side adjacent to the second side wall 110b). In some embodiments, the material of the control gate 110 may include polysilicon.

The first gate 120 is disposed on the second well region 104 of the substrate 100 and includes first sidewalls 120a and second sidewalls 120b opposite to each other. The first gate dielectric layer 122 may be disposed between the first gate 120 and the second well region 104 of the substrate 100 . The first side wall 120a of the first gate 120 may face the first side wall 110a of the control gate 110. In some embodiments, the first gate 120 may not overlap the first well region 103 of the substrate 100 in a direction perpendicular to the substrate 100 (eg, the second direction D2 ). In some embodiments, the material of the first gate 120 may include polysilicon. In some embodiments, the first gate dielectric layer 122 may include common gate dielectric materials such as silicon dioxide or high-k. In some embodiments, the control gate 110 and the first gate 120 may be formed simultaneously through the same process. In this way, when the top surface of the isolation structure STI1 and the top surface of the substrate 100 are at the same level and the first gate dielectric layer 122 is disposed between the first gate 120 and the substrate 100 , the first The top surface of the gate 120 may be higher than the top surface of the control gate 110 disposed directly on the isolation structure STI1.

The first charge storage structure 130 is disposed on the first sidewall 110a of the control gate 110, the first sidewall 120a of the first gate 120, and the substrate 100 is between the control gate 110 and the first gate 120 and includes On the area with the first interface 103a. The first charge storage structure 130 may include a first dielectric layer 132 and a first charge storage layer 134 disposed on the first dielectric layer 132 . The first dielectric layer 132 may be disposed on the first sidewall 110a of the control gate 110, the first sidewall 120a of the first gate 120, and between the control gate 110 and the first gate 120 of the substrate 100. on the area containing the first interface 103a. In an embodiment in which the control gate 110 exposes the isolation structure STI1, the first dielectric layer 132 may also be formed on a portion of the isolation structure STI1 exposed by the control gate 110 (such as the aforementioned first part).

In some embodiments, the first charge storage structure 130 may be formed through the following steps. First, a dielectric material layer (not shown) covering the control gate 110 and the first gate 120 is formed on the substrate 100 . The dielectric material layer may be conformally formed on the surfaces of the substrate 100 , the control gate 110 and the first gate 120 . Next, a charge storage material layer (not shown) is formed on the dielectric material layer. The distance between the control gate 110 and the first gate 120 is designed to be small enough so that the charge storage material layer located on the first sidewall 110a of the control gate 110 and the first sidewall 120a of the first gate 120 The charge storage material layers above merge together to fill the space between the control gate 110 and the first gate 120 . Afterwards, the charge storage material layer and the dielectric material layer located on the top surfaces of the control gate 110 and the first gate 120 and the charge storage material layer and the dielectric material layer located on the top surface of the substrate 100 are removed, In this way, the first dielectric layer 132 and the first charge storage layer 134 located on the first dielectric layer 132 can be formed on the first sidewall 110a of the control gate 110 and the first sidewall 120a of the first gate 120. Since the distance between the control gate 110 and the first gate 120 is designed to be small enough, compared with the charge storage material layer formed on the top surfaces of the control gate 110 and the first gate 120 , the charge storage material layer formed on The charge storage material layer between the control gate 110 and the first gate 120 will have a larger thickness because it fills the space between the control gate 110 and the first gate 120 . Therefore, after the above steps of removing the charge storage material layer and the dielectric material layer, the dielectric material layer located between the control gate 110 and the first gate 120 is only located on the first sidewall 110a of the control gate 110 A portion of the top end on the first gate electrode 120 and a portion of the top end located on the first sidewall 120a of the first gate electrode 120 are removed; and only a portion of the top end of the charge storage material layer located between the control gate electrode 110 and the first gate electrode 120 is removed. was removed. That is, as shown in FIG. 1 , the shape of the first charge storage structure 130 may be, for example, a spacer formed on the first side wall 110 a of the control gate 110 and a spacer formed on the first side wall 120 a of the first gate 120 . The shape of the spacers on the top surface merged together (the profile of the top surface can be, for example, the shape of two 1/4 circles in opposite directions touching each other). In the above embodiment, the first charge storage layer 134 may be formed such that the central region has a lower level (eg, a height in the second direction D2 ) than a surrounding area adjacent to the control gate 110 and the first gate 120 . In the above embodiment, the first dielectric layer 132 may be formed with a top end higher than a top end of the first charge storage layer 134 .

The material of the first dielectric layer 132 may include an oxide, such as silicon oxide. The material of the first charge storage layer 134 may include nitride, such as silicon nitride. In some embodiments, the first dielectric layer 132 may serve as a tunneling dielectric layer of the SONOS memory and/or a blocking dielectric layer of the SONOS memory. For example, the portion of the first dielectric layer 132 adjacent to the channel (for example, the portion where the first dielectric layer 132 contacts the substrate 100) can be used as a tunneling dielectric layer of the SONOS memory; while the first dielectric layer 132 is in The portion adjacent to the control gate 110 (eg, the first dielectric layer 132 located on the first sidewall 110 a of the control gate 110 ) may serve as a blocking dielectric layer of the SONOS memory. In some embodiments, the first charge storage layer 134 may serve as a charge trapping layer of the SONOS memory.

In some embodiments, in the case where the first charge storage structure 130 is formed through the above steps, the semiconductor device 10 may further include a second sidewall formed on the second sidewall 110b of the control gate 110 and the first gate 120 respectively. A plurality of dummy charge storage structures 140 on 120b. The dummy charge storage structure 140 may be, for example, formed on the second sidewall 110b of the control gate 110 and the second sidewall of the first gate 120 after performing the above steps of removing the charge storage material layer and the dielectric material layer. 120b on. That is, the dummy charge storage structure 140 may include a dielectric layer 142 and a charge storage layer 144 formed on the dielectric layer 142 . The material of dielectric layer 142 may include an oxide, such as silicon oxide. The material of charge storage layer 144 may include nitride, such as silicon nitride. In some embodiments. Since the dielectric layer 142 does not serve as a tunneling dielectric layer of the SONOS memory, it can also be called a dummy tunneling dielectric layer. In some embodiments, since the charge storage layer 144 does not serve as a charge trapping layer of the SONOS memory, it can also be called a dummy charge storage layer.

The source/drain region SD1 and the source/drain region SD2 are respectively provided in the substrate 100 . From a top view, the isolation structure STI1 is disposed between the source/drain region SD1 and the source/drain region SD2, and the first gate 120 is disposed between the isolation structure STI1 and the source/drain region SD1 and between one of the source/drain regions SD2. In some embodiments, the source/drain region SD1 and the source/drain region SD2 may be doped with a dopant having the first conductivity type, but are not limited thereto. In some embodiments, the source/drain region SD1 may be disposed in the second well region 104 of the substrate 100 , and the source/drain region SD2 may be disposed in the first well region 103 of the substrate 100 .

In the following, the operation mode of the semiconductor device 10 as a SONOS memory will be described by assuming that the first conductivity type is N type and the second conductivity type is P type, but it is not limited thereto. In some embodiments, the semiconductor device 10 may perform a programming operation by, for example, the following voltage operation mode: applying a high positive voltage to the source/drain region SD2 and the control gate 110; applying a high positive voltage to the first gate 120 applies a voltage greater than the threshold voltage (threshold voltage); and applies a ground voltage to the source/drain region SD1. In this way, electrons can be transferred from the source/drain region SD1 through the second well region 104 and the first well region 103 to the source along the path shown in FIG. 1 (see the solid arrow). /Drain area SD2. During the process of electrons transferring from the source/drain region SD1 to the source/drain region SD2, since the control gate 110 also applies a high positive voltage, the electrons will be attracted by the control gate 110 and enter the first gate. The charge storage structure 130 is stored in the first charge storage layer 134 . In some embodiments, the semiconductor device 10 may perform an erase operation through a Fowler-Nordheim tunneling (FN-tunneling) mechanism by, for example, the following voltage operation: changing the control gate A high negative voltage is applied to pole 110; and a high positive voltage is applied to second well region 104. In this way, the electrons stored in the first charge storage layer 134 can be erased.

In some embodiments, to further improve the performance of the semiconductor device 10, the substrate 100 may include a doped region 105 having a first conductivity type. The doped region 105 may be located under the first charge storage structure 130 and in contact with the first charge storage structure 130 , the first well region 103 and the second well region 104 . In this way, when the semiconductor device 10 performs a program operation, it is easier for electrons to enter the first charge storage layer 134 of the first charge storage structure 130 , or when the semiconductor device 10 performs an erasure operation, it is easier for electrons to escape from the third charge storage layer 134 . A charge storage layer 134 is erased. In some embodiments, as shown in FIG. 1 , the doped region 105 may span the first interface 103 a between the first well region 103 and the second well region 104 . In some embodiments, the doped region 105 may also be formed under the dummy charge storage structure 140 . In some embodiments, the doped region 105 may be integrated into a lightly doped drain (LDD) process in a CMOS logic process.

In some embodiments, the doping concentration of the source/drain regions SD1 and SD2 may be greater than the doping concentration of the doping region 105 and the first well region 103 . In some embodiments, the doping concentration of the doping region 105 may be greater than the doping concentration of the first well region 103 .

Based on the structure and manufacturing method as described above, the control gate 110, the first gate 120 and the first charge storage structure 130 are compatible with the CMOS logic process, so no additional mask is required for additional lithography processes. . For example, the control gate 110 and the first gate 120 may be compatible with a step of forming a CMOS gate in a logic process. The first charge storage structure 130 may be compatible with the step of forming spacers on the sidewalls of the CMOS gate during the logic process. In some embodiments, the above structure and manufacturing method can not only be integrated into the process of planar field effect transistors, but can also be applied to fin field effect transistors (FinFET) or surround gate field effect transistors (GAAFET). In process.

In some embodiments, the semiconductor device 10 may optionally include a silicone layer 150 formed on the source/drain regions SD1 and SD2 , the control gate 110 and the first gate 120 . The silicide layer 150 is, for example, self-aligned silicide (Salicide). The silicon compound layer 150 may be electrically connected to the source/drain regions SD1 and SD2, the control gate 110 and the first gate 120 that it contacts, respectively. The material of the silicide layer 150 may include metal silicide. For example, the material of the silicide layer 150 may include cobalt, titanium or nickel silicide, such as titanium silicide (TiSi ₂ ), cobalt silicide (CoSi ₂ ) or nickel silicide (NiSi).

In some embodiments, the semiconductor device 10 may further include a dielectric layer 160 formed on the substrate 100 and a conductive plug 170 formed in the dielectric layer 160 . The dielectric layer 160 covers the substrate 100, the isolation structure STI2, the control gate 110, the first gate 120, the first charge storage structure 130, the dummy charge storage structure 140, the silicide layer 150, and the source/drain regions SD1 and SD2 . The conductive plug 170 can be electrically connected to the corresponding control gate 110 , the first gate 120 and the source/drain regions SD1 and SD2 respectively. In some embodiments, the conductive plug 170 can be electrically connected to the corresponding control gate 110 , the first gate 120 and the source/drain regions SD1 and SD2 respectively through the silicon compound layer 150 . In some embodiments, the first gate 120 may be electrically connected to the word line (eg, connected to a common word line) through the conductive plug 170 . One of the source/drain regions SD1 and SD2 may be electrically connected to the source line through the conductive plug 170 . The other one of the source/drain regions SD1 and SD2 may be electrically connected to the bit line through the conductive plug 170 . The material of the dielectric layer 160 may include an oxide, such as silicon oxide deposited from a tetraethoxysilane (TEOS) source. The material of the conductive plug 170 may include metal, metal alloy, metal nitride, metal silicide, or combinations thereof. In some embodiments, metals and metal alloys may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof. The metal nitride may be, for example, titanium nitride, tungsten nitride, tantalum nitride, silicon tantalum nitride, silicon titanium nitride, silicon tungsten nitride, or combinations thereof. The metal silicide is, for example, tungsten silicide, titanium silicide, cobalt silicide, zirconium silicide, platinum silicide, molybdenum silicide, copper silicide, nickel silicide or combinations thereof.

FIG. 2 is a schematic cross-sectional view of a semiconductor device according to a second embodiment of the present invention. 3 is an equivalent circuit diagram of the semiconductor device according to the second embodiment of the present invention.

The semiconductor device 20 shown in FIG. 2 is similar to the semiconductor device 10 shown in FIG. 1 . The difference is that the semiconductor device 20 further includes a second gate 220 , a second gate dielectric layer 222 and a second charge storage structure 230 , and the substrate 200 includes a third well region 204 . Other identical or similar components use the same or similar element numbers and will not be described further below.

The substrate 200 of the semiconductor device 20 includes a third well region 204 located in the deep well region 101 and having a second conductivity type. The first well area 103 is between the second well area 104 and the third well area 204, and the first well area 103 and the third well area 204 have a second interface 103b in contact with each other. The isolation structure STI1 is spaced apart from the second interface 103b by a second distance d2.

The second gate 220 is disposed on the third well region 204 of the substrate 200 and includes first sidewalls 220a and second sidewalls 220b opposite to each other. The first side wall 220a of the second gate 220 faces the second side wall 110b of the control gate 110. The second gate dielectric layer 222 may be disposed between the second gate 220 and the third well region 204 of the substrate 200 . In some embodiments, the second gate 220 may not overlap the first well region 103 of the substrate 200 in a direction perpendicular to the substrate 200 (eg, the second direction D2 ). In some embodiments, the material of the second gate 220 may include polysilicon. In some embodiments, the second gate dielectric layer 222 may include common gate dielectric materials such as silicon dioxide or high-k. In some embodiments, the control gate 110 , the first gate 120 and the second gate 220 may be formed simultaneously through the same process. In this way, the top surface of the isolation structure STI1 and the top surface of the substrate 200 are at the same level, and the first gate dielectric layer 122 and the second gate dielectric layer 222 are respectively disposed on the first gate 120 and the substrate. 200 and between the second gate 220 and the substrate 200 , the top surface of the first gate 120 or the second gate 220 may be higher than the top surface of the control gate 110 directly disposed on the isolation structure STI1 surface.

The second charge storage structure 230 is disposed on the second sidewall 110b of the control gate 110, the first sidewall 220a of the second gate 220, and the substrate 200 is between the control gate 110 and the second gate 220 and includes on the area of the second interface 103b. The second charge storage structure 230 may include a second dielectric layer 232 and a second charge storage layer 234 disposed on the second dielectric layer 232 . The second dielectric layer 232 may be disposed on the second sidewall 110b of the control gate 110, the first sidewall 220a of the second gate 220, and the substrate 200 between the control gate 110 and the second gate 220. On the area including the second interface 103b. In an embodiment where the control gate 110 is exposed to the isolation structure STI1, the second dielectric layer 232 may also be formed on a portion of the isolation structure STI1 where the control gate 110 is exposed (such as the aforementioned second part). .

In some embodiments, the second charge storage structure 230 may be formed through the steps described above for forming the first charge storage structure 130 . That is to say, the distance between the control gate 110 and the second gate 220 is designed to be small enough so that the charge storage material layer located on the second sidewall 110b of the control gate 110 and the charge storage material layer located on the second gate 220 The charge storage material layers on the first sidewall 220a merge together to fill the space between the control gate 110 and the second gate 220. Therefore, the charge storage material layer and the dielectric material layer located on the top surfaces of the control gate 110 and the first gate 120 and the charge storage material layer and the dielectric material layer located on the top surface of the substrate 200 are removed. At this time, the second dielectric layer 232 and the second charge storage layer 234 located on the second dielectric layer 232 can be formed on the second sidewall 110b of the control gate 110 and the first sidewall 220a of the second gate 220. Since the distance between the control gate 110 and the second gate 220 is designed to be small enough, compared with the charge storage material layer formed on the top surfaces of the control gate 110 and the second gate 220, the charge storage material layer formed on The charge storage material layer between the control gate 110 and the second gate 220 will have a larger thickness due to filling the space between the control gate 110 and the second gate 220 . Therefore, after the steps of removing the charge storage material layer and the dielectric material layer, the dielectric material layer located between the control gate 110 and the second gate 220 is only located on the second sidewall 110b of the control gate 110 A portion of the top end and a portion of the top end located on the first sidewall 220a of the second gate 220 are removed; and only a portion of the top end of the charge storage material layer located between the control gate 110 and the second gate 220 is removed. Remove. That is, as shown in FIG. 2 , the shape of the second charge storage structure 230 may be, for example, a spacer formed on the second sidewall 110b of the control gate 110 and a first sidewall 220a formed on the second gate 220 . The shape in which the spacers on the top surface merge together (the profile of the top surface can be, for example, the shape of two 1/4 circles in opposite directions touching each other). In the above embodiment, the second charge storage layer 234 may be formed such that the central region has a lower level (for example, a height in the second direction D2 ) than a surrounding area adjacent to the control gate 110 and the second gate 220 . . In the above embodiment, the second dielectric layer 232 may be formed with a top end higher than a top end of the second charge storage layer 234 .

The material of the second dielectric layer 232 may include an oxide, such as silicon oxide. The material of the second charge storage layer 234 may include nitride, such as silicon nitride. In some embodiments, the second dielectric layer 232 may serve as a tunneling dielectric layer of the SONOS memory and/or a blocking dielectric layer of the SONOS memory. For example, the portion of the second dielectric layer 232 adjacent to the channel (for example, the portion where the second dielectric layer 232 contacts the substrate 200) can serve as a tunneling dielectric layer of the SONOS memory; while the second dielectric layer 232 is in The portion adjacent to the control gate 110 (eg, the second dielectric layer 232 located on the second sidewall 110b of the control gate 110) may serve as a blocking dielectric layer of the SONOS memory. In some embodiments, the second charge storage layer 234 may serve as a charge trapping layer of the SONOS memory.

In some embodiments, the second gate 220 and the first gate 120 may be formed simultaneously in the same process. In some embodiments, the second charge storage structure 230 and the first charge storage structure 130 may be formed simultaneously in the same process. In some embodiments, the second gate 220 and the second charge storage structure 230 are aligned with the first gate 120 and the first gate 120 on an axis passing through the first well region 103 of the substrate 200 , the isolation structure STI1 and the control gate 110 . A charge storage structure 130 has mirror symmetry.

In some embodiments, from a top view, the first gate 120 may be disposed between the isolation structure STI1 and the source/drain region SD1 , and the second gate 220 may be disposed between the isolation structure STI1 and the source region SD1 /Drain area between SD2.

In some embodiments, when the second charge storage structure 230 is formed through the steps of forming the first charge storage structure 130, the dummy charge storage structure 140 may be formed on the second sidewall 120b of the first gate 120 and the second gate. on the second side wall 220b of 220.

In the following, the operation mode of the semiconductor device 20 as a SONOS memory will be described by assuming that the first conductivity type is N type and the second conductivity type is P type, but it is not limited thereto. In some embodiments, the semiconductor device 20 may perform a programming operation by, for example, the following voltage operation mode: applying a high positive voltage to the source/drain region SD2 and the control gate 110; applying a high positive voltage to the first gate 120 and the second gate 220 apply a voltage greater than the threshold voltage (threshold voltage); and apply a ground voltage to the source/drain region SD1. In this way, electrons can pass from the source/drain region SD1 through the second well region 104, the first well region 103 and the third well region in sequence along the path shown in Figure 2 (see the solid arrow). 204 and passed to the source/drain region SD2. During the process of electrons transferring from the source/drain region SD1 to the source/drain region SD2, since the control gate 110 also applies a high positive voltage, the electrons will be attracted by the control gate 110 and enter the first gate. The charge storage structure 130 is stored in the first charge storage layer 134 . In some embodiments, since the source/drain region SD2 can apply a voltage greater than the control gate 110 , electrons will only enter into the source/drain region SD2 during the transfer from the source/drain region SD1 to the source/drain region SD2 . into the first charge storage structure 130 without entering the second charge storage structure 230 . In other words, the semiconductor device 20 can perform two-bit programming operations. For example, the semiconductor device 20 can perform a programming operation of another bit through the following voltage operation mode: applying a high positive voltage to the source/drain region SD1 and the control gate 110; The first gate 120 and the second gate 220 apply a voltage greater than a threshold voltage (threshold voltage); and a ground voltage is applied to the source/drain region SD2. In this way, electrons can pass from the source/drain region SD2 through the third well region 204, the first well region 103 and the second well region 104 sequentially along the path shown in Figure 2 (see the dotted arrow). And passed to the source/drain region SD1. During the process of electrons transferring from the source/drain region SD2 to the source/drain region SD1, since the control gate 110 also applies a high positive voltage, the electrons will be attracted by the control gate 110 and enter the second gate. The charge storage structure 230 is stored in the second charge storage layer 234 . In some embodiments, since the source/drain region SD1 can apply a voltage greater than the control gate 110 , electrons will only enter into the source/drain region SD1 during the transfer from the source/drain region SD2 to the source/drain region SD1 . into the second charge storage structure 230 without entering the first charge storage structure 130 .

In some embodiments, the semiconductor device 20 may perform an erase operation through a Fowler-Nordheim tunneling (FN-tunneling) mechanism by, for example, the following voltage operation: changing the control gate A high negative voltage is applied to the pole 110; and a high positive voltage is applied to the second well region 104 or the third well region 204. In this way, the electrons stored in the first charge storage layer 134 or the second charge storage layer 234 can be erased.

In some embodiments, to further improve the performance of the semiconductor device 20 , the substrate 200 may include a doped region 105 having a first conductivity type. The doped region 105 may be located under the first charge storage structure 130 and in contact with the first charge storage structure 130 , the first well region 103 and the second well region 104 . On the other hand, the doped region 105 may be located under the second charge storage structure 230 and in contact with the second charge storage structure 230, the first well region 103 and the third well region 204. In this way, when the semiconductor device 20 is executing a program operation, electrons are more likely to enter the first charge storage layer 134 of the first charge storage structure 130 and/or the second charge storage layer 234 of the second charge storage structure 230, Or when the semiconductor device 20 performs an erasing operation, electrons are more easily erased from the first charge storage layer 134 and/or the second charge storage layer 234 . In some embodiments, as shown in FIG. 2 , the doped region 105 below the first charge storage structure 130 may span the first interface 103 a between the first well region 103 and the second well region 104 . The doped region 105 below the second charge storage structure 230 may span the second interface 103b between the first well region 103 and the third well region 204.

Please refer to the equivalent circuit diagram of the semiconductor device 20 shown in FIG. 3 . The first gate 120 may serve as the gate of the first selection transistor ST1 and be electrically connected to the word line WL1. The second gate 220 can serve as the gate of the second selection transistor ST2 and is electrically connected to the word line WL2. The first charge storage structure 130 and the second charge storage structure 230 may serve as the first memory unit M1 and the second memory unit M2 respectively. The control gate 110 can be electrically connected to the control signal line CG. The source/drain region SD1 may be connected to one of the source line SL and the bit line BL (eg BL/SL), and the source/drain region SD2 may be connected to the source line SL and the bit line BL. the other of (e.g. SL/BL).

4 is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present invention.

The semiconductor device 30 shown in FIG. 4 is similar to the semiconductor device 10 shown in FIG. 1 . The difference is that the semiconductor device 30 replaces the control gate 110 with a conductive plug 370 and includes a first tunneling dielectric layer 332 and a The first spacer 330 of the first charge storage layer 334 replaces the first charge storage structure 130, and the semiconductor device 30 further includes a dielectric liner 372. Other identical or similar components use the same or similar element numbers and will not be described further below.

The conductive plug 370 is provided on the isolation structure STI1. The first gate 120 is disposed on the second well region 104 of the substrate 100 and includes a first sidewall 120a facing the conductive plug 370 and a second sidewall 120b opposite to the first sidewall 120a. In some embodiments, the material of the conductive plug 370 may include metal, metal alloy, metal nitride, metal silicide, or combinations thereof. In some embodiments, metals and metal alloys may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof. The metal nitride may be, for example, titanium nitride, tungsten nitride, tantalum nitride, silicon tantalum nitride, silicon titanium nitride, silicon tungsten nitride, or combinations thereof. The metal silicide is, for example, tungsten silicide, titanium silicide, cobalt silicide, zirconium silicide, platinum silicide, molybdenum silicide, copper silicide, nickel silicide or combinations thereof. In some embodiments, the conductive plug 370 and the conductive plug 170 are formed simultaneously in the same process, but this is not a limitation. In some embodiments, the top surface of the conductive plug 370 is higher than the top surface of the first gate 120 . In some embodiments, conductive plug 370 may extend into isolation structure STI1.

The first spacer 330 is disposed on the first sidewall 120 a of the first gate 120 and includes a first tunnel dielectric layer 332 and a first charge storage layer 334 disposed on the first tunnel dielectric layer 332 . The first tunnel dielectric layer 332 is disposed on the first sidewall 120a of the first gate 120 and on the region of the substrate 100 between the conductive plug 370 and the first gate 120 and including the first interface 103a. In an embodiment in which the conductive plug 370 exposes the isolation structure STI1, the first tunnel dielectric layer 332 may also be formed on a portion of the isolation structure STI1 exposed by the conductive plug 370.

The dielectric liner 372 is disposed between the conductive plug 370 and the first spacer 330 to space the first charge storage layer 334 from the conductive plug 370 .

In some embodiments, the first spacer 330 may be formed via the following steps. First, a dielectric material layer (not shown) covering the isolation structure STI1 and the first gate 120 is formed on the substrate 100 . The dielectric material layer may be conformally formed on the surfaces of the substrate 100 and the first gate 120 . Next, a charge storage material layer (not shown) is formed on the dielectric material layer. After that, the charge storage material layer and the dielectric material layer located on the top surface of the first gate 120 and the charge storage material layer and the dielectric material layer located on the top surface of the substrate 100 are removed, so that the first A first tunnel dielectric layer 332 and a first charge storage layer 334 located on the first tunnel dielectric layer 332 are formed on the first sidewall 120a of the gate 120 . In the above embodiment, the first tunnel dielectric layer 332 may be formed with a top end higher than a top end of the first charge storage layer 334 .

In some embodiments, conductive plug 370 and dielectric liner 372 may be formed via the following steps. First, an opening (not shown) exposing the first spacer 330 and the isolation structure STI1 is formed in the dielectric layer 160 . Next, a dielectric liner 372 is formed on the sidewall of the opening. Afterwards, a conductive material is filled into the opening to form a conductive plug 370 on the dielectric liner 372 . In the step of removing part of the dielectric layer 160 to form the opening, the first spacer 330 can serve as an etching mask, so the formed conductive plug 370 can be called a self-aligned conductive plug. In this embodiment, the dielectric layer 160 may be made of a material that has an etching selectivity ratio with the first tunneling dielectric layer 332 and the first charge storage layer 334 . In some embodiments, the step of forming the conductive plug 170 may be integrated with the step of forming the conductive plug 370, but this is not a limitation.

In some embodiments, the first tunnel dielectric layer 332 can be used as the tunnel dielectric layer of the MONOS memory, the conductive plug 370 can be used as the control gate of the MONOS memory, and the dielectric liner 372 can be used as the control gate of the MONOS memory. The blocking dielectric layer and the first charge storage layer 334 can serve as the charge trapping layer of the MMONOS memory.

In some embodiments, in the case where the first spacer 330 is formed through the above steps, the semiconductor device 30 may further include a dummy charge storage structure 140 formed on the second sidewall 120b of the first gate 120 . The dummy charge storage structure 140 may be correspondingly formed on the second sidewall 120b of the first gate 120 after performing the above steps of removing the charge storage material layer and the dielectric material layer. That is to say, the dummy charge storage structure 140 may include a dummy tunneling dielectric layer 142 and a dummy charge storage layer 144 formed on the dummy tunneling dielectric layer 142, wherein the dummy tunneling dielectric layer 142 may be disposed on the first gate. between pole 120 and dummy charge storage layer 144.

FIG. 5 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention.

The semiconductor device 40 shown in FIG. 5 is similar to the semiconductor device 30 shown in FIG. 4 . The difference is that the semiconductor device 40 further includes a second gate 220 , a second gate dielectric layer 222 and a second spacer 430 . And the substrate 200 includes a third well region 204. Other identical or similar components use the same or similar element numbers and will not be described further below.

The substrate 200 of the semiconductor device 40 includes a third well region 204 located in the deep well region 101 and having a second conductivity type. The first well area 103 is between the second well area 104 and the third well area 204, and the first well area 103 and the third well area 204 have a second interface 103b in contact with each other. The isolation structure STI1 is spaced apart from the second interface 103b by a second distance d2.

The second gate 220 is disposed on the third well region 204 of the substrate 200 and includes first sidewalls 220a and second sidewalls 220b opposite to each other. The first side wall 220a of the second gate 220 faces the conductive plug 370. The second gate dielectric layer 222 may be disposed between the second gate 220 and the third well region 204 of the substrate 200 . In some embodiments, the second gate 220 may not overlap the first well region 103 of the substrate 200 in a direction perpendicular to the substrate 200 (eg, the second direction D2 ). In some embodiments, the material of the second gate 220 may include polysilicon. In some embodiments, the second gate dielectric layer 222 may include common gate dielectric materials such as silicon dioxide or high-k. In some embodiments, the first gate 120 and the second gate 220 may be formed simultaneously through the same process. In some embodiments, the top surface of the conductive plug 370 may be higher than the top surface of the second gate 220 .

The second spacer 430 is disposed on the first sidewall 220a of the second gate 220 and includes a second tunnel dielectric layer 432 and a second charge storage layer 434 disposed on the second tunnel dielectric layer 432 . The second tunneling dielectric layer 432 is disposed on the first sidewall 220a of the second gate 220 and on the region of the substrate 200 between the conductive plug 370 and the second gate 220 and including the second interface 103b. In an embodiment in which the conductive plug 370 exposes the isolation structure STI1 , the second tunnel dielectric layer 432 may also be formed on a portion of the isolation structure STI1 exposed by the conductive plug 370 . The second spacer 430 can be formed through the steps of forming the first spacer 330 described above, which will not be repeated here. In some embodiments, the second tunneling dielectric layer 432 may be formed with a top end higher than a top end of the second charge storage layer 434 .

In some embodiments, the second tunneling dielectric layer 432 can be used as the tunneling dielectric layer of the MONOS memory, the conductive plug 370 can be used as the control gate of the MONOS memory, and the dielectric liner 372 can be used as the control gate of the MONOS memory. The blocking dielectric layer and the second charge storage layer 434 can serve as the charge trapping layer of the MMONOS memory. As described above for semiconductor device 20 , semiconductor device 40 may also perform two-bit operations.

In some embodiments, the second gate 220 and the second spacer 430 are aligned with the first gate 120 and the first spacer 430 on an axis passing through the first well region 103 of the substrate 200 , the isolation structure STI1 and the conductive plug 370 . The spacer 330 is mirror symmetrical.

In some embodiments, in the case where the second spacer 430 is formed through the steps of forming the first spacer 330 as described above, the semiconductor device 40 may further include a second spacer formed on the second sidewall 120b of the first gate 120 and a second spacer 430 formed on the second sidewall 120b of the first gate 120 . The dummy charge storage structure 140 on the second sidewall 220b of the gate 220. The dummy charge storage structure 140 may be, for example, formed on the second sidewall 120b of the first gate 120 and the second sidewall of the second gate 220 after performing the above steps of removing the charge storage material layer and the dielectric material layer. on the side wall 220b. That is to say, the dummy charge storage structure 140 may include a dummy tunneling dielectric layer 142 and a dummy charge storage layer 144 formed on the dummy tunneling dielectric layer 142, wherein the dummy tunneling dielectric layer 142 may be disposed on the first gate. between the electrode 120 and the dummy charge storage layer 144 and between the second gate 220 and the dummy charge storage layer 144 .

6 is a schematic cross-sectional view of a semiconductor device according to a fifth embodiment of the present invention.

The semiconductor device 50 shown in FIG. 6 is similar to the semiconductor device 40 shown in FIG. 5 , except that the semiconductor device 50 replaces the conductive plug 370 with a conductive plug 570 . Other identical or similar components use the same or similar element numbers and will not be described further below.

The conductive plug 570 is disposed on the isolation structure STI1, and the dielectric layer 160 is formed between the conductive plug 570 and the first spacer 330 and between the conductive plug 570 and the second spacer 430. In other words, the dielectric layer 160 can serve as a blocking dielectric layer of the MONOS memory. In some embodiments, the conductive plug 570 may be formed simultaneously with the conductive plug 170 in the same process. In some embodiments, conductive plug 570 may extend into isolation structure STI1. In some embodiments, the top surface of the conductive plug 570 may be higher than the top surface of the first gate 120 and/or the second gate 220 .

To sum up, in the semiconductor device of the above embodiment, since the control gate is designed on the isolation structure and the first charge storage structure is designed on the first side wall of the control gate, the first side wall of the first gate The semiconductor device of the above embodiment can be easily integrated into a CMOS logic process.

In the semiconductor device of another embodiment described above, since the conductive plug is designed on the isolation structure and the first spacer including the first tunneling dielectric layer and the first charge storage layer is designed on the first gate electrode, On one side wall, this allows the semiconductor device of another embodiment to be easily integrated into a CMOS logic process.

10, 20, 30, 40, 50: Semiconductor devices 100, 200: Base 101:Sham Tseng District 103:First well area 103a: First interface 103b: Second interface 104:Second well area 105: Doped area 110: Control gate 110a, 120a, 220a: first side wall 110b, 120b, 220b: second side wall 120: first gate 122: First gate dielectric layer 130: First charge storage structure 132: First dielectric layer 134: First charge storage layer 140: Dummy charge storage structure 142:Dielectric layer 144: Charge storage layer 150: Silicone layer 160: Dielectric layer 170, 370, 570: Conductive plug 204:Third well area 220: Second gate 222: Second gate dielectric layer 230: Second charge storage structure 232: Second dielectric layer 234: Second charge storage layer 330: first spacer 332: First tunneling dielectric layer 334: First charge storage layer 372:Dielectric lining 430: Second spacer 432: Second tunneling dielectric layer 434: Second charge storage layer CG: control signal line d1: first distance d2: second distance D1: first direction D2: second direction M1, M2: memory unit STI1, STI2: isolation structure ST1, ST2: select transistor SD1, SD2: source/drain area WL1, WL2: character lines BL: bit line SL: source line

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of a semiconductor device according to a second embodiment of the present invention. 3 is an equivalent circuit diagram of the semiconductor device according to the second embodiment of the present invention. 4 is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present invention. FIG. 5 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention. 6 is a schematic cross-sectional view of a semiconductor device according to a fifth embodiment of the present invention.

10:Semiconductor device 100:Base 101:Sham Tseng District 103:First well area 103a: First interface 104:Second well area 105: Doped area 110: Control gate 110a, 120a: first side wall 110b, 120b: second side wall 120: first gate 122: First gate dielectric layer 130: First charge storage structure 132: First dielectric layer 134: First charge storage layer 140: Dummy charge storage structure 142:Dielectric layer 144: Charge storage layer 150: Silicone layer 160: Dielectric layer 170: Conductive plug d1: first distance D1: first direction D2: second direction STI1, STI2: isolation structure SD1, SD2: source/drain area

Claims (9)

A semiconductor device includes: a substrate including a first well region and a second well region, the first well region has a first conductivity type, and the second well region has a second conductivity different from the first conductivity type. Type, the first well region and the second well region have a first interface in contact with each other; an isolation structure is disposed in the first well region of the substrate and spaced apart from the first interface a first distance; a first conductive plug disposed on the isolation structure; a first gate disposed on the second well region of the substrate and including a first sidewall facing the conductive plug; a second sidewall opposite to the first sidewall; a first spacer disposed on the first sidewall of the first gate and including a first tunnel dielectric layer and a first spacer disposed on the first tunnel a first charge storage layer on a dielectric layer, the first tunneling dielectric layer is disposed on the first sidewall of the first gate and on the substrate between the conductive plug and the On the area between the first gates and including the first interface; a dielectric liner disposed between the conductive plug and the first spacer, so that the first charge storage layer and The conductive plugs are spaced apart; a plurality of source/drain regions are respectively provided in the substrate. From a top view, the isolation structure is between the plurality of source/drain regions. , and the first gate is disposed between the isolation structure and one of the plurality of source/drain regions; and a second conductive plug is disposed between the plurality of source/drain regions. area, wherein the first conductive plug and the second conductive plug are formed simultaneously in the same process. The semiconductor device of claim 1, wherein a top of the first tunneling dielectric layer is higher than a top of the first charge storage layer. The semiconductor device of claim 1, wherein the substrate includes a doped region having the first conductivity type, the doped region being connected to the first spacer, the first well region and the third Erjing District Contact. The semiconductor device of claim 1, wherein the substrate includes a third well region having the second conductivity type, the first well region being between the second well region and the third well region , the first well region and the third well region have a second interface in contact with each other, the isolation structure is spaced apart from the second interface by a second distance, and the semiconductor device further includes: a second a gate disposed on the third well region of the substrate and including a first sidewall facing the conductive plug and a second sidewall opposite to the first sidewall; and a second spacer disposed on The first sidewall of the second gate electrode includes a second tunnel dielectric layer and a second charge storage layer disposed on the second tunnel dielectric layer. The second tunnel dielectric layer A layer is disposed on the first sidewall of the second gate and on a region of the substrate between the conductive plug and the second gate and including the second interface. The semiconductor device of claim 4, wherein the second gate is disposed between the isolation structure and another one of the plurality of source/drain regions from a top view. The semiconductor device of claim 4, wherein the second gate and the second spacer are in a position passing through the first well region of the substrate, the isolation structure and the conductive plug. The axis is mirror symmetrical to the first gate and the first spacer. The semiconductor device of claim 4, wherein the substrate includes a plurality of doped regions having the first conductivity type, and one of the plurality of doped regions is connected to the first spacer, the The first well region and the second well region are in contact, and another one of the plurality of doped regions is in contact with the second spacer, the first well region, and the third well region. The semiconductor device of claim 4, wherein a top surface of the conductive plug is higher than a top surface of the first gate or a top surface of the second gate. The semiconductor device according to claim 4, further comprising: a third spacer disposed on the second side wall of the first gate or on the second side wall of the second gate, the The third spacer includes a dummy charge storage layer and a dummy tunneling dielectric layer. The dummy tunneling dielectric layer is disposed between the first gate and the dummy charge storage layer or is the second gate. and between the dummy charge storage layer.

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