TWI809961B - Method for manufacturing semiconductor structure having vias with different dimensions - Google Patents

Abstract

The present application provides a method of manufacturing a semiconductor structure having vias with different dimensions. The method includes: providing a first wafer including a first substrate, a first dielectric layer over the first substrate, and a first conductive pad surrounded by the first dielectric layer; providing a second wafer including a second dielectric layer, a second substrate over the second dielectric layer, and a second conductive pad surrounded by the second dielectric layer; forming a passivation over the second substrate; forming a first conductive via extending from the first conductive pad through the second wafer and the passivation, and having a first width surrounded by the second wafer; and forming a second conductive via extending from the second conductive pad through the passivation and the second substrate and partially through the second dielectric layer, and having a second width surrounded by the second wafer.

Description

Method for fabricating semiconductor structures with through holes of different sizes

This application claims priority to US Patent Application Nos. 17/742,544 and 17/742,959 (ie, the priority date is "May 12, 2022"), the contents of which are incorporated herein by reference in their entirety.

The disclosure relates to a method for preparing a semiconductor structure. In particular, it relates to a method for preparing a semiconductor structure with through holes of different sizes.

Semiconductor components are used in various electronic applications, such as personal computers, mobile phones, digital cameras, or other electronic devices. The fabrication of semiconductor devices involves sequentially depositing layers of different materials on a semiconductor wafer, and patterning the layers of materials using lithography and etching processes to form microelectronic devices on or in the semiconductor wafer. In the circle, the microelectronic components include transistors, diodes, resistors and/or capacitors.

The semiconductor industry continues to increase the integration density of microelectronic components by continuously shrinking the minimum feature size, which allows more components to be integrated into a given area. In order to facilitate the formation and integration of devices of different sizes, smaller packaging structures with smaller footprints have been developed to package the semiconductor devices. However, such formation and integration may increase the complexity of the manufacturing process. Therefore, it is desirable to develop improvements that address the above-mentioned challenges.

The above "prior art" description is only to provide background technology, and does not acknowledge that the above "prior art" description discloses the subject of this disclosure, and does not constitute the prior art of this disclosure, and any description of the above "prior art" shall not form part of this case.

An embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes a first wafer with a first substrate, a first dielectric layer and a first conductive pad, the first dielectric layer is disposed on the first substrate, and the first conductive pad is covered by the first substrate. Surrounded by the first dielectric layer; a second wafer has a second dielectric layer, a second base and a second conductive pad, the second base is disposed on the second dielectric layer, the second The conductive pad is surrounded by the second dielectric layer; a passivation layer is disposed on the second substrate; a first conductive via extends from the first conductive pad through the second wafer and the passivation layer, and having a first width surrounded by the second wafer; and a second conductive via extending from the second conductive pad through the passivation layer and the second substrate and partially through the second dielectric layer, and has a second width surrounded by the second wafer; wherein the second width is substantially smaller than the first width.

In some embodiments, the second conductive via has a third width surrounded by the passivation layer and disposed on the second width.

In some embodiments, the third width is approximately equal to the first width.

In some embodiments, the third width is substantially greater than the second width.

In some embodiments, the second conductive via has a first portion in the second width, a second portion in the third width, and from the second portion the first portion tapers and is A tapered portion surrounded by the passivation layer, wherein the tapered portion is surrounded by the passivation layer.

In some embodiments, the tapered portion is disposed between the first portion and the second portion and is coupled with the first portion and the second portion.

In some embodiments, a thickness of the first wafer is substantially greater than a thickness of the second wafer.

In some embodiments, the semiconductor structure further includes a bonding dielectric disposed between the first dielectric layer and the second dielectric layer to bond the first dielectric layer to the second dielectric layer. layer.

In some embodiments, the first conductive via is at least partially surrounded by the bonding dielectric.

In some embodiments, the semiconductor structure further includes a dielectric liner disposed between the first conductive via and the second wafer, and between the second conductive via and the second wafer .

In some embodiments, the dielectric liner is disposed between the first conductive via and the passivation layer, and between the second conductive via and the passivation layer.

In some embodiments, the dielectric liner is disposed on the passivation layer.

Another embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes a first wafer; a second wafer disposed on the first wafer; a passivation layer disposed on the second wafer; a first conductive via passing through the second wafer a circle extending partially through the first wafer and having a first width surrounded by the second wafer and the passivation layer; and a second conductive via extending partially through the passivation layer The second wafer extends and has a second width surrounded by the second wafer and a third width surrounded by the passivation layer; wherein the first width is approximately equal to the third width and approximately greater than the second width.

In some embodiments, the first conductive via has a width that is consistent along a first width of the first conductive via, which is equal to the first width.

In some embodiments, a first height of the first conductive via is substantially greater than a second height of the second conductive via.

In some embodiments, a thickness of the first wafer is substantially greater than a thickness of the second wafer.

In some embodiments, the first conductive via contacts a first conductive pad in the first wafer.

In some embodiments, the second conductive via contacts a second conductive pad in the second wafer.

In some embodiments, each of the first conductive via and the second conductive via is completely surrounded by a dielectric liner.

In some embodiments, a first upper surface of the first conductive via and an upper surface of the second conductive via are exposed through the dielectric liner.

Yet another embodiment of the present disclosure provides a method for fabricating a semiconductor structure. The preparation method includes providing a first wafer, the first wafer includes a first substrate, a first dielectric layer and a first conductive pad, the first dielectric layer is disposed on the first substrate, the The first conductive pad is surrounded by the first dielectric layer; a second wafer is provided, the second wafer includes a second base, a second dielectric layer and a second conductive pad, the second dielectric layer is disposed on the second substrate, the second conductive pad is surrounded by the second dielectric layer; the first dielectric layer is bonded to the second dielectric layer; a passivation layer is disposed on the second wafer forming a patterned photoresist layer on the passivation layer, wherein the patterned photoresist layer includes a first through hole and a first recess; removing a first part of the passivation layer exposed through the first through hole to form a first opening, and removing a second portion of the passivation layer below the first recess to form a first depression; removing a third portion of the second substrate exposed through the first opening to form a second recess; removing a fourth portion of the passivation layer below the first recess to form a second opening; removing a fifth portion of the second substrate below the second recess to form a third opening , and remove a sixth portion of the second substrate exposed through the second opening to form a fourth opening; remove a seventh portion of the second dielectric layer exposed through the third opening to form a small portion exposing the second conductive pad, and removing an eighth portion of the second dielectric layer exposed through the fourth opening and a ninth portion of the first dielectric layer exposed through the fourth opening to at least partially exposing the first conductive pad, thereby forming a first trench extending through the second wafer and the passivation layer and partially through the first dielectric layer, and thereby forming a trench extending through the passivation layer and the second substrate and a second trench partially passing through the second dielectric layer; removing the patterned photoresist layer; disposing a dielectric liner on the passivation layer, conforming to the first trench and the passivation layer the second trench; and forming a first conductive via in the first trench and a second conductive via in the second trench.

In some embodiments, the first through hole has a stepped profile and has a stepped portion protruding inward toward the first through hole.

In some embodiments, the first recess has a first width, and the first through hole has a second width and a third width, the third width is above the second width and substantially larger than the second width.

In some embodiments, the first width is substantially greater than the second width and substantially equal to the third width.

In some embodiments, before forming the patterned photoresist layer, the preparation method further includes: disposing a photoresist layer on the passivation layer; disposing a mask on the photoresist layer; providing a predetermined electromagnetic radiation on the passivation layer on the mask; and irradiating the mask with the predetermined electromagnetic radiation.

In some embodiments, the mask has a second hole and a second recess, the second hole is vertically aligned with the first hole and corresponds to the first hole, the second hole is vertically aligned with the first The concave portion corresponds to the first concave portion.

In some embodiments, the second through hole has a central area and a peripheral area surrounding the central area.

In some embodiments, the central region has a first transmittance equal to an amount of the predetermined electromagnetic radiation allowed to pass through the central region, and the peripheral region has a second transmittance , the second transmittance is equal to a quantity of the predetermined electromagnetic radiation allowed to pass through the surrounding area, the second recess has a third transmittance equal to the amount allowed to pass through the second recess A quantity of the predetermined electromagnetic radiation.

In some embodiments, the first transmittance is substantially different than the second transmittance.

In some embodiments, the first transmittance is substantially different from the third transmittance.

In some embodiments, the first transmittance is substantially greater than the second transmittance.

In some embodiments, the first transmittance is substantially greater than the third transmittance.

In some embodiments, the first transmittance is approximately 100%, the second transmittance is approximately 6%, and the third transmittance is approximately less than 6%.

In some embodiments, the predetermined electromagnetic radiation is ultraviolet (UV).

In some embodiments, the manufacturing method further includes grinding the second substrate to reduce a thickness of the second substrate after bonding the first dielectric layer to the second dielectric layer.

In summary, since a mask having different dimensions at different regions is used during a lithography process, a semiconductor structure having at least two via holes of different sizes can be formed. Since at least two via holes with different sizes can be formed by one mask, the manufacturing cost and materials can be reduced or minimized.

The technical features and advantages of the present disclosure have been broadly summarized above, so that the following detailed description of the present disclosure can be better understood. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those skilled in the art of the present disclosure should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the disclosure defined by the appended claims.

Embodiments or examples of the present disclosure shown in the drawings will now be described using specific language. It should be understood that the scope of the present disclosure is not intended to be limited thereby. Any modification or improvement of the described embodiments, and any further application of the principles described in this document, would occur as would normally occur to one of ordinary skill in the art. Element numbers may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment apply to another, even if they share the same element number.

It should be understood that although the terms "first", "second", "third" etc. may be used herein to describe various elements, components, regions, layers and/or sections, These elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, a "first element", "component", "region", "layer" or "section" discussed below may be referred to as a second device , component, region, layer or section without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will be further understood that when the terms "comprises" and/or "comprising" are used in this specification, these terms specify the stated features, integers, steps, operations, elements, and/or components. Presence, but not excluding the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups of the above.

FIG. 1 is a schematic cross-sectional view illustrating a semiconductor structure 100 according to some embodiments of the present disclosure. In some embodiments, the semiconductor structure 100 is a part of a die, a package, or a device. In some embodiments, the semiconductor structure 100 is a die, a package or a device. In some embodiments, the semiconductor structure 100 includes a first wafer 101 , a second wafer 102 , a passivation layer 104 , a first conductive via 105 and a second conductive via 106 .

In some embodiments, the first wafer 101 is a workpiece including various features formed in or on the first wafer 101 . In some embodiments, the first die 101 is in different stages of fabrication and processed using different processes. In some embodiments, the first wafer 101 includes different electronic circuits suitable for a particular application. In some embodiments, FIG. 1 illustrates a portion of a first wafer 101 . In some embodiments, an upper surface of the first wafer 101 has a circular shape or any other suitable shape.

In some embodiments, the first wafer 101 includes a first substrate 101a, a first dielectric layer 101b, and a first conductive pad 101c, and the first conductive pad 101 is formed in the first dielectric layer 101b. In some embodiments, the first substrate 101 a is a part of the first wafer 101 . In some embodiments, the first substrate 101a is a semiconductor layer. In some embodiments, the first substrate 101a includes semiconductor materials such as silicon, germanium, gallium, arsenic or combinations thereof. In some embodiments, the first substrate 101a is a silicon substrate.

In some embodiments, electronic components or parts (such as different N-type metal oxide semiconductor (NMOS) and/or P-type metal oxide semiconductor (PMOS) components, capacitors, resistors, diodes, photodiodes, fuses wires and/or the like) are successively formed in or on the first substrate 101a and configured to be electrically connected to an external circuit.

In some embodiments, the first dielectric layer 101b is disposed on the first substrate 101a. In some embodiments, the first dielectric layer 101b includes a dielectric material such as oxide, nitride, silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, polymer or the like. In some embodiments, the first dielectric layer 101b includes a plurality of dielectric layers stacked on each other. In some embodiments, each dielectric layer includes a material that is the same as or different from the material in the other dielectric layers.

In some embodiments, the first wafer 101 defines a first surface 101d and a second surface 101e, and the second surface 101e is opposite to the first surface 101d. In some embodiments, the first surface 101 d is a front surface of the first wafer 101 , and the second surface 101 e is a rear surface of the first wafer 101 . In some embodiments, different features are formed in or on the first surface 101 d of the first wafer 101 .

In some embodiments, the first conductive pad 101c is disposed within the first dielectric layer 101b. In some embodiments, the first conductive pad 101c is surrounded by the first dielectric layer 101b. In some embodiments, the first conductive pad 101c is disposed adjacent to the first surface 101d of the first wafer 101 and at least partially exposed through the first dielectric layer 101b.

In some embodiments, the first conductive pad 101c extends laterally in the first dielectric layer 101b. In some embodiments, the first conductive pad 101 c is configured to be electrically connected to a die, a package, or a circuit outside the semiconductor structure 100 . In some embodiments, the first conductive pad 101c includes a conductive material such as gold, silver, copper, nickel, tungsten, aluminum, tin, alloys thereof, or the like. In some embodiments, an upper surface of the first conductive pad 101c has a circular or polygonal shape.

In some embodiments, the second wafer 102 is disposed on the first wafer 101 . In some embodiments, the second wafer 102 has a configuration similar to that of the first wafer 101 . In some embodiments, a thickness or a height H1 of the first wafer 101 is substantially greater than a thickness or a height H2 of the second wafer 102 .

In some embodiments, the second wafer 102 includes a second substrate 102a, a second dielectric layer 102b, and a second conductive pad 102c, and the second conductive pad 102c is formed in the second dielectric layer 102b. In some embodiments, the second substrate 102 a is part of the second wafer 102 . In some embodiments, the second substrate 102a has a configuration similar to that of the first substrate 101a. In some embodiments, a thickness of the first base 101a is substantially greater than a thickness of the second base 102a. In some embodiments, the thickness of the second substrate 102a ranges from about 20 µm to about 50 µm. In some embodiments, the thickness of the second substrate 102a is about 30 µm.

In some embodiments, the second substrate 102a is disposed on the second dielectric layer 102b. In some embodiments, the second dielectric layer 102b has a configuration similar to that of the first dielectric layer 101b. In some embodiments, the second dielectric layer 102b is disposed on the first dielectric layer 101b. In some embodiments, the second dielectric layer 102b includes a material that is the same as or different from the material in the first dielectric layer 101b. In some embodiments, a thickness of the second dielectric layer 102b is substantially equal to, greater than, or smaller than a thickness of the first dielectric layer 101b.

In some embodiments, the second wafer 102 includes a third surface 102d and a fourth surface 102e, and the fourth surface 102e is opposite to the third surface 102d. In some embodiments, the third surface 102 d is a front surface of the second wafer 102 , and the fourth surface 102 e is a rear surface of the second wafer 102 . In some embodiments, different features are formed in or on the third surface 102d of the second wafer 102 . In some embodiments, the first surface 101d is close to the third surface 102d and away from the fourth surface 102e.

In some embodiments, the second conductive pad 102c is disposed within the second dielectric layer 102b. In some embodiments, the second conductive pad 102c is surrounded by the second dielectric layer 102b. In some embodiments, the second conductive pad 102c is disposed adjacent to the third surface 102d of the second wafer 102 and at least partially exposed through the second dielectric layer 102b.

In some embodiments, the second conductive pad 102c extends laterally in the second dielectric layer 102b. In some embodiments, the second conductive pad 102c has a configuration similar to that of the first conductive pad 101c. In some embodiments, the second conductive pad 102c includes a material that is the same as or different from the material in the first conductive pad 101c. In some embodiments, the second conductive pad 102c includes a conductive material such as gold, silver, copper, nickel, tungsten, aluminum, tin, alloys thereof, or the like. In some embodiments, an upper surface of the second conductive pad 102c has a circular or polygonal shape.

In some embodiments, the second wafer 102 is bonded to the first wafer 101 by a bonding dielectric 103 . In some embodiments, the bonding dielectric 103 is disposed on the first dielectric layer 101b and the second dielectric layer 102b to bond the first dielectric layer 101b to the second dielectric layer 102b. In some embodiments, the bonding dielectric 103 is disposed between the first surface 101d and the third surface 102d. In some embodiments, the bonding dielectric 103 includes a polymer, benzocyclobutene (BCB), polyoxadiazole (PBO), polyimide (PI), or the like. In some embodiments, the bonding dielectric 103 includes oxide, nitride, or the like. In some embodiments, there is no interface within the junction dielectric 103 .

In some embodiments, the bonding dielectric 103 includes a plurality of bonding dielectric layers. In some embodiments, the bonding dielectric 103 includes a first bonding dielectric layer 103a and a second bonding dielectric layer 103b. In some embodiments, the second bonding dielectric layer 103b includes a material that is the same as or different from the material in the first bonding dielectric layer 103a.

In some embodiments, a thickness of the first bonding dielectric layer 103 is approximately less than 10 μm. In some embodiments, the thickness of the first bonding dielectric layer 103 a is approximately less than 5 μm. In some embodiments, a thickness of the second bonding dielectric layer 103b is approximately less than 10 μm. In some embodiments, the thickness of the second bonding dielectric layer 103b is approximately less than 5 μm. In some embodiments, there is an interface within the bonding dielectric 103 and between the first bonding dielectric layer 103a and the second bonding dielectric layer 103b.

In some embodiments, a passivation layer 104 is disposed on the second wafer 102 . In some embodiments, the passivation layer 104 is disposed on the second substrate 102a. In some embodiments, the passivation layer 104 is disposed on the fourth surface 102 e of the second wafer 102 . In some embodiments, the passivation layer 104 includes a dielectric material such as spin-on-glass (SOG), silicon oxide, silicon oxynitride, silicon nitride, or the like. In some embodiments, passivation layer 104 includes polymer, BCB, PBO, PI, or the like.

In some embodiments, the first conductive via 105 extends from the first conductive pad 101c and is electrically connected to the first conductive pad 101c. In some embodiments, the first conductive via 105 is at least partially surrounded by the bonding dielectric 103 , the passivation layer 104 and the second wafer 102 . In some embodiments, the first conductive via 105 extends through the bonding dielectric 103 , the passivation layer 104 , the second dielectric layer 102 b and the second substrate 102 a. In some embodiments, the first conductive via 105 extends at least partially through the first wafer 101 . In some embodiments, the first conductive via 105 should at least partially extend through the first dielectric layer 101b.

In some embodiments, the first conductive via 105 is coupled to the first conductive pad 101c. In some embodiments, the first conductive via 105 contacts the first conductive pad 101 c within the first wafer 101 . In some embodiments, the first conductive via 105 is substantially orthogonal to the first conductive pad 101c. In some embodiments, the first conductive via 105 is a through substrate via (TSV). In some embodiments, the first conductive via 105 includes a conductive material such as gold, silver, copper, nickel, tungsten, aluminum, tin, alloys thereof, or the like. In some embodiments, an upper surface of the first conductive via 105 has a circular or polygonal shape. In some embodiments, the first conductive via 105 has a cylindrical shape. In some embodiments, the first conductive via 105 has a first width W1 at a first section surrounded by the second wafer 102 and the passivation layer 104 . In some embodiments, the first conductive via 105 has a uniform width along a first height H3 of the first conductive via 105 , which is equal to the first width W1 .

In some embodiments, the second conductive via 106 extends from the second conductive pad 102c and is electrically connected to the second conductive pad 102c. In some embodiments, the second conductive via 106 is at least partially surrounded by the second wafer 102 and the passivation layer 104 . In some embodiments, the second conductive via 106 extends through the passivation layer 104 and the second substrate 102a and partially through the second dielectric layer 102b.

In some embodiments, the second conductive via 106 is coupled to the second conductive pad 102c. In some embodiments, the second conductive via 106 contacts the second conductive pad 102 c within the second wafer 102 . In some embodiments, an interface between the first conductive via 105 and the first conductive pad 101c is substantially larger than an interface between the second conductive via 106 and the second conductive pad 102c. In some embodiments, the second conductive via 106 is substantially orthogonal to the second conductive pad 102c. In some embodiments, the second conductive via 106 is a through substrate via (TSV). In some embodiments, the second conductive via 106 includes a conductive material such as gold, silver, copper, nickel, tungsten, aluminum, tin, alloys thereof, or the like. In some embodiments, an upper surface of the second conductive via 106 has a circular or polygonal shape. In some embodiments, the second conductive via 106 has a cylindrical shape.

In some embodiments, the second conductive via 106 has a first portion 106a, a second portion 106c and a tapered portion 106b, the first portion has a second width W3, the second portion 106c has a third width W4, The tapered portion 106b tapers from the second portion 106c to the first portion 106a. In some embodiments, the tapered portion 106b is disposed between and coupled to the first portion 106a and the second portion 106c. In some embodiments, the first portion 106a is surrounded by the second substrate 102a and the second dielectric layer 102b. In some embodiments, the tapered portion 106b and the second portion 106c are surrounded by the passivation layer 104 . In some embodiments, a width of the tapered portion 106b decreases from the third width W4 to the second width W3.

In some embodiments, the second conductive vias 106 have different widths along a second height H4 of the second conductive vias 106 . In some embodiments, the first height H3 of the first conductive via 105 is substantially greater than the second height H4 of the second conductive via 106 . In some embodiments, the second portion 106c having the third width W4 is above the first portion 106a having the second width W3. The first portion 106 a is surrounded by the second wafer 102 , and the second portion 106 c is surrounded by the passivation layer 104 . In some embodiments, the second width W3 of the second conductive via 106 is substantially smaller than the first width W1 of the first conductive via 105 . In some embodiments, the third width W4 is substantially equal to the first width W1 and substantially greater than the second width W3.

In some embodiments, the semiconductor structure 100 further includes a dielectric liner 109 disposed between the first conductive via 105 and the second wafer 102 , and between the second conductive via 106 and the second wafer 102 . In some embodiments, a dielectric liner 109 is disposed between the first conductive via 105 and the passivation layer 104 , and between the second conductive via 106 and the passivation layer 104 . In some embodiments, a dielectric liner 109 is disposed on the passivation layer 104 . In some embodiments, each of the first conductive via 105 and the second conductive via 106 is completely surrounded by the dielectric liner 109 . In some embodiments, the dielectric liner 109 contacts the first conductive pad 101c and the second conductive pad 102c.

In some embodiments, a first upper surface 105 a of the first conductive via 105 and a second upper surface 106 d of the second conductive via 106 are exposed through the dielectric liner 109 . In some embodiments, an upper surface 109 a of the dielectric liner 109 is substantially coplanar with the upper surface 105 a of the first conductive via 105 and the upper surface 106 d of the second conductive via 106 . In some embodiments, the dielectric liner 109 includes a dielectric material, such as an oxide or the like.

In some embodiments, the semiconductor structure 100 further includes a first trench 111 and a second trench 112 . In some embodiments, the first trench 111 extends through the second wafer 102 and the passivation layer 104 and partially through the first dielectric layer 101b. In some embodiments, the second trench 112 extends through the passivation layer 104 and the second substrate 102a and partially through the second dielectric layer 102b. In some embodiments, the first trench 111 has a fourth width W2. In some embodiments, the trench 111 has a uniform width along the first height H3 of the first conductive via 105 , which is equal to the fourth width W2 . In some embodiments, the second trench 112 has a fourth section and a fifth section, the fourth section has a fifth width W5, the fifth section has a sixth width W6, wherein the The fifth section is above the fourth section. In some embodiments, the fifth width W5 is substantially smaller than the sixth width W6. In some embodiments, the fourth width W2 is substantially equal to the sixth width W6.

2A to 2C are schematic flowcharts illustrating a method S200 for fabricating the semiconductor structure 100 according to some embodiments of the present disclosure. 3 to 24 are schematic cross-sectional views illustrating various intermediate stages in forming the semiconductor structure 100 according to some embodiments of the present disclosure.

The stages shown in Figures 3 to 24 are also schematically shown in the flowcharts of Figures 2A to 2C. In the following discussion, the various stages of fabrication shown in Figures 3-24 are discussed with reference to the various processing steps shown in Figures 2A-2C. The preparation method S200 includes multiple steps, and the descriptions and illustrations are not considered to limit the order of the steps. The preparation method S200 includes multiple steps (S201, S202, S203, S204, S205, S206, S207, S208, S209, S210, S211, S212, S213).

Please refer to FIG. 3 , according to step S201 of FIG. 2A , a first wafer 101 is provided. In some embodiments, the first wafer 101 has a first surface 101d and a second surface 101e, and the second surface 101e is disposed opposite to the first surface 101d. In some embodiments, the first wafer 101 includes a first substrate 101a, a first dielectric layer 101b, and a first conductive pad 101c, the first dielectric layer 101b is disposed on the first substrate 101a, and the first conductive The pad 101c is surrounded by the first dielectric layer 101b. In some embodiments, the first dielectric layer 101b is formed on the first substrate 101a by deposition, chemical vapor deposition (CVD) or other suitable operations.

In some embodiments, the fabrication technique of the first conductive pad 101c includes removing a portion of the first dielectric layer 101b to form a recess and disposing a conductive material to fill the recess to form the first conductive pad 101c. In some embodiments, fabrication techniques for providing conductive material include electroplating, sputtering, or other suitable operations. In some embodiments, the first wafer 101 , the first substrate 101 a , the first dielectric layer 101 b and the first conductive pad 101 c have configurations similar to those described above or as illustrated in FIG. 1 .

Please refer to FIG. 4 , according to step S202 of FIG. 2A , a second wafer 102 is provided. In some embodiments, the second wafer 102 includes a third surface 102d and an untreated fourth surface 102e', and the untreated fourth surface 102e' is disposed opposite to the third surface 102d. In some embodiments, the second wafer 102 includes a second substrate 102a, a second dielectric layer 102b, and a second conductive pad 102c, the second dielectric layer 102b is disposed on the second substrate 102a, and the second conductive pad 102c The pad 102c is surrounded by the second dielectric layer 102b. In some embodiments, the second dielectric layer 102b is formed on the second substrate 102a by deposition, CVD or other suitable operations.

In some embodiments, the fabrication technique of the second conductive pad 102c includes removing a portion of the second dielectric layer 102b to form a recess and disposing a conductive material to fill the recess to form the second conductive pad 102c. In some embodiments, fabrication techniques for providing conductive material include electroplating, sputtering, or other suitable operations. In some embodiments, the second wafer 102 , the second substrate 102 a , the second dielectric layer 102 b , and the second conductive pad 102 c have configurations similar to those described above or illustrated in FIG. 1 .

In some embodiments, as shown in FIG. 8 , a bonding dielectric 103 is formed between the first wafer 101 and the second wafer 102 . In some embodiments, the bonding dielectric 103 is formed on the first wafer 101 or the second wafer 102 . In some embodiments, the bonding dielectric 103 is formed on the first surface 101s or the third surface 102d. In some embodiments, the bonding dielectric 103 has a configuration similar to that described above or as shown in FIG. 1 .

In some embodiments, forming the bonding dielectric 103 includes disposing a first bonding dielectric layer 103a on the first wafer 101 as shown in FIG. 5, and disposing a second bonding dielectric layer 103a as shown in FIG. 103b is disposed on the second wafer 102 . In some embodiments, as shown in FIG. 5 , the first bonding dielectric layer 103 a is disposed on the first surface 101 d , and as shown in FIG. 6 , the second bonding dielectric layer 103 b is disposed on the third surface 102 d. In some embodiments, the disposing of the first bonding dielectric layer 103 a as shown in FIG. 5 and the disposing of the second bonding dielectric layer 103 b as shown in FIG. 6 are performed separately or simultaneously.

In some embodiments, after disposing the first bonding dielectric layer 103a on the first wafer 101 and disposing the second bonding dielectric layer 103b on the second wafer 102, as shown in FIG. Two wafers 102, such that the first dielectric layer 101b and the second dielectric layer 102b are adjacent to and opposite to each other. In some embodiments, the first surface 101d faces the third surface 102d.

Please refer to FIG. 8 , according to step S203 of FIG. 2A , the first dielectric layer 101b is bonded to the second dielectric layer 102b. In some embodiments, the second wafer 102 is bonded on the first wafer 101 . In some embodiments, the second wafer 102 is flipped before bonding the first dielectric layer 101b to the second dielectric layer 120b. In some embodiments, the first dielectric layer 101b is bonded to the second dielectric layer 102b by a bonding dielectric 103 . In some embodiments, the first wafer 101 and the second wafer 102 are bonded by an oxide-on-oxide bonding technique or other suitable operations.

In some embodiments, after bonding the first wafer 101 to the second wafer 102, as shown in FIG. 9, the second substrate 102a is grounded. In some embodiments, a thickness of the second substrate 102a is reduced by polishing, etching, chemical mechanical polishing (CMP), or other suitable operations. In some embodiments, the second substrate 102a is planarized, and after the thickness of the second substrate 102a is reduced, the untreated fourth surface 102e' becomes the fourth surface 102e. In some embodiments, the thickness of the second substrate 102a is substantially smaller than a thickness of the first substrate 101a.

Please refer to FIG. 10 , according to step S204 of FIG. 2A , a passivation layer 104 is disposed on the second wafer 102 . In some embodiments, the texturization layer 104 is disposed on the second wafer 102 after the thickness of the second substrate 102a is reduced. In some embodiments, a passivation layer 104 is formed on the second substrate 102a. In some embodiments, the fabrication techniques of the passivation layer 104 include deposition, CVD, or other suitable operations. In some embodiments, the passivation layer 104 has a configuration similar to that described above or as shown in FIG. 1 .

Please refer to FIG. 13 , according to step S205 of FIG. 2A , a patterned photoresist layer 107 is formed on the passivation layer 104 . In some embodiments, before forming the patterned photoresist layer 107, as shown in FIG. 11, a photoresist layer 107' is disposed on the passivation layer 104, and as shown in FIG. layer 107'. In some embodiments, the photoresist layer 107' is applied by spin coating or other suitable operations. In some embodiments, a mask 108 is used to apply an exposure process and a development process to the photoresist layer 107'.

In some embodiments, after the mask 108 is disposed on the photoresist layer 107', a predetermined electromagnetic radiation R is provided on the mask 108, and then the mask 108 is irradiated with the predetermined electromagnetic radiation R as shown in FIG. 12 . In some embodiments, the predetermined electromagnetic radiation R is ultraviolet (UV), light, or the like.

In some embodiments, the mask 108 includes a second through hole 108a and a second recess 108b. In some embodiments, the second through hole 108a has a central area 108c and a peripheral area 108d, and the peripheral area 108d surrounds the central area 108c. In some embodiments, the central region 108c has a first transmittance equal to an amount that allows the predetermined electromagnetic radiation R to pass through the central region 108c, and the peripheral region 108d has a second transmittance equal to the amount that allows the predetermined electromagnetic radiation R to pass through the central region 108c. R passes through an amount of the surrounding area 108d, and the second concave portion 108b has a third transmittance, which is equal to an amount allowing the predetermined electromagnetic radiation R to pass through the second concave portion 108b.

In some embodiments, the first transmittance is substantially different than the second transmittance. In some embodiments, the first transmittance is substantially different than the third transmittance. In some embodiments, the first transmittance is substantially greater than the second transmittance. In some embodiments, the first transmittance is substantially greater than the third transmittance.

In some embodiments, the first transmittance is about 100%. That is, the predetermined electromagnetic radiation R can completely pass through the mask 108 through the central region 108c of the second through hole 108a. In some embodiments, the second transmittance is about 6%. In some embodiments, the second transmittance is about 5% to 10%. That is, the predetermined electromagnetic radiation R can only partially pass through the mask 108 via the surrounding area 108d of the second through hole 108a.

In some embodiments, the third transmittance is approximately less than 6%. In some embodiments, the third transmittance is substantially less than 10%. That is, the predetermined electromagnetic radiation R can only partially pass through the shield 108 through the second concave portion 108b. In some embodiments, the third transmittance is 0%. That is, the predetermined electromagnetic radiation R cannot pass through the shield 108 via the second concave portion 108b.

In some embodiments, different portions of the photoresist layer 107' are exposed to different amounts of predetermined electromagnetic radiation R. In some embodiments, a portion of the photoresist layer 107' vertically aligned with the central region 108c receives predetermined electromagnetic radiation R that passes completely through the central region 108c. In some embodiments, the portion of the photoresist layer 107' is exposed to 100% or near 100% of the predetermined electromagnetic radiation R.

In some embodiments, the photoresist layer 107' is vertically aligned with other portions of the surrounding area 108d to receive a portion of the predetermined electromagnetic radiation R passing through the surrounding area 108d. In some embodiments, this other portion of the photoresist layer 107' is exposed to about 5% to 10% of the predetermined electromagnetic radiation R. In some embodiments, this other portion of the photoresist layer 107' is exposed to about 6% of the predetermined electromagnetic radiation R.

In some embodiments, the photoresist layer 107' is vertically aligned with other parts of the second recess 108b to receive a portion of the predetermined electromagnetic radiation R passing through the second recess 108b. In some embodiments, this other portion of the photoresist layer 107' is exposed to substantially less than 6% of the predetermined electromagnetic radiation R.

In some embodiments, a remaining portion of the photoresist layer 107' does not receive any predetermined electromagnetic radiation R. In some embodiments, the remaining portion of the photoresist layer 107' is exposed to 0% or substantially no predetermined electromagnetic radiation R.

In some embodiments, after the mask 108 is irradiated with the predetermined electromagnetic radiation R, the portions of the photoresist layer 107' exposed to the predetermined electromagnetic radiation R are removed to form the patterned photoresist layer 107. In some embodiments, as shown in FIG. 13 , a patterned photoresist layer 107 having a first through hole 107 a and a first recess 107 b is formed.

In some embodiments, the portion of the photoresist layer 107' exposed to 100% or close to 100% of the predetermined electromagnetic radiation R is completely removed, and the portion exposed to about 5% to 10% of the predetermined electromagnetic radiation R is partially removed. part, so as to form the first through hole 107a with a stepped profile. In some embodiments, the first through hole 107a has the stepped profile and has a stepped portion 107c protruding inward toward the first through hole 107a.

In some embodiments, the portion of the photoresist layer 107' exposed to substantially less than 6% of the predetermined electromagnetic radiation R is partially removed to form the first recess 107b. In some embodiments, the second through hole 108a is vertically aligned with the first through hole 107a and corresponds to the first through hole 107a, and the second recess 108b is vertically aligned with and corresponds to the first recess 107b.

In some embodiments, after the mask 108 is irradiated with predetermined electromagnetic radiation R or after the patterned photoresist layer 107 is formed, the mask 108 is removed as shown in FIG. 14 . In some embodiments, the first recess 107b has a seventh width W7, and the first through hole 107a has an eighth width W8 and a ninth width W9, wherein the part with the ninth width W9 is after the eighth width W8 and the ninth width W9 is substantially larger than the eighth width W8. In some embodiments, the seventh width W7 is substantially greater than the eighth width W8 and substantially equal to the ninth width W9.

Please refer to FIG. 15, according to step S206 of FIG. 2B, remove a first portion of the passivation layer 104 exposed through the first through hole 107a (as shown in FIG. 14 ) to form a first opening 104a, remove the passivation layer 104 in the second A second portion below a recess 107b (as shown in FIG. 14 ) forms a first recess 104b. In some embodiments, the first portion and the second portion of passivation layer 104 are removed by dry etching or any other suitable process. In some embodiments, the first opening 104 a extends through the passivation layer 104 , and the first recess 104 b partially extends through the passivation layer 104 . In some embodiments, a part of the first through hole 107a (as shown in FIG. 14 ) and a part of the first recess 107b (as shown in FIG. 14 ) are also removed during the formation of the first opening 104a and the first recess 104b respectively. .

In some embodiments, the first opening 104a tapers toward the second base 102a. In some embodiments, the first opening 104a has a fifth width W5 and a sixth width W6, and the sixth width W6 is at a position above a position of the fifth width W5. In some embodiments, the fifth width W5 is substantially smaller than the sixth width W6. In some embodiments, the first recess 104b has a fourth width W2, which is substantially greater than the fifth width W5 and substantially equal to the sixth width W6. In some embodiments, the fourth width W2 , the fifth width W5 , and the sixth width W6 are approximately equal to the seventh width W7 , the eighth width W8 , and the ninth width W9 (as shown in FIG. 14 ), respectively.

Referring to FIG. 16 , according to step S207 of FIG. 2B , a third portion of the second substrate 102a exposed through the first opening 104a is removed to form a second recess 102f. In some embodiments, the third portion of the second substrate 102a is removed by the etching or other suitable process. In some embodiments, the formation of the second recess 102f and the formation of the first opening 104a are performed in different process chambers. In some embodiments, a depth of the second recess 102f ranges from about 1 μm to about 5 μm. In some embodiments, the depth of the second recess 102f is about 2 µm.

Referring to FIG. 17 , according to step S208 of FIG. 2B , a fourth portion of the passivation layer 104 below the first recess 104 b (shown in FIG. 16 ) is removed to form a second opening 104 c. In some embodiments, the fourth portion of passivation layer 104 is removed by dry etching or any other suitable process. In some embodiments, the formation of the second opening 104c and the formation of the second recess 102f are performed in different process chambers. In some embodiments, the second opening 104c extends through the passivation layer 104 .

Please refer to FIG. 18, according to step S209 of FIG. 2B, a fifth part of the second substrate 102a in the second recess 102f (as shown in FIG. 17) is removed to form a third opening 102g, and the second substrate 102a is removed through A sixth portion exposed by the second opening 104c forms a fourth opening 102h. In some embodiments, the fifth and sixth portions of the second substrate 102a are removed by dry etching or any other suitable process. In some embodiments, the formation of the third opening 102g and the fourth opening 102f and the formation of the second opening 104c are implemented in different process chambers. In some embodiments, the third opening 102g and the fourth opening 102h extend through the second base 102a.

Please refer to FIG. 19, according to step S210 of FIG. 2C, remove a seventh portion of the second dielectric layer 102b exposed through the third opening 102g to at least partially expose the second conductive pad 102c, and remove the second dielectric layer 102b An eighth portion exposed through the fourth opening 102g and a ninth portion of the first dielectric layer 101b exposed through the fourth opening 102g are removed to at least partially expose the first conductive pad 101c.

In some embodiments, the seventh portion of the second dielectric layer 102b, the eighth portion of the second dielectric layer 102b, and the ninth portion of the first dielectric layer 101b are removed by this etching or any other suitable process. part. In some embodiments, the seventh portion of the second dielectric layer 102b, the eighth portion of the second dielectric layer 102b, and the ninth portion of the first dielectric layer 101b are removed separately or simultaneously. In some embodiments, a portion of the bonding dielectric 103 exposed through the fourth opening 102h is also removed. As a result, a first trench 111 extending through the second wafer 102, the passivation layer 104 and partly through the first dielectric layer 101b is formed, and a first trench 111 extending through the passivation layer 104 and the second substrate 102a and partly through the second dielectric layer 101b is formed. A second trench 112 of layer 102b.

Referring to FIG. 20 , according to step S211 of FIG. 2C , the patterned photoresist layer 107 is removed. In some embodiments, the patterned photoresist layer 107 is removed by stripping, etching or other suitable processes.

Referring to FIG. 22 , according to step S212 of FIG. 2C , a dielectric liner 109 is disposed on the passivation layer 104 and conforms to the first trench 111 and the second trench 112 . In some embodiments, the disposing of the dielectric liner 109 includes disposing a dielectric material 109' as shown in FIG. 21 and removing a portion of the dielectric material 109' to form the dielectric liner as shown in FIG. 22 109. In some embodiments, the dielectric material 109 ′ is disposed on the passivation layer 104 , on the first conductive pad 101 c exposed through the first trench 111 and on the second conductive pad 102 c exposed through the second trench 112 superior. In some embodiments, the dielectric material 109' is conformally disposed on the first trench 111 and the second trench 112. In some embodiments, the dielectric material 109' is provided by deposition, atomic layer deposition (ALD), CVD, or other suitable processes. In some embodiments, the dielectric material 109' includes a dielectric material such as an oxide or the like.

In some embodiments, portions of the dielectric material 109' on the first conductive pad 101c and the second conductive pad 102c are removed by etching or any other suitable process. In some embodiments, the first conductive pad 101 c and the second conductive pad 102 c are at least partially exposed through the dielectric liner 109 . In some embodiments, the dielectric liner 109 has a configuration similar to that described above or as illustrated in FIG. 1 .

Please refer to FIG. 24 , according to step S213 of FIG. 2C , a first conductive via 105 in the first trench 111 and a second conductive via 106 in the second trench 112 are formed. In some embodiments, the formation of the first conductive via 105 and the second conductive via 106 includes disposing a conductive material 110 in the first trench 111 and the second trench 112 as shown in FIG. The conductive material 110 is oxidized to form the first conductive via 105 and the second conductive via 106 as shown in FIG. 24 .

In some embodiments, before disposing the conductive material 110 , a diffusion barrier layer is disposed on the dielectric liner 109 and conforms to the first trench 111 and the second trench 112 . In some embodiments, the diffusion barrier layer is provided by ALD, CVD or similar methods. In some embodiments, the diffusion barrier layer includes titanium, titanium nitride, tantalum, tantalum nitride, nickel, or the like.

In some embodiments, after the diffusion barrier layer is disposed, a seed layer is disposed on the diffusion barrier layer. In some embodiments, the seed layer is provided by sputtering or other suitable operations. In some embodiments, the seed layer includes titanium, copper, nickel, gold, or the like.

In some embodiments, the conductive material 110 is disposed on the dielectric liner 109 and conforms to the first trench 111 and the second trench 112 . In some embodiments, the conductive material 110 contacts the dielectric liner 109, the second conductive pad 102c, the bonding dielectric 103, and the first conductive pad 101c. In some embodiments, conductive material 110 is provided by electroplating or other suitable operations. In some embodiments, conductive material 110 includes gold, silver, copper, nickel, tungsten, aluminum, tin, alloys thereof, or the like.

In some embodiments, after the conductive material 110 is disposed, a portion of the conductive material 110 is removed to form the first conductive via 105 and the second conductive via 106 as shown in FIG. 24 . In some embodiments, the portion of conductive material 110 is removed by polishing, etching, CMP, or other suitable operation. In some embodiments, after removing the portion of the conductive material 110, an upper surface 105a of the first conductive via 105, an upper surface 106d of the second conductive via 106, and an upper surface of the dielectric liner 109 109a are substantially coplanar.

In some embodiments, the first conductive via 105 has a shape similar to the first conductive via 105 described above or illustrated in FIG. 1 . In some embodiments, the second conductive via 106 has a shape similar to the second conductive via 106 described above or shown in FIG. 1 . In some embodiments, the semiconductor structure 100 shown in FIG. 1 is formed as shown in FIG. 24 .

In summary, since a mask having different transmittances in different regions is used during a lithography process, a semiconductor structure having at least two via holes of different sizes can be formed. Since at least two via holes of different sizes can be formed using one mask, manufacturing costs and materials can be reduced or minimized.

An embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes a first wafer with a first substrate, a first dielectric layer and a first conductive pad, the first dielectric layer is disposed on the first substrate, and the first conductive pad is covered by the first substrate. Surrounded by the first dielectric layer; a second wafer has a second dielectric layer, a second base and a second conductive pad, the second base is disposed on the second dielectric layer, the second The conductive pad is surrounded by the second dielectric layer; a passivation layer is disposed on the second substrate; a first conductive via extends from the first conductive pad through the second wafer and the passivation layer, and having a first width surrounded by the second wafer; and a second conductive via extending from the second conductive pad through the passivation layer and the second substrate and partially through the second dielectric layer, and has a second width surrounded by the second wafer; wherein the second width is substantially smaller than the first width.

Another embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes a first wafer; a second wafer disposed on the first wafer; a passivation layer disposed on the second wafer; a first conductive via passing through the second wafer a circle extending partially through the first wafer and having a first width surrounded by the second wafer and the passivation layer; and a second conductive via extending partially through the passivation layer The second wafer extends and has a second width surrounded by the second wafer and a third width surrounded by the passivation layer; wherein the first width is approximately equal to the third width and approximately greater than the second width.

Yet another embodiment of the present disclosure provides a method for fabricating a semiconductor structure. The preparation method includes providing a first wafer, the first wafer includes a first substrate, a first dielectric layer and a first conductive pad, the first dielectric layer is disposed on the first substrate, the The first conductive pad is surrounded by the first dielectric layer; a second wafer is provided, the second wafer includes a second base, a second dielectric layer and a second conductive pad, the second dielectric layer is disposed on the second substrate, the second conductive pad is surrounded by the second dielectric layer; the first dielectric layer is bonded to the second dielectric layer; a passivation layer is disposed on the second wafer forming a patterned photoresist layer on the passivation layer, wherein the patterned photoresist layer includes a first through hole and a first recess; removing a first part of the passivation layer exposed through the first through hole to form a first opening, and removing a second portion of the passivation layer below the first recess to form a first depression; removing a third portion of the second substrate exposed through the first opening to form a second recess; removing a fourth portion of the passivation layer below the first recess to form a second opening; removing a fifth portion of the second substrate below the second recess to form a third opening , and remove a sixth portion of the second substrate exposed through the second opening to form a fourth opening; remove a seventh portion of the second dielectric layer exposed through the third opening to form a small portion exposing the second conductive pad, and removing an eighth portion of the second dielectric layer exposed through the fourth opening and a ninth portion of the first dielectric layer exposed through the fourth opening to at least partially exposing the first conductive pad, thereby forming a first trench extending through the second wafer and the passivation layer and partially through the first dielectric layer, and thereby forming a trench extending through the passivation layer and the second substrate and a second trench partially passing through the second dielectric layer; removing the patterned photoresist layer; disposing a dielectric liner on the passivation layer, conforming to the first trench and the passivation layer the second trench; and forming a first conductive via in the first trench and a second conductive via in the second trench.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above can be performed in different ways and replaced by other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, A composition of matter, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patent scope of this application.

100: Semiconductor Structures

101:First Wafer

101a: First base

101b: first dielectric layer

101c: the first conductive pad

101d: first surface

101e: second surface

102:Second wafer

102a: Second base

102b: second dielectric layer

102c: second conductive pad

102d: third surface

102e: fourth surface

102e': untreated fourth surface

102f: second depression

102g: the third opening

102h: Fourth opening

103: Bonding Dielectric

103a: first bonding dielectric layer

103b: second bonding dielectric layer

104: Passivation layer

104a: first opening

104b: first depression

104c: second opening

105: the first conductive via

105a: first upper surface

106: Second conductive via

106a: Part I

106b: tapered part

106c: Part II

106d: second upper surface

107: Patterned photoresist layer

107a: First piercing

107b: first recess

107c: Ladder department

108: mask

108a: Second perforation

108b: second recess

108c: Central area

108d: surrounding area

109: Dielectric liner

109': Dielectric material

109a: upper surface

110: Conductive material

111: The first groove

112: Second groove

H1: height

H2: height

H3: first height

H4: second height

R: scheduled electromagnetic radiation

S200: Preparation method

S201: step

S202: step

S203: step

S204: step

S205: step

S206: step

S207: step

S208: step

S209: step

S210: step

S211: step

S212: step

S213: step

W1: first width

W2: Fourth width

W3: second width

W4: third width

W5: fifth width

W6: sixth width

W7: seventh width

W8: eighth width

W9: ninth width

A more complete understanding of the present disclosure can be obtained by reference to the detailed description and claims. The disclosure should also be understood in relation to the numbering of elements in the drawings, which are intended to represent like elements throughout the description. FIG. 1 is a schematic cross-sectional view illustrating a semiconductor structure of some embodiments of the present disclosure. FIG. 2A to FIG. 2C are schematic flowcharts illustrating the fabrication methods of semiconductor structures according to some embodiments of the present disclosure. 3 to 24 are schematic cross-sectional views illustrating various intermediate stages in forming a semiconductor structure according to some embodiments of the present disclosure.

100: Semiconductor Structures

101:First Wafer

101a: First base

101b: first dielectric layer

101c: the first conductive pad

101d: first surface

101e: second surface

102:Second wafer

102a: Second base

102b: second dielectric layer

102c: second conductive pad

102d: third surface

102e: fourth surface

103: Bonding Dielectric

103a: first bonding dielectric layer

103b: second bonding dielectric layer

104: Passivation layer

105: the first conductive via

105a: first upper surface

106: Second conductive via

106a: Part I

106b: tapered part

106c: Part II

106d: second upper surface

109: Dielectric liner

109a: upper surface

111: The first groove

112: Second groove

H1: height

H2: height

H3: first height

H4: second height

W1: first width

W2: Fourth width

W3: second width

W4: third width

W5: fifth width

W6: sixth width

Claims (19)

A method for preparing a semiconductor structure, comprising: providing a first wafer, the first wafer has a first substrate, a first dielectric layer and a first conductive pad, the first dielectric layer is disposed on the first On a base, the first conductive pad is surrounded by the first dielectric layer; providing a second wafer, the second wafer has a second base, a second dielectric layer and a second conductive pad, The second dielectric layer is disposed on the second substrate, the second conductive pad is surrounded by the second dielectric layer; the first dielectric layer is bonded to the second dielectric layer; a passivation layer is arranged on the On the second wafer; form a patterned photoresist layer on the passivation layer, wherein the patterned photoresist layer has a first through hole and a first recess; remove the passivation layer to expose through the first through hole A first portion of the passivation layer is removed to form a first opening, and a second portion of the passivation layer below the first recess is removed to form a first depression; a portion of the second substrate exposed through the first opening is removed third part to form a second recess; remove a fourth part of the passivation layer below the first recess to form a second opening; remove a fifth part of the second substrate below the second recess to form a third opening, and remove a sixth portion of the second substrate exposed through the second opening to form a fourth opening; removing a seventh portion of the second dielectric layer exposed through the third opening to at least partially expose the second conductive pad, and removing an eighth portion of the second dielectric layer exposed through the fourth opening partially and removing a ninth portion of the first dielectric layer exposed through the fourth opening to at least partially expose the first conductive pad, thereby forming a a first trench extending through a dielectric layer, thereby forming a second trench extending through the passivation layer and the second substrate and partially through the second dielectric layer; removing the patterned photoresist layer ; disposing a dielectric liner on the passivation layer and conformal to the first trench and the second trench; and forming a first conductive via in the first trench and in the second trench A second conductive via hole in the groove. The manufacturing method according to claim 1, wherein the first through hole has a stepped profile, and has a stepped portion protruding inward toward the first through hole. The preparation method according to claim 1, wherein the first recess has a first width, and the first through hole has a second width and a third width, and the third width is above the second width and substantially greater than the second width. The preparation method according to claim 3, wherein the first width is approximately larger than the second width and approximately equal to the third width. The preparation method as described in Claim 1, before forming the patterned photoresist layer, further includes: disposing a photoresist layer on the passivation layer; disposing a mask on the photoresist layer; providing a predetermined electromagnetic radiation On the mask; illuminating the mask with the electromagnetic radiation. The preparation method as described in claim 5, wherein the mask has a second perforation and a second recess, the second perforation is vertically aligned with the first perforation and corresponds to the first perforation, and the second concavity is vertically aligning with the first recess and corresponding to the first recess. The manufacturing method according to claim 6, wherein the second through hole has a central area and a peripheral area, and the peripheral area surrounds the central area. The preparation method as described in claim 7, wherein the central region has a first transmittance equal to a quantity of the predetermined electromagnetic radiation allowed to pass through the central region, and the peripheral region has a The second transmittance is equal to a quantity of the predetermined electromagnetic radiation that is allowed to pass through the surrounding area, and the second recess has a third transmittance that is equal to the amount of the predetermined electromagnetic radiation that is allowed to pass through A quantity of the predetermined electromagnetic radiation of the second recess. The preparation method according to claim 8, wherein the first transmittance is substantially different from the second transmittance. The preparation method as claimed in item 8, wherein the first transmittance is substantially different from the third transmittance transmittance. The preparation method according to claim 8, wherein the first transmittance is substantially different from the second transmittance. The preparation method according to claim 8, wherein the first transmittance is substantially greater than the third transmittance. The preparation method as claimed in item 8, wherein the first transmittance is approximately 100%, the second transmittance is approximately 6%, and the third transmittance is approximately less than 6%. The preparation method as described in claim 5, wherein the predetermined electromagnetic radiation is ultraviolet rays. The manufacturing method according to claim 1, further comprising grinding the second substrate to reduce a thickness of the second substrate after bonding the first dielectric layer to the second dielectric layer. A method for preparing a semiconductor structure, comprising: providing a first wafer; setting a second wafer on the first wafer; forming a passivation layer on the second wafer; forming a first conductive via, extending through the second wafer and the passivation layer and partially through the first wafer and having a first width surrounded by the second wafer and the passivation layer; and forming a second conductive via extending through the passivation layer and partially through the second wafer and having a second width surrounded by the second wafer and a third width surrounded by the passivation layer; Wherein the first width is approximately equal to the third width and different from the second width. The preparation method according to claim 16, further comprising: forming a patterned photoresist layer on the passivation layer, including: disposing a photoresist layer on the passivation layer; disposing a mask on the photoresist layer; providing a predetermined electromagnetic radiation on the mask; and irradiating the mask with the electromagnetic radiation; wherein the patterned photoresist layer has a first through hole and a first recess; wherein the mask has a second through hole and a The second recess, the second through hole is vertically aligned with the first through hole and corresponds to the first through hole, the second recess is vertically aligned with the first recess and corresponds to the first recess. The manufacturing method according to claim 17, wherein the second through hole has a central area and a peripheral area, and the peripheral area surrounds the central area. The preparation method as described in claim 18, wherein the central region has a first transmittance equal to a quantity of the predetermined electromagnetic radiation allowed to pass through the central region, and the peripheral region has a The second transmittance, the second transmittance is equal to a quantity of the predetermined electromagnetic radiation that is allowed to pass through the surrounding area, the second recess has a third transmittance, the third transmittance is equal to the allowable penetration A quantity of the predetermined electromagnetic radiation passing through the second recess.