TWI809636B - Pixel structure - Google Patents

Abstract

A pixel structure is provided. The pixel structure includes a substrate and a conductive line electrically connected to the substrate. The ratio of the height to the width of the conductive line is between 0.5 and 6. The pixel structure also includes an electrode electrically connected to the conductive line and a conversion element electrically connected to the conductive lines through the electrode.

Description

pixel structure

The disclosed embodiments are related to a pixel structure, and in particular, to a pixel structure capable of having high transparency and/or sensing properties.

With the development of technology (eg, touch and/or display technology), the application range of electronic devices with (touch) display screens is becoming wider and more diverse. For example, transparent display panels can be used in intelligent display applications that integrate virtual and real, such as interactive display devices such as artwork display windows and interactive sensing glass for vehicles.

However, limited by the existing manufacturing process and structural design, it is not easy to shrink the width of the wires and the size of the via hole in the display panel, and it is difficult to manufacture a display panel with a highly transparent and/or sensor-integrated structure. Insufficient transparency may reduce the clarity of background objects, affect the contrast between the background and the image presentation of the interactive display device, and further affect the user's viewing quality and operation convenience/smoothness, and also limit the use of the display panel.

The disclosed embodiments include a pixel structure. The pixel structure includes a substrate and conductive lines, and the conductive lines are electrically connected to the substrate. The height-to-width ratio of the conductive lines is between 0.5 and 6. The pixel structure also includes electrodes and conversion elements, the electrodes are electrically connected to the conductive wires, and the conversion elements are electrically connected to the conductive wires through the electrodes.

The following disclosure provides many different embodiments or examples for implementing different features of the present invention. The following disclosure describes specific examples of components and their arrangements for simplicity of illustration. Of course, these specific examples are not intended to be limiting. For example, if the embodiment of the present disclosure describes that the first characteristic component is formed on or above the second characteristic component, it means that it may include an embodiment in which the first characteristic component is in direct contact with the second characteristic component, and may also include Embodiments wherein additional features are formed between the first and second features such that the first and second features may not be in direct contact.

It should be understood that additional operational steps may be implemented before, during or after the method, and in other embodiments of the method, some of the operational steps may be replaced or omitted.

In addition, spatial terms may be used, such as "under", "below", "below", "over", "above", "on" and the like These space-related terms are used to describe the relationship between one (some) elements or feature parts and another (some) element or feature parts in the illustration. These space-related words include in use or in operation different orientations of the device, as well as the orientation depicted in the drawings. When the device is turned in a different orientation (eg, rotated 90 degrees or otherwise), then spatially relative adjectives used therein are also to be interpreted in terms of the turned orientation.

In the description, the terms "about", "approximately" and "substantially" usually mean within 20%, or within 10%, or within 5%, or within 3% of a given value or range , or within 2%, or within 1%, or within 0.5%. The quantities given here are approximate quantities, that is, the terms "about", "approximately" and "substantially" can still be implied if there is no specific description of "about", "approximately" and "substantially". meaning.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It can be understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having meanings consistent with the related art and the background or context of the present disclosure, rather than in an idealized or overly formal manner Interpretation, unless otherwise defined in the embodiments of the present disclosure.

Different embodiments disclosed below may reuse the same reference symbols and/or signs. These repetitions are for simplicity and clarity and are not intended to limit a particular relationship between the different embodiments and/or structures discussed.

"Aperture ratio" refers to the light transmittance ratio, that is, the ratio that allows the light source to be projected and reduces the consumption of the light source on the display panel (middle). The higher the aperture ratio, the more light is transmitted. For example, in a liquid crystal display device, when light is emitted through the backlight module, not all the light can pass through the liquid crystal display panel, and may be stored by signal lines such as drive chips, thin film transistors, and storage voltages. Capacitors, etc. block. Generally speaking, the ratio of the effective light-transmitting area to the overall area of the display panel can be referred to as the aperture ratio.

In the pixel structure of the display panel, the pixel aperture ratio is mainly affected by the size of the peripheral circuit and the size of the via hole of the circuit. In order to achieve finer display quality (for example, the higher the pixel per inch (PPI) or pixel density), the pixel size of the pixel structure is getting smaller and smaller, but this also makes the size of the peripheral circuit and the via hole of the circuit The effect of the size on the aperture ratio is more significant.

For example, under the condition that the width of the peripheral lines (ie, line width) is 5 micrometers (μm) and the width of the via holes is 5 μm, the pixel aperture ratio can only reach 70%. In a transparent display panel, a lower aperture ratio will reduce the transparency of the display panel, thereby affecting the display quality of the transparent display panel.

In an embodiment of the present disclosure, the conductive lines of the pixel structure of the display panel have a specific aspect ratio (ie, the ratio of height to width), such as about 0.5 to about 6. Referring to FIG. In addition, in some embodiments, in the corresponding region, the included angle between the via hole and the plane parallel to the surface of the substrate of the pixel structure is between about 60 degrees and about 85 degrees, such configuration can effectively improve the (pixel) of the pixel structure. Aperture ratio, so as to improve the clarity of the display image, and manufacture a display panel with a highly transparent and/or sensor-integrated structure.

FIG. 1 is a partial top view illustrating a pixel structure 100 according to some embodiments of the present disclosure. FIG. 2 is a partial cross-sectional view illustrating the region R1 of the pixel structure 100 in FIG. 1 according to some embodiments of the present disclosure. For example, Figure 2 may be a partial sectional view cut along line A-A' of Figure 1 . However, it should be noted that, for the sake of brevity, some components of the pixel structure 100 have been omitted in FIG. 1 and FIG. 2 , and the components shown in FIG. 1 and FIG. 2 may not exactly correspond to each other.

Referring to FIG. 1 , in some embodiments, the pixel structure 100 has (or is divided into) a display area 100D and a peripheral area 100P, and the peripheral area 100P may surround the display area 100D. For example, the display elements, photoelectric conversion elements, and sensing contact devices of the pixel structure 100 can be disposed in the display area 100D of the pixel structure 100, while the operating elements, sensing elements, display elements, conductive lines, and conductive elements of the pixel structure 100 Pads and the like can be disposed on the peripheral region 100P of the pixel structure 100 , but the embodiments of the present disclosure are not limited thereto.

Referring to FIG. 2 , in some embodiments, the pixel structure 100 may include a substrate 10 . For example, the substrate 10 can be a rigid circuit substrate, which can include elemental semiconductors (such as silicon or germanium, etc.), compound semiconductors (such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs) or indium phosphide (InP), etc.), alloy semiconductors (eg, SiGe, SiGeC, GaAsP, or GaInP, etc.), other appropriate semiconductors, or a combination of the foregoing. The substrate 10 can also be a flexible circuit substrate, a semiconductor-on-insulator (SOI) substrate, or a glass substrate. In addition, the substrate 10 can also serve as a gas barrier layer.

Referring to FIG. 1 and FIG. 2, in some embodiments, the pixel structure 100 includes conductive lines C1, C2, the conductive lines C1, C2 are disposed in the peripheral region 100P of the pixel structure 100, and the conductive lines C1 and the substrate 10 (electrically ) is connected, and the conductive line C2 is not connected to the substrate 10 . As shown in FIG. 2 , in some embodiments, the conductive line C1 is electrically connected to the substrate 10 through the via hole H1 and the conductive layer CS1 filled in the via hole H1 . Specifically, the conductive layer CS1 may be connected to the semiconductor layer 10C of the substrate 10 , but the embodiments of the present disclosure are not limited thereto.

The conductive lines C1 , C2 and the conductive layer CS1 may include conductive materials, such as metal, metal silicide, similar materials, or a combination thereof. Metals may include, for example, gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al ), copper (Cu), similar materials, alloys of the foregoing, or combinations of the foregoing, but embodiments of the present disclosure are not limited thereto. In addition, the semiconductor layer 10C may include semiconductor materials such as polysilicon.

As shown in FIG. 2 , in some embodiments, the ratio of the height HC1 to the width WC1 (ie, HC1 /WC1 ) of the conductive line C1 is between about 0.5 and about 6. Referring to FIG. In addition, in this embodiment, the width WC1 (ie, line width) of the conductive line C1 is 2 micrometers (μm) as an example. In some other embodiments, the ratio of the height HC1 to the width WC1 of the conductive lines C1 ranges from about 2 to about 5. According to the width WC1 of the conductive line C1 , the ratio of the height HC1 to the width WC1 of the conductive line C1 can be adjusted to an appropriate range.

As shown in FIG. 2, in some embodiments, the pixel structure 100 may further include a first interlayer dielectric layer 12, a second interlayer dielectric layer 14, and a third interlayer dielectric layer 16. The first interlayer dielectric layer Layer 12 , second ILD layer 14 and third ILD layer 16 are disposed between substrate 10 and conductive lines C1 , C2 . The first interlayer dielectric layer 12 may comprise, for example, silicon oxide, such as silicon nitride, similar materials, or a combination thereof, while the second interlayer dielectric layer 14 and the third interlayer dielectric layer 16 may comprise, for example, oxide Silicon, silicon nitride, silicon oxynitride, low-k dielectric material, aluminum oxide, aluminum nitride, similar materials or combinations thereof, but the embodiments of the present disclosure are not limited thereto. The first interlayer dielectric layer 12 may serve as a gate insulating layer. In addition, the via hole H1 can pass through the third interlayer dielectric layer 16 , the second interlayer dielectric layer 14 and the first interlayer dielectric layer 12 .

As shown in FIG. 2 , in some embodiments, the included angle θ between the via hole H1 and a plane parallel to the surface of the substrate 10 (for example, the top surface of the semiconductor layer 10C of the substrate 10 ) ranges from about 60 degrees to about 85 degrees. . By forming the conductive line C1 to have a specific aspect ratio (ie, the ratio of height to width), such as between about 0.5 and about 6, and/or making the angle between the via hole H1 and a plane parallel to the surface of the substrate 10 θ ranges from about 60 degrees to about 85 degrees, which can effectively increase the (pixel) aperture ratio of the pixel structure 100 .

3A to 3C are cross-sectional views illustrating the steps of forming the conductive line C1 and making it electrically connected to the substrate 10 according to some embodiments. Referring to FIG. 3A , firstly, a first interlayer dielectric layer 12 , a second interlayer dielectric layer 14 and a third interlayer dielectric layer 16 are formed on the substrate 10 . For example, the first interlayer dielectric layer 12 , the second interlayer dielectric layer 14 and the third interlayer dielectric layer 16 can be formed on the substrate 10 through a deposition process. The deposition process includes, for example, a chemical vapor deposition process, an atomic layer deposition process, a spin coating process, similar deposition processes or a combination thereof, but the embodiments of the present disclosure are not limited thereto. In addition, although the first interlayer dielectric layer 12, the second interlayer dielectric layer 14, and the third interlayer dielectric layer 16 are shown here as three different stacked layers, the first interlayer dielectric layer 12, The second interlayer dielectric layer 14 and the third interlayer dielectric layer 16 may also be the same layer, or the second interlayer dielectric layer 14 and the third interlayer dielectric layer 16 may be regarded as the same interlayer dielectric layer.

As shown in FIG. 3A , then, a via hole H1 is formed, and the via hole H1 can pass through the third interlayer dielectric layer 16 , the second interlayer dielectric layer 14 and the first interlayer dielectric layer 12 . For example, a patterning process can be performed to form the via hole H1. The patterning process includes forming a mask layer (not shown) on the third ILD layer 16, and then etching the third ILD layer 16, the second ILD layer 14 and the first ILD layer 12. The part not covered by the mask layer is used to form the via hole H1. It should be noted that although it is not clearly marked in FIG. 3A, the included angle θ between the via hole H1 and a plane parallel to the surface of the substrate 10 (for example, the top surface of the semiconductor layer 10C of the substrate 10) may be about 60 degrees. to about 85 degrees, similar to that shown in Figure 2.

For example, the mask layer may include photoresist, such as positive photoresist or negative photoresist. In addition, the mask layer may comprise a hard mask, such as silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbide nitride (SiCN), and the like. material or a combination of the foregoing. The mask layer can be a single-layer or multi-layer structure. The formation of the mask layer may include a deposition process, a photolithography process, other suitable processes or a combination thereof, but the embodiments of the present disclosure are not limited thereto.

For example, the deposition process may include spin-on coating, chemical vapor deposition, atomic layer deposition, similar processes, or combinations thereof. For example, the photolithography process may include photoresist coating (such as spin coating), soft baking (soft baking), mask alignment (mask aligning), exposure (exposure), post-exposure baking (post- Exposure baking (PEB), developing (developing), cleaning (rinsing), drying (such as hard baking), other suitable processes or a combination of the foregoing.

As shown in FIG. 3A, then, a sputtering process may be performed to form a conductive layer CS0 on the sidewall of the via hole H1. For example, the conductive layer CS0 includes conductive materials, examples of which are as described above and will not be repeated here. In some embodiments, the conductive layer CS0 may further cover a portion of the third interlayer dielectric layer 16 .

Referring to FIG. 3B , the conductive layer CS1 may be filled in the via hole H1 by, for example, an electroplating process or an electroless plating process. As shown in FIG. 3B , the top surface of the conductive layer CS1 may be substantially flush with the top surface of the conductive layer CS0 , but the embodiments of the present disclosure are not limited thereto.

Referring to FIG. 3C , another electroplating process or electroless plating process can be performed to form conductive lines C1 on the conductive layer CS1 . It should be noted that, although not explicitly shown in FIG. 3C , the ratio of the height HC1 to the width WC1 of the conductive line C1 (ie, HC1/WC1 ) may range from about 0.5 to about 6, similar to that shown in FIG. 2 .

In addition, although in the embodiments of FIG. 3B and FIG. 3C , the conductive layer CS1 and the conductive line C1 are formed through two processes, the embodiments of the present disclosure are not limited thereto. In some other embodiments, the conductive layer CS1 and the conductive line C1 can be formed through the same process.

In the embodiment of Figure 3A to Figure 3C, the conductive layer CS0, the conductive layer CS1 and the conductive Line C1. Therefore, the conductive material (eg, metal) can fill up the via hole H1 , thereby reducing the signal loss of the via hole H1 .

Please refer back to FIG. 2 , in some embodiments, the pixel structure 100 includes an electrode 20 , and the electrode 20 may be disposed on the conductive line C1 and electrically connected to the conductive line C1 . For example, electrode 20 may comprise a metal (e.g., copper, molybdenum, aluminum, tungsten, gold, chromium, nickel, platinum, titanium), an alloy (e.g., an alloy of the aforementioned metals), a transparent conductive material, other suitable conductive material, or combinations thereof, but the embodiments of the present disclosure are not limited thereto. The transparent conductive material includes, for example, indium tin oxide (ITO), tin oxide (tin oxide, TO), indium zinc oxide (indium zinc oxide, IZO), indium gallium zinc oxide (indium gallium zinc oxide, IGZO), Indium tin zinc oxide (ITZO), antimony-doped tin oxide (ATO), antimony zinc oxide (aluminum-doped zinc oxide, AZO), but the embodiment of the present disclosure is not limited thereto.

Referring to FIG. 2 , in some embodiments, the pixel structure 100 includes a conversion element 30 , and the conversion element 30 is electrically connected to the conductive line C1 through the electrode 20 . The conversion element 30 can be a photoelectric conversion element or other conversion elements. For example, the conversion element 30 can be a light emitting element of the pixel structure 100, such as light-emitting diode (light-emitting diode, LED), miniature light-emitting diode (micro LED or mini-LED), quantum dot light-emitting diode (quantum dot light-emitting diode, QLED/QDLED), quantum dots, organic light-emitting diode (organic light-emitting diode, OLED) or other suitable components, but the embodiments of the present disclosure are not limited thereto. Alternatively, the conversion element 30 can also be a sensing element of the pixel structure 100 of the touch display panel, such as a PIN-type photosensor, a diode sensing element or other suitable components, but this is not the case in the embodiments of the present disclosure. limit.

Referring to FIG. 2 , in some embodiments, the pixel structure 100 includes a flat layer 40 , and the flat layer 40 may be disposed between the conductive line C1 and the conversion element 30 . In more detail, the flat layer 40 is disposed between the conductive lines C1 and the electrodes 20 , between the conductive lines C1 , and/or between the conductive lines C1 and the conductive lines C2 . The flat layer 40 may include polyimide (PI), spin-on glass (SOG) or other suitable materials, but the disclosed embodiments are not limited thereto.

In the pixel structure 100 of the disclosed embodiment, since the ratio of the height HC1 to the width WC1 (ie, HC1/WC1) of the conductive line C1 is between about 0.5 and about 6, the design space and transparency of the pixel structure 100 can be increased, and The voltage degradation of the pixel structure 100 is reduced. In addition, in some embodiments, the angle θ between the via hole H1 and the plane parallel to the surface of the substrate 10 ranges from about 60 degrees to about 85 degrees, which can effectively increase the (pixel) aperture ratio of the pixel structure 100, thereby improving the pixel size. The resolution and transparency of the structure 100 (and the display panel using the pixel structure 100).

The following is the measurement of the pixel aperture ratios of the pixel structures of the embodiment and the comparative example under the condition that the pixel design is 100 PPI. The width (i.e., line width) of the conductive line of embodiment 1 is 2 microns, and the ratio of the height to width of the conductive line is about 5; the width (i.e., line width) of the conductive line of embodiment 2 is 2 microns, conductive The ratio of the height to the width of the line is about 6, and the angle between the via hole and the plane parallel to the surface of the substrate is about 85 degrees (similar to the pixel structure 100 shown in FIG. 1 and FIG. 2 ); The width of the line (i.e., linewidth) is 5 microns, the ratio of the height to width of the conductive line is about 0.1 (not in the range of 0.5 to 6), and the angle between the via hole and the plane parallel to the surface of the substrate is about 5° degrees (not in the range of 60 degrees to 85 degrees) (similar to the pixel structure of a general display panel). The measurement results are recorded in Table 1 below.

Table I Pixel Aperture Ratio Example 1 78.6% Example 2 81.4% comparative example 70%

From the results in Table 1, it can be known that the pixel aperture ratios of the pixel structures of Embodiment 1 and Embodiment 2 are significantly improved compared with the pixel aperture ratio of the pixel structure of Comparative Example. Therefore, the pixel structure according to the disclosed embodiments can have a higher pixel aperture ratio, thereby improving the resolution and transparency of the pixel structure and a display panel using the pixel structure.

As shown in FIG. 2, in some embodiments, the pixel structure 100 includes a first conductive layer M1, and the first conductive layer M1 is disposed in the second interlayer dielectric layer 14 and interposed between the substrate 10 and the conductive lines C1 and/or between conductive wires C2. The first conductor layer M1 may comprise a metal or a metal oxide, wherein the metal may be, for example, gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium ( Cr), tungsten (W), aluminum (Al), copper (Cu), similar materials, alloys of the foregoing, or combinations of the foregoing, but embodiments of the present disclosure are not limited thereto.

As shown in FIG. 2, in some embodiments, the pixel structure 100 includes a second conductor layer M2, and the second conductor layer M2 is disposed in the third interlayer dielectric layer 16 and interposed between the first conductor layer M1 and the conductive line C2. between. The second conductor layer M2 includes the same or similar material as that of the first conductor layer M1 , which will not be repeated here, but the embodiments of the present disclosure are not limited thereto. The first conductor layer M1 , the interlayer dielectric layer (for example, the second interlayer dielectric layer 14 ) and the second conductor layer M2 can form a metal-insulator-metal (MIM) capacitor element.

As shown in FIG. 2 , in some embodiments, the conductive line C2 is electrically connected to the second conductive layer M2 . Similarly, the conductive line C2 can be electrically connected to the second conductive layer M2 through the via hole H2 and the conductive layer CS2 filled in the via hole H2 . In addition, the included angle between the via hole H2 and the plane parallel to the surface of the substrate 10 (for example, the top surface of the second conductive layer M2 ) may also range from about 60 degrees to about 85 degrees.

FIG. 4 to FIG. 7 are partial cross-sectional views illustrating the region R1 of the pixel structure 100 in FIG. 1 according to some other embodiments of the present disclosure. Similarly, Figures 4 to 7 may be partial cross-sectional views taken along line A-A' of Figure 1 .

The sectional view shown in FIG. 4 has a similar structure to the sectional view shown in FIG. 2 . Referring to FIG. 4 , the conductive line C1 can be formed through a single process (such as electroplating), that is, the conductive line C1 can be directly filled into the via hole H1 without the conductive layer CS1. Similarly, the conductive line C2 can be formed through a single process (such as electroplating), that is, the conductive line C2 can be directly filled into the via hole H2 without the conductive layer CS2. Therefore, the top of the conductive line C1 and the top of the conductive line C2 may respectively have a concave portion CA1 and a concave portion CA2, and the concave portion CA1 and the concave portion CA2 correspond to the via hole H1 and the via hole H2 respectively. In addition, as shown in FIG. 4 , in some embodiments, a part of the electrode 20 may be disposed in the concave portion CA1 of the conductive line C1 .

The sectional view shown in FIG. 5 has a similar structure to the sectional view shown in FIG. 2 . Referring to FIG. 5, the pixel structure 100 may not include the second conductor layer M2. In this embodiment, the first conductor layer M1, the interlayer dielectric layer (for example, the second interlayer dielectric layer 14 and the third interlayer dielectric layer 16) and the conductive line C2 can form a metal-insulator-metal (MIM) capacitive element.

The sectional view shown in FIG. 6 has a structure similar to the sectional view shown in FIG. 2 . Referring to FIG. 6 , the conductive line C2 is not electrically connected to the second conductive layer M2 . In some embodiments, the conductive wire C2 is electrically connected to the first conductive layer M1. Similarly, the conductive line C2 can be electrically connected to the first conductive layer M1 through the via hole H2 and the conductive layer CS2 filled in the via hole H2 . In this embodiment, the second conductor layer M2 , the interlayer dielectric layer (eg, the third interlayer dielectric layer 16 ) and the conductive line C2 can form a metal-insulator-metal (MIM) capacitor.

The sectional view shown in FIG. 7 has a structure similar to the sectional view shown in FIG. 6 . Referring to FIG. 7 , the conductive line C1 can be formed through a single process (such as electroplating), that is, the conductive line C1 can be directly filled into the via hole H1 without the conductive layer CS1. Similarly, the conductive line C2 can be formed through a single process (such as electroplating), that is, the conductive line C2 can be directly filled into the via hole H2 without the conductive layer CS2. Therefore, the top of the conductive line C1 and the top of the conductive line C2 may respectively have a concave portion CA1 and a concave portion CA2, and the concave portion CA1 and the concave portion CA2 correspond to the via hole H1 and the via hole H2 respectively. In addition, in this embodiment, the flat layer 40 is further disposed in the concave portion CA1 and the concave portion CA2 and on the conductive line C1 and the conductive line C2 .

FIG. 8 is a partial schematic diagram illustrating a pixel structure 102 according to some embodiments of the present disclosure. Fig. 9 is a partial cross-sectional view along line B-B' of Fig. 8 according to some embodiments of the present disclosure. Similarly, for the sake of brevity, some components of the pixel structure 102 have been omitted in FIGS. 8 and 9 , and the components shown in FIGS. 8 and 9 may not exactly correspond to each other.

Referring to FIG. 8 and FIG. 9, in some embodiments, the pixel structure 102 includes a substrate 10 and a conductive line C1. For example, the substrate 10 may include passive matrix circuits. That is, a plurality of pixel structures 102 can constitute a passive matrix display device, but the embodiments of the present disclosure are not limited thereto. In addition, although FIG. 9 does not show that the conductive wire C1 is in direct contact with the substrate 10 , the conductive wire C1 can actually be electrically connected to the substrate 10 .

As shown in FIG. 9, in some embodiments, the pixel structure 102 includes an electrode 20, and the electrode 20 is electrically connected to the conductive line C1. In addition, as shown in FIG. 8 and FIG. 9 , in some embodiments, the pixel structure 102 may include a conversion element 30 , and the conversion element 30 is electrically connected to the conductive line C1 through the electrode 20 . Similarly, in the present embodiment, the ratio of the height HC1 to the width WC1 of the conductive line C1 (ie, HC1/WC1 ) may range from about 0.5 to about 6. Referring to FIG.

In addition, as shown in FIG. 9 , in some embodiments, the conductive line C1 is electrically connected to the conversion element 30 through the via hole H1 and the electrode 20 filled in the via hole H1 . Specifically, the electrode 20 may be disposed at the bottom of the conductive line C1 and extend into the via hole H1 to be in contact with the conversion element 30 , but the embodiment of the present disclosure is not limited thereto. Similarly, in the present embodiment, the included angle θ1 between the via hole H1 and a plane parallel to the surface of the substrate 10 (eg, the top surface of the converting element 30 ) ranges from about 60 degrees to about 85 degrees.

As shown in FIG. 9 , in some embodiments, the substrate 10 has a conductive metal CM, and the conversion element 30 is electrically connected to the conductive metal CM through another via hole H3 and another electrode 22 filled in the via hole H3 . Similarly, in some embodiments, the included angle θ2 between the via hole H3 and a plane parallel to the surface of the substrate 10 (eg, the top surface of the conductive metal CM) ranges from about 60 degrees to about 85 degrees.

For example, the conversion element 30 can be a light-emitting element of the pixel structure 102, and the electrodes 20 and 22 can be metal oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), or other transparent conductive films, such as conductive Polymers, carbon nanotubes, graphene, metal nanowires or other similar materials, but the embodiments of the present disclosure are not limited thereto. The conductive line C1 and the signal connection (bridge) wire of the conversion element 30 (for example, a light emitting element) and the signal connection (bridge) wire of the conductive metal CM and the conversion element 30 (that is, the electrode 20 and the electrode 22) can use transparent metal, so that The pixel structure 102 can perform up-and-down light-emitting display (such as the light L shown in FIG. 9 ), but the embodiments of the present disclosure are not limited thereto.

As shown in FIG. 9 , in some embodiments, the pixel structure 102 may include planar layers 41 , 42 disposed between the conductive lines C1 and the substrate 10 . The planarization layers 41, 42 may comprise the same or similar materials as the planarization layer 40 shown in FIGS. 2, 4-7, which will not be repeated here. As shown in FIG. 9 , in some embodiments, conversion element 30 is disposed in planar layer 42 . In addition, the flat layer 42 can also be filled into the via hole H3 and located on the electrode 22 , but the embodiment of the present disclosure is not limited thereto. It should be noted that although FIG. 9 shows the planarization layers 41 and 42 as two different planarization layers, the planarization layers 41 and 42 may also be the same planarization layer.

FIG. 10 is a partial schematic diagram illustrating a pixel structure 104 according to some embodiments of the present disclosure. Fig. 11 is a partial cross-sectional view taken along line C-C' of Fig. 10 according to some embodiments of the present disclosure. Similarly, for the sake of brevity, some components of the pixel structure 104 have been omitted in FIGS. 10 and 11 , and the components shown in FIGS. 10 and 11 may not exactly correspond to each other.

Referring to FIG. 10 and FIG. 11 , in some embodiments, the pixel structure 104 includes a substrate 10 and a conductive line C1 . Similarly, substrate 10 may contain passive matrix circuitry. In addition, although FIG. 11 does not show that the conductive wire C1 is in direct contact with the substrate 10 , the conductive wire C1 can actually be electrically connected to the substrate 10 .

As shown in FIG. 11 , in some embodiments, the pixel structure 104 may include a conversion element 30 , and the conductive line C1 is disposed on the conversion element 30 and directly contacts the conversion element 30 . In addition, as shown in FIG. 11 , in some embodiments, the substrate 10 has a conductive metal CM, and the conversion element 30 is electrically connected to the conductive metal CM through the via hole H3 and the electrode 22 filled in the via hole H3 .

Similarly, in some embodiments, the included angle θ2 between the via hole H3 and a plane parallel to the surface of the substrate 10 (eg, the top surface of the conductive metal CM) ranges from about 60 degrees to about 85 degrees. Specifically, as shown in FIG. 11 , the electrode 22 can extend from the bottom surface of the conversion element 30 to the via hole H3 and fill the via hole H3 to be electrically connected to the conductive metal CM. The conductive metal CM and the signal connection (bridge) wire (ie, the electrode 22) of the conversion element 30 (eg, a light-emitting element) can use a transparent metal, so that the pixel structure 104 can perform a down-emitting display (such as the light shown in FIG. 11 L), but the embodiments of the present disclosure are not limited thereto.

FIG. 12 is a partial schematic diagram illustrating a pixel structure 106 according to some embodiments of the present disclosure. Fig. 13 is a partial cross-sectional view along the line D-D' of Fig. 12 according to some embodiments of the present disclosure. Similarly, for the sake of brevity, some components of the pixel structure 106 have been omitted in FIGS. 12 and 13, and the components shown in FIG. 12 and FIG. 13 may not exactly correspond to each other.

Referring to FIG. 12 and FIG. 13, in some embodiments, the pixel structure 106 includes an electrode 20, and the electrode 20 is electrically connected to the conductive lines C1 and C2. In addition, as shown in FIG. 12 and FIG. 13 , in some embodiments, the pixel structure 106 may include a conversion element 30 , and the conversion element 30 is electrically connected to the conductive lines C1 and C2 through the electrode 20 . The conductive lines C1 , C2 can be disposed in the planar layer 42 , and the converting element 30 can be disposed on the planar layer 42 . As shown in FIG. 13, in some embodiments, the conductive line C2 has a via hole H2 (for example, the via hole H2 is located on the top of the conductive line C2), and the conductive line C2 passes through the via hole H2 and fills the electrode of the via hole H2. 20 is electrically connected to the conversion element 30 .

In addition, as shown in FIG. 13, in some embodiments, the conductive metal CM has a via hole H4, and a part of the conductive line C2 is disposed in the via hole H4. Similarly, in some embodiments, the angle θ3 between the via hole H4 and the plane parallel to the surface of the substrate 10 ranges from about 60 degrees to about 85 degrees.

As shown in FIG. 13 , in some embodiments, the substrate 10 of the pixel structure 106 further includes a reflective electrode 10R, and the reflective electrode 10R can be disposed between the substrate 10 and the conversion element 30 . The pixel structure 106 can perform up and down light-emitting display (such as the light L shown in FIG. 13), and the reflective electrode 10R can further reflect the light L under the conversion element 30 (for example, a light-emitting element) to become a reflected light RL to enhance Light is emitted from above, but the embodiments of the present disclosure are not limited thereto.

FIG. 14 to FIG. 16 are partial top views illustrating the pixel structure 108 , the pixel structure 110 and the pixel structure 112 according to some other embodiments of the present disclosure. Similarly, for simplicity, some components of the pixel structure 108 , the pixel structure 110 and the pixel structure 112 have been omitted in FIGS. 14 to 16 .

The partial cross-sectional view of the region R2 of the pixel structure 108 in FIG. 14 may be similar to the cross-sectional views shown in FIG. 2 or FIGS. 4 to 7 . In other words, the conductive line C1 or C2 of the pixel structure 108 can be located in the peripheral area 108P of the pixel structure 108 , that is, it does not overlap with the display area 108D of the pixel structure 108 .

A partial cross-sectional view cut along the line E-E' of the pixel structure 110 in FIG. 15 may be similar to the cross-sectional view shown in FIG. 9 , FIG. 11 or FIG. 13 . That is, in some embodiments, the orthographic projection of the conductive line C1 or C2 of the pixel structure 110 on the substrate 10 does not overlap with the orthographic projection of the display area 110D of the pixel structure 110 on the substrate 10 , but is consistent with the periphery of the pixel structure 110 Orthographic projections of the region 110P on the pixel structure substrate 10 are at least partially overlapped. In addition, the conversion element 30 of the pixel structure 110 can be disposed in the peripheral area 110P of the pixel structure 110 .

The partial cross-sectional view of the region R3 of the pixel structure 112 in FIG. 16 may be similar to the cross-sectional views shown in FIG. 2 or FIGS. 4 to 7 . In other words, the conductive line C1 or C2 of the pixel structure 112 can be located in the peripheral area 100P of the pixel structure 112 , that is, it does not overlap with the display area 112D of the pixel structure 112 . In addition, in some embodiments, the conductive lines C1 and C2 may be data lines or scan lines of the pixel structure 112 .

FIG. 17 is a partial top view illustrating the pixel structure 114 according to some embodiments of the present disclosure. FIG. 18 is a partial cross-sectional view illustrating a region R4 of the pixel structure 114 in FIG. 17 according to some embodiments of the present disclosure. Similarly, for the sake of brevity, some components of the pixel structure 114 have been omitted in FIGS. 17 and 18, and the components shown in FIGS. 17 and 18 may not exactly correspond to each other.

Referring to FIG. 17 , in some embodiments, the pixel structure 114 has (or is divided into) a display area 114D and a peripheral area 114P, and the peripheral area 114P may surround the display area 114D. For example, the display elements, photoelectric conversion elements, and sensing contact devices of the pixel structure 114 can be disposed in the display area 114D of the pixel structure 114, and the operating elements, sensing elements, display elements, conductive lines, and conductive elements of the pixel structure 114 Pads and the like can be disposed on the peripheral region 114P of the pixel structure 114 , but the embodiment of the present disclosure is not limited thereto.

Referring to FIG. 18 , in some embodiments, the pixel structure 114 includes a substrate 10 and a conductive line C1 , and the conductive line C1 is electrically connected to the substrate 10 . The substrate 10 can be used as a buffer layer, for example. As shown in FIG. 18, in some embodiments, the pixel structure 114 includes a plurality of alternately stacked oxide layers 11 (for example, silicon oxide) and nitride layers 13 (for example, silicon nitride), and the oxide layers 11 and The nitride layer 13 can be stacked sequentially on the substrate 10 , for example.

As shown in FIG. 18, in some embodiments, the pixel structure 114 includes a PIN-type diode, and the PIN-type diode includes a P-type semiconductor material layer P, an amorphous silicon (amorphous silicon, a-Si) layer I and The N-type semiconductor material layer N, and the PIN-type diode pass through a part of the oxide layer 11 and the nitride layer 13 that are stacked alternately. In some embodiments, the conductive line C1 is electrically connected to the N-type semiconductor material layer N of the PIN diode through the via hole H1 and the conductive layer CS1 filled in the via hole H1 . Similarly, the included angle θ5 between the via hole H1 and a plane parallel to the surface of the substrate 10 (eg, the top surface of the N-type semiconductor material layer N) ranges from about 60 degrees to about 85 degrees.

According to the above description, in the pixel structure of the disclosed embodiment, the conductive line has a specific aspect ratio, which can increase the design space and transparency of the pixel structure, and reduce the voltage degradation of the pixel structure. In addition, in some embodiments, the included angle between the via hole in the corresponding region and the plane parallel to the surface of the substrate of the pixel structure ranges from about 60 degrees to about 85 degrees, which can effectively improve the (pixel) aperture ratio of the pixel structure. , so as to improve the definition of the display image, and manufacture a display panel with a highly transparent and/or sensor-integrated structure.

The components of several embodiments are summarized above, so that those skilled in the art of the present disclosure can better understand the viewpoints of the embodiments of the present disclosure. Those with ordinary knowledge in the technical field of the present disclosure should understand that they can design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purpose and/or advantages as the embodiments described herein. Those with ordinary knowledge in the technical field to which this disclosure belongs should also understand that such equivalent structures do not depart from the spirit and scope of this disclosure, and they can make various changes without departing from the spirit and scope of this disclosure. Various changes, substitutions and substitutions. Therefore, the scope of protection of this disclosure should be defined by the appended scope of patent application and its equivalent scope. In addition, although the present disclosure has been disclosed above with several preferred embodiments, it is not intended to limit the present disclosure.

Reference throughout this specification to features, advantages, or similar language does not imply that all features and advantages that may be realized with the present disclosure should or can be achieved in any single embodiment of the disclosure. Conversely, language referring to the features and advantages is understood to mean that a specific feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, discussions of the features and advantages, and similar language, throughout this specification may, but do not necessarily, refer to the same embodiment.

Furthermore, the features, advantages, and characteristics described in the present disclosure may be combined in any suitable manner in one or more embodiments. Based on the description herein, one skilled in the relevant art will recognize that the present disclosure can be practiced without one or more of the specific features or advantages of a particular embodiment. In other cases, additional features and advantages may be recognized in certain embodiments, which may not be present in all embodiments of the present disclosure.

100,102,104,106,108,110,112,114: pixel structure 100D, 108D, 110D, 112D, 114D: display area 100P, 108P, 110P, 112P, 114P: Peripheral area 10: Substrate 10C: Semiconducting layer 10R: reflective electrode 11: oxide layer 12: The first interlayer dielectric layer 13: Nitride layer 14: The second interlayer dielectric layer 16: The third interlayer dielectric layer 20,22: electrode 30: Conversion element 40, 41, 42: flat layers C1, C2: conductive thread CA1, CA2: concave part CM: conductive metal CS0, CS1, CS2: conductive layer H1, H2, H3, H4: via holes HC1: the height of the conductive line I: Amorphous silicon layer L: light M1: the first conductor layer M2: second conductor layer N: N-type semiconductor material layer P: P-type semiconductor material layer R1, R2, R3: area RL: reflected light WC1: the width of the conductive line A-A', B-B', C-C', D-D', E-E': lines θ, θ1, θ2, θ3, θ4, θ5: included angle

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that the various features are not drawn to scale and are used for illustrative purposes only. In fact, the dimensions of elements may be enlarged or reduced to clearly show the technical features of the embodiments of the present disclosure. FIG. 1 is a partial top view illustrating a pixel structure according to some embodiments of the present disclosure. FIG. 2 is a partial cross-sectional view illustrating the region of the pixel structure in FIG. 1 according to some embodiments of the present disclosure. 3A to 3C are cross-sectional views illustrating steps of forming conductive lines and electrically connecting them to a substrate according to some embodiments. FIG. 4 to FIG. 7 are partial cross-sectional views illustrating regions of the pixel structure in FIG. 1 according to some other embodiments of the present disclosure. FIG. 8 is a partial schematic diagram illustrating a pixel structure according to some embodiments of the present disclosure. Fig. 9 is a partial cross-sectional view along line B-B' of Fig. 8 according to some embodiments of the present disclosure. FIG. 10 is a partial schematic diagram illustrating a pixel structure according to some embodiments of the present disclosure. Fig. 11 is a partial cross-sectional view taken along line C-C' of Fig. 10 according to some embodiments of the present disclosure. FIG. 12 is a partial schematic diagram illustrating a pixel structure according to some embodiments of the present disclosure. Fig. 13 is a partial cross-sectional view along the line D-D' of Fig. 12 according to some embodiments of the present disclosure. FIG. 14 to FIG. 16 are partial top views illustrating pixel structures according to some other embodiments of the present disclosure. FIG. 17 is a partial top view illustrating a pixel structure according to some embodiments of the present disclosure. FIG. 18 is a partial cross-sectional view illustrating the region of the pixel structure in FIG. 17 according to some embodiments of the present disclosure.

10: Substrate 10C: Semiconducting layer 12: The first interlayer dielectric layer 14: The second interlayer dielectric layer 16: The third interlayer dielectric layer 20: electrode 30: Conversion element 40: flat layer C1, C2: conductive thread CS0, CS1, CS2: conductive layer H1, H2: via holes HC1: the height of the conductive line M1: the first conductor layer M2: second conductor layer WC1: the width of the conductive line θ: included angle

Claims (20)

A pixel structure comprising: a substrate; a conductive line electrically connected to the substrate, wherein the ratio of the height to width of the conductive line is between 0.5 and 6; an electrode electrically connected to the conductive thread; and A conversion element is electrically connected with the conductive wire through the electrode. The pixel structure according to claim 1, wherein the width of the conductive line is 2 microns. The pixel structure according to claim 1, wherein the ratio of the height to the width of the conductive line is between 2 and 5. The pixel structure according to claim 1, wherein the conductive line is electrically connected to the substrate through a via hole. The pixel structure according to claim 4, wherein an angle between the via hole and a plane parallel to the surface of the substrate is between 60 degrees and 85 degrees. For example, the pixel structure of claim item 4 further includes: An interlayer dielectric layer is disposed between the substrate and the conductive line, wherein the via hole passes through the interlayer dielectric layer. For example, the pixel structure of claim item 6 further includes: a plurality of such conductive wires; and A first conductor layer is disposed in the interlayer dielectric layer and between the substrate and the conductive lines. The pixel structure according to claim 7, wherein one of the conductive lines is electrically connected to the first conductive layer. For example, the pixel structure of claim item 7 further includes: A second conductor layer is disposed in the interlayer dielectric layer and between the first conductor layer and the conductive lines. The pixel structure according to claim 9, wherein one of the conductive lines is electrically connected to the second conductive layer. The pixel structure according to claim 4, wherein the top of the conductive line has a concave portion corresponding to the via hole. The pixel structure according to claim 11, wherein a part of the electrode is disposed in the concave portion. For example, the pixel structure of claim item 1 further includes: A flat layer is arranged between the conductive line and the converting element. The pixel structure according to claim 1, wherein the conductive line is electrically connected to the conversion element through a via hole and the electrode filled in the via hole. The pixel structure of claim 14, wherein the substrate has a conductive metal, the conversion element is electrically connected to the conductive metal through another via hole and another electrode filled in the via hole, and the other via hole is parallel to the The included angle of a plane on the surface of the substrate ranges from 60° to 85°. The pixel structure according to claim 1, wherein the substrate has a conductive metal, the conductive metal has a via hole, a part of the conductive line is arranged in the via hole, and the via hole is parallel to a plane parallel to the surface of the substrate The included angle is between 60° and 85°. The pixel structure according to claim 1, wherein the conversion element is a light emitting element, and the substrate further includes a reflective electrode, and the reflective electrode is disposed between the substrate and the conversion element. The pixel structure according to claim 1, wherein the orthographic projection of the conductive line on the substrate does not overlap with the orthographic projection of a display area of the pixel structure on the substrate. The pixel structure according to claim 1, wherein the conductive line is a data line or a scan line of the pixel structure. The pixel structure of claim item 1, wherein the conductive line is electrically connected to the N-type semiconductor material layer of a PIN type diode through a via hole and a conductive layer filled in the via hole, and the via hole is parallel to The included angle of a plane on the surface of the substrate is between 60 degrees and 85 degrees.

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