TWI807668B - Memory device with high content density - Google Patents

Abstract

A memory device is disclosed, which includes a first driving circuit, a second driving circuit, a sensing circuit and an in-memory search (IMS) array. A plurality of memory units of the in-memory search array are arranged as a plurality of horizontal rows and a plurality of vertical columns. A respective control terminal of each the memory units in the same vertical column is coupled to the first driving circuit through a corresponding word line. The memory units of the same vertical column are connected in series and coupled to the second driving circuit through the bit line, and coupled to the sensing circuit through the source line. Every 2N adjacent memory units in the same vertical column are arranged as a memory cell, and this memory cell is used to store an encoded data of 2N bits corresponding to an original data of M bits, where N and M are positive integers, and N is greater than or equal to two.

Description

High content density memory device

The present disclosure relates to a semiconductor device, and more particularly to a memory device capable of storing high content density data.

In artificial intelligence algorithms, a large number of data comparisons and data searches need to be performed. In order to meet the computational requirements of a large amount of data comparison/search, conventional technologies often use ternary content addressable memory (TCAM) to perform highly parallel search.

The types of memory used in the conventional TCAM memory are, for example, Static Random Access Memory (SRAM), 2T2R Resistive Memory (RRAM), Ferroelectric Random Access Memory (FeRAM), etc. However, when the above-mentioned type of TCAM memory is applied to parallel search operations, its performance in power consumption and on/off ratio is still not ideal, so that it is difficult to distinguish between an all-match and a 1-bit-mismatch when comparing data. In addition, the conventional TCAM memory has a low density of storage content, which is not enough for searching data of a large amount of content.

Therefore, technicians in related industries in this technical field are devoting themselves to improving the data configuration of the TCAM memory, encoding the original data of the TCAM memory, and hoping to effectively increase the density of the storage content of the TCAM memory.

According to one aspect of the present disclosure, a memory device is provided, including a first driving circuit, a second driving circuit, a sensing circuit and an In-Memory Search (IMS) array. A plurality of memory cells of the internal memory search array are configured into a plurality of horizontal columns and a plurality of vertical rows, the respective control terminals of the memory cells in the same vertical row are coupled to the first drive circuit via corresponding word lines, and the memory cells in the same vertical row are connected in series and coupled to the second drive circuit via the bit lines and coupled to the sensing circuit via the source lines. Every 2N adjacent memory cells in the memory cells of the same vertical row are configured as a memory cell, and the memory cell is used to store 2N bits of encoded data corresponding to M bits of original data, where N and M are positive integers and N is greater than or equal to two.

According to another aspect of the present disclosure, a memory device is provided, including a first driving circuit, a sensing circuit, and an In-Memory Search (IMS) array. A plurality of memory cells of the internal memory search array are arranged in a plurality of horizontal columns and a plurality of vertical rows, the respective control terminals of the memory cells in the same horizontal column are coupled to the first driving circuit through corresponding word lines, and the memory cells in the same horizontal column are coupled to the sensing circuit through matching signal lines. Every 2N adjacent memory cells in the same horizontal column are configured as a memory cell, and the memory cell is used to store 2N bits of encoded data corresponding to M bits of original data, where N and M are positive integers and N is greater than or equal to two.

By means of the above technical solution, the raw data of the TCAM memory is encoded to increase the density of the storage content of the TCAM memory. It can be applied to NAND type or NOR type memory, and cooperates with the corresponding encoding data configuration and search data configuration to effectively perform parallel data comparison and data search.

Other aspects and advantages of this disclosure can be seen by reading the following drawings, detailed description and claims.

1000, 1000b, 2000, 3000, 3000b: memory device

100: the first drive circuit

200: the second drive circuit

300: sensing circuit

400, 400b: In-memory search (IMS) array

WL1~WL12, WL2N, WL(2N+1), WL(2N+2): word line

WL4N, WLm, WL13, WL14, WL47: word line

WL48,WL95,WL96: word line

BL1~BL12, BLn: bit line

SL1~SL12, SLn: source line

ML1~ML4, MLn: matching signal line

MP-1, MP-n: pre-charged transistor

V-ML1~V-ML4, V-MLn: voltage level

VM1: The first matching voltage level

VM2: Second matching voltage level

St: control signal

Vref: reference voltage

VH: the first voltage level

VL: the second voltage level

VH2: the third voltage level

VH1: the fourth voltage level

VD1: the first drain voltage level

VD2: The second drain voltage level

VS1: The first gate voltage level

VS2: The second gate voltage level

H-Vt: the first critical voltage

L-Vt: the second critical voltage

1/0,1,0: logic value

Is: source current

Is-H: first source current

Is-L: second source current

C11~C23, C11~C41: memory cells

C11b, C11c, C11d, Cn1, Cn2: memory cells

M(1,1)a: first end

M(6,1)b: second end

M(1,1)~M(6,1), M(1,1)~M(1,12): memory unit

M(1,3)~M(6,3), M(13,1), M(14,1), M(47,1): memory unit

M(48,1), M(9,2), M(12,2), M(95,1), M(96,1): memory unit

M(2,1)~M(2,12), M(2N,1), M(2N+1,1): memory unit

M(2N+2,1), M(n,1)~M(n,8): memory unit

M(2N+1,2), M(2N+2,2): memory unit

M(2N,2), M(4N,1), M(4N,2): memory unit

FIG. 1 is a circuit diagram of a NAND memory device utilizing word line search (WL-wise search) according to an embodiment of the present disclosure.

FIGS. 2A-2C are schematic diagrams of one of the memory cells of the memory device in FIG. 1 searching for data via word lines.

FIG. 3 is a relationship diagram between the search bias inputted through the word line and the threshold voltage of the memory cell of the memory device in FIG. 1 .

FIG. 4 is a schematic diagram of the memory device in FIG. 1 performing data search through word lines.

FIG. 5 is a graph showing the relationship between the search bias voltage input by the word line and the threshold voltage of the memory cell in another embodiment of the memory device of FIG. 1 .

FIG. 6 is a schematic diagram of inputting the search bias voltage in FIG. 5 via word lines in another embodiment of the memory device in FIG. 1 to perform data search.

FIGS. 7A-7C are schematic diagrams of memory cells of different layers in a NAND memory device.

FIG. 8 is a circuit diagram of a NAND memory device utilizing bit line search (BL-wise search) according to an embodiment of the present disclosure.

FIG. 9 is a circuit diagram of a NOR memory device according to an embodiment of the present disclosure.

FIG. 10 is a timing diagram of voltage levels of matching signal lines of the memory device in FIG. 9 .

FIG. 11 is a circuit diagram of a NOR memory device according to another embodiment of the present disclosure.

FIG. 12 is a timing diagram of the voltage levels of the matching signal lines in another embodiment of the memory device of FIG. 9 .

The technical terms in this specification refer to the customary terms in this technical field. If some terms are explained or defined in this specification, the explanations or definitions of these terms shall prevail. Each embodiment of the disclosure has one or more technical features. On the premise of possible implementation, those skilled in the art may selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

FIG. 1 is a circuit diagram of a NAND type memory device 1000 utilizing word line search (WL-wise search) according to an embodiment of the present disclosure. . Please refer to FIG. 1, the memory device 1000 is a NAND memory, and the memory device 1000 includes a first driving circuit 100, a second driving circuit 200, a sensing circuit 300, an in-memory searching (IMS) array 400, a plurality of word lines (word lines) WL1-WLm, a plurality of bit lines (bit lines) BL1-BLn and complex Several source lines (source lines) SL1˜SLn.

The memory type of the IMS array 400 may be, for example, a floating gate memory, a floating dot memory, a phase-change memory (PCM), a ferroelectric random access memory (FeRAM), or a variable resistance random access memory (ReRAM), and the like. The IMS array 400 may include a plurality of memory cells M(i,j) configured in NAND type, and these memory cells M(i,j) may be configured into m horizontal columns (rows) and n vertical rows (columns). The control terminals (eg, gate terminals) of the memory cells M(i,j) in the i-th column can be coupled to the first driving circuit 100 via the word line WLi. The memory cells M(i,j) in the jth row are connected in series, and are coupled to the second driving circuit 200 via the bit line BLj, and coupled to the sensing circuit 300 via the source line SLj.

。對應的，可經由字元線WL1~WL2N輸入2N個搜尋偏壓以表示搜尋資料，此 些搜尋資料的組合數量亦為

。可對於M個位元的原始資料執行編碼機制而得到上述2N個位元的編碼資料，M為正整數。2N個位元的編碼資料的編碼組合數量

大於或等於「二的M次方」， 例如，N=3、M=4時，編碼組合數量

大於或等於「二的4次方」。 The IMS array 400 has a parameter N, which is a positive integer and N is greater than or equal to two. 2N adjacent memory cells in the same row in the IMS array 400 can be configured as a memory cell. For example, memory cells M(1,1)~M(2N,1) from column 1 to column 2N in row 1 are configured as memory cell C11, memory cells M((2N+1),1)~M(4N,1) in row 1 from column (2N+1) to column (4N) are configured as memory cell C21, and memory cells M(1,2)~M(2N,2) in column 1 to column 2N in row 2 are configured as memory cell C11. cell C12, and so on. The 2N memory units of each memory cell Cij can store 2N bits of encoded data. Among them, the coded data of the 1st~N bits can form the first coding area, and the coded data of the (N+1)~2N bits can form the second coded area, and the number of coding combinations between the first coded area and the second coded area is

. Correspondingly, 2N search bias voltages can be input through the word lines WL1~WL2N to represent the search data, and the number of combinations of these search data is also

. The above-mentioned 2N-bit coded data can be obtained by performing a coding mechanism on the M-bit raw data, where M is a positive integer. Number of encoding combinations for 2N bits of encoded data

Greater than or equal to "two to the M power", for example, when N=3, M=4, the number of coding combinations

Greater than or equal to "two to the 4th power".

The first driving circuit 100 can apply a programming voltage to the memory cell M(i,j) through the word lines WL1˜WLm to change the threshold voltage (threshold voltage, Vt) of the memory cell M(i,j), so that the memory cell M(i,j) stores a logic value “1” or a logic value “0”. A search bias can be applied through the word lines WL1 ˜WLm to search the encoded data stored in the memory cells Cij. When the search bias voltage matches the encoded data stored in the memory cell Cij, the corresponding source line SLj can output a source current Is to the sensing circuit 300, indicating that the search is successful.

FIGS. 2A-2C are schematic diagrams of one memory cell C11 of the memory device 1000 in FIG. 1 performing data search through word lines WL1-WL6. Please refer to FIG. 2A first. Taking the parameter N=3 as an example, the memory cell C11 is a 6-layer memory cell, which includes six memory units M(1,1)˜M(6,1). The control terminals (eg, gate terminals) of the memory cells M(1,1)-M(6,1) are directly or indirectly coupled to the first driving circuit 100 through the word lines WL1-WL6. The first end (for example, the drain end) M(1,1)a of the memory cell M(1,1) is directly or indirectly coupled to the second driving circuit 200 via the bit line BL1. The second terminal (for example, the source terminal) M( 6 , 1 )b of the memory unit M( 6 , 1 ) is directly or indirectly coupled to the sensing circuit 300 via the source line SL1 .

。表一所示為記憶胞C11儲存的原始資料、編碼資料及字元線WL1~WL6輸入的搜尋資料的對應關係：

The memory cell C11 can store 4-bit original data, and encode the original data into 6-bit coded data through the coding mechanism, and the coded data is stored in the memory cells M(1,1)~M(6,1). The code combination quantity of the code data stored in the memory cell C11 and the combination quantity of the search data input by the word lines WL1~WL6 are both

. Table 1 shows the correspondence between the original data stored in the memory cell C11, the coded data, and the search data input by word lines WL1~WL6:

Please refer to Table 1. In the encoding mechanism of this embodiment, the four-bit raw data of the binary value "0000" to "1111" (corresponding to the decimal value "0" to "15") can be encoded into six-bit encoded data "000111" to "101100". Furthermore, the encoded data "111111" represents "don't care" and corresponds to any one of the binary values "0" to "19" in the original data. Furthermore, the encoded data "000000" represents "invalid data".

Please refer to FIG. 2A , the first driving circuit 100 can program the memory cells M(1,1)-M(6,1) of the memory cell C11 to have "first critical voltage H-Vt" or "second critical voltage L-Vt" via word lines WL1-WL6. The first threshold voltage H-Vt has a higher voltage level and corresponds to stored data of a logic value “0”, the second threshold voltage L-Vt has a lower voltage level and corresponds to stored data of a logic value “1”, and the first threshold voltage H-Vt is greater than the second threshold voltage L-Vt. The threshold voltages of the memory cells M(1,1)~M(6,1) can be programmed as "L-Vt, H-Vt, L-Vt, L-Vt, H-Vt, H-Vt", so that the memory cells M(1,1)~M(6,1) store the six-bit encoded data "101100", which corresponds to the four-bit original data "1111" (ie, the decimal value "15").

Moreover, the first driving circuit 100 can input a search bias voltage through the word lines WL1 ˜ WL6 to search the encoded data stored in the memory cells M( 1 , 1 ) ˜ M( 6 , 1 ). Please refer to FIG. 3 at the same time, which shows the relationship between the search bias inputted through the word line WLi and the threshold voltage of the memory cell M(i,j) of the memory device 1000 in FIG. 1 . In this embodiment, the input search bias may have a "first voltage level VH" or a "second voltage level VL". The first voltage level VH of the search bias has a higher voltage A level, which represents the bit corresponding to the logical value "0" stored in the memory unit M(i,j) for the search data "H". The second voltage level VL of the search bias voltage has a lower voltage level, which represents the bit of the search data "L" corresponding to the logical value "1" stored in the memory unit M(i,j). The first voltage level VH of the search bias is greater than the second voltage level VL, the first voltage level VH of the search bias is greater than the first threshold voltage H-Vt of the memory cell M(i,j), and the second voltage level VL of the search bias is smaller than the first threshold voltage H-Vt of the memory cell M(i,j) and greater than the second threshold voltage L-Vt. The search bias of the first voltage level VH or the second voltage level VL is input to the gate of the memory cell M(i,j) through the word line WLi. If the search bias of the first voltage level VH is input, no matter the memory cell M(i,j) stores logic value “1” or logic value “0”, the search bias of the first voltage level VH can turn on the memory cell M(i,j) to generate the source current Is. If the search bias of the second voltage level VL is input, the search bias of the second voltage level VL can turn on the memory cell M(i,j) to generate the source current Is only when the memory cell M(i,j) stores logic value “1”.

Please refer to FIG. 2A again, the search bias voltage of “VL, VH, VL, VL, VH, VH” is input through the word lines WL1˜WL6 to represent the search data “LHLLHH”. The memory cells M(1,1)~M(6,1) of the memory cell C11 store the encoded data "101100", and the threshold voltages of the memory cells M(1,1)~M(6,1) are "L-Vt, H-Vt, L-Vt, L-Vt, H-Vt, H-Vt". Therefore, the search bias whose voltage level is “VL, VH, VL, VL, VH, VH” can turn on all the memory cells M(1,1)˜M(6,1), so that each of the memory cells M(1,1)˜M(6,1) generates a source current Is. Accordingly, the sensing circuit 300 can sense the source line SL1 The output source current Is can be used as a "match current". When the sensing circuit 300 senses the matching current, it can be judged that the search data “LHLLHH” input by the word lines WL1 ˜ WL6 matches the code data “101100” stored in the memory cell C11 , indicating that the search is successful.

Referring to FIG. 2B and Table 1, when each of the word lines WL1˜WL6 is input with a search bias of the first voltage level VH, the search data “HHHHHH” input by the word lines WL1˜WL6 can be used as a “wildcard”. At this time, regardless of whether the memory cells M(1,1)~M(6,1) store a logic value "0" and have the first threshold voltage H-Vt or store a logic value "1" and have the second threshold voltage L-Vt, the search bias of the first voltage level VH can turn on the memory cells M(1,1)~M(6,1) to generate the source current Is. The sensing circuit 300 can sense the matching current to determine that the search is successful. In other words, the search data "HHHHHH" as a wildcard can unconditionally match coded data of various combinations of logical values "0" or "1".

In contrast, referring to FIG. 2C and Table 1, when each of the word lines WL1˜WL6 is input with the search bias of the second voltage level VL, the search data “LLLLLL” input by the word lines WL1˜WL6 can be regarded as “invalid-search”. At this time, if the memory cells M(1,1)~M(6,1) store the logic value "0" and have the first critical voltage H-Vt, the search bias of the second voltage level VL cannot turn on the memory cells M(1,1)~M(6,1), thus no source current Is is generated. The sensing circuit 300 cannot sense the matching current and judges that the search fails.

Figure 4 shows the memory device 1000 in Figure 1 via word lines Schematic diagram of WL1~WL12 performing data search. The IMS array 400 of the memory device 1000 includes, for example, memory cells C11, C12, C13, C21, C22, and C23. The memory cells C11 and C21 are coupled to the bit line BL1, the memory cell C11 stores the encoded data “101100”, and the memory cell C21 stores the encoded data “101001”. When a search bias with a voltage level of “VL, VH, VL, VL, VH, VH” is input through the word lines WL1˜WL6 to represent the search data “LHLLHH”, the memory cell C11 storing the encoded data “101100” can be turned on to generate a source current Is. Moreover, when a search bias voltage with a voltage level of “VL, VH, VL, VH, VH, VL” is input through the word lines WL7˜WL12 to represent the search data “LHLHHL”, the memory cell C21 storing the encoded data “101001” can be turned on to generate a source current Is. Accordingly, the sensing circuit 300 can receive the source current Is (that is, the matching current) through the source line SL, and can judge that the code data “101100” stored in the memory cell C11 matches the search data “LHLLHH” and the code data “101001” stored in the memory cell C21 matches the search data “LHLHHL”, indicating that the search is successful.

On the other hand, the memory cell C12 and the memory cell C22 are coupled to the bit line BL2, the memory cell C12 stores the encoded data “011010”, and the memory cell C22 stores the encoded data “100110”. When the input voltage levels of the word lines WL1-WL6 are the search bias voltages of “VL, VH, VL, VL, VH, VH”, the memory cells M(1,2) and M(4,2) of the memory cell C12 cannot be turned on, so the memory cell C12 cannot provide the source current Is. When the input voltage levels of the word lines WL7-WL12 are the search bias voltages of “VL, VH, VL, VH, VH, VL”, the memory cells M(9,2) and M(12,2) of the memory cell C22 cannot be turned on, so the memory cell C22 cannot provide the source current Is. The sensing circuit 300 cannot sense the source current Is of the source line SL2, and it can be judged that the encoded data stored in the memory cells C12 and C22 do not match the search data, indicating that the search fails.

Furthermore, the memory cell C13 and the memory cell C23 are coupled to the bit line BL3. The encoded data "111111" stored in the memory cell C13 represents "random" and corresponds to any one of the binary values "0" to "19" of the original data. No matter the word lines WL1-WL6 input the search bias of the first voltage level VH or the second voltage level VL, each of the memory cells M(1,3)-M(6,3) can be turned on to generate the source current Is, so the encoded data “111111” stored in the memory cell C13 can match the search bias of the first voltage level VH or the second voltage level VL. Moreover, the encoded data "101001" stored in the memory cell C23 is the same as the memory cell C21 and matches the search data "LHLHHL" input by the word lines WL7-WL12.

FIG. 5 is a graph showing the relationship between the search bias input from the word line WLi and the threshold voltage of the memory cell M(i,j) in another embodiment of the memory device 1000 in FIG. 1 . In the embodiment of FIG. 5 , the search bias may have a "third voltage level VH2" or a "fourth voltage level VH1". The third voltage level VH2 of the search bias represents the bit of the search data “H” corresponding to the logical value “0” stored in the memory unit M(i,j). The fourth voltage level VH1 of the search bias represents the bit of the search data “L” corresponding to the logical value “1” stored in the memory unit M(i,j). The third voltage level VH2 of the search bias is greater than the fourth voltage level VH1, and the fourth voltage level VH1 is greater than the first threshold voltage H-Vt and the second threshold voltage L-Vt of the memory cell M(i,j).

When the search bias of the third voltage level VH2 matches the bit of logic value “0” stored in the memory cell M(i,j), and the logic value “0” corresponds to the first threshold voltage H-Vt, the voltage difference between the search bias of the third voltage level VH2 and the first threshold voltage H-Vt is relatively large; therefore, the memory cell M(i,j) can generate a relatively large source current Is (ie, matching current). When the search bias of the fourth voltage level VH1 matches the bit of the logic value “1” stored in the memory unit M(i,j), and the logic value “1” corresponds to the second threshold voltage L-Vt, the voltage difference between the search bias of the fourth voltage level VH1 and the second threshold voltage L-Vt is relatively large; therefore, the memory unit M(i,j) can also generate a relatively large source current Is. On the other hand, when the search bias of the fourth voltage level VH1 does not match the bit of the logic value “0” stored in the memory cell M(i,j), the voltage difference between the search bias of the fourth voltage level VH1 and the first threshold voltage H-Vt corresponding to the logic value “0” is relatively small, so the source current Is of the memory cell M(i,j) is relatively small. From the above, when the sensing circuit 300 senses a large matching current, it can be determined that the search data matches the bit of the stored data. On the contrary, if the matching current is small, it is determined that the search data does not match the bit of the storage data.

FIG. 6 is a schematic diagram of inputting the search bias (with the third voltage level VH1 or the fourth voltage level VH2 ) in FIG. 5 through the word lines WL1-WL12 in another embodiment of the memory device 1000 in FIG. 1 for data search. The encoded data stored in the memory cells C11-C23 in FIG. 6 is the same as the embodiment in FIG. 4. The input voltage levels of word lines WL1~WL6 are “VH1, VH2, VH1, VH1, VH2, VH2” to represent the search data “LHLLHH”, and the input voltage levels of word lines WL7~WL12 are “VH1, VH2, VH1, VH2, VH2, The search bias voltage VH1" represents the search data "LHLHHL". At this time, the memory cells C11 and C21 match the search data to generate the first source current Is-H with a larger current value.

On the other hand, the bits of the logic value “0” stored in the memory cells M(1,2) and M(4,2) of the memory cell C12 do not match the search bias of the fourth voltage level VH1, and the bits of the logic value “0” stored in the memory cells M(9,2) and M(12,2) of the memory cell C22 do not match the search bias of the fourth voltage level VH1, so the source line SL2 provides the second source current Is-L, the current value of the second source current Is-L less than the first source current Is-H.

Furthermore, each of the memory cells M(1,3)˜M(6,3) of the memory cell C13 stores a logic value “1” and corresponds to a random “111111”, and the memory cell C13 matches the search data to generate the first source current Is-H with a relatively large current value.

。由於9個位元的二進位數值的組合數量為512，10個位元的二進位數值的組合數量為1024，因此組合數量為924的十四層記憶胞C11b可儲存約9.5個位元的等效位元數。 FIGS. 7A-7C are schematic diagrams of memory cells C11b, C11c, and C11d in different layers of a NAND memory device, respectively. The memory cell C11b in FIG. 7A is a 14-layer memory cell, which is composed of 14 adjacent memory cells M(1,1)˜M(14,1) arranged in the same row. The data can be searched through 14 word lines WL1~WL14. The parameter N=7 of the 14-layer memory cell C11b, the number of combinations of its encoding data and search data is

. Since the combination number of 9-bit binary values is 512 and the combination number of 10-bit binary values is 1024, the fourteen-layer memory cell C11b with a combination number of 924 can store an equivalent bit number of about 9.5 bits.

而相當於45個位元的等效位元數。 The memory cell C11c in FIG. 7B is a 48-layer memory cell, which is composed of 48 memory units M(1,1)~M(48,1). The data can be searched through 48 word lines WL1~WL48. The parameter N=24 of the forty-eight-layer memory cell C11c, the number of combinations of its coding data and the number of combinations of search data are both

And the equivalent number of bits is equivalent to 45 bits.

而相當於92個位元的等效位元數。 The memory cell C11d in FIG. 7C is a 96-layer memory cell, which is composed of 96 memory units M(1,1)˜M(96,1). The data can be searched through 96 word lines WL1~WL96. The parameter N=48 of the ninety-six-layer memory cell C11d, the number of combinations of the encoded data and the number of combinations of the search data are both

And the number of bits equivalent to 92 bits.

FIG. 8 is a circuit diagram of a NAND type memory device 2000 utilizing bit line search (BL-wise search) according to an embodiment of the present disclosure. The memory device 2000 is also a NAND type memory, and the search data can be input through the bit lines BL1-BL12. 2N adjacent memory cells in the same column in the IMS array 400b of the memory device 2000 can be configured as a memory cell. Taking a six-layer memory cell with parameter N=3 as an example, the memory cells M(1,1)~M(1,6) in the first column and row 1~6 are configured as memory cell C11, and the memory cells M(1,7)~M(1,12) in the first column and row 7~12 are configured as memory cell C12, and so on.

In this embodiment, the memory device 2000 inputs the search bias voltage through the bit lines. The search bias can have a "first drain voltage level VD1" or a "second drain voltage level VD2". The first drain voltage level VD1 of the search bias represents the bit of the search data “H” corresponding to the logical value “0” stored in the memory unit M(i,j). The second drain voltage level VD2 of the search bias represents the bit of the search data “L” corresponding to the logical value “1” stored in the memory unit M(i,j). The first drain voltage level VD1 of the search bias is greater than the second drain voltage level VD2, and the second drain voltage level VD2 is approximately zero volts (the second drain voltage level VD2 can also be expressed as “0v”). Taking the memory cell C11 as an example, the input voltage level is “VD2, VD1, VD2, VD2, VD1, VD1” (that is, “0v, VD1, 0v, 0v, VD1, VD1”) through the bit lines BL1~BL6 and the search bias corresponds to the search data “LHLLHH”, and the selection voltage Vsel is input through the word line WL1 to be applied to the memory cells M(1,1)~M(1,6 ) gate. The memory cells M(1,2), M(1,5), M(1,6) are programmed to have the first threshold voltage H-Vt, so the memory cells M(1,2), M(1,5), M(1,6) cannot be turned on by the selection voltage Vsel and cannot provide the source current Is. On the other hand, the memory cells M(1,1), M(1,3), M(1,4) are programmed to have the second threshold voltage L-Vt and thus can be turned on by the selection voltage Vsel. However, the drains of the memory cells M(1,1), M(1,3), and M(1,4) receive the search bias of the second drain voltage level VD2 through the bit lines BL1, BL3, and BL4, and the second drain voltage level VD2 is approximately zero volts, so the memory cells M(1,1), M(1,3), and M(1,4) cannot provide the source current Is. From the above, when the search data “LHLLHH” input by the bit lines BL1-BL6 matches the encoded data “101100” stored in the memory cell C11, the memory cells M(1,1)-M(1,6) of the memory cell C11 cannot generate the source current Is, and the sensing amplifier (sensing amplifier, SA) 310 of the sensing circuit 300 cannot sense the source current Is.

Next, the word line WL2 inputs the selection voltage Vsel to the gates of the memory cells M(2,1)˜M(2,6) of the memory cell C21. The memory cells M(2,1), M(2,4), and M(2,6) are programmed to have the first threshold voltage H-Vt, so they cannot be turned on by the selection voltage Vsel, and cannot provide the source current Is. On the other hand, the memory cells M(2,2), M(2,3), M(2,5) are programmed to have the second threshold voltage L-Vt and can be turned on by the selection voltage Vsel, wherein the drains of the memory cells M(2,2), M(2,5) receive the search bias of the first drain voltage level VD1 from the bit line BL2, BL5, so the memory cells M(2,2), M(2,5) can generate the source current Is. From the above, when the search data “LHLLHH” input by the bit lines BL1-BL6 does not match the code data “011010” stored in the memory cell C21, the sense amplifier 310 can sense the source current Is of some of the memory cells in the memory cell C21 (ie, the memory cells M(2,2), M(2,5)).

In the embodiment of FIG. 8 , the sense amplifier 310 senses the source current Is through the source lines SL1 ˜ SL12 to determine whether the search data matches the stored code data. In other embodiments, the output of the sense amplifier 310 can also be counted, accumulated and weighted, and the matching degree between the search data and the stored code data can be analyzed.

FIG. 9 is a circuit diagram of a NOR memory device 3000 according to an embodiment of the present disclosure. Taking a four-layer memory cell with parameter N=2 as an example, the memory cell C11 includes four memory cells M(1,1)˜M(1,4) configured in a NOR type. The control terminals (for example, gate terminals) of the memory cells M(1,1)-M(1,4) are respectively coupled to the word lines WL1-WL4, and the first terminals (for example, drain terminals) of the memory cells M(1,1)-M(1,4) are commonly coupled to a match signal line (match signal line) ML1. And, match the message The signal line ML1 is coupled to the source of the pre-charge transistor MP- 1 and the sense circuit 300 .

The drain of the pre-charging transistor MP-1 is coupled to a DC voltage source or receives a DC voltage signal (not shown in the figure), and the DC voltage source or the DC voltage signal has a “first matching voltage level VM1”, so the drain of the pre-charging transistor MP-1 also has a first matching voltage level VM1. Moreover, the gate of the precharge transistor MP- 1 receives the control signal St. Before inputting the search bias for data search, the control signal St can turn on the precharge transistor MP-1 to pull up the source of the precharge transistor MP-1 to the first matching voltage level VM1, so that the matching signal line ML1 is also pulled up to the first matching voltage level VM1. After the search bias is input, the matching signal line ML1 can be maintained at the first matching voltage level VM1 or pulled-down to the “second matching voltage level VM2” according to the matching result of the search bias voltage and the stored data of the memory unit. Wherein, the first matching voltage level VM1 is greater than the second matching voltage level VM2.

In this embodiment, the search bias can be input through the word lines WL1 - WL4 . The search bias can have "first gate voltage level VS1" or "second gate voltage level VS2". The first gate voltage level VS1 of the search bias represents the search data "H" corresponding to the bit of logic value "0" stored in the memory unit M(i,j). The second gate voltage level VS2 of the search bias represents the bit of the search data “L” corresponding to the logical value “1” stored in the memory unit M(i,j). The first gate voltage level VS1 of the search bias is greater than the second gate voltage level VS2, the first gate voltage level VS1 is greater than the first threshold voltage H-Vt, and the second gate voltage level VS2 is approximately zero volts (the second gate voltage level VS2 can also be expressed as “0v”). Table 2 shows the corresponding relationship between the raw data stored in the memory cell of the memory device 3000, the coded data, the search bias voltage input by the word line, and the search data:

FIG. 10 is a timing change diagram of the voltage levels V-ML1 and V-MLn of the matching signal lines ML1 and MLn of the memory device 3000 in FIG. 9 . At the same time, see Figure 9, 10, and Table 2. The voltage level is entered through the WL1 ~ WL4 of the word line. The information "0011" ("00" corresponding to the two -bit price). The threshold voltages of the memory cells M(1,1)~M(1,4) are programmed as "H-Vt, H-Vt, L-Vt, L-Vt", and the memory cells M(1,1)~M(1,4) will not be turned on by the search bias whose voltage levels are "VS1, VS1, 0v, 0v". The voltage level V-ML1 of the matching signal line ML1 will not be pulled down to the second matching voltage level VM2 which is a lower voltage level, and the sensing circuit 300 can sense that the voltage level V-ML1 of the matching signal line ML1 is still maintained at the first matching voltage level VM1 which is a higher voltage level. Accordingly, it can be determined that the encoded data “0011” stored in the memory cell C11 matches the search data “HHLL”. Similarly, the memory cells M(1,5)-M(1,8) of the memory cell C12 will not be turned on by the search bias with the voltage levels “VS1, VS1, 0v, 0v”, so the voltage level V-ML1 of the matching signal line ML1 is still maintained at the first matching voltage level VM1.

On the other hand, the four memory cells M(n,1)~M(n,4) of the memory cell Cn1 in the nth column store the encoded data "0101", which does not match the search data "HHLL" input by the word lines WL1~WL4. Wherein, the memory cell M(n,2) is programmed to have the second threshold voltage L-Vt and can be turned on by the search bias of the first gate voltage level VS1 input from the word line WL2, so the voltage level VM-n of the matching signal line MLn can be pulled down to the second matching voltage level through the turned-on memory cell M(n,2). When the sensing circuit 300 senses that the voltage level VM-n is lower than the reference voltage Vref, it can determine that the storage data of the memory cell Cn1 does not match the search data. Similarly, the memory unit M(n,6) of the memory cell Cn2 can be turned on, and the voltage level VM-n can be pulled down to the second matching voltage level VM2 via the memory unit M(n,6).

FIG. 11 is a circuit diagram of a NOR memory device 3000b according to another embodiment of the present disclosure. The memory cells C11, C21, C31 and C41 of the memory device 3000b are respectively coupled to the matching signal lines ML1, ML2, ML3 and ML4, and each of the memory cells C11, C21, C31 and C41 is connected via the word lines WL1˜WL4 Receive seek bias. The search biases of the word lines WL1 - WL4 of the memory device 3000b can be encoded inversely. Table 3 shows the corresponding relationship between the original data stored in the memory cell of the memory device 3000b, the coded data, and the search bias voltage input by the word line, wherein the first gate voltage level VS1 of the search bias voltage in Table 2 is reversed to the second gate voltage level VS2 of the search bias voltage in Table 3 (the second gate voltage level VS2 can be expressed as "0v"), and vice versa.

FIG. 12 is a timing change diagram of the voltage levels V-ML1-V-ML4 of the matching signal lines ML1-ML4 in another embodiment of the memory device 3000b shown in FIG. Please refer to Figures 11 and 12 and Table 3 at the same time. The encoded data "1001" stored in the memory cell C11 matches the search bias voltage level "VS1, 0v, 0v, VS1". The memory cells M(1,1) and M(1,4) of the memory cell C11 have the second critical voltage L-Vt and can be turned on by the search bias voltage of the first gate voltage level VS1. Therefore, the voltage level V-ML1 of the matching signal line ML1 can pass through two memory cells that are turned on. M(1,1), M(1,4) are quickly pulled down to the second matching voltage level VM2 at the first discharge rate. The sensing circuit 300 can sense a relatively rapid drop of the voltage level V-ML1 which is smaller than the reference voltage Vref.

In addition, part of the encoded data “0011” stored in the memory cell C21 does not match the search bias voltage level of “VS1, 0v, 0v, VS1”. The memory cell M(2, 4) of the memory cell C21 has the second critical voltage L-Vt and can be turned on by the search bias voltage of the first gate voltage level VS1. Therefore, the voltage level V-ML2 of the matching signal line ML2 is pulled down to the second matching voltage level at a slower rate through only one memory cell M(2,4) at a second discharge rate, which is smaller than the first discharge rate. Similarly, part of the encoded data “0101” stored in the memory cell C31 does not match the search bias voltage level of “VS1, 0v, 0v, VS1”, and the memory cell M(3,4) of the memory cell C31 has the second threshold voltage L-Vt and can be turned on by the search bias voltage of the first gate voltage level VS1. Therefore, the voltage level V-ML3 of the matching signal line ML3 is pulled down to the second matching voltage level VM2 at a slower rate through only one memory unit M(3,4) at the second discharge rate.

On the other hand, the encoded data “0110” stored in the memory cell C41 does not match the search bias at voltage levels “VS1, 0v, 0v, VS1”, that is, each bit of the encoded data “0110” does not match the search bias at voltage levels “VS1, 0v, 0v, VS1”. The memory cells M(4,1)-M(4,4) of the memory cell C41 are not turned on, and the voltage level V-ML4 of the matching signal line ML4 remains at the first matching voltage level VM1 which is a higher voltage level.

From the above, the memory device 3000b judges the matching degree of the storage data and the search data of the memory cells C11-C41 according to the time (that is, the discharge time) when the voltage levels V-ML1-V-ML4 of the matching signal lines ML1-ML4 are pulled down to the second matching voltage level.

Moreover, in another embodiment (not shown) of the memory device 3000 in FIG. 9 , the storage data of the memory unit can be reverse-coded, as shown in Table 4. The logical value of the coded data in Table 4 and the coded data in Table 2 is reversed.

According to the memory devices of the above embodiments, the original data of M bits is encoded into 2N bits of encoded data by using the encoding mechanism, and stored in 2N memory units of one memory cell, so as to increase the density of storage content. The search bias can be input through the word line or the bit line to correspond to the search data, so as to search the encoded data stored in the NAND type or NOR type memory device. Moreover, the degree of matching between the coded data and the searched data can be judged.

Although the present invention has been disclosed above in detail with preferred embodiments and examples, it should be understood that these examples are meant to be illustrative rather than limiting. It is expected that those skilled in the art can conceive various modifications and combinations, and the various modifications and combinations fall within the spirit of the present invention and the scope of the appended patent application.

1000: memory device

100: the first drive circuit

200: the second drive circuit

300: sensing circuit

400: In-memory search (IMS) array

WL1, WL2, WL2N, WL(2N+1), WL(2N+2): word line

WL4N,WLm: word line

BL1, BL2, BLn: bit lines

SL1, SL2, SLn: source lines

1/0: logical value

Is: source current

C11, C12, C21, C22: memory cells

M(1,1), M(2,1), M(2N,1), M(2N+1,1): memory unit

M(2N+2,1), M(4N,1), M(1,2), M(2,2), M(2N,2): memory unit

M(2N+1,2), M(2N+2,2), M(4N,2): memory unit

Claims (18)

A memory device, comprising: a first drive circuit; a second drive circuit; a sensing circuit; and an internal memory search (IMS) array, including a plurality of memory cells, a plurality of word lines and a plurality of bit lines, the memory cells are configured as a plurality of horizontal columns and a plurality of vertical rows, a control terminal of each of the memory cells in the same vertical row is coupled to the first drive circuit through a corresponding one of the word lines, and the memory cells in the same vertical row are connected in series and respectively coupled through the bit lines Connected to the second driving circuit and coupled to the sensing circuit through a source line, wherein, every 2N adjacent memory cells in the same longitudinal row are configured as a memory cell, and the memory cell is used to store 2N bits of coded data to represent M bits of original data, N and M are both positive integers greater than or equal to 2, and the relationship between N and M is N=(M/2)+1, the coded data has a first coded area and a second coded area, and the first coded area includes the first coded data of the coded data bit to Nth bit, the second coding area includes the (N+1)th bit to the 2Nth bit of the coded data, the coded data has a number of coded combinations, the number of coded combinations is equal to

. The memory device according to claim 1, wherein the number of encoding combinations of the encoding data is greater than or equal to "two to the M power". The memory device as described in claim 1, wherein each of the memory cells is programmed to have a first threshold voltage to store a bit of logic value "0" in the coded data, or is programmed to have a second threshold voltage to store a bit of logic value "1" in the coded data, and the first threshold voltage is greater than the second threshold voltage. The memory device as described in claim 3, wherein the first drive circuit applies a search bias to the corresponding memory cell via one of the word lines, the search bias has a first voltage level and matches the bit of the logic value "0" in the encoded data, or the search bias has a second voltage level and matches the bit of the logic value "1" in the encoded data, wherein the first voltage level of the search bias is greater than the first threshold voltage, and the second voltage level of the search bias is lower than the first The critical voltage is greater than the second critical voltage. The memory device according to claim 4, wherein when the search bias matches the bit in the encoded data, the memory cell storing the bit generates a source current, and the sensing circuit senses the source current through the corresponding source line. The memory device according to claim 4, wherein when the coded data is 2N bits of logical value "1", the search biases applied through the word lines match the coded data. The memory device as claimed in claim 4, wherein when the search bias voltages applied through the word lines all have the first voltage level, the search bias voltages match the encoded data. The memory device as described in claim 3, wherein the first driving circuit applies a search bias to the corresponding memory cell via one of the word lines, the search bias has a third voltage level and matches the bit of the logic value "0" in the code data, or the search bias has a fourth voltage level and matches the bit of the logic value "1" in the code data, wherein the third voltage level of the search bias is greater than the fourth voltage level, and the fourth voltage level of the search bias is greater than the first threshold voltage. The memory device as described in claim 8, wherein when the search bias matches the bit in the encoded data, the memory cell storing the bit generates a first source current; when the search bias does not match the bit, the memory cell generates a second source current, the current value of the first source current is greater than the second source current, and the sensing circuit senses the first source current and the second source current through the corresponding source line. The memory device as described in claim 3, wherein the first drive circuit selects one of the horizontal columns by applying a selection voltage, and the second drive circuit applies a search bias to the corresponding memory cell of the selected horizontal column through one of the bit lines, the search bias has a first drain voltage level matching the bit of the logic value "0" in the encoded data, or the search bias has a second The drain voltage level matches the bit of logic value "1" in the encoded data, the first drain voltage level of the search bias is greater than the second drain voltage level, and the second drain voltage level is substantially equal to zero volts (0v). The memory device according to claim 10, wherein when the search bias voltage matches the bit in the encoded data, the memory cell storing the bit generates a source current, and the sensing circuit senses the source current through the corresponding source line. A memory device, comprising: a first driving circuit; a sensing circuit; and an internal memory search (IMS) array, including a plurality of memory cells, a plurality of word lines and a plurality of bit lines, the memory cells are configured as a plurality of horizontal rows and a plurality of vertical rows, a control terminal of each of the memory cells of the same horizontal row is coupled to the first driving circuit via a corresponding one of the word lines, and the memory cells of the same horizontal row are commonly coupled to the sensing circuit via a matching signal line, wherein Each 2N adjacent memory cells in the same horizontal row are configured as a memory cell, which is used to store 2N bits of coded data to represent M bits of original data, N and M are both positive integers greater than or equal to 2, and the relationship between N and M is N=(M/2)+1, the coded data has a first coded area and a second coded area, the first coded area includes the first bit to the Nth bit of the coded data, and the second coded area includes the (N+th) of the coded data 1) bit to the 2Nth bit, the encoded data has a number of encoding combinations, the number of encoding combinations is equal to

. The memory device according to claim 12, wherein the number of encoding combinations of the encoded data is greater than or equal to "two to the M power". The memory device as described in claim 12, wherein each of the memory cells is programmed to have a first threshold voltage to store a bit of logic value "0" in the coded data, or is programmed to have a second threshold voltage to store a bit of logic value "1" in the coded data, and the first threshold voltage is greater than the second threshold voltage. The memory device as described in claim 14, wherein the first driving circuit applies a search bias to the corresponding memory cell via one of the word lines, the search bias has a first gate voltage level and matches the bit of the logic value "0" in the encoded data, or the search bias has a second gate voltage level and matches the bit of the logic value "1" in the encoded data, the first gate voltage level of the search bias is greater than the second gate voltage level, the first gate The voltage level is greater than the first threshold voltage, and the second gate voltage level is approximately equal to zero volts (0v). The memory device as described in claim 15, wherein when the search bias voltage matches the bit in the encoded data, the corresponding matching signal line is maintained at a first matching voltage level, and when the search bias voltage does not match the bit, the matching signal line The line is pulled down to a second matching voltage level, the first matching voltage level is greater than the second matching voltage level. The memory device as described in claim 14, wherein the first drive circuit applies a search bias to the corresponding memory cell via one of the word lines, the search bias has a first gate voltage level matching the bit of the logic value "1" in the encoded data, or the search bias has a second gate voltage level and matches the bit of the logic value "0" in the encoded data, the first gate voltage level of the search bias is greater than the second gate voltage level, the first gate The voltage level is greater than the first threshold voltage, and the second gate voltage level is approximately equal to zero volts (0v). The memory device according to claim 17, wherein when the search bias voltage matches the bit in the encoded data, the corresponding matching signal line is pulled down to a second matching voltage level at a first discharge rate, and when the search bias voltage does not match the bit, the matching signal line is maintained at a first matching voltage level or is pulled down to the second matching voltage level at a second discharge rate, wherein the first matching voltage level is greater than the second matching voltage level, and the first discharge rate is greater than the second discharge rate.