TWI806484B - Memory device and memory operation method - Google Patents

Abstract

A memory operation method, including the following steps: using conductances of multiple first memory strings to store multiple multiplication coefficients, wherein the multiple first memory strings are electrically connected to multiple first bit lines and a common source line; receiving multiple input signals through the first bit lines, and generating an output current on the common source line according to the conductances of the first memory strings and the input signals; scaling the output current according to a correction ratio to generate a first correction current by a first correction circuit; and receiving the first correction current by an analog-digital conversion circuit, and obtaining a multiplication operation signal according to the first correction current.

Description

Memory device and memory operation method

The disclosure relates to a memory operation method, in particular to a memory device capable of performing a product operation.

With the improvement of computer computing speed, the requirements for memory speed and stability are getting higher and higher. In the case of many different market demands, how to improve the application of memory so that it can not only read and write data, but also be used as a part of calculation processing has become a major issue at present.

An aspect of the present disclosure is a memory operation method, comprising the following steps: storing a plurality of product coefficients by utilizing a plurality of conductances of a plurality of first memory series, wherein the first memory series are electrically connected to a plurality of A first bit line and a common source line; through the first bit lines, a plurality of input signals are received, and the input signals and the conductance of the first memory series generate an output on the common source line current; through the first correction circuit, the output current is scaled according to the correction ratio to generate the first correction current; and through the analog-to-digital conversion circuit, the first correction current is received, and a product operation signal is obtained according to the first correction current.

Another aspect of the disclosure is a memory device, including a memory array and a first correction circuit. The memory array includes a plurality of first memory series. A plurality of conductances of the first memory series are used to store a plurality of product coefficients. The first memory series are electrically connected to a plurality of first bit lines and a common source line for receiving a plurality of input signals through the first bit lines and generating output on the common source line current. The first correction circuit is electrically connected to the common source line, and is used for scaling the output current according to the correction ratio to generate a first correction current, wherein the first correction current is analyzed as a product operation signal.

The content of this disclosure corrects the offset current of the memory device by scaling the output current, so that the memory device can accurately identify the current distribution state from the current signal, and then obtain the correct product operation result.

Several embodiments of the present invention will be disclosed in the following figures. For the sake of clarity, many practical details will be described together in the following description. It should be understood, however, that these practical details should not be used to limit the invention. That is, in some embodiments of the present invention, these practical details are unnecessary. In addition, for the sake of simplifying the drawings, some well-known structures and components will be shown in a simple and schematic manner in the drawings.

Herein, when an element is referred to as "connected" or "coupled", it may mean "electrically connected" or "electrically coupled". "Connected" or "coupled" may also be used to indicate that two or more elements cooperate or interact with each other. In addition, although terms such as “first”, “second”, . Unless clearly indicated by the context, the terms do not imply any particular order or sequence, nor are they intended to be limiting of the invention.

《公式1》 The present disclosure relates to a memory device for performing calculations, such as performing vector-matrix multiplication. For the convenience of explanation, the method of vector-matrix multiplication (Vector-Matrix Multiplication) using the memory is illustrated in Figure 1. The following formula is an embodiment of vector-matrix multiplication:

"Formula 1"

The result of the above vector matrix multiplication includes two values O ₁ and O ₂ , if the calculation process is expanded, it is "W ₁₁ ×V ₁ +W ₂₁ ×V ₂ =O ₁ "and "W ₁₂ ×V ₁ +W ₂₂ × V ₂ =O ₂ ”. Please refer to FIG. 1 . FIG. 1 is a simplified structural diagram of a memory 100 . The memory 100 includes a plurality of memory cells 110 , and each memory cell 110 receives an input voltage through a bit line. If the conductance (reciprocal of resistance) of each memory unit 110 is regarded as the product coefficient (or weight value, W ₁₁ , W ₂₁ , W ₁₂ , W ₂₂ ) of the first matrix in "Formula 1", And the input voltage is regarded as the operation value of the second matrix in "Formula 1" (ie, V ₁ , V ₂ ). According to the characteristics of voltage, current, and conductance (V×G=I, where V is voltage, I is current, and _G is conductance), it can be known that the value O ₁ of the aforementioned vector matrix multiplication result corresponds to _two The sum of the current outputs of two memory cells 110, and the value _O2 corresponds to the sum of the current outputs of two memory cells 110 with conductances _W12 and _W22 . In other words, the memory 100 can store the product coefficient through the conductance of the memory unit 110, and utilize the characteristics of voltage, current, and conductance, so that the sum of the currents of the memory unit 110 can be used as the result of the product operation. To make the drawing simple, only four memory units 110 are shown in Fig. 1, but the present disclosure is not limited thereto. The memory 100 in Fig. 1 may contain a very large number of memory units 110, so as to increase the number of "Formula 1 "The number of elements in the first matrix and the second matrix.

FIG. 2 is a schematic diagram of a memory device 200 according to some embodiments of the present disclosure. As shown in FIG. 2 , the memory device 200 at least includes a memory array 210 , a first correction circuit 220 and an analog-to-digital conversion circuit 230 . The structure of the memory array 210 can be as shown in Figure 1, and its type can be 2D NAND Flash, 3D NAND Flash, Phase Change Memory (Phase Change Memory, PCM), variable resistance memory (Resistive RAM) or magnetic Resistive RAM (Magnetoresistive RAM), but the disclosure is not limited thereto.

FIG. 3 is a schematic diagram of a memory array 210 according to some embodiments of the present disclosure. In one embodiment, the memory array 210 is a 3D NAND memory. The memory array 210 may include a plurality of memory blocks MB (block), and each memory block MB has a plurality of memory strings (String).

Specifically, the memory array 210 includes a plurality of first memory series MS1. Each first memory series MS1 includes a plurality of first memory cells MC1. The first memory cell MC1 can be implemented by a floating gate transistor, and according to the charge amount in the floating gate, the first memory cell MC1 will have different threshold voltages. The equivalent resistance value of the first memory cell MC1 corresponds to its threshold voltage. Therefore, by setting the threshold voltage of the first memory cell MC1, the conductance value of the first memory cell MC1 can be determined.

As shown in FIG. 3, one end of the first memory series MS1 is electrically connected to a plurality of first bit lines BL1~BLn (Bit line), and the other end is electrically connected to the same common source line. CSL (Common Source line). memory array 210 through multiple source selection lines SSL (Source Select Line), a plurality of ground selection lines GSL, a plurality of bit lines BL1-BLn and a plurality of word lines WL0-WLn sequentially select and provide an input signal Vin to each first memory series MS1.

In one embodiment, the conductance value of the first memory unit MC1 represents the binary data stored in the memory unit MC1, for example, the high resistance state can be set as “0” and the low resistance state can be set as “1”. . A plurality of first memory strings MS1 corresponding to the same first bit line (for example, first bit line BL1), on which all first memory cells corresponding to the same word line (for example, word line WL0) The conductance of MC1 is used to represent/store one of the multiplication coefficients. When the first memory series MS1 in the same memory block MB receives the input signal Vin from the first bit lines BL1~BLn, it can output current to the common source as shown in the operation principle shown in Figure 1 Line CSL. The sum of the currents on the common source line CSL (hereinafter referred to as "output current I0") is the result of the product operation.

However, because the electrical characteristics of the memory unit will vary with external factors (such as: temperature, process factors or 3D structure levels), the output of the first memory series MS1 in the same memory block MB The current I0 may not be exactly equal to the correct result of the product operation. In one embodiment, the memory cell may cause current errors due to external factors, such as additional biased current. Offset currents are also more pronounced when multiple currents are added together. Therefore, the memory device 200 corrects the output current I0 output from the common source line CSL through the first calibration circuit 220 to improve the calculation error caused by the accumulation of the offset current on the common source line CSL.

The first calibration circuit 220 is electrically connected to the common source line CSL for receiving the output current, and scales the output current I0 according to a calibration ratio SF (Scaling Factor) to generate the first calibration current I1. The first correction current I1 is analyzed to generate a product operation result (referred to as a product operation signal here). The structure of the first correction circuit 220 and the analysis method of the first correction current I1 will be described in the following paragraphs.

The analog-to-digital conversion circuit 230 (eg, Analog-to-digital converter, ADC) is electrically connected to the first correction circuit 220 for receiving the first correction current I1. The analog-to-digital conversion circuit 230 is used to analyze the first analog correction current I1 to obtain the "current distribution state", and then generate a digital product operation signal. In other words, the analog-to-digital conversion circuit 230 recognizes the current distribution state therein according to the received current signal.

The "current distribution state" is used to represent the number of all the first memory cells MC1 that are turned on and whose inputs are "1" in the same memory block MB. In one embodiment, after the analog-to-digital conversion circuit 230 receives the first correction current I1 through the common source line CSL, it will identify various operating states of the corresponding memory block MB according to the current value of the first correction current I1 (i.e. , current distribution state). The "operating state" of the memory block MB is the combination of resistance states of the first memory cells MC1 (for example: how many first memory cells MC1 are in a low resistance state). Since those skilled in the art can understand the operation principle of the analog-to-digital conversion circuit 230 to identify the current distribution state, it will not be repeated here. The recording form of the current distribution state will be described in the following paragraphs with the help of diagrams.

As shown in FIG. 3, the memory array 210 selects and provides the input signal Vin through multiple source selection lines SSL, multiple ground selection lines GSL, multiple bit lines BL1~BLn, and multiple word lines WL1~WLn. To the selected first memory string MS1, therefore, the current output by the first memory string MS1 will be collected in the common source line CSL to form the output current I0. Then, the first correction current I1 output by the first correction circuit 220 will be provided to the analog-to-digital conversion circuit 230 to analyze the current distribution state, such as the wave packet of the distribution state shown in FIGS. 4A-4D .

4A-4D are schematic diagrams of waveforms of current distribution states generated by the analog-to-digital conversion circuit 230 after analyzing various current signals in some embodiments according to the present disclosure. Wherein, each waveform diagram can be divided into multiple state intervals according to multiple initial reference thresholds r1-r7, and each "state interval" represents the operation state of the memory block MB, for example: how many first A memory cell MC1 is in a low-impedance state and its input is "1". The horizontal axis is the magnitude of the current, and the vertical axis is the distribution density (Probability Density). "Distribution density" refers to the area under the curve of the first memory cell MC1 in the state interval, which can be regarded as the probability of the current appearing in the current interval.

In some embodiments, the memory device 200 further includes a reference circuit 240 . The reference circuit 240 is electrically connected to the analog-to-digital conversion circuit 230 and used to generate the initial reference current Ir. The analog-to-digital conversion circuit 230 generates initial reference thresholds r1-r7 according to multiple initial reference currents Ir to divide multiple state intervals (for example, if the initial reference current is 1, then the initial reference thresholds r1-r7 are "0, 1 , 2, 3...").

FIG. 4A is a schematic diagram of an ideal current Id under ideal conditions (ie, the output current of the first memory unit MC1 in the same column has no error). As shown in the figure, the peak value of the waveform of the ideal current Id will be accurately divided by the initial reference thresholds r1˜r7, so that different state intervals can be accurately analyzed.

FIG. 4B is a current distribution state diagram of the output current I0 under actual conditions. As shown in the figure, the current distribution state contains multiple peaks, and the peaks on the right correspond to larger currents, so the accumulated error will also be larger. FIG. 4C is a diagram showing the current distribution state of the first correction current I1. As mentioned above, since the first correction circuit 220 will scale the output current I0 (shown as enlarged in FIG. 4C ), the peaks in the current distribution state diagram will be corrected to be more corresponding to the initial reference thresholds r1˜r7 .

In some embodiments, the memory device 200 further includes a deviation estimation circuit 250 . The deviation estimation circuit 250 is electrically connected to the first correction circuit 220 for predicting the average deviation of the memory array 210 so that the first correction circuit 220 can generate the correction ratio SF according to the average deviation. The average deviation is different from the correction ratio SF. For example, the average deviation calculated by the deviation estimation circuit 250 is 5%, and the correction ratio SF can be 4% or 6%.

In some embodiments, the deviation estimation circuit 250 may include at least one sensor (such as a temperature sensor) and a processor with analog functions for detecting external factors (such as temperature) and based on Computes the current mean deviation. In other embodiments, the deviation estimation circuit 250 can be implemented by the analog-to-digital conversion circuit 230, and the high-precision analog-to-digital conversion circuit 230 can determine the received current value in advance, so as to estimate possible errors from the actual current value. For example: since the initial reference current is a preset fixed value, when the analog-to-digital conversion circuit 230 receives the initial reference thresholds r1-r7 actually generated by the reference circuit 240, the average deviation can be judged. Since there are many ways to predict the average deviation, and those skilled in the art can understand the principles of prediction, they will not be repeated here.

FIG. 5 is a flowchart of a memory operation method according to some embodiments of the present disclosure. In step S501, use the conductance storage product coefficients of multiple first memory cells MC1 (in one embodiment, multiple first memory strings MS1 corresponding to the same first bit line BL1-BL are used to record a product coefficient), and receive the input signal Vin through the first bit lines BL1-BLn to generate the output current I0 on the common source line CSL. Since those skilled in the art can understand the operation principle of the memory array 210 , it will not be repeated here.

In step S502 , through the first calibration circuit 220 , the output current I0 is scaled according to the calibration ratio SF, and the first calibration current I1 is generated. In addition, as mentioned above, the first correction circuit 220 can first obtain the average deviation corresponding to the first memory series MS1 in the same memory block MB, and then generate (determine) the correction ratio SF accordingly, so as to output The current I0 is proportionally scaled and converted into the first correction current I1.

Here, the operation of the first correction circuit 220 will be described first. FIG. 6 is a schematic diagram of a first correction circuit 220 according to some embodiments of the present disclosure. In some embodiments, the first calibration circuit 220 includes a current mirror 221 and an analog switch 222 . The current mirror 221 includes an input transistor T1 and a plurality of output transistors T2 - T6 . The input transistor T1 is electrically connected to the common source line CSL for receiving the output current I0 output by the first memory cells MC1 . The gates of the output transistors T2-T6 are all electrically connected to the gates of the input transistor T1, and the channel aspect ratio of the output transistors T2-T6 is different from that of the input transistor.

Continuing from the above, the analog switch 222 is electrically connected to the output transistors T2-T6, and is used to selectively conduct the circuit corresponding to one of the output transistors T2-T6 (for example: there are multiple circuits corresponding to the output transistors T2-T6 T6 switch) to output current through one or more of the output transistors T2-T6. According to the characteristic formula of the transistor, in the case of the same gate voltage, the magnitude of the current will correspond to the aspect ratio of the channel. Therefore, when the first correction circuit 220 confirms the correction ratio SF, it turns on the corresponding control switch of at least one of the output transistors T2 - T6 having the corresponding channel aspect ratio, so as to generate the first correction current I1 .

In other words, the ratio of the channel aspect ratio of the input transistor T1 to the channel aspect ratio of the turned-on output transistor is the calibration ratio SF. The analog switch 222 selectively controls a plurality of internal switches Ta-Te through at least one or more of the control signals Ca-Ce to generate the first calibration current I1.

For example, the correction ratio SF is 5%, the channel aspect ratio of the input transistor T1 is "X", the channel aspect ratio of the output transistor T2 is "0.4X", and the channel aspect ratio of the output transistor T3 is "0.65X", the analog switch 222 will selectively turn on the transistor T2 and the transistor T3, and gather the current to the first correction current I1, and the other output transistors will be turned off. At this time, the current output by the first correction circuit 220 is the magnitude of the current after the output current I0 is amplified by 5% (ie, 1.05 times).

As mentioned above, after receiving the first correction current I1, the analog-to-digital conversion circuit 230 will confirm the current distribution state according to the initial reference current Ir. However, as shown in FIG. 4C , since the first calibration current I1 may not completely correct the error, in some embodiments, the memory device 200 also uses the second calibration circuit 260 to adjust the initial reference current Ir. Correction.

In step S503 , the memory device 200 generates an initial reference current Ir through the reference circuit 240 and generates a second correction current I2 through the second correction circuit 260 . The initial reference current Ir and the second calibration current I2 are superimposed to form the calibration reference current Ir'.

FIG. 7 is a schematic diagram of a reference circuit 240 and a second correction circuit 260 according to some embodiments of the present disclosure. The reference circuit 240 includes a plurality of reference memory strings 241. The reference circuit 240 has preset the on or off state of each memory cell in the reference memory strings 241. These reference memory strings 241 also pass through a plurality of source selection lines. SSL', a plurality of ground selection lines GSL', a plurality of bit lines BL1'~BLn' and a plurality of word lines WL1'~WLn' are sequentially selected and provided with a reference signal Vb for the common source line CSL' Generate an initial reference current Ir on.

The common source line CSL' of the second correction circuit 260 is electrically connected to the common source line CSL'' of the reference circuit 240 for generating the second correction current I2. The second calibration current I2 is superimposed with the initial reference current Ir to become the calibration reference current Ir'.

In step S504, the analog-to-digital conversion circuit 230 receives the first correction current I1 and the correction reference current Ir', so as to adjust the initial reference thresholds r1-r7 according to the correction reference current Ir', and then generate a plurality of correction reference thresholds r1'-r7' . According to the correction reference current Ir' (calibration reference thresholds r1'˜r7'), the analog-to-digital conversion circuit 230 can analyze the current distribution state in the first correction current I1, and obtain a product operation signal.

As shown in FIG. 2, in one embodiment, the analog-to-digital conversion circuit 230 is electrically connected to the first calibration circuit 220, the reference circuit 240, and the second calibration circuit 260 to receive the first calibration current I1 and the calibration reference current. Ir'. The analog-to-digital conversion circuit 230 is used to analyze the first correction current I1 according to the correction reference current Ir' to obtain a product operation signal.

As shown in Figures 4C and 4D, after the output current I0 is adjusted to the first correction current I1 shown in Figure 4C, each state interval of the first correction current I1 still does not completely correspond to the initial reference thresholds r1-r7, Therefore, the current distribution state cannot be accurately judged. Therefore, by shifting the initial reference thresholds r1~r7 (as shown in FIG. 4D, the corrected reference thresholds r1'~r7' add a same value to the initial reference thresholds r1~r7), the A plurality of state intervals of the first correction current I1 are distinguished. Accordingly, according to the calibration reference current Ir', the current distribution state of the analyzed analog first calibration current I1 is the digital product operation signal (operation result).

As mentioned above, as shown in FIG. 7 , the second correction circuit 260 includes a plurality of second memory series MS2. The second memory series MS2 includes a plurality of second memory cells MC2. The second memory series MS2 is electrically connected to the second bit lines BLx˜Bly. These second memory series MS2 also pass through a plurality of source selection lines SSL'', a plurality of ground selection lines GSL'', a plurality of bit lines BLx-Bly and a plurality of word lines WL1''-WLn'' to drive. In some embodiments, the second memory cells MC2 in the second memory series MS2 are all kept on, and the second correction circuit 260 selectively turns on some of the second bit lines BLx-Bly to pass through some of the second bit lines BLx-Bly. The second bit lines BLx-Bly transmit calibration signals to the corresponding second memory series MS2. Accordingly, the sum of the currents output by the second memory series MS2 on the common source line CSL'' is the second calibration current I2. The second correction current I2 is used to superimpose with the initial reference current Ir, and its function is equivalent to "shifting the initial reference thresholds r1-r7", that is, the changes shown in FIGS. 4C and 4D.

Various components, method steps or technical features in the above-mentioned embodiments can be combined with each other, and are not limited by the order of description in words or presentation in drawings in the present disclosure.

Although the content of this disclosure has been disclosed above in terms of implementation, it is not intended to limit the content of this disclosure. Anyone who is skilled in this art can make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, this disclosure The scope of protection of the content shall be defined by the scope of the attached patent application.

100: Memory 110: memory unit 200: memory device 210: memory array 220: the first correction circuit 221: current mirror 222: Analog switch 230: Analog to digital conversion circuit 240: Reference circuit 241: Reference memory series 250: Bias estimation circuit 260: the second correction circuit MS1: First Memory Serial MS2: Second Memory Serial MC1: the first memory unit MC2: second memory unit BLa-BLb: bit line BL1-BLn: the first bit line BLx-BLy: Second bit line CSL: common source line CSL': common source line CSL'': common source line GSL: Ground Selection Line GSL’: ground selection line GSL'': ground selection line SSL1-SSLn: source selection lines SSL1'-SSLn': source selection line SSL1''-SSLn'': source selection line WL0-WLn: word line WL0'-WLn': word line WL0''-WLn'': word line T1: input transistor T2-T5: output transistor Vin: input signal Vb: reference signal Id: ideal current I0: output current I1: the first correction current I2: Second correction current Ir: initial reference current Ir': correction reference current r1-r7: initial reference threshold r1'-r7': correction reference threshold Ca-Ce: control signal Ta-Te: switch SF: Calibration Scale S501-S504: Steps

Figure 1 is a schematic diagram of vector-matrix multiplication using memory. FIG. 2 is a schematic diagram of a memory device according to some embodiments of the present disclosure. FIG. 3 is a schematic diagram of a memory array according to some embodiments of the present disclosure. 4A-4D are schematic diagrams of multiple current distribution states of current signals according to some embodiments of the present disclosure. FIG. 5 is a flowchart of a memory operation method according to some embodiments of the present disclosure. FIG. 6 is a schematic diagram of a first correction circuit according to some embodiments of the present disclosure. FIG. 7 is a schematic diagram of a second correction circuit according to some embodiments of the present disclosure.

Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none

S501-S504: Steps

Claims (10)

A method for operating a memory, comprising: using a plurality of conductances of a plurality of first memory strings to store a plurality of product coefficients, wherein the first memory strings are electrically connected to a plurality of first bit lines and a common source Pole line; through the first bit lines, a plurality of input signals are received, and the input signals and the conductances of the first memory series generate an output current on the common source line; through a first The correction circuit scales the output current according to a correction ratio to generate a first correction current; and receives the first correction current through an analog-to-digital conversion circuit, and obtains a product operation signal according to the first correction current. The memory operation method as described in claim 1, wherein the method of scaling the output current according to the correction ratio includes: obtaining an average deviation corresponding to the first memory strings; obtaining the correction ratio according to the average deviation, Wherein the correction ratio is different from the average deviation; and according to the correction ratio, the output current is converted into the first correction current. The memory operation method as described in claim 1, wherein the first correction circuit includes a current mirror and an analog switch, and the current mirror includes an input transistor and a plurality of output transistors, which are scaled according to the correction ratio The method of outputting current includes: receiving the output current through the input transistor; selectively generating the first correction current through at least one of the output transistors through the analog switch, wherein the input transistor The ratio of the channel aspect ratio to the channel aspect ratio of at least one of the output transistors is the calibration ratio. The memory operation method as described in claim 3, further comprising: generating an initial reference current through a reference circuit; generating a second correction current through a second correction circuit; superimposing the second correction current and the initial reference current to generate a calibration reference current; receive the first calibration current and the calibration reference current through the analog-to-digital conversion circuit; and analyze the first calibration current according to the calibration reference current to obtain the product operation signal. The memory operation method as described in claim 4, wherein the second correction circuit includes a plurality of second memory strings, and the second memory strings are electrically connected to a plurality of second bit lines, and generate the first memory strings The method for correcting the current includes: turning on a part of the second bit lines to send a plurality of correcting signals to the corresponding part of the second memory strings. A memory device, comprising: a memory array, including a plurality of first memory strings, wherein the plurality of conductances of the first memory strings are used to store a plurality of product coefficients, and the electrical properties of the first memory strings are connected to a plurality of first bit lines and a common source line, for receiving a plurality of input signals through the first bit lines, and generating an output current on the common source line; a first correction circuit , electrically connected to the common source line, for scaling the output current according to a calibration ratio to generate a first calibration current, wherein the first calibration current is analyzed as a product operation signal. The memory device as described in claim 6, wherein the first correction circuit includes a current mirror and an analog switch, and the current mirror includes: an input transistor electrically connected to the common source line for receiving the output current; and a plurality of output transistors, the gates of these output transistors are electrically connected to the gates of the input transistors, wherein the channel aspect ratio of the input transistors is the same as that of the turned-on output transistors The ratio of channel aspect ratio is the correction ratio, and at least one of the output transistors outputs the first correction current through the analog switch. The memory device according to claim 7, further comprising: a reference circuit for generating an initial reference current; a second correction circuit for generating a second correction current, wherein the second correction current is the same as the initial reference currents are summed to produce a corrected reference current flow; and an analog-to-digital conversion circuit electrically connected to the first calibration circuit, the reference circuit, and the second calibration circuit to receive the first calibration current and the calibration reference current, wherein the analog-to-digital conversion circuit is used for According to the calibration reference current, the first calibration current is analyzed to obtain the product operation signal. The memory device according to claim 8, wherein the second correction circuit includes: a plurality of second memory strings electrically connected to a plurality of second bit lines, wherein the plurality of second memory strings The memory cells are kept on, and the second memory series are used to receive a plurality of calibration signals provided by some of the second bit lines to generate the second calibration current. The memory device according to claim 6, wherein the first memory strings corresponding to the same first bit lines are used to store one of the multiplication coefficients.

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