TWI805866B - Processor to detect redundancy of page table walk - Google Patents

Abstract

A processor includes a page table walk cache that stores address translation information, and a page table walker. The page table walker fetches first output addresses indicated by first indexes of a first input address by looking up the address translation information and at least a part of page tables, and compares a matching level between second indexes of a second input address and the first indexes of the first input address with a walk cache hit level obtained by looking up the page table walk cache using the second indexes.

Description

Processors that detect page table walkthrough redundancy

The present invention relates to a processor, and more particularly to a processor configured to detect page table walk redundancy.

[CROSS-REFERENCE TO RELATED APPLICATIONS]

This patent application claims priority to U.S. Provisional Patent Application No. 62/803,227, filed with the U.S. Patent and Trademark Office on February 8, 2019, and Korean filed with the Korea Intellectual Property Office on February 26, 2019. Priority rights to patent application No. 10-2019-0022184, the disclosures of each patent application are incorporated herein by reference in their entirety.

A system on chip (hereinafter referred to as "SoC") is an integrated circuit in which multiple components of an electronic system or multiple intellectual property (IP) are integrated. The terms "intellectual property" and the abbreviation "IP" both refer to unique circuits and circuit components that are each individually protected by intellectual property. When used in the description herein, the terms and abbreviations are interchangeable with similar terms (e.g. Synonymous with "IP block" or "IP circuit"). The processor of the SoC can execute multiple application programs desired by the user, and for this purpose, the processor can exchange data with the memory device. However, since users want to execute multiple applications quickly and simultaneously, it is necessary for the processor to efficiently use the limited resources of the memory device. The processor can use virtual memory space and can manage page tables through functions including mapping information between the virtual memory space and the physical memory space of the memory device. The processor can look up the page table and can perform a translation between a virtual address in the virtual memory space and a physical address in the physical memory space.

Embodiments of the present invention provide a processor for detecting page table walkthrough redundancy.

According to an exemplary embodiment, a processor includes a page table walk cache and a page table walker. The page table walkthrough cache stores address translation information. The page table walker extracts the first output address indicated by the first index of the first input address by searching the address translation information and at least a part of the page table. The page table walker also compares the matching level with the walk cache hit level. The matching level is a matching level between the second index of the second input address and the first index of the first input address. The walkthrough cache hit level is obtained by using the second index to look up the page table walkthrough cache.

According to another exemplary embodiment, a processor includes a page table walkthrough cache and a page table walkthrough. The page table walkthrough cache stores address translation information. The page table The walkthrough extracts the first intermediate address indicated by the first index of the first input address by searching the address translation information and at least a part of the first page table of the first level. The page table walker also extracts the first index indicated by the second index of each of the first intermediate addresses by looking up the address translation information and at least a portion of a second page table of the second level. - output address. Additionally, the page table walker compares the match level to the walk cache hit level. The matching hierarchy is the fourth index of each of the second intermediate addresses indicated by the third index of the second input address and the second index of each of the first intermediate addresses. Matching hierarchy between indexes. The walkthrough cache hit level is obtained by using the fourth index to look up the page table walkthrough cache.

According to yet another exemplary embodiment, a processor includes a page table walkthrough cache and a page table walkthrough. The page table walkthrough cache stores address translation information. The page table walker extracts a first intermediate address indicated by a first index of a first input address by searching the address translation information and at least a part of the first page table of the first level. The page table walker also extracts the first index indicated by the second index of each of the first intermediate addresses by looking up the address translation information and at least a portion of a second page table of the second level. - output address. Additionally, the page table walker compares the first match level with the first walk cache hit level. The first matching level is a matching level between the third index of the second input address and the first index of the first input address. The first walkthrough cache hit level is obtained by using the third index to look up the page table walkthrough cache. Additionally, the page table walker compares the second match level with the second walk cache hit level. The second matching level is for each of the second intermediate addresses indicated by the third index of the second input address A level of matching between a fourth index and the second index of each of the first intermediate addresses. The second walkthrough cache hit level is obtained by using the fourth index to look up the page table walkthrough cache.

100: Electronic device

1000: System on Chip (SoC)

1100: Core

1100_1: the first core/core

1100_2: second core/core

1100_3: The third core/core

1100_4: fourth core/core

1110: extraction unit

1120: decoding unit

1130: Register renaming unit

1140: release/export unit

1150: Arithmetic Logic Unit (ALU)

1160: Floating point unit (FPU)

1170: branch check unit

1180:Load/store unit

1190: L2 cache

1200: Memory Management Unit (MMU)

1200_1: The first memory management unit

1200_2: Second memory management unit

1200_3: The third memory management unit

1200_4: The fourth memory management unit

1210:Transform lookaside buffer (TLB)

1220: page table walkthrough

1221: Page table walkthrough scheduler

1222: Hazard/Replay Controller

1223, 1224: walkthrough device

1225: Redundant walkthrough detector

1226:Second redundant walkthrough detector

1230: page table scan cache

1241: Transformation Table Base Register (TTBR)

1242: Virtual Transformation Table Base Register (VTTBR)

1300: cache memory

1400: busbar

2000: Main memory

AP1: Application/First Application

AP2: Application/Secondary Application

AP3: Application/Third Application

AP4: Application/Fourth Application

IA0, IA1: input address

L0, L1, L2, L3: levels

S103, S106, S109, S113, S116, S119, S123, S126, S129, S133, S136, S139, S143, S146, S203, S206, S209, S213, S216, S219, S223, S226, S229, S233, S2 36. S239, S243, S246, S249, S253, S256, S259, S263, S266, S269, S273, S276, S279: Operation

S1WC: First-level page table scan cache

S2WC: Second-level page table walkthrough cache

OS1: the first operating system

OS2: second operating system

FIG. 1 shows a block diagram of an electronic device according to an embodiment of the present invention.

FIG. 2 shows a block diagram of any one of the first to fourth cores in the SoC shown in FIG. 1 .

FIG. 3 shows the main memory and the applications and operating system executable by the SoC shown in FIG. 1 .

FIG. 4 shows the mapping between the virtual address spaces (virtual address spaces) and the physical address spaces (physical address spaces) of the application shown in FIG. 3 .

FIG. 5 shows an operation in which the page table walkthrough shown in FIG. 2 performs a page table walkthrough.

FIG. 6 shows the main memory and the applications and operating system executable by the SoC shown in FIG. 1 .

FIG. 7 shows the mapping between the virtual address space and the physical address space of the application shown in FIG. 6 .

FIGS. 8A and 8B are flow charts showing operations in which the page table walkthrough shown in FIG. 2 performs page table walkthrough based on a first stage and a second stage.

FIG. 9 shows a detailed block diagram and operation of the page table walker shown in FIG. 2 .

FIG. 10 shows another detailed block diagram and operation of the page table walker shown in FIG. 2 .

FIG. 11 shows another detailed block diagram and operation of the page table walker shown in FIG. 2 .

FIG. 12 shows another detailed block diagram and operation of the page table walker shown in FIG. 2 .

FIG. 13 shows a flowchart in which the page table walker shown in FIG. 2 performs a page table walk to convert virtual addresses into physical addresses.

14A and FIG. 14B show that the page table walkthrough shown in FIG. 2 executes the first-level page table walkthrough to transform the virtual address into an intermediate physical address and executes the second-level page table walkthrough to convert the intermediate A flow chart of the operation of converting physical address to physical address.

FIG. 1 shows a block diagram of an electronic device according to an embodiment of the present invention. The electronic device 100 may include a system on chip (SoC) 1000 and a main memory 2000 . The electronic device 100 may also be referred to as an "electronic system". For example, the electronic device 100 can be a desktop computer, a laptop computer, a workstation, a server, a mobile device, and the like. SoC 1000 may be one chip in which various (multiple different) systems are integrated, eg, on a single integrated substrate and/or eg, within an integrated housing.

The SoC 1000 can function as an application processor (application processor, AP) to control the overall operation of the electronic device 100 . The SoC 1000 may include a first core 1100_1 to a fourth core 1100_4 (each of which may also be referred to as a “processor” or a “central processing unit (CPU)”), a cache memory 1300 and a bus 1400 . Although not shown in the drawings, SoC 1000 may further include any other intellectual property (IP), such as a memory controller. Each of the first to fourth cores 1100_1 to 1100_4 can execute various software such as applications, operating industry system and/or device drivers. The numbers of the first cores 1100_1 to the fourth cores 1100_4 shown in FIG. 1 are just examples, and the SoC 1000 may include one or more homogeneous or heterogeneous cores.

The first core 1100_1 to the fourth core 1100_4 may respectively include a first memory management unit (MMU) 1200_1 to a fourth MMU 1200_4. The first MMU 1200_1 to the fourth MMU 1200_4 can convert the used virtual address into a hardware memory device (such as the cache memory 1300 in the SoC 1000, the main memory 2000 outside the SoC 1000 and/or the SoC Physical address used in auxiliary memory (not shown) other than 1000. When the first core 1100_1 to the fourth core 1100_4 respectively execute the first software to the fourth software, the first MMU 1200_1 to the fourth MMU 1200_4 can convert virtual addresses into physical addresses. The first MMU 1200_1 to the fourth MMU 1200_4 can manage address translation information (for example, a translation table) between virtual addresses and physical addresses. The first MMU 1200_1 to the fourth MMU 1200_4 can allow applications to have private (dedicated) virtual memory space, and can allow the first core 1100_1 to the fourth core 1100_4 to execute multiple tasks.

The cache memory 1300 can be respectively connected to the first core 1100_1 to the fourth core 1100_4, and can be shared by the first core 1100_1 to the fourth core 1100_4. For example, the cache memory 1300 can be implemented by using registers, flip-flops, static random access memory (static random access memory, SRAM) or a combination thereof. For the first core 1100_1 to the fourth core 1100_4 , the cache memory 1300 may have a faster access speed than the main memory 2000 . The cache memory 1300 can store data for the first core 1100_1 to the fourth core 1100_4 and/or with the first core 1100_1 to the fourth core 1100_4 Instructions, data, addresses, address conversion information, etc. associated with the fourth core 1100_4.

The bus 1400 can connect internal IPs of the SoC 1000 (such as the cores 1100_1 to 1100_4 , the cache memory 1300 , etc.), or can provide an access path to the main memory 2000 for the internal IPs of the SoC 1000 . The bus 1400 can be an Advanced Microcontroller Bus Architecture (AMBA) standard bus protocol type. The AMBA bus type can be Advanced High-Performance Bus (AHB), Advanced Peripheral Bus (APB) or Advanced Extensible Interface (AXI).

The main memory 2000 can communicate with the SoC 1000 . The main memory 2000 can provide the first core 1100_1 to the fourth core 1100_4 with a larger capacity than the cache memory 1300 . The main memory 2000 can store instructions, data, addresses, address conversion information, etc. provided by the SoC 1000 . For example, the main memory 2000 can be a dynamic random access memory (dynamic random access memory, DRAM). In an embodiment, in addition to the main memory 2000, the electronic device 100 may further include any other hardware memory devices (not shown) communicating with the SoC 1000, such as solid state drives (solid state drives, SSDs), Hard disk drive (hard disk drive, HDD) or memory card.

FIG. 2 shows a block diagram of any one of the first to fourth cores in the SoC shown in FIG. 1 . The core 1100 can be any one of the first core 1100_1 to the fourth core 1100_4 shown in FIG. 1 . The core 1100 may include a fetch unit 1110, a decode unit 1120, a register rename unit 1130, an issue/retire unit 1140, an arithmetic logic unit (arithmetic logic unit, ALU) 1150 , floating-point unit (floating-point unit, FPU) 1160 , branch check unit (branch check unit) 1170 , load/store unit 1180 , L2 cache 1190 and MMU 1200 . All components of the core 1100 (including detailed components of the MMU 1200 ) can be implemented in hardware by using analog circuits, digital circuits, logic circuits, clock circuits, flip-flops, registers, etc.

Fetch unit 1110 may fetch instructions and may store the fetched instructions in an instruction register (not shown) with reference to a memory address stored in a program counter (not shown), which tracks the instructions. memory address. For example, instructions may be stored in a memory such as cache memory (not shown) in core 1100, cache memory 1300, or main memory 2000. The decoding unit 1120 can decode the instructions stored in the instruction register, and can determine what instructions are to be executed, so that the instructions are executed. The register renaming unit 1130 can map logical registers specified by instructions into physical registers in the core 1100 . The register renaming unit 1130 can map logical registers specified by consecutive instructions into different physical registers, and can remove dependencies between instructions. Issue/extract unit 1140 may control when decoded instructions are issued (or dispatched) to the pipeline and when returned results are evicted.

The ALU 1150 may perform arithmetic, logical, or shift operations based on the dispatched instructions. The ALU 1150 can be provided with necessary operation codes and operands for operation from the memory. The FPU 1160 can perform floating point operations. The branch checking unit 1170 can check whether the branch direction of the branch instruction is predicted to improve pipeline flow. The load/store unit 1180 can execute load and store instructions, and can generate The virtual address used in the operation, and can load data from L2 cache 1190, cache memory 1300 or main memory 2000, or can store data in L2 cache 1190, cache memory 1300 or main memory Body 2000.

The MMU is a component of a core such as core 1100 . The MMU 1200 can be any one of the first MMU 1200_1 to the fourth MMU 1200_4 shown in FIG. 1 . The MMU 1200 may include a translation lookaside buffer (TLB) 1210, a page table walker 1220, a page table walkthrough cache 1230, a translation table base register (TTBR) 1241 and virtual translation Table base register (virtual translation table base register, VTTBR) 1242 . Page table walker 1220 is described below and may be implemented as a unit similar to other units of core 1100 . Page table walker 1220 may be implemented as or include a unit that performs logical operations, including operations of fetching or enabling fetching by core 1100 and operations of comparing or enabling comparison by core 1100 . Recently accessed page translations may be cached in the TLB 1210 . For each memory access performed by core 1100 , MMU 1200 may check whether a translation for a given virtual address is cached in TLB 1210 . The TLB 1210 may store a plurality of entries each divided into tags and data. For example, information for a virtual address can be in a tag, and information for a physical address can be in a data. In cases where the translation (mapping information) of the virtual address is cached in the TLB 1210 (in the case of a TLB hit), the translation is available immediately. In the case where there is no valid translation of the virtual address in the TLB 1210 (in the case of a TLB miss), the translation of the virtual address should be updated in the TLB 1210 by a page table walk, the page Table walkthrough involves searching cache memory 1300 and /or the page table stored in the main memory 2000 . The page table can be a data structure that stores the mapping between virtual addresses and physical addresses.

The page table walker 1220 may perform a page table walk for virtual addresses not found or looked up from the TLB 1210 . The page table walker 1220 may "walk" or look up the page table to translate virtual addresses into physical addresses. The page table walker 1220 can extract the address translation information about the virtual address from the page table stored in the cache memory 1300 or the main memory 2000 .

The page table walkthrough cache 1230 can cache or store partial or full address translation information of virtual addresses. For example, page tables may be structured hierarchically. The page table walker 1220 can access or search the page table sequentially, extract local address translation information from the page table, and store the extracted information in the page table walkthrough cache 1230 . In addition, the page table walker 1220 can skip accessing or looking up some page tables stored in the cache memory 1300 or the main memory 2000, and can scan the page table by looking up the previous (already) cached page table The local address translation information in 1230 is fetched to speed up the page table walkthrough.

The TTBR 1241 can store the base address indicating the page table. VTTBR 1242 may also store base addresses indicating page tables. The value of the base address stored in TTBR 1241 and VTTBR 1242 may vary with software executable by core 1100 (eg, application programs, operating systems, etc.).

FIG. 3 shows the main memory and the applications and operating system executable by the SoC shown in FIG. 1 . FIG. 4 shows the mapping between the virtual address space and the physical address space of the application shown in FIG. 3 . 3 and 4 will be described together.

Referring to FIG. 3 , the operating system may manage hardware including the SoC 1000 and the main memory 2000 and software including the application program AP1 and/or the application program AP2. The operating system can run to allow the application program AP1 and/or the application program AP2 to execute on the SoC 1000 and the main memory 2000 . The numbers of application programs AP1 and application programs AP2 shown in FIG. 3 are merely examples. Referring to FIG. 4 , when the first application program AP1 is executed, the operating system can map the virtual address (VA) space of the process into the physical address (PA) space. When executing the second application program AP2, the operating system can map the virtual address space of the process into the physical address space. By managing the above mapping, the operating system can efficiently use the limited capacity of memory installed on the hardware.

FIG. 5 shows an operation in which the page table walkthrough shown in FIG. 2 performs a page table walkthrough. The page table walker 1220 can receive the virtual address from the load/store unit 1180 . The virtual address received by the page table walker 1220 may be an address looked up in the TLB 1210 (ie, a TLB miss address). The multi-bit (eg, K bits, where "K" is a natural number) part of the virtual address can be divided into L0 index, L1 index, L2 index, L3 index and offset area. Indexes of virtual addresses can be divided according to levels L0 to L3. In addition, the page table can be divided or structured hierarchically according to levels L0 to L3. Therefore, the index can reflect the segments of the multi-bit part each having a different weight, and the page table can be arranged in a hierarchy constructed corresponding to the weights of the segments of the multi-bit part of the virtual address. In FIG. 5, the number of levels, the number of indexes, and the number of page tables are examples only. The page table walker 1220 can search the page tables hierarchically structured according to the levels L0 to L3 in sequence. Regarding the search order, "L0" can be the first level, and "L3" can be the last level.

First, the page table walker 1220 can search the entry indicated by the L0 index of the virtual address from the entries of the L0 page table indicated by the base address stored in the TTBR 1241 . The L0 page table (page table, PT) can be indexed by the L0 index. Descriptors stored in each entry may include attributes and output addresses (marked by dark shading). For example, attributes may include permission bits, access bits, dirty bits, secure bits, etc. associated with the output address. Page table walker 1220 may fetch the descriptor contained in the entry indicated by the L0 index of the virtual address, and may store or update local information of the descriptor (i.e., about the virtual bits) in page table walk cache 1230 local address translation information for the L0 index of the address).

The page table walker 1220 can freely search the entry indicated by the L1 index of the virtual address among the entries of the L1 page table indicated by the L0 output address of the descriptor extracted from the L0 page table. In other words, the page table walker 1220 may search for the entry indicated by the L1 index of the virtual address among the entries of the L1 page table indicated based on the L0 output address of the descriptor extracted from the L0 page table. Page table walker 1220 may fetch the descriptor contained in the entry indicated by the L1 index of the virtual address, and may store or update local information of the descriptor (i.e., about the virtual bits) in page table walk cache 1230 local address translation information for the L1 index of the address).

The page table walker 1220 can freely search the entry indicated by the L2 index of the virtual address among the entries of the L2 page table indicated by the L1 output address of the descriptor extracted from the L1 page table. In other words, the page table walker 1220 can automatically The entry indicated by the L2 index of the virtual address is looked up among the entries of the L2 page table indicated by the L1 output address of the descriptor. Page table walker 1220 may fetch the descriptor contained in the entry indicated by the L2 index of the virtual address, and may store or update local information for the descriptor (i.e., about the virtual bits) in page table walk cache 1230 local address translation information for the L2 index of the address).

The page table walker 1220 can freely search the entry indicated by the L3 index of the virtual address among the entries of the L3 page table indicated by the L2 output address of the descriptor extracted from the L2 page table. In other words, the page table walker 1220 may search for the entry indicated by the L3 index of the virtual address among the entries of the L3 page table indicated based on the L2 output address of the descriptor extracted from the L2 page table. Page table walker 1220 may fetch the descriptor contained in the entry indicated by the L3 index of the virtual address, and may store or update local information for the descriptor (i.e., about the virtual bits) in page table walk cache 1230 local address translation information for the L3 index of the address). In addition, since the level corresponding to the L3 index and the L3 page table is the last level, the page table walker 1220 can also store the descriptor in the TLB 1210 .

The MMU 1200 is free to look up the page indicated by the offset of the virtual address from the page indicated by the L3 output address of the descriptor extracted from the L3 page table, and can calculate the final physical address (e.g., final physical address = L3 output address + offset). In cases where the mapping (i.e., the final translation) between the virtual address and the L3 output address of the L3 page table is cached in the TLB 1210, the MMU 1200 can be cached in the TLB 1210 by using the offset and The address is output to immediately calculate the final physical address, and the final physical address may be passed back to the load/store unit 1180 .

In an embodiment, the page table walker 1220 may perform a virtual address A page table walk is performed, and a page table walk can then be performed for another virtual address. When performing a page table walk for a virtual address, local address translation information may have been stored in the page table walk cache 1230 . In cases where local address translation information for a portion of the index of another virtual address is stored in the page table walk cache 1230, the page table walker 1220 may skip fetching descriptors from a particular level. For example, in situations where local address translation information for the L0 index is already stored in the page table walkthrough cache 1230 (i.e., when a hit occurs in the page table walkthrough cache), the page table walkthrough 1220 may Skip the lookup of the L0 page table. As in the above operations at the L0 level, the page table walker 1220 can perform the remaining operations at the L1 level, L2 level, and L3 level.

FIG. 6 shows the main memory and the applications and operating system executable by the SoC shown in FIG. 1 . FIG. 7 shows the mapping between the virtual address space and the physical address space of the application shown in FIG. 6 . 6 and 7 will be explained together, and the description will focus on the differences between the embodiment based on FIGS. 6 and 7 and the embodiment based on FIGS. 3 and 4 .

Referring to FIG. 6 , the first operating system may manage hardware including the SoC 1000 and the main memory 2000 and software including the application program AP1 and/or the application program AP2. The second operating system may manage the same hardware including SoC 1000 and main memory 2000 and software including application program AP3 and/or application program AP4. There may be another software layer between the first operating system, the second operating system and the hardware, that is, a hypervisor. The hypervisor can be used to operate two or more operating systems by using limited hardware resources.

Referring to FIG. 7, when executing the first application program AP1, the first operating system OS1 can map the virtual address space of the process into an intermediate entity address (intermediate physical address, IPA) space. When executing the second application program AP2, the first operating system OS1 can also map the virtual address space of the process into an intermediate physical address space. Similarly, when the third application program AP3 is executed, the second operating system OS2 can map the virtual address space of the process into an intermediate physical address space. When executing the fourth application program AP4, the second operating system OS2 can also map the virtual address space of the process into an intermediate physical address space. Each of the first operating system OS1 and the second operating system OS2 can manage a first level of address translation between virtual addresses and intermediate physical addresses. The hypervisor can manage the second-level address translation between the intermediate physical address and the physical address. In contrast to the situation shown in FIG. 4, the use of a hypervisor in a computer system provides a second level of address translation and other capabilities among the features described above.

8A and 8B are flowcharts illustrating operations in which the page table walkthrough shown in FIG. 2 performs page table walkthrough based on the first level and the second level. 8A and 8B will be explained together. In FIG. 8A and FIG. 8B, "S", "L" and "PT" denote a level, a hierarchy and a page table, respectively. The page table walker 1220 may receive the virtual address looked up from the TLB 1210 from the load/store unit 1180 . Indexes of virtual addresses can be divided according to levels L0 to L3. The page table may be divided into a first level S1 and a second level S2, and may be divided into levels L0 to L3 in each level or structured hierarchically according to the levels L0 to L3. As described with reference to FIGS. 6 and 7 , the hypervisor can be used for virtualization. The page table walker 1220 can calculate the S1L0 intermediate physical address (IPA) (also called "intermediate address") by adding the base address stored in the TTBR 1241 to the L0 index of the virtual address ).

The page table walker 1220 can free the base address stored in the VTTBR 1242 Find the entry indicated by the L0 index of the S1L0 intermediate entity address in the entry of the indicated S2L0 page table, the descriptor contained in the entry can be extracted, and the local information of the descriptor can be stored in the page table walkthrough cache 1230 ( That is, local address translation information about the L0 index of the S1L0 intermediate physical address). The page table walker 1220 can search the entry indicated by the L1 index of the S1L0 intermediate entity address in the entry of the S2L1 page table indicated by the S2L0 output address, and can extract the descriptor contained in the entry, and can walk in the page table The lookup cache 1230 stores the local information of the descriptor (ie, the local address translation information about the L1 index of the S1L0 intermediate entity address). As in the operations associated with the S2L1 page table, the page table walker 1220 may perform operations associated with the S2L2 and S2L3 page tables indicated by the S2L1 and S2L2 output addresses, respectively. The page table walker 1220 can freely search the entry indicated by the offset of the S1L0 intermediate entity address from the entry of the S1L0 page table indicated by the S2L3 output address of the descriptor extracted from the S2L3 page table, and can extract the entries contained in the entry. descriptor, and the local information of the descriptor (ie, the local address translation information about the offset of the S1L0 intermediate physical address) can be stored in the page table walkthrough cache 1230 .

The page table walker 1220 can calculate the S1L1 intermediate physical address by adding the S1L0 output address extracted from the S1L0 page table to the L1 index of the virtual address. As in the second-level page table walkthrough performed on the S1L0 intermediate entity address, the page table walker 1220 may perform a second-level page table walkthrough on the S1L1 intermediate entity address. As in the second level of page table walkthrough performed on the S1L1 intermediate entity address, the page table walker 1220 may perform the second level on the S1L2 intermediate entity address, the S1L3 intermediate entity address, and the final intermediate entity address, respectively. The page table walkthrough. Second-level page table walkthrough instructions lookup The operations of S2L0 to S2L3 page tables and extracting descriptors, and the first-level page table scan indicates the operations of searching S1L0 to S1L3 page tables and extracting descriptors.

The page table walker 1220 can calculate the S1L0 intermediate physical address by adding the base address stored in the TTBR 1241 to the L0 index of the virtual address, and can perform a second-level page table on the S1L0 intermediate physical address walk through. The page table walker 1220 can also calculate the S1L1 intermediate physical address by adding the S1L0 output address and the L1 index of the virtual address, and can perform a second-level page table walk on the S1L1 intermediate physical address. The page table walker 1220 can additionally calculate the S1L2 intermediate physical address by adding the S1L1 output address to the L2 index of the virtual address, and can perform a second level of page table walk on the S1L2 intermediate physical address. The page table walker 1220 can further calculate the S1L3 intermediate physical address by adding the S1L2 output address to the L3 index of the virtual address, and can perform a second-level page table walk on the S1L3 intermediate physical address. In addition, the page table walker 1220 can calculate the final intermediate physical address by adding the S1L3 output address and the offset of the virtual address, and can perform a second-level page table walkthrough on the final intermediate physical address . After performing the second-level page table walk on the final intermediate entity address, the page table walker 1220 may store the last fetched descriptor in the page table walk cache 1230 . In addition, the page table walker 1220 may also store the last extracted descriptor in the TLB 1210 as the final result. The above operations of the page table walker 1220 may be called "nested walk".

The MMU 1200 is free to look up the page indicated by the offset of the virtual address from the page indicated by the S2L3 output address of the descriptor extracted from the S2L3 page table, and can obtain the physical address (e.g., the final physical bit Address = S2L3 output address + offset shift). That is, in cases where the mapping (i.e., the final translation) between virtual addresses and S2L3 output addresses is cached in the TLB 1210, the MMU 1200 can use the offset and output cached in the TLB 1210 Address to calculate the entity address immediately, and can return the entity address.

Examples are shown in FIGS. 8A and 8B as the number of levels per level is 4 and the number of levels is 2, but the teachings of the present invention are not limited thereto. For example, the number of levels of the first level may be "m" ("m" is a natural number of 1 or greater), and the number of levels of the second level may be "n" ("n" is a natural number of 1 or greater of natural numbers). In the case where the page table walker 1220 performs a page table walk for a virtual address under TLB miss and page table walk cache miss conditions, the number of descriptor fetches from the page table may be "(m+ 1)×(n+1)-1”. Of course, when the page table walkthrough device 1220 executes the first-level and second-level page table walkthroughs respectively, the page table walkthrough device 1220 can refer to the local address conversion information stored in the page table walkthrough cache 1230 Skip fetching descriptors.

9 to 11 illustrate the detailed block diagram and operation of the page table walker shown in FIG. 2 . 9 to 11 will be explained together. In FIGS. 9 to 11 , it is assumed that the page table walker performs the page table walk described with reference to FIGS. 3 to 5 .

The page table walker 1220 may include a page table walk scheduler 1221 , walkers 1223 and 1224 and a redundant walk detector 1225 . All components of the page table walker 1220 can be implemented in hardware by using analog circuits, digital circuits, logic circuits, clock circuits, flip-flops, registers, etc. In other words, whether implemented as a processor/memory combination (e.g., microprocessor/memory) for storing and executing software instructions or as an implementation The page table walker 1220 can be accurately labeled as a page table walker circuit, for example, as a logic circuit such as an ASIC. The page table walk scheduler 1221 may receive one or more input addresses (virtual addresses) that have not yet been looked up from the TLB 1210 . The page table walk scheduler 1221 can manage entries, each of which stores or includes an L0 to L3 index of an input address, a hazard bit, a hazard level bit and Hazard Identification (ID) bits. Information associated with a walkthrough request with an input address may be entered into each entry of the page table walkthrough scheduler 1221 .

Hazard/replay controller (hazard/replay controller) 1222 can check or identify the hazard bit, hazard level bit and hazard ID bit of each entry, and can input address stored in each entry or with Information associated with a walkthrough request with an input address is provided to either of the walkthroughs 1223 and 1224 . Each of walkers 1223 and 1224 may perform a page table walk on input addresses provided from page table walker 1220 and may extract output addresses. The input addresses may be virtual addresses, and each of the output addresses extracted by each of walkers 1223 and 1224 may be physical addresses. Different from the illustration in FIG. 9 , the number of walkers 1223 and 1224 can be more than 2, and the page table walker 1220 can perform 2 or more page table walks in parallel or simultaneously.

Redundant walkthrough detector 1225 may calculate input addresses of page table walkthroughs that have been determined to be performed by walkthroughs 1223 and 1224 and inputs of page table walkthroughs that have not been determined as to whether page table walkthroughs are performed consecutively The level of matching between addresses. The matching level may indicate how well the index of one input address matches the index of another input address. Since the similarity between input addresses can become higher as the matching level becomes higher, the The execution results of the respective page table walkthroughs of the input addresses may be similar to each other and may be duplicated (or redundant). The matching level may also be called "redundancy hit level". The matching level can be calculated by the redundancy walk detector 1225 , or can be calculated by the page table walk scheduler 1221 .

Redundant walkthrough detector 1225 may manage entries that store or include input addresses to walkthroughs 1223 and 1224 . For example, the input address of an entry input to page table walk scheduler 1221 may be provided to an entry of redundant walk detector 1225 without modification. The redundant walk detector 1225 may obtain and store the walk cache hit hierarchy by looking up the page table walk cache 1230 using an index of the input address stored in each of the entries. Redundant walkthrough detector 1225 may use the walkthrough cache hit level comparison (ie, match level with the index of the input address) to pre-detect and predict the page for the input address Table walkthrough redundancy. As an example of the practical implications of using a walkthrough cache hit hierarchy, this improves efficiency, avoids unnecessary power consumption, and avoids unnecessary processing when redundancy can thus be avoided. In addition, the redundant walkthrough detector 1225 may obtain and store updated when the aforementioned walkthroughs 1223 and 1224 store each output address indicated by the index of the input address respectively in the page table walkthrough cache 1230 The walkthrough cache hierarchy.

In the case where the descriptor indicated by any index has already been scheduled to be fetched from memory storing the page table or already stored in the page table walk cache 1230, this descriptor need not be fetched from memory again. The redundant scan detector 1225 can compare the match level to the scan cache hit level, and can flag dangerous bits based on the comparison result. The redundant walkthrough detector 1225 can pre-detect and predict based on the comparison results Redundancy in page table walkthroughs for incoming addresses. The redundancy of the page table walk for the input address means that by using the index of the input address that matches the index of the input address of another page table walk that has been determined to be performed, lookup Redundancy exists in at least a part of the operation of the page table. The page table walker 1220 can perform a page table walk where there is no redundancy instead of a page table walk where there is redundancy, thus improving the performance of the SoC 1000 and reducing the power consumption of the SoC 1000 . The redundant walkthrough detector 1225 can compare the matching level with the walkthrough cache level, and can clear the flagged dangerous bits based on the comparison result. A method for detecting page table walkthrough redundancy will be described more fully below.

Referring to FIG. 9 , assuming that the input addresses are respectively input to the entry 0 and the entry 1 of the page table scan scheduler 1221, the dangerous bit, the dangerous level bit and the dangerous ID bit are in the cleared state, and the previously executed The result of the page table walkthrough (ie, address translation information) is stored in entry 0 of the page table walkthrough cache 1230 . The number of entries is not limited to the examples shown in FIGS. 9 to 11 . In FIGS. 9-11 , valid bits of valid entries among the plurality of entries may be marked by "Y".

The page table walk scheduler 1221 may assign the input address IA0 input to entry 0 to the walker 1223 (which is in a waiting state), and the walker 1223 may perform a page table walk for the input address IA0. The walkthrough device 1223 can check (or determine) whether the output address indicated by the L0 index 0x12, the L1 index 0x23, the L2 index 0x34, and the L3 index 0x78 is found from the page table walkthrough cache 1230. Referring to FIG. 9 , the output address 0x100 indicated by the L0 index 0x12 has been stored in the page table walkthrough cache 1230 (the L0 level hit occurred in the page table walkthrough cache 1230 ). Redundant Walkthrough Detector 1225 can be The walkthrough cache hit level of the input address IA0 is obtained or calculated by using the L0 index 0x12, the L1 index 0x23, the L2 index 0x34 and the L3 index 0x78 of the input address IA0 to look up the page table walkthrough cache 1230. L0". In addition, when the output address 0x100 indicated by the L0 index 0x12 is stored in the page table walkthrough cache 1230, the redundant walkthrough detector 1225 can mark that the walkthrough cache level of the input address IA0 is "L0 "(Y). Since the output address 0x100 indicated by the L0 index 0x12 is already stored in the page table lookup cache 1230, the operation of fetching the output address 0x100 from the memory can be skipped. However, since the output address indicated by the L1 index 0x23 is not stored in the page table walk cache 1230 (i.e., a miss occurred in the page table walk cache 1230), the walk walker 1223 may start (start or start) fetches the output address indicated by L1 index 0x23 from the memory.

Referring to FIG. 10 , the page table walk scheduler 1221 may assign the input address IA1 input to entry 1 to the walk walker 1224 . The walker 1224 can perform a page table walkthrough for the input address IA1. The walkthrough 1224 can check whether the output address indicated by the L0 index 0x12, the L1 index 0x23, the L2 index 0x9A, and the L3 index 0xBC is found from the page table walkthrough cache 1230. Referring to FIG. 10 , the output address 0x100 indicated by the L0 index 0x12 has been stored in the page table walkthrough cache 1230 . Redundant walkthrough detector 1225 may obtain or calculate a walkthrough cache hit for input address IA1 by looking up page table walkthrough cache 1230 using L0 index 0x12, L1 index 0x23, L2 index 0x9A, and L3 index 0xBC The level is "L0". In addition, when the output address 0x100 indicated by the L0 index 0x12 is stored in the page table walkthrough cache 1230, the redundant walkthrough detector 1225 can mark that the walkthrough cache level of the input address IA1 is "L0 "(Y).

Since the output address 0x100 indicated by the L0 index 0x12 is already stored in the page table lookup cache 1230, the operation of fetching the output address 0x100 from the memory can be skipped. Since the output address indicated by the L1 index 0x23 is not stored in the page table walk cache 1230, the walker 1224 can start fetching the output address indicated by the L1 index 0x23 from the memory.

In the case where all walkers 1223 and 1224 fetch the output address indicated by L1 index 0x23 from memory, walkers 1223 and 1224 may fetch the same output address, and therefore the walkers 1223 and 1224's Operations can be redundant and can be repeated. Since walker 1223 first starts fetching the output address indicated by L1 index 0x23 from memory, the operation in which walker 1224 fetches the output address indicated by L1 index 0x23 from memory may be redundant and may for repeated. The redundancy of the page table walk-through for the input address IA1 is the operation of fetching the output address indicated by the L1 index 0x23 from the L1 page table stored in memory. Accordingly, redundancies in page table walks to be performed by walker 1224 may be predicted and/or detected to prevent redundancies.

To detect redundancy in the page table walk to be performed by walkthrough detector 1224, redundancy walkthrough detector 1225 may compare input address IA0 with input address IA1 in units of indices or levels. or hierarchies based on segments each being a different part of the input virtual address. The increase in the index level can reflect the granularity of the input virtual address, and the higher the matching degree between the current input virtual address and the existing and/or previous input virtual address, the more redundancy in the process can be avoided , as described in this article. The L0 index 0x12 and L1 index 0x23 of the input address IA1 can be compared with the input address L0 index 0x12 and L1 index 0x23 of IA0 match (equal). The redundant walkthrough detector 1225 can calculate that the matching level between the input addresses IA0 and IA1 is "L1". In addition, the redundant walkthrough detector 1225 can calculate that the walkthrough cache hit level of the different input address IA0 and input address IA1 that are compared when calculating the matching level is "L0". The redundant walkthrough detector 1225 can compare the matching level L1 between the input address IA0 and the input address IA1 with the walkthrough cache hit level L0 of the input address IA1 .

Since the match level L1 is larger (or higher) than the walk cache hit level L0, the redundant walk detector 1225 can mark the dangerous bit (Y) of entry 1 of the page table walk scheduler 1221 . The flagged hazard bit indicates that the match level L1 of the input address IA1 is greater than the walkthrough cache hit level L0 and indicates that there is redundancy in the page table walkthrough for the input address IA1 . In cases where dangerous bits are marked, the page table walk being performed in walker 1224 for input address IA1 may be cancelled. Instead, the walker 1224 may perform a page table walk for an input address stored in another entry (eg, 2, 3, or 4) of the page table walk scheduler 1221 . The redundant walkthrough detector 1225 prevents the walkthrough detector 1224 from being used redundantly. By using the walkthrough cache hit hierarchy in this way, as an example of the practical implications of using the walkthrough cache hit hierarchy, redundancy can be avoided, which in turn improves efficiency, avoids unnecessary power consumption, and avoids unnecessary processing.

In the above example, the following explanation is given: cancel the page table walk in the case where the dangerous bit is marked when the walker 1224 performs the page table walk for the input address IA1. In another embodiment, the page table walk scheduler 1221 may first check the input Whether the dangerous bit of the input address IA1 is marked, and then the input address IA1 can be provided to the scanner 1224 . In this case, the page table walk may be performed after removing the redundancy of the page table walk for the input address IA1 (ie, after the dangerous bits are cleared).

The redundant walkthrough detector 1225 can mark the dangerous level bit of entry 1 of the page table walkthrough scheduler 1221 as "1". Here, "1" indicates "L1" in the level used to construct the page table hierarchically, and is only an exemplary value. The hazard level bit may indicate the highest level of matching indices in input addresses IAO and IA1, or may indicate another level of matching indices in input addresses IA0 and IA1. The redundant walkthrough detector 1225 can mark the hazard ID of entry 1 of the page table walkthrough scheduler 1221 as "0". The hazard ID may indicate which of walkers 1223 and 1224 (walker 1223 in the above example) performs a page table walk for input address IA0 with the same index as some of input address IA1.

Referring to FIG. 11 , the walkthrough device 1223 can extract the output address 0x200 indicated by the L1 index 0x23 of the input address IA0 from the memory, and can store the output address 0x200 in the entry 1 of the page table walkthrough cache 1230 to populate entry 1. The local address translation information of the L1 index 0x23 of the input address IA0 can be stored and updated in the page table walkthrough cache 1230 . When the output address 0x200 is stored in entry 1 of the page table walkthrough cache 1230, the redundant walkthrough detector 1225 can update the walkthrough cache levels of the input address IA0 and the input address IA1 to "L1 ". For example, the walkthrough cache hit level may be calculated as the level to which the index of the input address corresponding to the most recently fetched output address belongs. Therefore, the user can be dynamically updated based on the operation of the redundant walkthrough detector 1225 Hierarchy of walkthrough caches to reduce redundancy.

Since the walkthrough level L1 of the input address IA0 is updated, the redundant walkthrough detector 1225 can match the matching level L1 of the input address IA1 with the walkthrough level L1 of the input address IA0 Compare. Since match level L1 is not greater than (i.e., the same as) walkthrough cache hit level L1, redundant walkthrough detector 1225 may clear entry 1 of page table walkthrough scheduler 1221 containing input address IA1 Hazard bit, Hazard level bit, and Hazard ID.

When the hazard bit of entry 1 is cleared, the hazard/replay controller 1222 of the page table walk scheduler 1221 can provide the input address IA1 to the walker 1224 again. The walker 1224 can look up the output addresses 0x100 and 0x200 indicated by the L0 index and the L1 index in the page table walkthrough cache 1230 , and then can start fetching the output address indicated by the L2 index from the memory. The walkthrough unit 1224 can replay or re-execute the page table walkthrough for the input address IA1.

When a hit on the L0 index occurs in the page table walk cache 1230, the lookup of the L0 page table is skipped, and the lookup of the remaining L1 to L3 page tables is performed. The scan unit 1223 extracts the output address indicated by the index of the input address IA0 by looking up the address translation information (output address 0x100) stored in the page table scan cache 1230 and at least a part of the page table. When the walkthrough 1223 extracts the output address, the redundant walkthrough detector 1225 can compare the match level between the input address IA0 and the input address IA1 with the walkthrough cache hit level of the input address IA1 comparison, and can detect redundancy in the page table walkthrough for input address IA1. The page table scan scheduler 1221 may not input the input address IA1 until the redundant scan detector 1225 clears the dangerous bit of the input address IA1 Provided to the walkthroughs 1223 and 1224.

FIG. 12 shows a detailed block diagram of the page table walker shown in FIG. 2 and the entries managed by the page table walker. In FIG. 12 , it is assumed that the page table walkthrough executes the first-level page table walkthrough and the second-level page table walkthrough described with reference to FIGS. 6 to 8B . The description will focus on the differences between the embodiment based on FIG. 12 and the embodiment based on FIGS. 9 to 11 .

The page table walker 1220 may include a redundant walkthrough detector 1225 and a second redundant walkthrough detector 1226 as a first redundant walkthrough detector. Redundant walk detector 1225, which is the first redundant walk detector, may be associated with a first level of page table walk used to translate virtual addresses into intermediate physical addresses. The second redundant walkthrough detector 1226 may be associated with a second level of page table walkthrough for translating intermediate physical addresses into physical addresses.

Like the redundancy walkthrough detector 1225 described with reference to FIGS. 9 to 11 , the first redundancy walkthrough detector can detect redundancy of the first level page table walkthrough. Redundant walkthrough detector 1225, which is a first redundant walkthrough detector, can compare the difference between an input address (virtual address) such as a current input address and another input address such as a previous input address. The first match level is compared with the first walk cache hit level obtained by using the index lookup page table walk cache 1230 of the input address. The redundant scrutiny detector 1225 as the first redundant scrutiny detector can mark the hazard bit, the first-level hazard level bit, and the hazard ID bit based on the comparison result.

Like the redundant walkthrough detector 1225 described with reference to FIGS. 9 to 11 , the second redundant walkthrough detector 1226 can detect the redundancy of the second-level page table walkthrough. The second redundant scan detector 1226 can compare a second match between an input address with another input address The hierarchy is compared to a second walkthrough cache hit hierarchy obtained by looking up the page table walkthrough cache 1230 using the index of the input address. For example, the input address may be an intermediary entity address such as a current intermediary entity address, and another input address may be another intermediary entity address such as a previous intermediary entity address. The second redundant walkthrough detector 1226 can flag the hazard bit, the second hazard level bit, and the hazard ID bit based on the comparison result. The dangerous bits marked or cleared by redundant walkthrough detector 1225 as the first redundant walkthrough detector may be the same or different from the dangerous bits marked or cleared by second redundant walkthrough detector 1226 .

The walker 1223 extracts the intermediate entity address as the output address extracted from the S1L0 to S1L3 page tables shown in FIG. 8A and FIG. 8B and indicated by the index of the input address such as the current input address. The walk-through device extracts the intermediate entity address by searching the first-level address translation information stored in the page-table walkthrough cache 1230 and at least a part of the first-level page table. When the walker 1223 extracts the intermediate entity address, the redundant walkthrough detector 1225 as the first redundant walkthrough detector can compare the first matching level with the first walkthrough cache hit level , and can detect redundancies in page table walkthroughs for incoming addresses. In addition, the walker 1223 extracts the physical address as the output address extracted from the S2L0 to S2L3 page tables shown in FIG. 8A and FIG. 8B and indicated by the index of the intermediate physical address. The walkthrough unit 1223 extracts the physical address by searching the second-level address translation information stored in the page table walkthrough cache 1230 and at least a part of the second-level page table. When the walker 1223 extracts physical addresses, the second redundant walkthrough detector 1226 can compare a second level of matching between intermediate physical addresses with a second level of walkthrough cache hits, and can Detect redundancy in page table walkthroughs for intermediate physical addresses. walk through Each of detectors 1223 and 1224 can perform a page table walk on the input address provided from page table walker 1220, and can extract an output address. For example, the input addresses may be virtual addresses, and each of the output addresses may be intermediate physical addresses. For another example, the input addresses may be intermediate physical addresses, and each of the output addresses may be physical addresses.

FIG. 13 shows a flowchart in which the page table walker shown in FIG. 2 performs a page table walk to convert virtual addresses into physical addresses, and is explained with reference to FIG. 5 . In operation S103, the page table walker 1220 may receive a dummy address (ie, an input address) after the TLB miss. The input address received by the page table walker 1220 is an address not found from the TLB 1210 . The MMU 1200 can look up the TLB 1210 by using the input address and context. For ease of illustration, the input address is shown in FIGS. 5, 8A, and 8B as including an index and an offset, but the input address may further include a context. For example, the context may be address space ID (address space ID, ASID), privilege level (privilege level), non-security, virtual machine ID (virtual machine ID, VMID) and other information.

In operation S106 , the page table walker 1220 may allocate or provide the input address and context to the page table walk (PTW) scheduler 1221 . For example, as described with reference to FIG. 9 , the input addresses may be stored in entries of the page table walker 1220 respectively.

In operation S109, the page table walk scheduler 1221 may check whether the dangerous bit of the input address is marked. When the dangerous bit is marked (S109=Yes), the page table scan scheduler 1221 may not assign the input address to the scan until the dangerous bit is cleared Devices 1223 and 1224. The page table walk for the input address may not be performed until the dangerous bits are cleared.

In operation S113, when the dangerous bit is not marked (S109=No) or cleared, the page table walk scheduler 1221 may assign the input address to any one of the walkers 1223 and 1224 (for example , an idle walker that does not perform a page table walk). In addition, the page table walk scheduler 1221 can distribute the input address to a redundant walk detector (redundant walk detector, RWD) 1225 .

In operation S116 , the walkthrough device may check whether the page table walkthrough cache 1230 stores local address translation information and all address translation information. For example, the walker can be any one of the walkers 1223 and 1224, and the partial address translation information and the full address translation information can be descriptors indicated by an index of an input address (such as a current input address), And the page table walkthrough cache 1230 may be the first level page table walkthrough cache S1WC. That is, in operation S116, the walkthrough device assigned the input address can check whether the page table walkthrough cache 1230 stores local address translation information and all address translation information associated with the input address and context Information. The walker can identify the highest level stored in the page table walkthrough cache 1230 among the first level of hierarchies of the output address indicated by the index of the input address. The walker may examine the hierarchy of the first level of the output address stored in the page table walk cache 1230 indicated by the index of the input address. When the walker searches the page table walkthrough cache 1230 , the walker may further refer to the context and the index of each of the first-level levels L0 to L3 . For example, the walker may use the context and index of the page table walk cache 1230 for entries that match the requested context and index, respectively, with local address translation information.

In operation S119, when a hit occurs in the page table walkthrough cache 1230 (S116=Yes), the walkthrough may skip fetching the output address stored in the page table walkthrough cache 1230 or indicated by the hit index operation. The walkthrough can skip extracting output addresses until the first level hit hierarchy. For example, in the case where the current input address is the input address IA1 shown in FIG. 11, the walkthrough may skip the operation of fetching the output addresses indicated by the L0 and L1 indices, respectively. The walkthrough may skip the operation of extracting the corresponding output address from the first level (eg, L0) of the first level to the hit level (eg, L1) hit in operation S116. As the hit hierarchy of the first level becomes higher, the number of page tables looked up by the walker can be reduced.

In operation S123, the redundant walkthrough detector 1225 can detect where the walkthrough fetches are not in the page table walkthrough cache 1230 by comparing the matching level with the walkthrough cache hit level Whether there is redundancy in the operation (eg, page table walk-through) of the output address indicated by the hit index. The redundant walkthrough detector 1225 can calculate the first level of matching hierarchy between the incoming address of the incomplete page table walkthrough (or any other incoming address) and the current incoming address. The match level may indicate the level of the index that matches the current input address with any other input address (eg, the match level corresponding to the risk level bit). As the matching level becomes higher, the degree to which the index of the current input address and the index of another input address match each other may be higher. The redundant walkthrough detector 1225 can calculate the highest (maximum) matching level in the matching levels as the matching level of the current input address. In addition, the redundant walkthrough detector 1225 can search the page table walkthrough cache 1230 by using the index of the current input address, and can obtain the first level walkthrough cache hit hierarchy.

In operation S126, when the matching level is higher than the walkthrough cache hit level (i.e., when redundancy is detected) (S123=Yes), the redundancy walkthrough detector 1225 may update hazard information (e.g., hazard bits, hazard levels) in entries that store or include the input address and context rank bit and hazard ID bit) so that no page table walk including redundancy is performed. The redundant walkthrough detector 1225 can flag the first-level dangerous bits for the input address. In addition, the input addresses whose dangerous bits are flagged can be deallocated from the redundant walkthrough detector 1225 . As described for operation S109 , until the flagged dangerous bits are cleared, the input address may not be allocated to the walkthroughs 1223 and 1224 and the redundant walkthrough detector 1225 . The page table walkthrough device 1220 may not provide the current input address to the walkthrough devices 1223 and 1224, may not execute the page table walkthrough for the current input address, and may cancel or stop the page table walkthrough when the page table walkthrough is being performed. .

In operation S129, when the matching level is not higher than the walkthrough cache hit level (S123=No), the walkthrough device may check whether the page table walkthrough for the input address is completed. In operation S133, when the page table walkthrough for the input address is not completed (S129=No), the walkthrough device can extract the output indicated by the index of the input address and not found from the page table walkthrough cache 1230 address. In operation S136, the walkthrough may store the extracted output address in the page table walkthrough cache 1230 (ie, the page table walkthrough cache 1230 is updated). The output addresses extracted by the walkthrough detector may also be stored in the redundant walkthrough detector 1225 (ie, the redundant walkthrough detector 1225 is updated).

In operation S139 , the redundant walkthrough detector 1225 may obtain or calculate a walkthrough cache level that is updated when the output address indicated by the index of the input address is stored in the page table walkthrough cache 1230 . The redundant walkthrough detector 1225 can be based on the walkthrough cache level of the current input address and the matching levels of the current input address and other input addresses Compare the results to clear the first-level dangerous bits of any other page table walkthrough. For example, when the walkthrough cache level reaches or is equal to the matching level, the redundant walkthrough detector 1225 may clear the dangerous bit of another input address previously input. Operation S133 and operation S136 may be repeatedly performed until it is determined in operation S129 that the page table scan is completed; as operation S133 and operation S136 are repeatedly performed, the scan cache level may gradually become higher.

When the page table walkthrough is completed (S129=Yes), in operation S143, the input address may be deallocated from the page table walkthrough scheduler 1221 and the redundant walkthrough detector 1225. In operation S146, the MMU 1200 may refer to the address translation information stored in the TLB 1210 to obtain a physical address corresponding to the virtual address (ie, the input address).

14A and FIG. 14B show that the page table walkthrough shown in FIG. 2 executes the first-level page table walkthrough to transform the virtual address into an intermediate physical address and executes the second-level page table walkthrough to convert the intermediate The flow chart of physical address conversion into physical address, these conversions are explained with reference to FIG. 8A and FIG. 8B. 14A and 14B will be explained together.

Like in operation S103, in operation S203, the page table walker 1220 may receive a dummy address (ie, an input address) after a TLB miss. Like in operation S106, in operation S206, the page table walker 1220 may allocate or provide the virtual address and the context to the page table walk scheduler 1221. Like in operation S109, in operation S209, the page table walk scheduler 1221 may check whether a dangerous bit is marked for the first level or the second level of the virtual address. As mentioned above, regarding the first level and the second level, the dangerous bits can be managed together by the redundant scrutiny detector 1225 as the first redundant scrutiny detector 1226 and the second redundant scrutiny detector 1226 . Alternatively, the first level of risk Danger bits can be managed by redundant walkthrough detector 1224 as the first redundant walkthrough detector, and second-level risk bits can be managed by second redundant walkthrough detector 1226 .

As in operation S113, in operation S213, when the dangerous bit is not marked or cleared (S209=No), the page table walkthrough scheduler 1221 may allocate virtual addresses to the walkthroughs 1223 and 1224 any one of and redundant walkthrough detector 1225 as the first redundant walkthrough detector. As in operation S116, in operation S216, the walker assigned the virtual address may check whether the page table walkthrough cache 1230 stores local address translation information and all associated virtual addresses and contexts. Address translation information. For example, the local transformation information and the whole transformation information may be descriptors indicated by the index of the virtual address, and the page table walkthrough cache 1230 may be the first level page table walkthrough cache S1WC. As in operation S119 , in operation S219 , the walkthrough may skip extracting output addresses until the hit level of the first level in operation S216 . Like in operation S123, in operation S223, the redundant walkthrough detector 1225 as the first redundant walkthrough detector may be performed by matching the walkthrough cache hit level with the matching level of the first level. The comparison detects whether there is redundancy in an operation in which the walker fetches an output address indicated by an index that is not hit in the page table walk cache 1230 (eg, a page table walk). As in operation S126, in operation S226, when the matching level of the first level is higher than the walkthrough cache hit level (S223=Yes), redundant walkthrough as the first redundant walkthrough detector The detector 1225 may flag first-level risky bits for the virtual address. The input address where the dangerous bit is marked can be deallocated from the redundant scrutiny detector 1225 as the first redundant scrutiny detector.

In operation S229, when the matching level is not greater than the walkthrough cache hit level (S223=No), the page table scan scheduler 1221 may allocate the intermediate physical address of the virtual address to the second redundant scan detector 1226 . In operation S233, the walk-through device (for example, the same as the walk-through device in operation S216) can determine whether intermediate Local address translation information for physical addresses and full address translation information (eg, descriptors indicated by indexes of intermediate physical addresses). Here, the first-level page table walkthrough cache S1WC and the second-level page table walkthrough cache S2WC can be included in the page table walkthrough cache 1230, or the first-level page table walkthrough cache S1WC and the second-level page table walkthrough cache S2WC can be implemented in the page table walkthrough cache 1230 independently. In operation S236, the walkthrough may skip the operation of extracting the output address until the hit level of the second level in operation S233.

In operation S239, the second redundant walkthrough detector 1226 may detect a situation where the walkthrough cache hit level is compared with the match level of the second level in which the walkthrough fetches the Whether there is redundancy in the operation of walking through the output address indicated by the hit index in cache 1230 (eg, page table walkthrough). The second redundant walkthrough detector 1226 can calculate a second-level matching hierarchy between the intermediate physical address of the unfinished page table walkthrough and the current intermediate physical address. The matching hierarchy may indicate the hierarchy of indices where the current intermediate entity address matches any other input address. The second redundant walkthrough detector 1226 can calculate the highest (maximum) matching level in the matching levels as the matching level of the current intermediate entity address. In addition, the second redundant walkthrough detector 1226 can search the page table walkthrough cache 1230 by using the index of the current intermediate physical address, and can obtain the second level walkthrough cache hit hierarchy. In operation S243, when the matching hierarchy of the second level When higher than the walkthrough cache hit level (S239=Yes), the second redundant walkthrough detector 1226 can mark the second-level dangerous bits for the intermediate entity address. The intermediate entity address where the dangerous bit is marked may be deallocated from the second redundant walkthrough detector 1226 .

In operation S246, when the matching level is not higher than the walkthrough cache hit level (S239=No), the walkthrough device may check whether the second-level page table walkthrough for the intermediate physical address is completed. When the page table walkthrough is not completed (S246=No), in operation S249, the walkthrough may fetch output addresses indicated by the index of the intermediate entity address and not found from the page table walkthrough cache 1230. In operation S253, the walkthrough may store the extracted output address in the page table walkthrough cache 1230 (ie, the page table walkthrough cache 1230 is updated). The output address extracted by the walkthrough detector can also be stored in the second redundant walkthrough detector 1226 (ie, the second redundant walkthrough detector 1226 is updated).

In operation S256, the second redundant walkthrough detector 1226 may obtain or calculate the walkthrough cache which is updated when the output address indicated by the index of the intermediate entity address is stored in the page table walkthrough cache 1230 Hierarchy. The second redundant walkthrough detector 1226 may flush any other pages based on a comparison of the walkthrough cache level of the current IR and the matching levels between the current IR and other IR The second level of dangerous bits in the table walkthrough. Operation S249 and operation S253 may be repeatedly performed until it is determined in operation S246 that the page table scan of the second level is completed. As operations S249 and S253 are repeatedly performed, the walkthrough cache hit level may gradually become higher.

When the page table walkthrough is completed (S246=Yes), in operation S259, the intermediate entity address may be deallocated from the second redundant walkthrough detector 1226. Thereafter, operation S263 to operation S273 may be substantially the same as operation S129 to operation S139 shown in FIG. same. When the first page table walkthrough is completed (S263=Yes), in operation S276, the input address can be sent from the page table walkthrough scheduler 1221 and the redundant walkthrough as the first redundant walkthrough detector The detector 1225 deallocates. In operation S279, the MMU 1200 may refer to the address translation information stored in the TLB 1210 to obtain a physical address corresponding to the virtual address (ie, the input address).

According to an embodiment of the present invention, redundancies in page table walkthroughs can be predicted and detected by comparing the match level with the walkthrough cache hit level. The processor can perform another page table walk where there is no redundancy, thus improving the performance of the processor and reducing power consumption.

While the teachings of the inventive concept have been made with reference to exemplary embodiments of the inventive concept described herein, it should be apparent to those of ordinary skill in the art that the invention may be made without departing from the invention described in the claims below. Various changes and modifications of the described embodiments are made within the spirit and scope of the described embodiments.

1220: page table walkthrough

1221: Page table walkthrough scheduler

1222: Hazard/Replay Controller

1223, 1224: walkthrough device

1225: Redundant walkthrough detector

1230: page table scan cache

IA0: input address

L0, L1, L2, L3: levels

Claims (17)

A processor, comprising: a page table walkthrough cache configured to store address translation information; and a page table walkthrough, wherein the page table walkthrough is configured to: by looking up the address translation information and at least a portion of the page table to extract a first output address indicated by a first index of a first input address; and combining a second index of a second input address with said first index of said first input address The matching level between is compared with the walkthrough cache hit level obtained by looking up the page table walkthrough cache using the second index, wherein based on the matching level and the walkthrough cache Taking the comparison result of the hit level, the page table walker detects in advance that the first index with the first input address in the second index using the second input address An index that matches an index has redundancy in the operation of looking up at least a portion of the page table. The processor described in claim 1, wherein each of the first input address and the second input address is a virtual address, and the first output address and the Each of the second output addresses indicated by the second index of the second input addresses is a physical address. The processor described in claim 1, wherein each of the first input address and the second input address is an intermediate address, and the first output address and the Each of the second output addresses indicated by the second index of the second input addresses is a physical address. The processor described in claim 1, wherein each of the first input address and the second input address is a virtual address, and the first output address and the Each of the second output addresses indicated by the second index of the second input address is an intermediate address. The processor described in item 1 of the scope of the patent application, wherein when it is detected that the matching level is higher than the walkthrough cache hit level, the page table walkthrough until the matching level is the same fetches from the second input address are performed at or below a walkthrough cache level that is updated when each of the first output addresses is stored in the page table walkthrough cache The second output address indicated by the second index. The processor according to claim 1, wherein when fetching the second output address indicated by the second index of the second input address, it is detected that the matching level is higher than the When the walkthrough cache hit level is specified, the page table walker stops fetching the second output address indicated by the second index until the matching level is equal to or less than that at the first Each of the output addresses is updated at the walkthrough level when stored in the page table walkthrough cache. The processor described in item 1 of the scope of the patent application, wherein the matching level is the first matching level, and wherein the page table walker is further configured to: by searching the address translation information and at least a portion of said page table to fetch a third output address indicated by a third index of a third input address; and said second output address when fetching said first output address and said third output address The second index of the input address and the first index of the third input address When the second matching level among the three indexes is greater than the first matching level, the second matching level is compared with the walkthrough cache hit level. The processor described in item 1 of the scope of the patent application, wherein the page table walk-through device includes: a page table walk-through scheduler configured to manage the first entry and the second entry, regarding the inclusion of the second entry information about a walkthrough request for an input address is entered into the first entry, information about a walkthrough request including the second input address is entered into the second entry; and a plurality of walkthroughs a register configured to extract the first output address and extract a second output address indicated by the second index of the second input address. The processor according to claim 8 of the patent application, wherein the second entry of the page table walk scheduler includes a comparison result based on the matching level and the walkthrough cache hit level And the flagged dangerous bits. The processor according to claim 9 of the patent application, wherein when the dangerous bit is marked, the page table walk-through scheduler does not add the dangerous bit to the second entry until the dangerous bit is cleared The second index of the walkthrough request included with the second input address is provided to the plurality of walkers. A processor, comprising: a page table walkthrough cache configured to store address translation information; and a page table walkthrough, wherein the page table walkthrough is configured to: by looking up the address translation information and at least part of the first level a page table to extract a first intermediate address indicated by a first index of a first input address, and to extract the first intermediate address indicated by the first index by looking up the address translation information and at least a portion of a second page table of the second stage the first output address indicated by the second index of each of the intermediate addresses; and the fourth index of each of the second intermediate addresses indicated by the third index of the second input address with the A matching level between the second index for each of the first intermediate addresses and a walkthrough hit level obtained by looking up the page table walkthrough using the fourth index comparing, and wherein said page table walker includes: a page table walk scheduler configured to manage a first entry and a second entry, with respect to a walkthrough request comprising said first input address information is input into the first entry, information about a walkthrough request including the second input address is entered into the second entry; a plurality of walkthroughs configured to extract information related to the second entry the first intermediate address and the first output address associated with an input address, and extract the second intermediate address associated with the second input address and the second intermediate address associated with the second intermediate address a second output address indicated by the fourth index of each of the addresses; and a redundant walkthrough detector configured to match the match level with the walkthrough cache hit level Compare. The processor of claim 11, wherein the walkthrough cache hierarchy is updated when each of the first output addresses is stored in the page table walkthrough cache, and When it is detected that the walkthrough cache level reaches the matching level , the page table walker performs extraction of information from each of the second intermediate addresses by looking up the address translation information and at least a portion of the second page table of the second level The second output address indicated by the fourth index. The processor according to claim 11, wherein the second entry of the page table walk scheduler includes a comparison result based on the matching level and the walkthrough cache hit level And the flagged dangerous bits. The processor according to claim 13, wherein a first walker among the plurality of walkers executes a first page table walk to extract the first intermediate address and the first output address, wherein a second walker of the plurality of walkers performs a second page table walk to extract the second intermediate address and the second output address, and wherein when the redundant The second page table walk performed by the second walker is canceled when the walkthrough detector flags the dangerous bit. The processor according to claim 13, wherein the second entry of the page table scan scheduler further includes a hazard identification bit indicating the plurality of scans The serial number of the scan device that executes extracting the first intermediate address and the first output address in the device. The processor of claim 11, wherein the matching hierarchy indicates the fourth index of each of the second intermediate addresses and each of the first intermediate addresses How well does the second index of the user match. A processor comprising: a page table walkthrough cache configured to store address translation information; and A page table walker, wherein the page table walker is configured to: extract a first index from a first input address by looking up the address translation information and at least a portion of the first page table of the first level first intermediate addresses indicated, and extracting a second index indicated by each of the first intermediate addresses by looking up the address translation information and at least a portion of a second page table of the second level first output address; combining a first matching level between a third index of a second input address and said first index of said first input address by looking up said comparing the first walkthrough cache hit levels obtained by page table walkthrough; and comparing the second intermediate addresses indicated by the third index of the second input address A second matching level between the four indexes and the second index of each of the first intermediate addresses obtained by looking up the page table walkthrough cache using the fourth index A second walkthrough cache hit level is compared, and wherein said page table walker comprises: a page table walkthrough scheduler configured to manage a first entry and a second entry, with respect to the inclusion of said second entry information about a walkthrough request for an input address is entered into the first entry, information about a walkthrough request including the second input address is entered into the second entry; a plurality of walkthroughs , configured to extract the the first intermediate address and the first output address, and extracting the second intermediate address associated with the second input address and by each of the second intermediate address a second output address indicated by the fourth index; a first redundant walkthrough detector configured to compare the first match level with the first walkthrough cache hit level; and a second redundant walkthrough detector configured to compare the second match level with the second walkthrough cache hit level.

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