TWI805820B - Neural processing system - Google Patents

Abstract

A neural processing system includes a first frontend module, a second frontend module, a first backend module, and a second backend module. The first frontend module executes a feature extraction operation using a first feature map and a first weight, and outputs a first operation result and a second operation result. The second frontend module executes the feature extraction operation using a second feature map and a second weight, and outputs a third operation result and a fourth operation result. The first backend module receives an input of the first operation result provided from the first frontend module and the fourth operation result provided from the second frontend module via a second bridge to sum up the first operation result and the fourth operation result. The second backend module receives an input of the third operation result provided from the second frontend module and the second operation result provided from the first frontend module via a first bridge to sum up the third operation result and the second operation result.

Description

neural processing system

The present disclosure relates to a neural processing system.

Deep learning refers to a type of operation based on a deep learning architecture using an algorithm set that attempts to use a deep graph with multiple processing levels in a hierarchy. graph) to model a high-level abstraction of the input data. In general, a deep learning architecture may include multiple neuron hierarchies and parameters. The Convolutional Neural Network (CNN) in the deep learning architecture is widely used in many artificial intelligence and machine learning applications, such as image classification, image caption creation (image caption creation), visual question response, and autonomous vehicles middle.

Since the CNN system includes many parameters and needs to perform many operations, such as for image classification, the CNN system has high complexity. Therefore, in order to implement the CNN system, the cost of hardware resources becomes a problem, and the power consumed by the hardware resources also becomes a problem. Specifically, in the case of CNNs implemented in recent mobile systems (eg, mobile communication devices), an architecture capable of implementing artificial intelligence while having low cost and low power consumption is required.

Various aspects of the present disclosure provide a neural network system capable of implementing artificial intelligence while having low cost and low power consumption.

However, aspects of the present disclosure are not limited to the aspects described herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by reference to the detailed description of the disclosure given below.

According to an aspect of the present disclosure, a neural processing system includes a first front-end module, a second front-end module, a first back-end module, and a second back-end module. The first front-end module performs a feature extraction operation by using the first feature map and the first weight, and outputs a first operation result and a second operation result. The second front-end module performs the feature extraction operation by using the second feature map and the second weight, and outputs a third operation result and a fourth operation result. The first back-end module receives input of the first calculation result provided from the first front-end module and the fourth calculation result provided from the second front-end module through a second bridge, and summing up the first operation result and the fourth operation result. The second back-end module receives the input of the third calculation result provided from the second front-end module and the second calculation result provided from the first front-end module through the first bridge, and summing up the third operation result and the second operation result.

According to another aspect of the present disclosure, a neural processing system includes a first neural processing unit, a bridge unit, and a second neural processing unit. The first neural processing unit includes a first front-end module and a first back-end module. The bridge unit is electrically connected to the first neural processing unit. The second NPU operates in a different clock domain than the first NPU. The first front-end module provides a part of a first operation result obtained by performing a feature extraction operation using a first feature map and a first weight to the first back-end module. The bridge unit provides a part of the result of the second operation performed in the second neural processing unit to the first backend module. The first backend module sums the part of the first operation result and the part of the second operation result.

According to another aspect of the present disclosure, a neural processing system includes a first neural processing unit, a second neural processing unit, and a workload manager. The first neural processing unit includes a first front-end module and a first back-end module. The second neural processing unit includes a second front-end module and a second back-end module. The workload manager distributes a first one of the data for performing feature extraction to the first neural processing unit, and distributes a second one of the data to the second neural processing unit. The first front-end module performs a feature extraction operation on the first data by using the first feature map and the first weight, and outputs a first operation result and a second operation result. The second front-end module performs the feature extraction operation on the second data by using the second feature map and the second weight, and outputs a third operation result and a fourth operation result. The first backend module sums the first operation result and the fourth operation result. The second backend module sums the third operation result and the second operation result.

FIG. 1 is a schematic diagram illustrating a computing system according to an embodiment of the present disclosure.

Referring to FIG. 1 , a computing system 1 according to an embodiment of the present disclosure includes a neural processing system 10 , a clock management unit 20 (clock management unit, CMU), a processor 30 and a memory 40 . The neural processing system 10 , the processor 30 and the memory 40 can transmit and receive data through the bus 90 . Neural processing system 10 may be or include one or more neural network processors that may implement, for example, a convolutional neural network (CNN) by executing instructions and processing data. However, the present disclosure is not limited thereto. That is, neural processing system 10 may alternatively be implemented by a processor that handles arbitrary vector operations, matrix operations, and the like. Neural processing system 10 may also include instructions stored therein, or may execute instructions stored in memory 40 or dynamically received from an external source. The neural processing system 10 may also include a memory that is dynamically updated during the learning process described herein, so as to update the learning content so as to dynamically update new learning. An example of a neural network processor is a graphics processing unit (GPU), although more than one processor (eg, multiple graphics processors) may be used to implement neural processing system 10 . Therefore, the neural processing system 10 used herein includes at least a neural network processor, but can also be considered to include functionally separable but interdependent software modules, functionally separable but interdependent circuits of individual circuit elements modules, data and memory specific to each module and/or unit, and other elements described herein. Meanwhile, although the neural processing system 10 is shown in FIG. 1 and explained with reference to FIG. It can be partially implemented by or using the resources of the clock management unit 20 , the processor 30 and the memory 40 .

Additionally, computing system 1 in FIG. 1 may be a computer system including one or more computing devices each including one or more processors. The processors of computing system 1 are tangible and non-transitory. The term "non-transitory" expressly disavows ephemeral properties, such as carrier waves or signals or other forms of properties that exist only temporarily anywhere at any time. Processors are articles and/or machine components. A processor of a computer system for implementing neural processing system 10 in FIG. 1 or other embodiments herein is configured to execute software instructions to carry out functions as described in various embodiments herein. The processor of a computer system can be a general-purpose processor, part of an application specific integrated circuit (ASIC), a microprocessor, a microcomputer, a processor chip, a controller, a microcontroller, or a digital signal processor (digital signal processor). processor, DSP), state machine, or programmable logic device. The processor of a computer system may also be a logic circuit including a programmable gate array (PGA) (eg, a field programmable gate array (FPGA)) or include discrete gates and/or circuits. Crystal logic is another type of circuit. The processor may also be a central processing unit (central processing unit, CPU), a graphics processing unit (GPU), or both. Additionally, any processor described herein may include multiple processors, parallel processors, or both. Multiple processors may be included in or coupled to a single device or multiple devices.

A computer system implementing the computing system 1 in FIG. 1 can implement all or part of the methods described herein. For example, functions such as feature extraction, summation, and initiation as described herein may be implemented by a computer system executing software instructions through one or more processors described herein.

In this embodiment, the neural processing system 10 may implement and/or process a neural network including multiple layers (eg, a feature extraction layer and a feature classification layer). Here, the feature extraction layer corresponds to the initial layer of the neural network and can be used, for example, to extract low-level features such as edges and gradients from the input image. On the other hand, the feature classification layer corresponds to the secondary layer of the neural network, and can be used, for example, to extract more complex and advanced features such as face, eyes, nose, etc. from the input image. To explain, the feature extraction layer can be viewed as extracting low-level features before the feature classification layer extracts more complex and high-level features. The feature classification layer corresponds to a fully-connected layer.

To extract features from an input image, the neural processing system 10 may use filters or kernels to compute input images or feature maps. For example, the neural processing system 10 may use convolution filters or convolution kernels to perform convolution operations on input images or feature maps. In addition, the neural processing system 10 may utilize weights corresponding to the feature maps to perform calculations, and the weights are determined according to the purpose of the specific implementation.

In this embodiment, it should be particularly noted that the neural processing system 10 includes a plurality of neural processing units, and the plurality of neural processing units include a first neural processing unit 100a and a second neural processing unit 100b. The first neural processing unit 100a and the second neural processing unit 100b may be implemented by physically separate neural network processors as described above, and/or by logic executed by the same or different physically separate neural network processors and/or functionally separate software module implementations. For ease of illustration, in this embodiment, the neural processing system 10 is shown as including the first neural processing unit 100a and the second neural processing unit 100b, but the scope of the present disclosure is not limited thereto. According to the purpose of the specific implementation, the neural processing system 10 may include n (herein, n is a natural number of 2 or greater than 2) neural processing units.

Using multiple neural processing units such as the first neural processing unit 100a and the second neural processing unit 100b described herein provides several real opportunities to reduce cost and/or power consumption.

The clock management unit 20 generates a first clock signal CLK1 and a second clock signal CLK2 for driving the neural processing system 10 . The clock management unit 20 provides the first clock signal CLK1 and the second clock signal CLK2 to each of the first neural processing unit 100a and the second neural processing unit 100b. Therefore, the first neural processing unit 100a is driven according to the first clock signal CLK1. The second neural processing unit 100b is driven according to the second clock signal CLK2. As explained herein, different neural processing units, such as the first neural processing unit 100a and the second neural processing unit 100b, can be selectively controlled to reduce power consumption, increase power consumption, reduce processing speed, or increase processing speed. different clocks.

In some embodiments of the present disclosure, the frequencies of the first clock signal CLK1 and the second clock signal CLK2 may be different from each other. In other words, the clock domain in which the first neural processing unit 100a operates may be different from the clock domain in which the second neural processing unit 100b operates.

The clock management unit 20 can control each frequency of the first clock signal CLK1 and the second clock signal CLK2 as required. In addition, the clock management unit 20 can also perform clock gating on the first clock signal CLK1 and the second clock signal CLK2 as required.

The processor 30 is a processor that performs general arithmetic operations, which are different from artificial intelligence operations, vector operations, matrix operations, and the like processed by the neural processing system 10 . The processor 30 may include, for example, a central processing unit (CPU), a graphics processing unit (GPU), etc., but the scope of the present disclosure is not limited thereto. In this embodiment, the processor 30 can generally control the computing system 1 .

The memory 40 can store data used when the processor 30 executes application programs or controls the computing system 1 . Memory 40 may also be used to store data for neural processing system 10, but neural processing system 10 may include its own memory for storing instructions and data. The memory 40 may be, for example, a dynamic random-access memory (Dynamic Random-Access Memory, DRAM), but the scope of the present disclosure is not limited thereto. In this embodiment, the image data to be processed by the neural processing system 10 using, for example, CNN can be stored in the memory 40 .

FIG. 2 is a block diagram illustrating a neural processing system according to an embodiment of the present disclosure.

Referring to FIG. 2 , the neural processing system 10 according to an embodiment of the present disclosure includes a first neural processing unit 100 a and a second neural processing unit 100 b. A bridge unit 110 is provided between the first neural processing unit 100a and the second neural processing unit 100b. As described above, the first neural processing unit 100a and the second neural processing unit 100b may be physically separated and functionally separated. As explained herein, use of one or more bridges, for example in bridge unit 110, enhances selective control of the first neural processing unit in a manner that reduces power consumption, increases power consumption, reduces processing speed, or increases processing speed 100a and the actual capabilities of the second neural processing unit 100b.

Firstly, the bridge unit 110 includes a first bridge 111 and a second bridge 112 . The first bridge 111 is used to transmit the intermediate result generated by the operation of the first neural processing unit 100a to the second neural processing unit 100b. The second bridge 112 is used to transmit the intermediate result generated by the operation of the second neural processing unit 100b to the first neural processing unit 100a.

For this reason, the first neural processing unit 100 a and the second neural processing unit 100 b can operate in different clock domains. In this case, the bridge unit 110 may be electrically connected to the first neural processing unit 100a and the second neural processing unit 100b operating in a different clock domain than the first neural processing unit 100a.

Therefore, when the first neural processing unit 100a and the second neural processing unit 100b operate in mutually different clock domains, the first bridge 111 and the second bridge 112 included in the bridge unit 110 are implemented as non- The bridges are synchronized so that data can be transferred between different clock domains.

In this embodiment, the first neural processing unit 100a includes a first front-end module 102a and a first back-end module 104a. The second neural processing unit 100b includes a second front-end module 102b and a second back-end module 104b. The first neural processing unit 100 a can process the first data DATA1 among the data to be processed by the neural processing system 10 . The second neural processing unit 100 b can process the second data DATA2 among the data to be processed by the neural processing system 10 . Specifically, the first front-end module 102a uses the first feature map and the first weight to perform a feature extraction operation on the first data DATA1, and outputs a first operation result R11 and a second operation result R12. In addition, the second front-end module 102b uses the second feature map and the second weight to perform a feature extraction operation on the second data DATA2, and outputs a third operation result R21 and a fourth operation result R22.

The first back-end module 104a receives the first calculation result R11 provided from the first front-end module 102a and the fourth calculation result R22 provided from the second front-end module 102b through the second bridge 112 . The first backend module 104a sums the first operation result R11 and the fourth operation result R22. On the other hand, the second back-end module 104b receives the third calculation result R21 provided from the second front-end module 102b and the second calculation result R12 provided from the first front-end module 102a through the first bridge 111 . The second backend module 104b sums the third operation result R21 and the second operation result R12.

In some embodiments of the present disclosure, the first front-end module 102a and the first back-end module 104a are driven according to the first clock signal CLK1, and the second front-end module 102b and the second back-end module 104b can be driven according to The second clock signal CLK2 having a frequency different from that of the first clock signal CLK1 is driven. That is, the first front-end module 102a and the first back-end module 104a can operate in different clock domains than the second front-end module 102b and the second back-end module 104b.

On the other hand, in this embodiment, the first back-end module 104a can provide the first write-back data WB DATA1 to the first front-end module 102a, and the second back-end module 104b can provide the second front-end module 102b Provide the second write-back data WB DATA2. The first write-back data WB DATA1 and the second write-back data WB DATA2 are input to each of the first front-end module 102a and the second front-end module 102b to allow repeated feature extraction operations.

Referring now to FIG. 3 , a more detailed structure of neural processing system 10 according to an embodiment of the present disclosure will be set forth.

FIG. 3 is a block diagram illustrating a neural processing system according to an embodiment of the present disclosure.

Referring to FIG. 3 , the first front-end module 102a included in the first neural processing unit 100a of the neural processing system 10 according to an embodiment of the present disclosure includes a plurality of first internal memories 1021a and 1022a, a plurality of first extraction units 1023a and 1024a, a plurality of first dispatch units 1025a and 1026a, and a first MAC array 1027a (multiply and accumulate array).

The first internal memory 1021a and 1022a can store the first feature map and the first weight used by the first front-end module 102a to perform feature extraction operations on the data DATA11 and DATA12. In this embodiment, the first internal memories 1021a and 1022a may be implemented as Static Random-Access Memory (SRAM), but the scope of the disclosure is not limited thereto.

The first extraction units 1023a and 1024a extract the first feature map and the first weight from each of the first internal memories 1021a and 1022a, and transmit the first feature map and the first weight to the first dispatching unit 1025a and 1026a.

The first dispatch units 1025a and 1026a transmit the extracted first feature maps and first weights to the first MAC array 1027a for each channel. For example, the first assignment units 1025a and 1026a select weights and corresponding feature maps for each of k (here, k is a natural number) channels, and may transmit the weights and corresponding feature maps to the first MAC array 1027a.

The first MAC array 1027a performs a multiply-accumulate operation on the data transmitted from the first dispatch unit 1025a and 1026a. For example, the first MAC array 1027a performs a multiply accumulate operation on the data for each of the k channels. In addition, the first MAC array 1027a outputs the first operation result R11 and the second operation result R12.

Then, as described above, the first operation result R11 is provided to the first back-end module 104a, and the second operation result R12 may be provided to the second back-end module of the second neural processing unit 100b through the first bridge 111. Group 104b.

On the other hand, the first backend module 104a included in the first neural processing unit 100a of the neural processing system 10 according to the embodiment of the present disclosure includes a first summing unit 1041a, a first starting unit 1043a and a first loop Write unit 1045a.

The first summation unit 1041a performs a summation operation on the first operation result R11 and the fourth operation result R22 to generate a summation result. Here, the fourth operation result R22 can be provided from the second front-end module 102b of the second neural processing unit 100b through the second bridge 112 .

The first activation unit 1043a may perform an activation operation on the execution result of the summation operation to generate an activation result. In some embodiments of the present disclosure, the activation operation may include an operation using an activation function (for example, a rectified linear unit (ReLU), a Sigmoid function, and a hyperbolic tangent function (tanh)), but this The scope of disclosure is not limited to this.

The first write-back unit 1045a executes a write-back operation to provide the execution result of the startup operation to the first front-end module 102a. Specifically, the first write-back unit 1045a can store the execution result of the startup operation in the first internal memories 1021a and 1022a.

On the other hand, the second front-end module 102b included in the second neural processing unit 100b of the neural processing system 10 according to an embodiment of the present disclosure includes a plurality of second internal memories 1021b and 1022b, a plurality of second extraction units 1023b and 1024b, a plurality of second dispatch units 1025b and 1026b, and a second MAC array 1027b.

The plurality of second internal memories 1021b and 1022b can store a second feature map and a second weight used by the second front-end module 102b to perform feature extraction operations on the data DATA21 and DATA22. In this embodiment, the second internal memory 1021b and 1022b can be implemented as SRAM, but the scope of the present disclosure is not limited thereto.

The second extraction units 1023b and 1024b extract the second feature map and the second weight from each of the second internal memories 1021b and 1022b, and transmit the second feature map and the second weight to the second dispatching unit 1025b and 1026b.

The second dispatch units 1025b and 1026b transmit the extracted second feature maps and second weights to the second MAC array 1027b for each channel. For example, the second assignment units 1025b and 1026b select weights and corresponding feature maps for each of k (here, k is a natural number) channels, and may transmit the weights and corresponding feature maps to the second MAC array 1027b.

The second MAC array 1027b performs a multiply-accumulate operation on the data transmitted from the second dispatch unit 1025b and 1026b. For example, the second MAC array 1027b performs a multiply-accumulate operation on the data for each of the k channels. In addition, the second MAC array 1027b outputs the third operation result R21 and the fourth operation result R22.

Then, as described above, the third operation result R21 is provided to the second back-end module 104b, and the fourth operation result R22 may be provided to the first back-end module of the first neural processing unit 100a through the second bridge 112. Group 104a.

On the other hand, the second backend module 104b included in the second neural processing unit 100b of the neural processing system 10 according to an embodiment of the present disclosure includes a second summing unit 1041b, a second starting unit 1043b and a second loop Write unit 1045b.

The second summation unit 1041b performs a summation operation on the third operation result R21 and the second operation result R12 to generate a summation result. Here, the second calculation result R12 can be provided from the first front-end module 102 a of the first neural processing unit 100 a through the first bridge 111 .

The second activation unit 1043b may perform an activation operation on the execution result of the sum operation to generate an execution result. In some embodiments of the present disclosure, activation operations may include operations using activation functions such as Rectified Linear Units (ReLU), Sigmoid functions, and hyperbolic tangent functions (tanh), although the scope of the present disclosure is not It doesn't stop there.

The second write-back unit 1045b performs a write-back operation for providing the execution result of the start-up operation to the second front-end module 102b. Specifically, the second write-back unit 1045b can store the execution result of the startup operation in the second internal memory 1021b and 1022b.

4 and 5 are block diagrams illustrating front-end modules of a neural processing system according to an embodiment of the disclosure.

Referring to FIG. 4, each of the first internal memories 1021a and 1022a stores a first feature map and a first weight for performing feature extraction operations on the data DATA11 and the data DATA12. The first extraction units 1023a and 1024a extract the first feature map and the first weight from each of the first internal memories 1021a and 1022a, and transmit the first feature map and the first weight to the first dispatching unit 1025a and 1026a.

The first allocation unit 1025a selects weights and corresponding feature maps for each of the six channels of the data DATA11, and transmits the weights and corresponding feature maps to the first MAC array 1027a. The first allocation unit 1026a selects weights and corresponding feature maps for each of the six channels of the data DATA12, and transmits the weights and corresponding feature maps to the first MAC array 1027a.

The first MAC array 1027a performs a multiply accumulate operation on the data transmitted from the first dispatch units 1025a and 1026a for each of the six lanes.

In this embodiment, the first operation result R11 among the operation results output from the first MAC array 1027a corresponds to the result of the multiplication and accumulation operation for the first channel, the third channel and the sixth channel. The second operation result R12 corresponds to the result of the multiplication and accumulation operation for the second channel, the fourth channel, and the fifth channel.

The first operation result R11 is provided to the first summation unit 1041a of the first back-end module 104a, and the second operation result R12 is provided to the first bridge 111 to be transmitted to the second Neural processing unit 100b. On the other hand, the first summation unit 1041a of the first back-end module 104a receives the operation result of the second neural processing unit 100b operating in another clock domain through the second bridge 112, for example, the fourth operation result R22 .

Next, referring to FIG. 5 , each of the second internal memories 1021 b and 1022 b stores a second feature map and a second weight for performing feature extraction operations on the data DATA21 and the data DATA22 . The second extraction units 1023b and 1024b extract the second feature map and the second weight from each of the second internal memories 1021b and 1022b, and transmit the second feature map and the second weight to the second dispatching unit 1025b and 1026b.

The second allocation unit 1025b selects weights and corresponding feature maps for each of the six channels of the data DATA21, and transmits the selected weights and corresponding feature maps to the second MAC array 1027b. The second allocation unit 1026b selects weights and corresponding feature maps for each of the six channels of the data DATA22, and transmits the selected weights and corresponding feature maps to the second MAC array 1027b.

The second MAC array 1027b performs a multiply-accumulate operation on data transmitted from the second dispatch units 1025b and 1026b for each of the six lanes.

In this embodiment, the third operation result R21 among the operation results output from the second MAC array 1027b corresponds to the result of the multiplication and accumulation operation on the second channel, the fourth channel, and the fifth channel. The fourth operation result R22 corresponds to the result of the multiplication and accumulation operation on the first channel, the third channel and the sixth channel.

The third operation result R21 is provided to the second summation unit 1041b of the second back-end module 104b, and the fourth operation result R22 is provided to the second bridge 112 to be transmitted to the first Neural processing unit 100a. On the other hand, the second summation unit 1041b of the second back-end module 104b receives the operation result of the first neural processing unit 100a operating in other clock domains through the first bridge 111, for example, the second operation result R12 .

FIG. 6 is a block diagram illustrating backend modules of a neural processing system according to an embodiment of the disclosure.

Referring to FIG. 6 , the first summation unit 1041a performs a summation operation on the first operation result R11 and the fourth operation result R22 for each channel to generate a summation result. In FIGS. 4 and 5, since the total first operation result R11 includes the values of three channels among the six channels, and the fourth operation result R22 also includes the values of three channels, the sum of each of them is performed for three channels.

Subsequently, the first start-up unit 1043a performs a start-up operation on the execution result of the sum operation of each channel to generate a start-up result, and the first write-back unit 1045a performs a start-up operation for each channel to provide the first front-end module 102a The write-back operation of the execution result. For example, the first write-back unit 1045a can write back the data corresponding to the first channel in the execution result of the startup operation to the first internal memory 1021a, and can write back the data corresponding to the second channel and the third channel Write back to the first internal memory 1022a.

On the other hand, the second summation unit 1041b also performs a summation operation on the third operation result R21 and the second operation result R12 for each channel to generate a summation result. In FIGS. 4 and 5, since the total third operation result R21 includes the values of three channels among the six channels, and the second operation result R12 also includes the values of three channels, the sum of each of them is performed for three channels.

Subsequently, the second activation unit 1043b performs an activation operation on the execution result of the sum operation of each channel to generate an activation result. The second write-back unit 1045b performs a write-back operation for providing the execution result of the startup operation to the second front-end module 102b for each channel. For example, the second write-back unit 1045b can write back the data corresponding to the first channel in the execution result of the startup operation to the second internal memory 1021b, and can write back the data corresponding to the second channel and the third channel Write back to the second internal memory 1022b.

FIG. 7 is a schematic diagram illustrating a computing system according to another embodiment of the present disclosure, and FIG. 8 is a block diagram illustrating a neural processing system according to another embodiment of the present disclosure.

Referring to FIG. 7 and FIG. 8 , different from the embodiment shown in FIG. 1 , the neural processing system 10 of the computing system 2 according to this embodiment further includes a workload manager 120 . As explained herein, use of a workload manager such as workload manager 120 enhances selective control of neural processing units in multiple neural processing units in a manner that reduces power consumption, increases power consumption, reduces processing speed, or increases processing speed. The actual capabilities of individual neural processing units.

The workload manager 120 distributes the first data DATA1 among the data DATA for performing feature extraction to the first neural processing unit 100a. The workload manager 120 distributes the second data DATA2 in the data DATA to the second neural processing unit 100b. Specifically, the workload manager 120 distributes the first data DATA1 of the data DATA used for feature extraction to the first front-end module 102a, and distributes the second data DATA2 of the data DATA to the second front-end module 102b.

Therefore, the first front-end module 102a performs a feature extraction operation on the first data DATA1 by using the first feature map and the first weight. The second front-end module 102b can use the second feature map and the second weight to perform a feature extraction operation on the second data DATA2.

Specifically, in some embodiments of the present disclosure, the amount of the first data DATA1 and the amount of the second data DATA2 may be different from each other.

The clock management unit 20 controls the frequency of at least one of the first clock signal CLK1 and the second clock signal CLK2, and can control the first neural processing unit 100a and the second neural processing unit 100a according to the allocation operation of the workload manager 120 Performance and power of unit 100b. For example, the clock management unit 20 can perform operations on the first front-end module 102a, the first back-end module 104a, the second front-end module 102b, and the second back-end module 104b according to the allocation operation of the workload manager 120. At least one of the performs clock gating.

In this way, the neural processing system 10 according to various embodiments of the present disclosure can control the clock signals of the first neural processing units 100a and the second neural processing units 100b therein to control performance or power consumption. For example, in order to improve the performance of the first neural processing unit 100a and reduce the power consumption of the second neural processing unit 100b, the clock management unit 20 may increase the first clock signal CLK1 for driving the first neural processing unit 100a frequency and can reduce the frequency of the second clock signal CLK2 for driving the second neural processing unit 100b. As another example, in a specific case where only the first neural processing unit 100a is used and the second neural processing unit 100b is not used, it may be performed by controlling the second clock signal CLK2 for driving the second neural processing unit 100b Clock gating. Therefore, according to a computing system including the neural processing system 10 according to various embodiments of the present disclosure, artificial intelligence can be realized while reducing cost and power consumption.

FIG. 9 is a schematic diagram illustrating a computing system according to yet another embodiment of the present disclosure, and FIG. 10 is a block diagram illustrating a neural processing system according to another embodiment of the present disclosure.

Referring to FIG. 9 and FIG. 10 , different from the embodiments shown in FIG. 7 and FIG. 8 , the computing system 3 according to this embodiment further includes a power management unit 50 (power management unit, PMU). As explained herein, the use of a power management unit such as power management unit 50 enhances selective control of individual neural processing units in multiple neural processing units in a manner that reduces power consumption, increases power consumption, reduces processing speed, or increases processing speed. The actual capability of the processing unit's power.

As described above, the workload manager 120 allocates the first data DATA1 of the data DATA for performing feature extraction to the first front-end module 102a, and distributes the second data DATA2 of the data DATA to the second front-end module 102b .

Therefore, the first front-end module 102a can use the first feature map and the first weight to perform a feature extraction operation on the first data DATA1. The second front-end module 102b can use the second feature map and the second weight to perform a feature extraction operation on the second data DATA2.

The power management unit 50 provides a first power gating signal PG1 to the first neural processing unit 100a, and provides a second power gating signal PG2 to the second neural processing unit 100b. Specifically, the power management unit 50 can provide the first power gating signal PG1 to the first front-end module 102a and the first back-end module 104a. The power management unit 50 can provide the second power gating signal PG2 to the second front-end module 102b and the second back-end module 104b.

The power management unit 50 may control at least one value of the first power gating signal PG1 and the second power gating signal PG2 , thereby executing the first neural processing unit 100 a and the second neural processing unit 100 a and the second neural processing unit 100 a in response to the allocation operation of the workload manager 120 . Power control of the processing unit 100b. For example, the power management unit 50 can perform power gating on at least one of the first front-end module 102a, the first back-end module 104a, the second front-end module 102b, and the second back-end module 104b.

In this way, the neural processing system 10 according to various embodiments of the present disclosure may perform power gating on at least a part of the first neural processing unit 100a and the second neural processing unit 100b as required, thereby reducing the power of the neural processing system 10. consumption. Therefore, according to a computing system including the neural processing system 10 according to various embodiments of the present disclosure, artificial intelligence can be realized while reducing cost and power consumption.

FIG. 11 is a schematic diagram illustrating a computing system according to another embodiment of the present disclosure.

Referring to FIG. 11 , the computing system 4 according to the present embodiment includes a first neural processing unit 100a, a second neural processing unit 100b, a third neural processing unit 100c, and a fourth neural processing unit 100d. For ease of explanation, in this embodiment, the neural processing system 10 is shown as including a first neural processing unit 100a, a second neural processing unit 100b, a third neural processing unit 100c, and a fourth neural processing unit 100d, but the present disclosure The scope is not limited to this.

The clock management unit 20 generates a first clock signal CLK1 , a second clock signal CLK2 , a third clock signal CLK3 and a fourth clock signal CLK4 for driving the neural processing system 10 . The clock management unit 20 provides a clock signal to each of the first neural processing unit 100a, the second neural processing unit 100b, the third neural processing unit 100c and the fourth neural processing unit 100d. Therefore, the first neural processing unit 100a is driven according to the first clock signal CLK1. The second neural processing unit 100b is driven according to the second clock signal CLK2. The third neural processing unit 100c is driven according to the third clock signal CLK3. The fourth neural processing unit 100d is driven according to the fourth clock signal CLK4.

In some embodiments of the present disclosure, the frequencies of the first clock signal CLK1 , the second clock signal CLK2 , the third clock signal CLK3 and the fourth clock signal CLK4 may not all be the same. In other words, the clock domains in which the first neural processing unit 100a, the second neural processing unit 100b, the third neural processing unit 100c, and the fourth neural processing unit 100d operate may not be the same.

The clock management unit 20 can control each frequency of the first clock signal CLK1 , the second clock signal CLK2 , the third clock signal CLK3 and the fourth clock signal CLK4 as required. In addition, the clock management unit 20 may also perform clock gating on at least one of the first clock signal CLK1 , the second clock signal CLK2 , the third clock signal CLK3 and the fourth clock signal CLK4 as required.

12 and 13 are block diagrams illustrating a neural processing system according to yet another embodiment of the present disclosure.

Referring to FIG. 12, the neural processing system 10 according to the present embodiment includes first to fourth neural processing units 100a to 100d. One or more bridges 1112 , 1113 and 1114 are disposed between the first neural processing unit 100 a to the fourth neural processing unit 100 d.

In this embodiment, the third neural processing unit 100c includes a third front-end module 102c and a third back-end module 104c. The fourth neural processing unit 100d includes a fourth front-end module 102d and a fourth back-end module 104d. The third neural processing unit 100c can process the third data DATA3 among the data to be processed by the neural processing system 10 . The fourth neural processing unit 100d can process the fourth data DATA4 among the data to be processed by the neural processing system 10 .

The bridge 1112 transmits the intermediate result R12 generated by the operation of the first neural processing unit 100a to the second neural processing unit 100b. The bridge 1113 transmits the intermediate result R13 generated by the operation of the first neural processing unit 100a to the third neural processing unit 100c. In addition, the bridge 1114 transmits the intermediate result R14 generated by the operation of the first neural processing unit 100a to the fourth neural processing unit 100d.

For this reason, the first neural processing unit 100 a and the second neural processing unit 100 b can operate in different clock domains. In this case, the bridge 1112 may be electrically connected to the first NPU 100a and the second NPU 100b operating in a different clock domain than the first NPU 100a. Similarly, the bridge 1113 may be electrically connected to the first NPU 100a and the third NPU 100c operating in a different clock domain than the first NPU 100a. The bridge 1114 may be electrically connected to the first NPU 100a and the fourth NPU 100d operating in a different clock domain than the first NPU 100a.

Therefore, bridges 1112, 1113, and 1114 are implemented as asynchronous bridges to enable data transfer between different clock domains.

Subsequently, referring to FIG. 13 , one or more bridges 1122 , 1123 and 1124 are disposed between the first neural processing unit 100 a and the fourth neural processing unit 100 d.

The bridge 1122 transmits the intermediate result R22 generated by the operation of the second neural processing unit 100b to the first neural processing unit 100a. The bridge 1123 transmits the intermediate result R33 generated by the operation of the third neural processing unit 100c to the first neural processing unit 100a. In addition, the bridge 1124 transmits the intermediate result R44 generated by the operation of the fourth neural processing unit 100d to the first neural processing unit 100a.

For this reason, the first neural processing unit 100 a and the second neural processing unit 100 b can operate in different clock domains. In this case, the bridge 1122 may be electrically connected to the first NPU 100a and the second NPU 100b operating in a different clock domain than the first NPU 100a. Similarly, the bridge 1123 may be electrically connected to the first NPU 100a and the third NPU 100c operating in a different clock domain than the first NPU 100a. The bridge 1124 may be electrically connected to the first NPU 100a and the fourth NPU 100d operating in a different clock domain than the first NPU 100a.

Therefore, bridges 1122, 1123, and 1124 are implemented as asynchronous bridges to enable data transfer between different clock domains.

In the embodiments shown in FIGS. 12 and 13 , bridging between the second NPU 100b , the third NPU 100c , and the fourth NPU 100d , which are different from the first NPU 100a , has been described. device, but the scope of the present disclosure is not limited thereto, and this content can also be similarly applied between the third neural processing unit 100c and the fourth neural processing unit 100d different from the second neural processing unit 100b, and the third neural processing unit 100b Between the processing unit 100c and the fourth neural processing unit 100d.

FIG. 14 is a block diagram illustrating a computing system according to yet another embodiment of the present disclosure.

Referring to FIG. 14 , the neural processing system 10 of the computing system 5 according to the present embodiment further includes a workload manager 120 . Similar to the descriptions of FIG. 7 and FIG. 8, the workload manager 120 can distribute and distribute the data DATA used for feature extraction to the first neural processing unit 100a, the second neural processing unit 100b, and the third neural processing unit 100c. and a fourth neural processing unit 100d. In addition, the amount of data distributed from the first neural processing unit 100a to the fourth neural processing unit 100d may not be the same.

The clock management unit 20 may control the frequency of at least one of the first to fourth clock signals CLK1 to CLK4 in the same manner as explained with reference to FIGS. 7 and 8 in response to the workload manager 120 The allocation operation of the control the performance and power of the first neural processing unit 100a to the fourth neural processing unit 100d.

In this way, the neural processing system 10 according to various embodiments of the present disclosure can control the clocks of the first neural processing unit 100a, the second neural processing unit 100b, the third neural processing unit 100c, and the fourth neural processing unit 100d. signal to control performance or power consumption. For example, in order to improve the performance of the first neural processing unit 100a, the second neural processing unit 100b and the third neural processing unit 100c and reduce the power consumption of the fourth neural processing unit 100d, the clock management unit 20 can increase the The frequencies of the first clock signal CLK1, the second clock signal CLK2 and the third clock signal CLK3 for driving the first neural processing unit 100a to the third neural processing unit 100c can be reduced to drive the fourth neural processing unit 100d The frequency of the fourth clock signal CLK4. As another example, when only the first neural processing unit 100a and the second neural processing unit 100b are used and the third neural processing unit 100c and the fourth neural processing unit 100d are not used, the third neural processing unit can be driven by controlling The third clock signal CLK3 and the fourth clock signal CLK4 of the 100c and the fourth neural processing unit 100d perform clock gating. Therefore, according to a computing system including the neural processing system 10 according to various embodiments of the present disclosure, artificial intelligence can be realized while reducing cost and power consumption.

FIG. 15 is a block diagram illustrating a computing system according to yet another embodiment of the present disclosure.

Referring to FIG. 15 , different from the embodiment shown in FIG. 14 , the neural processing system 10 of the computing system 6 according to this embodiment further includes a power management unit 50 (PMU).

As mentioned above, the workload manager 120 allocates and distributes the data DATA for feature extraction to the first neural processing unit 100a, the second neural processing unit 100b, the third neural processing unit 100c, and the fourth neural processing unit 100d.

The power management unit 50 provides the first neural processing unit 100a, the second neural processing unit 100b, the third neural processing unit 100c and the fourth neural processing unit 100d with the first power gating signal PG1, the second power gating signal Three power gating control signals PG3 and a fourth power gating control signal PG4 .

The power management unit 50 can control the first power gating signal PG1, the second power gating signal PG2, the third power gating signal PG3 and the fourth power gating signal PG4 in the same manner as described with reference to FIG. 9 and FIG. At least one value whereby power control of the first NPU 100 a , the second NPU 100 b , the third NPU 100 c , and the fourth NPU 100 d are performed in response to the allocation operation of the workload manager 120 .

In this way, the neural processing system 10 according to various embodiments of the present disclosure can control the first neural processing unit 100a, the second neural processing unit 100b, the third neural processing unit 100c, and the fourth neural processing unit 100d as needed. One or more perform power gating to reduce power consumption of the neural processing system 10 . Therefore, according to a computing system including the neural processing system 10 according to various embodiments of the present disclosure, artificial intelligence can be realized while reducing cost and power consumption.

FIG. 16 is a block diagram illustrating a computing system according to yet another embodiment of the present disclosure.

Referring to FIG. 16 , the computing system 7 according to this embodiment may be a computing system including a neural processing system 10 , a clock management unit 20 , a processor 30 , a memory 40 , a power management unit 50 , a storage 60 , a display 70 and a camera 80 . system. The neural processing system 10 , the clock management unit 20 , the processor 30 , the memory 40 , the power management unit 50 , the storage 60 , the display 70 and the camera 80 can transmit and receive data through the bus 90 .

In some embodiments of the invention, computing system 7 may be a mobile computing system. Computing system 7 may be, for example, a computing system including a smartphone, tablet, laptop, or the like. Of course, the scope of the present disclosure is not limited thereto.

As explained so far, the neural processing system 10 according to various embodiments of the present disclosure is capable of performing feature extraction on image data generated by the camera 80 or stored in the memory 60 using a CNN with low cost and low power. operation.

As described above, the neural processing system 10 employs an architecture including a plurality of neural processing units capable of individually controlling clock and power, thereby faithfully implementing and executing artificial intelligence while reducing cost and power consumption.

From the summary of the detailed description, those skilled in the art will recognize that many changes and modifications can be made to the preferred embodiment without materially departing from the principles of this disclosure. Therefore, the disclosed preferred embodiments of the present invention are used in a general and descriptive sense only and not for limiting purposes.

1, 2, 3, 4, 5, 6, 7: computing systems 10: Neural Processing System 20: Clock Management Unit (CMU) 30: Processor 40: Memory 50: Power Management Unit (PMU) 60: Storage 70: display 80: camera 90: busbar 100a: first neural processing unit 100b: second neural processing unit 100c: The third neural processing unit 100d: Fourth neural processing unit 102a: The first front-end module 102b: Second front-end module 102c: The third front-end module 102d: The fourth front-end module 104a: The first backend module 104b: Second backend module 104c: The third backend module 104d: The fourth backend module 110: Bridge unit 111: First bridge 112: Second bridge 120:Workload Manager 1021a, 1022a: first internal memory 1021b, 1022b: the second internal memory 1023a, 1024a: the first extraction unit 1023b, 1024b: the second extraction unit 1025a, 1026a: the first dispatch unit 1025b, 1026b: the second dispatch unit 1027a: first MAC array 1027b: second MAC array 1041a: first summation unit 1041b: second summation unit 1043a: first activation unit 1043b: second activation unit 1045a: first write-back unit 1045b: the second write-back unit 1112, 1113, 1114, 1122, 1123, 1124: bridge CLK1: the first clock signal CLK2: Second clock signal CLK3: The third clock signal CLK4: The fourth clock signal DATA, DATA3, DATA4, DATA11, DATA12, DATA21, DATA22: data DATA1: the first data DATA2: Second data DATA3: the third data DATA4: the fourth data PG1: The first power gating signal PG2: Second power gating signal PG3: The third power gate control signal PG4: The fourth power gate control signal R11: The result of the first operation R12: second operation result/intermediate result R13, R14: intermediate results R21: The result of the third operation R22: Fourth operation result/intermediate result R33, R44: intermediate results WB DATA1: write data for the first time WB DATA2: Write data for the second time.

The above and other aspects and features of the present disclosure will become more apparent by elaborating exemplary embodiments of the present disclosure in detail with reference to the accompanying drawings, in which: FIG. 1 is a schematic diagram illustrating a computing system according to an embodiment of the present disclosure. FIG. 2 is a block diagram illustrating a neural processing system according to an embodiment of the present disclosure. FIG. 3 is a block diagram illustrating a neural processing system according to an embodiment of the present disclosure. 4 and 5 are block diagrams illustrating front-end modules of a neural processing system according to an embodiment of the disclosure. FIG. 6 is a block diagram illustrating backend modules of a neural processing system according to an embodiment of the disclosure. FIG. 7 is a schematic diagram illustrating a computing system according to another embodiment of the present disclosure. FIG. 8 is a block diagram illustrating a neural processing system according to another embodiment of the present disclosure. FIG. 9 is a schematic diagram illustrating a computing system according to yet another embodiment of the present disclosure. FIG. 10 is a block diagram illustrating a neural processing system according to yet another embodiment of the present disclosure. FIG. 11 is a schematic diagram illustrating a computing system according to yet another embodiment of the present disclosure. 12 and 13 are block diagrams illustrating a neural processing system according to yet another embodiment of the present disclosure. FIG. 14 is a block diagram illustrating a computing system according to yet another embodiment of the present disclosure. FIG. 15 is a block diagram illustrating a computing system according to yet another embodiment of the present disclosure. FIG. 16 is a block diagram illustrating a computing system according to yet another embodiment of the present disclosure.

1: Computing system

10: Neural Processing System

20: Clock Management Unit (CMU)

30: Processor

40: Memory

90: busbar

100a: first neural processing unit

100b: second neural processing unit

CLK1: the first clock signal

CLK2: Second clock signal

Claims (20)

A neural processing system, comprising: a first front-end module, which uses a first feature map and a first weight to perform a feature extraction operation, and outputs a first operation result and a second operation result; a second front-end module, which uses a second feature map and the second weight to perform the feature extraction operation, and output the third operation result and the fourth operation result; the first back-end module receives the first operation result provided from the first front-end module and passes the first operation result Two bridges receive an input of the fourth operation result from the second front-end module to sum the first operation result and the fourth operation result; and a second back-end module receives input from the The third operation result provided by the second front-end module and the input of the second operation result provided from the first front-end module through the first bridge are used to sum the third operation result and the first operation result. 2. Operation results. The neural processing system described in item 1 of the scope of the patent application, wherein the first front-end module and the first back-end module are driven according to a first clock signal, and the second front-end module and the The second back-end module is driven according to a second clock signal having a frequency different from that of the first clock signal. The neural processing system according to claim 1, wherein the first bridge and the second bridge are asynchronous bridges. The neural processing system described in item 1 of the scope of the patent application, wherein the first back-end module provides first write-back data to the first front-end module, and the second back-end module provides the first write-back data to the first front-end module The second front-end module provides second write-back data. The neural processing system described in item 1 of the scope of the patent application, wherein the first front-end module includes: a plurality of first internal memories storing the first feature map and the first weight, and a plurality of first An extracting unit, extracting the first feature map and the first weight from each of the plurality of first internal memories, and a plurality of first dispatching units, for each channel, extracting the extracted first feature map A feature map and the first weights are transmitted to a first multiply and accumulate array, and the first multiply and accumulate array performs multiply accumulate operations on data transmitted from the plurality of first dispatch units. The neural processing system according to claim 5, wherein the first multiplication and accumulation array outputs the first operation result and the second operation result, and the first operation result is provided to the first operation result A backend module, and the second calculation result is provided to the second backend module through the first bridge. The neural processing system described in item 1 of the scope of the patent application, wherein the second front-end module includes: a plurality of second internal memories for storing the second feature map and the second weight, and a plurality of second An extracting unit extracts the second feature map and the second weight from each of the plurality of second internal memories, and a plurality of second dispatching units extracts the extracted first feature map for each channel Two feature maps and said second weights are sent to a second multiply and accumulate array, and said second multiply and accumulate array is sent from said plurality of second dispatch units Perform multiplication and accumulation operations on the data. The neural processing system described in item 1 of the scope of the patent application further includes: a workload manager, which distributes the first data among the data used for feature extraction to the first front-end module, and distributes the data assigning the second data in the second front-end module to the second front-end module, wherein the first front-end module uses the first feature map and the first weight to perform the feature extraction operation on the first data, and The second front-end module uses the second feature map and the second weight to perform the feature extraction operation on the second data. The neural processing system according to claim 8, wherein the quantity of the first data and the quantity of the second data are different from each other. The neural processing system described in item 8 of the scope of the patent application further includes: a clock management unit that provides a first clock signal to the first front-end module and the first back-end module, and sends the first clock signal to the The second front-end module and the second back-end module provide a second clock signal, wherein the clock management unit controls at least one of the first clock signal and the second clock signal frequency to at least one of the first front-end module, the first back-end module, the second front-end module, and the second back-end module according to the allocation operation of the workload manager One performs clock gating. The neural processing system described in item 8 of the scope of the patent application further includes: a power management unit, which provides a first power gating signal to the first front-end module and the first back-end module, and provides the first power gating signal to the The second front-end module and the second back-end module provide a second power gating signal, Wherein the power management unit controls at least one value of the first power gating signal and the second power gating signal, so as to control the first front-end module, the At least one of the first back-end module, the second front-end module, and the second back-end module performs power gating. A neural processing system, comprising: a first neural processing unit, including a first front-end module and a first rear-end module; and a bridge unit, electrically connected to the first neural processing unit, and a second neural processing unit , operating in a clock domain different from that of the first neural processing unit, wherein the first front-end module performs a part of a first operation result obtained by performing a feature extraction operation using a first feature map and a first weight provided to the first backend module, the bridge unit provides a portion of the result of the second operation performed in the second neural processing unit to the first backend module, and the first The backend module sums the part of the first operation result and the part of the second operation result. The neural processing system according to claim 12 of the patent application, wherein the bridge unit is electrically connected to a third neural processing unit, and the third neural processing unit operates at a clock different from that of the first neural processing unit operating in the domain, the first front-end module provides another part of the first operation result to the bridge unit, and the bridge unit provides the other part of the first operation result to The third neural processing unit. The neural processing system described in item 12 of the scope of the patent application, wherein the first front-end module includes: a plurality of first internal memories for storing the first feature map and the first weight, and a plurality of first An extracting unit, extracting the first feature map and the first weight from each of the plurality of first internal memories, and a plurality of first dispatching units, for each channel, extracting the extracted first feature map A feature map and the first weights are transmitted to a first multiply and accumulate array, and the first multiply and accumulate array performs a multiply accumulate operation on the data transmitted from the plurality of first dispatch units, and outputs the The result of the first operation. A neural processing system, comprising: a first neural processing unit including a first front-end module and a first back-end module; a second neural processing unit including a second front-end module and a second back-end module; and a workload a manager for distributing a first of the data for performing feature extraction to the first neural processing unit, and distributing a second of the data to the second neural processing unit, wherein the first A front-end module uses the first feature map and the first weight to perform a feature extraction operation on the first data, and outputs the first operation result and the second operation result, and the second front-end module uses the second feature map and the second Two weights perform the feature extraction operation on the second data, and output a third operation result and a fourth operation result, and the first back-end module sums the first operation result and the fourth operation result result, and the second back-end module sums the sum of the third operation result and the second operation result. The neural processing system described in item 15 of the scope of the patent application further includes: a clock management unit, which provides a first clock signal to the first front-end module and the first back-end module, and sends the first clock signal to the The second front-end module and the second back-end module provide a second clock signal, wherein the clock management unit controls at least one of the first clock signal and the second clock signal frequency to at least one of the first front-end module, the first back-end module, the second front-end module, and the second back-end module according to the allocation operation of the workload manager One performs clock gating. The neural processing system described in item 15 of the scope of the patent application further includes: a power management unit, which provides a first power gating signal to the first front-end module and the first back-end module, and provides the first power gating signal to the The second front-end module and the second back-end module provide a second power gating signal, wherein the power management unit controls at least one value of the first power gating signal and the second power gating signal , to at least one of the first front-end module, the first back-end module, the second front-end module, and the second back-end module according to the allocation operation of the workload manager or perform power gating. The neural processing system as described in item 15 of the scope of the patent application, wherein the first neural processing unit is driven according to a first clock signal, and the second neural processing unit is driven according to a clock signal different from the first clock signal frequency of the second clock signal is driven. The neural processing system described in item 15 of the scope of the patent application, wherein the first front-end module includes: a plurality of first internal memories storing the first feature map and the first weight, and a plurality of first An extracting unit, extracting the first feature map and the first weight from each of the plurality of first internal memories, and a plurality of first dispatching units, for each channel, extracting the extracted first feature map A feature map and the first weights are transmitted to a first multiply and accumulate array, and the first multiply and accumulate array performs multiply accumulate operations on data transmitted from the plurality of first dispatch units. The neural processing system described in item 15 of the scope of the patent application, wherein the second front-end module includes: a plurality of second internal memories for storing the second feature maps and the second weights, and a plurality of second An extracting unit extracts the second feature map and the second weight from each of the plurality of second internal memories, and a plurality of second dispatching units extracts the extracted first feature map for each channel The second feature map and the second weights are transmitted to a second multiply and accumulate array, and the second multiply and accumulate array performs a multiply accumulate operation on the data transmitted from the plurality of second dispatch units.

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