TWI804192B - Digital Phase Locked Loop Circuit - Google Patents

Abstract

A digital phase-locked loop circuit is provided, comprising: a synchronous control module configured to generate an input representative signal representing a periodic change of the input periodic signal relative to the basic clock signal based on a basic clock signal and an input periodic signal; a counting control module The group is configured to generate a clock counting result representing the multiple relationship between the period of the input characterization signal and the period of the basic clock signal based on the basic clock signal and the input characterization signal; the operation control module is configured to be based on the output clock signal A preset multiplication factor between the frequency and the frequency of the input periodic signal generates a base clock control variable, and generates an output clock control variable based on a clock count result; and an output control module configured to control the base clock based on the base clock control variable and the output clock The variable generates an output control signal, and generates an output clock signal based on the output control signal and the base clock signal.

Description

Digital Phase Locked Loop Circuit

The invention relates to the field of circuits, in particular to a digital phase-locked loop circuit.

A phase-locked loop circuit is a common circuit that can be used to generate an output clock signal that is synchronized with the input periodic signal (synchronous in both frequency and phase) based on the input periodic signal. Fig. 1 shows a schematic block diagram of a traditional analog phase-locked loop circuit. As shown in Figure 1, the analog phase-locked loop circuit includes three parts: a phase detector, a loop filter, and a voltage-controlled oscillator. When the frequency of the input periodic signal Sin changes, the loop filter cannot follow the The frequency of the input periodic signal Sin changes to quickly adjust the voltage supplied to the voltage-controlled oscillator. The frequency of the output clock signal Sout generated by the voltage-controlled oscillator will oscillate to a greater extent and require a longer adjustment time to match the input periodic signal. The frequency of Sin is synchronized; in addition, due to the limitation of the filtering parameters of the loop filter, the analog phase-locked loop circuit is not suitable for the case where the frequency range of the input periodic signal is wide.

The digital phase-locked loop circuit according to an embodiment of the present invention includes: a synchronous control module configured to generate an input representative signal representing a periodic change of the input periodic signal relative to the basic clock signal based on the basic clock signal and the input periodic signal; The counting control module is configured to generate a clock counting result representing the multiple relationship between the period of the input representative signal and the period of the basic clock signal based on the basic clock signal and the input representative signal; the operation control module is configured to output The preset frequency multiplication coefficient between the frequency of the clock signal and the frequency of the input periodic signal generates a basic clock control variable, and generates an output clock control variable based on the clock counting result; and the output control module is configured to be based on the basic clock control variable and The output clock control variable generates the output control signal, and generates the output clock signal based on the output control signal and the base clock signal.

The digital phase-locked loop circuit according to the embodiment of the present invention can realize the synchronization between the output clock signal and the input periodic signal (synchronization in both frequency and phase) with an adjustment time much shorter than that of the analog phase-locked loop circuit, and there is no analog phase-locked loop The loop oscillation problem of the circuit.

0,1: terminal

200: Digital PLL circuit

202: Synchronous control module

204: Counting control module

206: Operation control module

208: Output control module

AND2: AND gate

DPLL_CLK: output clock signal

DPLL_PASS: output control signal

DPLL_SUM: output clock control variable

Fin, Fosc, Fout: Frequency

Nset: preset multiplication factor

Nsin: clock count result

OSC_CLK: basic clock signal

OSC_SUM: Base clock control variable

Q1: The first characteristic signal

Q2: The second characteristic signal

Sin: input periodic signal

Sin_start: input characterization signal

Sout: output clock signal

SUM_COMP: variable comparison signal

T1~T7: D flip-flop

U1~U5: 2-way selector

The present invention can be better understood from the following description of specific embodiments of the present invention in conjunction with the drawings, wherein:

Fig. 1 shows a schematic block diagram of a traditional analog phase-locked loop circuit.

Fig. 2 shows a schematic block diagram of a digital phase-locked loop circuit according to an embodiment of the present invention.

FIG. 3 shows a schematic diagram of an example implementation of the synchronous control module shown in FIG. 2;

Figure 4 shows a waveform diagram of a plurality of signals related to the synchronous control module shown in Figure 3;

Fig. 5 shows a schematic diagram of an example implementation of the counting control module shown in Fig. 2;

Fig. 6 shows a schematic diagram of a partial example implementation of the operation control module shown in Fig. 2;

Fig. 7 shows a schematic diagram of a partial example implementation of the operation control module shown in Fig. 2;

FIG. 8 shows a schematic diagram of an example implementation of the output control module shown in FIG. 2;

Fig. 9 shows the control flowchart of the digital PLL circuit according to an embodiment of the present invention;

FIG. 10 shows waveform diagrams of various signals related to the output control module shown in FIG. 8 .

Features and exemplary embodiments of various aspects of the invention will be described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is only to provide a better understanding of the present invention by showing examples of the present invention. The present invention is by no means limited to any specific configurations and algorithms set forth below, but covers any modification, substitution and improvement of elements, components and algorithms without departing from the spirit of the invention. In the drawings and the following description, well-known structures and techniques have not been shown in order to avoid unnecessarily obscuring the present invention.

In view of one or more problems existing in the traditional analog phase-locked loop circuit, a digital phase-locked loop circuit is proposed, which can realize fast phase-locked control through digital operations, and can improve the signal frequency range of the phase-locked loop circuit And greatly reduce the circuit complexity of the phase-locked loop circuit.

FIG. 2 shows a schematic block diagram of a digital phase-locked loop circuit 200 according to an embodiment of the present invention. As shown in Figure 2, the digital PLL circuit 200 includes a synchronous control module 202, a counting control module 204, an operation control module 206, and an output control module 208, wherein: the synchronous control module 202 is configured based on The clock signal OSC_CLK and the input cycle signal Sin generate a representative input cycle The input representative signal Sin_start of the periodic change of the signal Sin relative to the basic clock signal OSC_CLK; the counting control module 204 is configured to generate a period representing the input representative signal Sin_start and the basic clock signal OSC_CLK based on the basic clock signal OSC_CLK and the input representative signal Sin_start The clock counting result Nsin of the multiple relationship between the periods of ; the operation control module 206 is configured to generate the basic clock control variable OSC_SUM based on the preset frequency multiplication coefficient Nset between the frequency of the output clock signal DPLL_CLK and the frequency of the input period signal Sin , and generate the output clock control variable DPLL_SUM based on the clock counting result Nsin; the output control module 208 is configured to generate the output control signal DPLL_PASS based on the basic clock control variable OSC_SUM and the output clock control variable DPLL_SUM, and based on the output control signal DPLL_PASS and the basic clock signal OSC_CLK generates the output clock signal DPLL_CLK.

Here, it is assumed that the frequency of the basic clock signal OSC_CLK is Fosc, the frequency of the input periodic signal Sin is Fin, and the frequency of the output clock signal DPLL_CLK is Fout=Nset×Fin, where the frequency of the basic clock signal OSC_CLK is usually much higher than that of the input periodic signal. A high frequency clock signal (for example, a high frequency oscillator signal).

FIG. 3 shows a schematic diagram of an example implementation of the synchronization control module 202 shown in FIG. 2 . As shown in FIG. 2 , in some embodiments, the synchronous control module 202 may be further configured to: use D flip-flop T1 to generate the first characteristic signal Q1 based on the falling edge of the basic clock signal OSC_CLK and the input periodic signal Sin; The falling edge of the basic clock signal OSC_CLK and the first characteristic signal Q1, use the D flip-flop T2 to generate the second characteristic signal Q2; and based on the inversion signal of the second characteristic signal Q2 and the first characteristic signal Q1, use the AND gate AND1 to generate the input Characterize the signal Sin_start.

FIG. 4 shows a waveform diagram of various signals related to the synchronous control module 202 shown in FIG. 3 . It should be noted that the waveform diagram shown in FIG. 4 is a waveform diagram generated by the synchronous control module 202 shown in FIG. 3 with the rising edge of the input periodic signal Sin as the valid edge and the falling edge of the basic clock signal OSC_CLK as the valid edge. .

FIG. 5 shows a schematic diagram of an example implementation of the count control module 204 shown in FIG. 2 . As shown in FIG. 5 , in some embodiments, the counting control module 204 can be further configured to: when the input characteristic signal Sin_start is at an inactive level (for example, a low level), use the clock counter to control the basic clock signal OSC_CLK The number of cycles is counted; when the input characterization signal Sin_start is at a valid level (for example, a high level), the counting result of the clock counter is updated to the clock counting result Nsin and clears the clock counter.

Specifically, in the example implementation of the counting control module 204 shown in FIG. 5 , the 2-way selector U1, the D flip-flop T3, and the adder (+1 operation) constitute a clock counter, wherein the input characterization signal Sin_start is used As the output control signal of the 2-way selector U1, when the input representative signal Sin_start is logic 0, the signal received by the output terminal 0 of the 2-way selector U1, when the input representative signal Sin_start is logic 1, the output terminal of the 2-way selector U1 1 signal received; 2-way selector U2 and D flip-flop T4 constitute a count output device, which is used to update the counting result of the clock counter to the clock counting result Nsin and output it to the outside, where the input characterization signal Sin_start is used as 2-way selection The output control signal of the device U2, when the input representative signal Sin_start is logic 0, the signal received by the 2-way selector U2 output terminal 0, when the input representative signal Sin_start is logic 1, the signal received by the 2-way selector U2 output terminal 1 .

FIG. 6 shows a schematic diagram of a partial implementation of the calculation control module 206 shown in FIG. 2 . As shown in FIG. 6, in some embodiments, the operation control module 206 can be further configured to: when the input characteristic signal Sin_start is at a valid level (for example, a high level), based on the frequency Fout of the output clock signal DPLL_CLK and the input The preset frequency multiplication factor Nset between the frequencies Fin of the periodic signal Sin initializes the basic clock control variable OSC_SUM. For example, the variable value of the basic clock control variable OSC_SUM may be initialized as OSC _SUM =1.5×N _set .

As shown in FIG. 6 , in some embodiments, the operation control module 206 can be further configured to: when the input characteristic signal Sin_start is at an inactive level (for example, a low level), based on the frequency Fout and the frequency of the output clock signal DPLL_CLK The preset frequency multiplication coefficient Nset between the frequencies Fin of the input periodic signal Sin updates the basic clock control variable OSC_SUM. For example, the variable value temporarily updated based on the basic clock control variable OSC_SUM at the previous effective edge of the basic clock signal OSC_CLK and the preset frequency multiplication coefficient Nset between the frequency Fout of the output clock signal DPLL_CLK and the frequency Fin of the input periodic signal Sin , calculate the update variable value of the basic clock control variable OSC_SUM, and use the calculated update variable value to update the basic clock control variable OSC_SUM when the current effective edge of the basic clock signal OSC_CLK comes. For example, the variable value of the basic clock control variable OSC_SUM may be updated as OSC_SUM=OSC_SUM+N _Set .

Specifically, in some example implementations of the operation control module 206 shown in FIG. 6 , the 2-way selector U3, the D flip-flop T5, and the adder (+Nset operation) constitute the first operation unit, which is used to To initialize and update the basic clock control variable OSC_SUM, wherein the input signal Sin_start is used as the output control signal of the 2-way selector U3, when the input signal Sin_start is logic 0, the output terminal 0 of the 2-way selector U3 receives The signal of the basic clock control variable OSC_SUM (that is, the sum of the updated variable value and the preset frequency multiplication coefficient Nset when the basic clock control variable OSC_SUM is on the previous effective edge of the basic clock signal OSC_CLK), when the input characterization signal Sin_start is logic 1, the 2-way selector U3 outputs the signal received at terminal 1 (ie, 1.5*Nset).

FIG. 7 shows a schematic diagram of a partial example implementation of the calculation control module 206 shown in FIG. 2 . As shown in FIG. 7 , in some embodiments, the operation control module 206 can be further configured to: when the input characterization signal Sin_start is at a valid level (for example, a high level), control the output clock variable based on the clock counting result Nsin DPLL_SUM is initialized. For example, the variable value of the output clock control variable DPLL_SUM may be initialized as DPLL_SUM=N _Sin .

As shown in FIG. 7 , in some embodiments, the operation control module 206 can be further configured to: when the input characteristic signal Sin_start is at an inactive level (for example, a low level), control the output clock based on the clock count result Nsin The variable DPLL_SUM is updated. For example, the updated variable value of the output clock control variable DPLL_SUM can be calculated based on the temporarily updated variable value of the output clock control variable DPLL_SUM at the previous effective edge of the basic clock signal OSC_CLK, the clock counting result Nsin, and the output control signal DPLL_PASS, and then When the current effective edge of the basic clock signal OSC_CLK comes, the calculated update variable value is used to update the output clock control variable DPLL_SUM, wherein the output control signal DPLL_PASS represents that the basic clock control variable OSC_SUM and the output clock control variable DPLL_SUM are in the previous period of the basic clock signal. The effective edge is the size comparison relationship between the variable values that are updated temporarily. For example, the variable value of the output clock control variable DPLL_SUM may be updated as DPLL_SUM=DPLL_SUM+DPLL_PAss*N _Sin .

Specifically, in some example implementations of the operation control module 206 shown in FIG. 7 , the 2-way selectors U4 and U5, the D flip-flop T6, and the adder constitute a second operation unit for controlling the output clock variable DPLL_SUM Initialize and update, wherein, the output control signal DPLL_PASS is used as the output control signal of the 2-way selector U4, when the output control signal DPLL_PASS is logic 0, the signal received by the 2-way selector U4 output terminal 0 (that is, logic 0 ), when the output control signal DPLL_PASS is logic 1, the 2-way selector U4 outputs the signal received by terminal 1 (that is, the clock counting result Nsin), and the input characterization signal Sin_start is used as 2-way selection The output control signal of the device U5, when the input characterization signal Sin_start is logic 0, the signal received by the output terminal 0 of the 2-way selector U5 (that is, the variable that the output clock control variable DPLL_SUM is updated on the previous valid edge of the basic clock signal OSC_CLK value and the output signal of the 2-way selector U4), when the input signal Sin_start is logic 1, the 2-way selector U5 outputs the signal received by terminal 1 (that is, the clock counting result Nsin).

FIG. 8 shows a schematic diagram of an example implementation of the output control module 208 shown in FIG. 2 . As shown in FIG. 8 , in some embodiments, the output control module 208 can be further configured to: use a comparator to generate a variable comparison signal SUM_COMP based on the basic clock control variable OSC_SUM and the output clock control variable DPLL_SUM; based on the basic clock signal OSC_CLK The falling edge of the variable comparison signal SUM_COMP, using the D flip-flop T7 to generate the output control signal DPLL_PASS; and based on the basic clock signal OSC_CLK and the output control signal DPLL_PASS, using the AND gate AND2 to generate the output clock signal DPLL_CLK. Here, when the basic clock control variable OSC_SUM is greater than the output clock control variable DPLL_SUM, the output control signal DPLL_PASS is logic 1, and the next pulse of the basic clock signal OSC_CLK is output as a pulse of the output clock signal DPLL_CLK; when the basic clock control variable OSC_SUM is not greater than When the clock control variable DPLL_SUM is output, the output control signal SUM_COMP is logic 0, and the output clock signal DPLL_CLK is logic 0.

In some embodiments, the counting control module 204 and the operation control module 206 regard the rising edge of the basic clock signal OSC_CLK as the valid edge, and the synchronization control module 202 and the output control module 208 regard the falling edge of the basic clock signal OSC_CLK as the valid edge. Alternatively, the counting control module 204 and the operation control module 206 use the falling edge of the basic clock signal OSC_CLK as the valid edge, and the synchronous control module 202 and the output control module 208 use the rising edge of the basic clock signal OSC_CLK as the valid edge .

FIG. 9 shows a control flowchart of a digital phase-locked loop circuit according to an embodiment of the present invention. As shown in FIG. 9 , the control flow of the digital phase-locked loop circuit according to the embodiment of the present invention includes: when the valid edge of the basic clock signal OSC_CLK comes, it is judged whether the valid edge of the input periodic signal Sin is coming (that is, the input characteristic signal Sin_start Whether it is at a valid level (for example, a high level)); when the valid edge of the input periodic signal Sin comes (that is, when the input characterization signal Sin_start is at a valid level), the clock counting result Nsin is updated, and the clock counter is cleared , the output clock control The control variable DPLL_SUM is initialized, and the basic clock control variable OSC_SUM is initialized; when the valid edge of the input periodic signal Sin does not come (that is, when the input characterization signal Sin_start is at an inactive level (for example, low level)), the clock counter Add 1 to the count number of the output clock control variable DPLL_SUM, and accumulate the basic clock control variable OSC_SUM; judge whether the basic clock control variable OSC_SUM is greater than the output clock control variable DPLL_SUM; if the basic clock control variable OSC_SUM is greater than the output clock control variable DPLL_SUM, the output control signal DPLL_PASS is logic 1, and the next pulse of the basic clock signal OSC_CLK is output as the output clock signal DPLL_CLK; if the basic clock control variable OSC_SUM is not greater than the output clock control variable DPLL_SUM, the output control signal DPLL_PASS is logic 0, blocking The next pulse of the basic clock signal OSC_CLK, that is, the output clock signal DPLL_CLK is logic 0. Here, the steps in box 1 correspond to the rising edge of the basic clock signal OSC_CLK, and the steps in box 2 correspond to the falling edge of the basic clock signal OSC_CLK.

FIG. 10 shows a waveform diagram of various signals related to the output control module 208 shown in FIG. 8 . Specifically, FIG. 10 shows a waveform diagram of a plurality of signals related to the output control module 208 in the following example: based on the basic clock signal OSC_CLK of 10MHz and the input periodic signal Sin of 1kHz, the frequency of the input periodic signal Sin is The output clock signal DPLL_CLK whose frequency is 3000 times; the clock counting result Nsin is 10,000, and the preset frequency multiplication coefficient Nset between the frequency of the output clock signal DPLL_CLK and the frequency of the input periodic signal Sin is 3,000; when the rising edge of the input periodic signal Sin When it comes (that is, when Sin_start is at a valid level), the basic clock control variable OSC_SUM and the output clock control variable DPLL_SUM are initialized to 4500 (1.5Nset) and 10,000 (Nsin) respectively when the rising edge of the basic clock signal OSC_CLK comes, and the output control The signal DPLL_PASS is updated to logic 0 when the falling edge of the basic clock signal OSC_CLK comes, masking the next pulse of the basic clock signal OSC_CLK, and so on. The corresponding results of the subsequent basic clock control signal OSC_CLK and the output clock signal DPLL_CLK are as follows:

It can be seen from Figure 10 that the output clock signal DPLL_CLK is synchronized with the clock edge of the basic clock signal OSC_CLK; since the frequency (10MHz) of the basic clock signal OSC_CLK and the frequency (3MHz) of the output clock signal DPLL_CLK are not integer multiples, the output clock signal DPLL_CLK is not evenly distributed, and its counting/timing maximum deviation is 0.5 period (50ns) of the basic clock signal OSC_CLK. In the long term, when the output clock signal DPLL_CLK is used for functions such as counting and timing, the error of 1s is 50ns/1s (5 parts per billion), and the error of 1ms is 50ns/1ms (0.5 parts per ten thousand). is almost negligible, and as the underlying clock signal The improvement of the frequency of OSC_CLK can further reduce its error.

Next, mathematically deduce the effect achieved by the digital phase-locked loop circuit according to the embodiment of the present invention:

Assume that when the input characterization signal Sin_start is at a valid level, any rising edge of the output clock signal DPLL_CLK is the Nth _DPLL rising edge, and the basic clock signal OSC_CLK corresponds to the rising edge of the Nth _DPLL rising edge of the output clock signal DPLL_CLK The edge is the rising edge of N _OSC .

When the N _OSC rising edge of the basic clock signal OSC_CLK comes, the basic clock control variable OSC_SUM will output the update variable value calculated as follows:

When the N _OSC rising edge of the basic clock signal OSC_CLK comes, the output clock control variable DPLL_SUM will output the update variable value calculated as follows:

From the working mechanism of the digital phase-locked loop circuit according to the embodiment of the present invention:

Combining (1), (2), (3) can get:

個脈衝的時刻產生，N_OSC為對

四捨 五入後的取整結果。 That is, the Nth _DPLL pulse of the output clock signal DPLL_CLK needs to be at the

pulses are generated at the moment, N _OSC is the pair

The rounded result after rounding.

Continuing with the above example:

The first pulse of the output clock signal DPLL_CLK should theoretically be generated at the moment of the 3.33rd pulse of the basic clock signal OSC_CLK, but actually it is generated at the moment of the third pulse of the basic clock signal OSC_CLK.

The second pulse of the output clock signal DPLL_CLK should theoretically be generated at the moment of the 6.67th pulse of the basic clock signal OSC_CLK, but actually it is generated at the moment of the seventh pulse of the basic clock signal OSC_CLK.

The third pulse of the output clock signal DPLL_CLK should theoretically be generated at the time of the 10th pulse of the basic clock signal OSC_CLK, actually at the time of the 10th pulse of the basic clock signal OSC_CLK The moment of the 10th pulse is generated.

And so on:

The 30th pulse of the output clock signal DPLL_CLK should theoretically be generated at the time of the 100th pulse of the basic clock signal OSC_CLK, but it is actually generated at the time of the 100th pulse of the basic clock signal OSC_CLK.

The 3000th (Nset) pulse of the output clock signal DPLL_CLK should theoretically be generated at the moment of the 10000th (Nsin) pulse of the basic clock signal OSC_CLK. At this time, the next pulse corresponding to the input signal Sin_start comes, and a cycle ends.

The digital phase-locked loop circuit according to the embodiment of the present invention can ensure that the output clock signal DPLL_CLK of Nset periods is approximately uniformly generated within one period of the input period signal Sin, thereby realizing Nset frequency multiplication of the input period signal Sin. Although the frequency of the basic clock signal OSC_CLK will affect the operation process of the digital PLL circuit according to the embodiment of the present invention, it will not significantly affect the output clock signal DPLL_CLK. Using the basic clock signal OSC_CLK of different frequencies (as long as its frequency is higher than the expected frequency of the output clock signal DPLL_CLK) can achieve the Nset frequency multiplication effect of the input periodic signal Sin, so the frequency accuracy of the basic clock signal OSC_CLK is not high. For the case where the frequency of the input periodic signal Sin changes, the clock counting result Nsin will be updated immediately at the end of one cycle of the input periodic signal Sin, so its response only lags by 1 cycle, which is much faster than the analog phase-locked loop circuit. And there will be no oscillation problem caused by the loop filter in the analog phase-locked loop circuit. In addition, when the frequency of the input periodic signal Sin is low, it is only necessary to ensure that the bit width of the corresponding variable (for example, Nsin, OSC_SUM, DPLL_SUM) is sufficient and no overflow occurs, so that the digital lock according to the embodiment of the present invention The phase loop circuit can also work normally when the frequency range of the input periodic signal Sin is wide.

In summary, the digital phase-locked loop circuit according to the embodiment of the present invention only needs to use components such as adders, comparators, and flip-flops to realize the synchronization of the input periodic signal and the output clock signal (synchronization of both frequency and phase) , no need to use arithmetic units such as multiplication and division, which greatly simplifies the complexity of calculation and circuit design.

The present invention may be embodied in other specific forms without departing from its spirit and essential characteristics. For example, the algorithms described in certain embodiments may be modified without departing from the basic spirit of the invention in terms of system architecture. Accordingly, the present embodiments are to be considered in all respects as exemplary and not Without limitation, the scope of the present invention is defined by the appended claims rather than the above description, and all changes that come within the meaning and range of equivalents of the claims are thereby embraced in the scope of the present invention.

200: Digital PLL circuit

202: Synchronous control module

204: Counting control module

206: Operation control module

208: Output control module

DPLL_CLK: output clock signal

Nset: preset multiplication factor

OSC_CLK: basic clock signal

Sin: input periodic signal

Claims (18)

A digital phase-locked loop circuit, comprising: a synchronous control module configured to generate, based on a basic clock signal and an input periodic signal, an input representative signal representing a periodic change of the input periodic signal relative to the basic clock signal, namely , based on the basic clock signal and the input periodic signal, using a first D flip-flop to generate a first characterization signal; based on the basic clock signal and the first characterization signal, using a second D flip-flop to generate a second characterization signal; and based on the inversion signal of the second characterization signal and the first characterization signal, using the first AND gate to generate the input characterization signal; the counting control module is configured to be based on the basic clock signal and the The input representative signal generates a clock counting result representing the multiple relationship between the period of the input representative signal and the period of the basic clock signal; the operation control module is configured to be based on the frequency of the output clock signal and the input A preset frequency multiplication factor between the frequencies of the periodic signal generates a basic clock control variable, and generates an output clock control variable based on the clock counting result; and an output control module configured to control the basic clock variable based on the basic clock control variable and the An output clock control variable generates an output control signal, and generates the output clock signal based on the output control signal and the base clock signal. According to the digital phase-locked loop circuit described in claim 1, wherein the counting control module is further configured to: use a clock counter to count the number of cycles of the basic clock signal when the input representative signal is at an inactive level Counting; when the input representative signal is at a valid level, updating the counting result of the clock counter to the clock counting result and clearing the clock counter. The digital phase-locked loop circuit according to claim 1, wherein the operation control module is further configured to: when the input representative signal is at a valid level, based on the frequency of the output clock signal and the input period initializing said base clock control variable with a preset multiplication factor between frequencies of the signal; and When the input representative signal is at an inactive level, the basic clock control variable is updated based on a preset frequency multiplication factor between the frequency of the output clock signal and the frequency of the input periodic signal. The digital phase-locked loop circuit according to claim 3, wherein the operation control module is further configured to: based on the variable value of the basic clock control variable that is temporarily updated when the previous valid edge of the basic clock signal comes and the preset frequency multiplication coefficient between the frequency of the output clock signal and the frequency of the input periodic signal, calculate the update variable value of the basic clock control variable; and when the current effective edge of the basic clock signal comes , updating the basic clock control variable with the calculated update variable value. According to the digital phase-locked loop circuit described in claim 1, wherein the operation control module is further configured to: when the input representative signal is at a valid level, control the variable of the output clock based on the clock count result performing initialization; and updating the output clock control variable based on the clock counting result when the input representative signal is at an inactive level. According to the digital phase-locked loop circuit described in claim 5, wherein the operation control module is further configured to: based on the variable value of the output clock control variable that is temporarily updated at the previous valid edge of the basic clock signal , the clock counting result, and the output control signal, calculate the update variable value of the output clock control variable, wherein the output control signal represents the base clock control variable and the output clock control variable in the The size comparison relationship between the variable values updated when the previous valid edge of the basic clock signal comes; and when the current valid edge of the basic clock signal comes, update the output clock control variable with the calculated update variable value . The digital phase-locked loop circuit according to claim 6, wherein the output control signal is logic 1 when the basic clock control variable is greater than the output clock control variable, and is logic 1 when the basic clock control variable is not greater than the Logic 0 when the output clock controls the variable. According to the digital phase-locked loop circuit described in claim 1, wherein the output control module The group is further configured to: use a comparator to generate a variable comparison signal based on the basic clock control variable and the output clock control variable; use a third D flip-flop to generate the variable comparison signal based on the basic clock signal and the variable comparison signal. the output control signal; and based on the basic clock signal and the output control signal, using a second AND gate to generate the output clock signal. According to the digital phase-locked loop circuit described in claim 1, wherein, the counting control module and the operation control module use the rising edge of the basic clock signal as a valid edge, and the synchronization control module and the The output control module takes the falling edge of the basic clock signal as the valid edge, or the counting control module and the operation control module take the falling edge of the basic clock signal as the valid edge, and the synchronous control module and the output control module takes the rising edge of the basic clock signal as a valid edge. A control method implemented by a digital phase-locked loop circuit, including: based on a basic clock signal and an input periodic signal, generating an input characterization signal that characterizes the periodic change of the input periodic signal relative to the basic clock signal, that is, based on the The basic clock signal and the input periodic signal, using a first D flip-flop to generate a first representative signal; based on the basic clock signal and the first representative signal, using a second D flip-flop to generate a second representative signal; and Based on the inversion signal of the second characterization signal and the first characterization signal, using a first AND gate to generate the input characterization signal; based on the basic clock signal and the input characterization signal, generating the input characterization signal A clock counting result of the multiple relationship between the period of the signal and the period of the basic clock signal; a basic clock control variable is generated based on a preset frequency multiplication factor between the frequency of the output clock signal and the frequency of the input periodic signal, and generating an output clock control variable based on the clock count result; and generating an output control signal based on the base clock control variable and the output clock control variable, and generating an output clock signal based on the output control signal and the base clock signal. According to the control method described in claim 10, wherein the processing of generating the clock counting result includes: When the input representative signal is at an inactive level, use a clock counter to count the number of cycles of the basic clock signal; when the input representative signal is at a valid level, update the counting result of the clock counter to the clock counts the result and clears the clock counter. The control method according to claim 10, wherein the process of generating the basic clock control variable includes: when the input representative signal is at a valid level, based on the frequency of the output clock signal and the frequency of the input periodic signal Initialize the basic clock control variable with a preset multiplication factor between; and when the input representative signal is at an inactive level, based on the frequency of the output clock signal and the frequency of the input periodic signal The preset frequency multiplication coefficient updates the basic clock control variable. The control method according to claim 12, wherein the process of updating the basic clock control variable includes: based on the variable value and A preset frequency multiplication coefficient between the frequency of the output clock signal and the frequency of the input periodic signal is used to calculate the update variable value of the basic clock control variable; and when the current effective edge of the basic clock signal comes, The base clock control variable is updated with the calculated update variable value. The control method according to claim 10, wherein the process of generating the output clock control variable includes: when the input representative signal is at a valid level, initializing the output clock control variable based on the clock count result; and updating the output clock control variable based on the clock counting result when the input representative signal is at an inactive level. The control method according to claim 14, wherein the process of updating the output clock control variable includes: based on the variable value temporarily updated when the output clock control variable comes at the previous valid edge of the basic clock signal, The clock counting result and the output control signal are used to calculate the output clock The updated variable value of the control variable, wherein the output control signal represents the size comparison between the basic clock control variable and the variable value updated when the previous valid edge of the basic clock signal comes. relationship; and updating the output clock control variable with the calculated update variable value when the current effective edge of the basic clock signal comes. The control method according to claim 15, wherein the output control signal is logic 1 when the basic clock control variable is greater than the output clock control variable, and is logic 1 when the basic clock control variable is not greater than the output clock control variable Logical 0 when variable. The control method according to claim 10, wherein the process of generating the output clock signal includes: using a comparator to generate a variable comparison signal based on the basic clock control variable and the output clock control variable; signal and the variable comparison signal, using a third D flip-flop to generate the output control signal; and based on the basic clock signal and the output control signal, using a second AND gate to generate the output clock signal. According to the control method described in claim 10, wherein the processing of generating the clock counting result and the processing of generating the basic clock control variable and the output clock control variable use the rising edge of the basic clock signal as an effective edge, The processing of generating the input characterization signal and the processing of generating the output clock signal take the falling edge of the basic clock signal as an effective edge, or the processing of generating the clock counting result and generating the basic clock control variable and the The process of outputting the clock control variable takes the falling edge of the basic clock signal as a valid edge, and the process of generating the input representative signal and the process of generating the output clock signal take the rising edge of the basic clock signal as a valid edge.

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