TWI803375B - Method for fabricating semiconductor device having contact structure - Google Patents

Abstract

The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a semiconductor substrate including an active region and an isolation structure. The method also includes forming a contact structure on the active region of the semiconductor substrate. The method further includes forming a dielectric spacer on opposite sides of the contact structure. The method also includes forming a conductive element on the isolation structure of the semiconductor substrate, wherein the dielectric spacer has a concave surface facing the conductive element.

Description

Method for producing semiconductor element with contact structure

This application claims priority to US Patent Application Nos. 17/723,764 and 17/724,161 (ie, the priority date is "April 19, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a method for manufacturing a semiconductor device, in particular to a method for manufacturing a semiconductor device with a contact structure.

With the rapid development of the electronics industry, the development of semiconductor components has achieved high performance and miniaturization. As the dimensions of semiconductor components shrink, unintended short circuits between conductive features have become a critical issue.

The above "prior art" description is only to provide background technology, and does not acknowledge that the above "prior art" description discloses the subject of this disclosure, and does not constitute the prior art of this disclosure, and any description of the above "prior art" shall not form part of this case.

One aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate, a contact structure, a first conductive element, and a first dielectric spacer structure. The semiconductor substrate includes an active region and an isolation structure. The contact structure is located on the semiconductor on the active region of the bulk substrate. The first conductive element is located on the isolation structure of the semiconductor substrate. The first dielectric interstitial substructure is located between the contact structure and the first conductive element. The first dielectric gap substructure has a first concave surface facing the first conductive element.

Another aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate, a contact structure, and a dielectric spacer. The contact structure is located on the semiconductor substrate. The half-contact structure has a first side and a second side opposite to the half-first side. The semi-dielectric spacer is adjacent to the semi-contact structure and has a first concave surface.

Another aspect of the present disclosure provides a method for manufacturing a semiconductor device. The preparation method includes providing a semiconductor base, and the semiconductor base includes an active region and an isolation structure. The manufacturing method also includes forming a contact structure on the active region of the semiconductor substrate. The fabrication method also includes forming a dielectric spacer on opposite sides of the contact structure. The manufacturing method further includes forming a conductive element on the isolation structure of the semiconductor substrate, wherein the dielectric spacer has a concave surface facing the conductive element.

In semiconductor devices, through the network structure design of dielectric spacers, contact structures (such as bit line contacts) and conductive elements (such as contacts with capacitors) can be relatively large by dielectric spacers. The distances are spaced apart so that undesired short circuits between contact structures (eg, bitline contacts) and conductive elements (eg, contacts to capacitors) are effectively prevented.

The technical features and advantages of the present disclosure have been broadly summarized above, so that the following detailed description of the present disclosure can be better understood. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those skilled in the art of the present disclosure should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. The technical field to which this disclosure belongs Those with ordinary knowledge should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims.

1: Semiconductor components

1A: Semiconductor components

2-2': Cross section line

10: Semiconductor substrate

20: Contact structure

20A: Contact structure

20B: Contact structure

20C: Contact structure

20D: Contact structure

30: Conductive element

30A: conductive element

30B: Conductive element

30C: Conductive elements

30D: Conductive element

30E: Conductive elements

40: Dielectric Interstitial Substructures

40A: Dielectric interstitial substructure

40B: Dielectric Interstitial Substructure

40C: Dielectric interstitial substructure

40D: Dielectric gap substructure

40E: Dielectric Interstitial Substructures

45:Dielectric spacers

50A: Dielectric structure

50B: Dielectric structure

50C: Dielectric structure

50D: Dielectric structure

60: buffer layer

60A: Cushioning material

70: passivation layer

80: Conductive structure

81: Conductive layer

82: Conductive layer

90: Hard mask structure

110: active area

130: Isolation structure

201: side

202: side

203: lateral surface

204: lateral surface

300: pattern sacrificial layer

301: curved surface

310: opening

360: bottom layer

370: Anti-reflection coating

400: pattern mask layer

400A: mask material

401: Concave

401A: Concave

401B: Concave

401C: Concave

402: surface

402C: surface

410: dielectric layer

410A: part

410B: part

420: dielectric layer

420A: part

420B: part

430: dielectric layer

440: part

600: ditches

600A: Ditch

600B: Ditch

600C: Ditch

600D: Ditch

600E: Ditch

800: Preparation method

R1: Region

R2: area

The disclosure content of the present application can be understood more comprehensively when referring to the embodiments and the patent scope of the application for combined consideration of the drawings, and the same reference numerals in the drawings refer to the same components.

FIG. 1 is a top view illustrating a semiconductor device of some embodiments of the present disclosure.

FIG. 2A is a cross-sectional view illustrating a semiconductor device of some embodiments of the present disclosure.

FIG. 2B is a cross-sectional view illustrating a semiconductor device of some embodiments of the present disclosure.

FIG. 3A illustrates one or more fabrication stages, illustrating a fabrication method of a semiconductor device according to some embodiments of the present disclosure.

FIG. 3B is one or more fabrication stages, illustrating the fabrication method of the semiconductor device according to some embodiments of the present disclosure.

FIG. 4A is one or more fabrication stages, illustrating the fabrication method of the semiconductor device according to some embodiments of the present disclosure.

FIG. 4B is one or more fabrication stages, illustrating the fabrication method of the semiconductor device according to some embodiments of the present disclosure.

FIG. 5A illustrates one or more fabrication stages, illustrating a fabrication method of a semiconductor device according to some embodiments of the present disclosure.

FIG. 5B is one or more fabrication stages, illustrating the fabrication method of the semiconductor device according to some embodiments of the present disclosure.

FIG. 6A is one or more fabrication stages, illustrating the fabrication method of the semiconductor device according to some embodiments of the present disclosure.

Figure 6B is one or more stages of fabrication illustrating semiconductor devices according to some embodiments of the present disclosure method of preparation.

FIG. 7A is one or more fabrication stages, illustrating the fabrication method of the semiconductor device according to some embodiments of the present disclosure.

FIG. 7B is one or more fabrication stages, illustrating the fabrication method of the semiconductor device according to some embodiments of the present disclosure.

FIG. 8 is a flowchart illustrating a method for fabricating a semiconductor device according to some embodiments of the present disclosure.

Embodiments, or examples, of the present disclosure illustrated in the drawings will now be described in specific language. It should be understood that no limitation of the scope of the present disclosure is intended herein. Any changes or modifications to the described embodiments, and any further applications of the principles described herein, are considered to be within the ordinary skill of the art to which this disclosure pertains. Reference numerals may be repeated throughout an embodiment, but this does not necessarily mean that features of one embodiment are applicable to another embodiment, even if they share the same reference numeral.

It will be understood that although the terms first, second, third etc. may be used to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections should not be limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the inventive concept.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concepts. As used herein, the singular forms "a", "an" and "the" also include plural forms unless the context clearly dictates otherwise. It should be further understood that the words "comprises" and "comprises", when used in this specification, indicate that the features, integers, steps steps, operations, elements or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components or groups thereof.

FIG. 1 is a top view illustrating a semiconductor device 1 according to some embodiments of the present disclosure. The semiconductor element 1 includes a semiconductor substrate 10, one or more contact structures (such as contact structures 20, 20A, 20B, 20C, and 20D), one or more conductive elements (such as conductive elements 30, 30A, 30B, 30C, 30D, and 30E ), the dielectric spacer 45, and the buffer layer 60. It should be noted that some elements may be omitted for clarity.

The semiconductor substrate 10 may include one or more active regions 110 and one or more isolation structures 130 adjacent to the active regions 110 . In some embodiments, the active region 110 of the semiconductor substrate 10 may be defined by the isolation structure 130 . The semiconductor substrate 10 may comprise or include, for example, silicon, doped silicon, silicon germanium, silicon-on-insulator, silicon-on-sapphire, silicon-germanium-on-insulator, silicon carbide, germanium, gallium arsenide, gallium phosphide, arsenide Gallium phosphide, indium phosphide, gallium indium phosphide or any other Group IV-IV, III-V or I-VI semiconductor material. The isolation structure 130 may comprise or include an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

The contact structure 20 can be disposed or formed on the semiconductor substrate 10 . In some embodiments, the contact structure 20 is disposed or formed on the active region 110 of the semiconductor substrate 10 . In some embodiments, the contact structure 20 has a side 201 (also referred to as a "side" or "side surface") and a side 202 (also referred to as a "side" or "side surface") opposite to the side 201 . In some embodiments, the contact structure 20 further has a side surface 203 (also referred to as “side”) extending between the side 201 and the side 202 . In some embodiments, the side surface 203 may be or include a concave arc-shaped surface. In some embodiments, the contact structure 20 further has a side surface 204 (also referred to as a “side surface”) extending between the side 201 and the side 202 . In some embodiments, side surface 204 is opposite side surface 203 . In some embodiments, the side surface 204 may be or include a concave arc-shaped surface.

In some embodiments, the side surface 203 and the side surface 204 of the contact structure 20 are recessed in opposite directions. In some embodiments, the side surfaces 203 and 204 of the contact structure 20 are recessed toward the interior of the contact structure 20 . In some embodiments, from a top view, the side surface 203 and the side surface 204 of the contact structure 20 are concave arc-shaped surfaces.

In some embodiments, the contact structure 20 may include a conductive material, such as doped polysilicon, metal, or metal silicide. The metal can be, for example, aluminum, copper, tungsten, cobalt, or alloys thereof. The metal silicide may be, for example, nickel silicide, platinum silicide, titanium silicide, molybdenum silicide, cobalt silicide, tantalum silicide, tungsten silicide, or the like. In some embodiments, the contact structure 20 includes doped polysilicon. In some embodiments, the contact structure 20 can be used as a bit line contact.

The conductive element 30 can be disposed or formed on the semiconductor substrate 10 . In some embodiments, the conductive element 30 is disposed or formed on the isolation structure 130 of the semiconductor substrate 10 . In some embodiments, conductive element 30 has a curved surface 301 . In some embodiments, conductive element 30 may comprise or include silicon or metal. Metals may include, for example, aluminum, copper, tungsten or cobalt. In some embodiments, conductive element 30 may include doped materials including silicon (Si), germanium (Ge), phosphorus (P), arsenic (As), antimony (Sb), or any combination thereof. In some embodiments, conductive element 30 may comprise or include doped polysilicon. In some embodiments, conductive element 30 may comprise or include aluminum, copper, tungsten, cobalt, or alloys thereof. In some embodiments, conductive element 30 may comprise or include metal nitride or metal silicide. In some embodiments, the conductive element 30 can be used as a contact plug to be electrically connected to the capacitor.

The dielectric spacer 45 may be adjacent to the contact structure 20 and have at least one concave surface (eg, concave surfaces 401 , 401A, 401B, and 401C). In some embodiments, conductive element 30 is partially surrounded by concave surface 401 of dielectric spacer 45 . In some embodiments, the curvature of the curved surface 301 of the conductive element 30 is greater than the curvature of the concave surface 401 of the dielectric spacer 45 .

In some embodiments, the dielectric spacers 45 have a mesh structure. In some embodiments, dielectric spacer 45 includes a plurality of dielectric spacer structures (eg, dielectric spacer structures 40, 40A, 40B, 40C, 40D, and 40E) and a plurality of dielectric structures (eg, dielectric Structures 50A, 50B, 50C and 50D). Dielectric structures 50A, 50B, 50C, and 50D may comprise or include dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. In some embodiments, dielectric structures 50A, 50B, 50C, and 50D include silicon nitride.

In some embodiments, dielectric interstitial substructures 40 , 40A, 40B, 40C, 40D, and 40E are connected to dielectric structures 50A, 50B, 50C, and 50D. In some embodiments, dielectric interstitial substructures 40 and 40A are connected to each other through dielectric structure 50A. In some embodiments, dielectric interstitial substructures 40 and 40B are connected to each other through dielectric structure 50B. In some embodiments, dielectric interstitial substructures 40C and 40D are connected to each other through dielectric structure 50C. In some embodiments, dielectric interstitial substructures 40C and 40E are connected to each other through dielectric structure 50D.

In some embodiments, the dielectric interstitial substructure 40 is located on the side 201 of the contact structure 20 and has a concave surface 401 . In some embodiments, the dielectric interstitial substructure 40 is located between the contact structure 20 and the conductive element 30 . In some embodiments, the concave surface 401 of the dielectric interstitial substructure 40 faces the conductive element 30 . In some embodiments, the concave surface 401 of the dielectric spacer substructure 40 surrounds a portion of the conductive element 30 . In some embodiments, the dielectric interstitial substructure 40 further has a surface 402 opposite to the concave surface 401 . In some embodiments, the surface 402 of the dielectric interstitial substructure 40 is in direct contact with the contact structure 20 . In some embodiments, the surface 402 of the dielectric interstitial substructure 40 is a substantially planar surface.

In some embodiments, the dielectric interstitial substructure 40 has a U-shaped structure when viewed from a top view. In some embodiments, the dielectric interstitial substructure 40 includes dielectric layers 410 , 420 and 430 .

In some embodiments, the dielectric layer 410 is located on the side 201 of the contact structure 20 . In some embodiments, the dielectric layer 410 has a U-shaped structure viewed from a top view. In some embodiments, the dielectric layer 410 includes a portion 410A at the side 201 of the contact structure 20 and a portion 410B adjacent to the conductive element 30 . In some embodiments, portion 410A of dielectric layer 410 is in contact with side 201 of contact structure 20 . In some embodiments, the portion 410A of the dielectric layer 410 has a U-shaped structure when viewed from a top view. In some embodiments, portion 410A of dielectric layer 410 has a concave surface facing conductive element 30 . In some embodiments, the portion 410B of the dielectric layer 410 is in contact with the isolation structure 130 of the semiconductor substrate 10 . In some embodiments, portion 410B of dielectric layer 410 is in contact with conductive element 30 . In some embodiments, the portion 410B of the dielectric layer 410 has a U-shaped structure when viewed from a top view. In some embodiments, portion 410B of dielectric layer 410 has a concave surface (eg, concave surface 401 ) facing conductive element 30 . The dielectric layer 410 may comprise or include a dielectric material, such as silicon oxide, silicon nitride, silicon oxide, or a combination thereof. In some embodiments, the dielectric layer 410 includes silicon nitride.

In some embodiments, dielectric layer 420 is adjacent to dielectric layer 410 . In some embodiments, the dielectric layer 420 has a U-shaped structure viewed from a top view. In some embodiments, dielectric layer 420 includes a portion 420A adjacent side 201 of contact structure 20 and a portion 420B adjacent conductive element 30 . In some embodiments, portion 420A of dielectric layer 410 is in contact with portion 410A of dielectric layer 410 . In some embodiments, the portion 420A of the dielectric layer 420 has a U-shaped structure when viewed from a top view. In some embodiments, portion 420A of dielectric layer 420 has a concave surface facing conductive element 30 . In some embodiments, portion 420B of dielectric layer 420 is in contact with portion 410B of dielectric layer 410 . In some embodiments, the portion 420B of the dielectric layer 420 has a U-shaped structure when viewed from a top view. In some embodiments, portion 420B of dielectric layer 420 has a concave surface facing conductive element 30 . The dielectric layer 420 may comprise or include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some embodiments, the dielectric layer 420 includes silicon oxide.

In some embodiments, dielectric layer 430 is adjacent to dielectric layer 420 . In some embodiments, dielectric layer 430 is located between portion 420A and portion 420B of dielectric layer 420 . In some embodiments, the dielectric layer 430 has a U-shaped structure viewed from a top view. In some embodiments, dielectric layer 430 has a concave surface facing conductive element 30 . The dielectric layer 430 may comprise or include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some embodiments, the dielectric layer 430 includes silicon nitride.

In some embodiments, conductive element 30A is adjacent to conductive element 30 . In some embodiments, the conductive element 30A is disposed or formed on the isolation structure 130 of the semiconductor substrate 10 .

In some embodiments, dielectric interstitial substructure 40A is adjacent to conductive element 30A. In some embodiments, dielectric interstitial substructure 40A is located between contact structure 20A and conductive element 30A. In some embodiments, the dielectric interstitial substructure 40A has a concave surface 401A facing the conductive element 30A. In some embodiments, the concave surface 401A of the dielectric spacer substructure 40A surrounds a portion of the conductive element 30A. In some embodiments, the dielectric interstitial substructure 40A further has a substantially planar surface opposite to the concave surface 401A and in direct contact with the contact structure 20A. In some embodiments, the dielectric interstitial substructure 40A has a U-shaped structure when viewed from the top.

In some embodiments, the concave surface 401 of the dielectric spacer substructure 40 faces in the opposite direction from the concave surface 401A of the dielectric spacer substructure 40A.

In some embodiments, dielectric structure 50A is disposed or formed between dielectric interstitial substructure 40 and dielectric interstitial substructure 40A. In some embodiments, dielectric structure 50A is in direct contact with dielectric interstitial substructure 40 and dielectric interstitial substructure 40A.

In some embodiments, conductive element 30C is adjacent to conductive element 30 . In some embodiments, the conductive element 30C is disposed or formed on the isolation structure 130 of the semiconductor substrate 10 superior.

In some embodiments, the dielectric interstitial substructure 40C is located on the side 202 of the contact structure 20 and has a concave surface 401C. In some embodiments, dielectric interstitial substructure 40C is located between contact structure 20 and conductive element 30C. In some embodiments, the concave surface 401C of the dielectric interstitial substructure 40C faces the conductive element 30C. In some embodiments, the concave surface 401C of the dielectric interstitial substructure 40C surrounds a portion of the conductive element 30C. In some embodiments, the dielectric interstitial substructure 40C further has a surface 402C opposite to the concave surface 401C. In some embodiments, surface 402C of dielectric interstitial substructure 40C is in direct contact with contact structure 20 . In some embodiments, the surface 402C of the dielectric interstitial substructure 40C is a substantially planar surface. In some embodiments, the dielectric interstitial substructure 40C has a U-shaped structure when viewed from the top.

In some embodiments, dielectric interstitial substructure 40 and dielectric interstitial substructure 40C are disposed on opposite sides 201 and 202 of contact structure 20 . In some embodiments, the concave surface 401 of the dielectric spacer substructure 40 faces in the opposite direction to the concave surface 401C of the dielectric spacer substructure 40C.

In some embodiments, conductive element 30B is adjacent to conductive element 30 . In some embodiments, the conductive element 30B is disposed or formed on the isolation structure 130 of the semiconductor substrate 10 .

In some embodiments, dielectric interstitial substructure 40B is adjacent to conductive element 30B. In some embodiments, dielectric interstitial substructure 40B is located between contact structure 20B and conductive element 30B. In some embodiments, the dielectric interstitial substructure 40B has a concave surface 401B facing the conductive element 30B. In some embodiments, the concave surface 401B of the dielectric interstitial substructure 40B surrounds a portion of the conductive element 30B. In some embodiments, the dielectric interstitial substructure 40B further has a substantially planar surface opposite to the concave surface 401B and in direct contact with the contact structure 20B. In some embodiments, the dielectric interstitial substructure 40B has a U-shaped structure when viewed from the top.

In some embodiments, the concave surface 401 of the dielectric spacer substructure 40 faces in the opposite direction to the concave surface 401B of the dielectric spacer substructure 40B.

In some embodiments, dielectric structure 50B is disposed or formed between dielectric interstitial substructure 40 and dielectric interstitial substructure 40B. In some embodiments, dielectric structure 50B is in direct contact with dielectric interstitial substructure 40 and dielectric interstitial substructure 40B.

In some embodiments, conductive element 30D is adjacent to conductive element 30C. In some embodiments, the conductive element 30D is disposed or formed on the isolation structure 130 of the semiconductor substrate 10 .

In some embodiments, dielectric interstitial substructure 40D is adjacent to conductive element 30D. In some embodiments, dielectric interstitial substructure 40D is located between contact structure 20C and conductive element 30D. In some embodiments, dielectric interstitial substructure 40D has a concave surface facing conductive element 30D. In some embodiments, the concave surface of the dielectric spacer substructure 40D surrounds a portion of the conductive element 30D. In some embodiments, the dielectric interstitial substructure 40D further has a substantially planar surface opposite the concave surface and in direct contact with the contact structure 20C. In some embodiments, the dielectric interstitial substructure 40D has a U-shaped structure when viewed from the top.

In some embodiments, the concave surface 401C of the dielectric spacer substructure 40C faces in the opposite direction to the concave surface of the dielectric spacer substructure 40D.

In some embodiments, dielectric structure 50C is disposed or formed between dielectric interstitial substructure 40C and dielectric interstitial substructure 40D. In some embodiments, dielectric structure 50C is in direct contact with dielectric interstitial substructure 40C and dielectric interstitial substructure 40D.

In some embodiments, conductive element 30E is adjacent to conductive element 30C. In some embodiments, the conductive element 30E is disposed or formed on the isolation structure 130 of the semiconductor substrate 10 .

In some embodiments, dielectric interstitial substructure 40E is adjacent to conductive element 30E. In some embodiments, dielectric interstitial substructure 40E is located between contact structure 20D and conductive element 30E. In some embodiments, dielectric interstitial substructure 40E has a concave surface facing conductive element 30E. In some embodiments, the concave surface of dielectric interstitial substructure 40E surrounds a portion of conductive element 30E. In some embodiments, the dielectric interstitial substructure 40E further has a substantially planar surface opposite the concave surface and in direct contact with the contact structure 20D. In some embodiments, the dielectric interstitial substructure 40E has a U-shaped structure when viewed from the top.

In some embodiments, the concave surface 401C of the dielectric spacer substructure 40C faces in the opposite direction to the concave surface of the dielectric spacer substructure 40D.

In some embodiments, dielectric structure 50D is disposed or formed between dielectric interstitial substructure 40C and dielectric interstitial substructure 40D. In some embodiments, dielectric structure 50D is in direct contact with dielectric interstitial substructure 40C and dielectric interstitial substructure 40D.

The buffer layer 60 may be a pattern layer defined by the contact structures 20 , 20A, 20B, 20C and 20D and the dielectric spacers 45 . In some embodiments, buffer layer 60 is in direct contact with dielectric spacer 45 . The buffer layer 60 can be formed as a stack or a single layer, including silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, fluorine-doped silicate, and the like. In some embodiments, buffer layer 60 includes silicon nitride.

According to some embodiments of the present disclosure, through the network structure design of the dielectric spacers 45, the contact structure 20 and the conductive element 30 can be separated from each other by a relatively large distance generated by the dielectric spacers 45, thus effectively Undesirable short circuits between contact structures 20 (eg, bit line contacts) and conductive elements 30 (eg, contacts to capacitors) are prevented.

In addition, according to some embodiments of the present disclosure, the dielectric spacer 45 has at least one concave arc-shaped surface facing the conductive element 30 , and the conductive element 30 can be formed by the dielectric spacer 45 partially surrounded. Thus, an electrical isolation between the contact structure 20 and the conductive element 30 can be achieved by a relatively large displacement tolerance of the contact structure 20 and the conductive element 30 during production. Therefore, the reliability of the semiconductor device 1 is improved, and the process stability and process window are both improved.

Furthermore, according to some embodiments of the present disclosure, since the specific network structure of the dielectric spacers 45 defines the shape design of the contact structure 20 , the contact area of the contact structure 20 can be increased. Therefore, resistance can be reduced, and thus electrical performance can be improved.

FIG. 2A is a cross-sectional view illustrating a semiconductor device 1 according to some embodiments of the present disclosure. In some embodiments, FIG. 2A is a cross-sectional view along cross-section line 2-2' in FIG. 1 .

In some embodiments, the semiconductor device 1 includes a semiconductor substrate 10, one or more contact structures (such as the contact structure 20), one or more conductive elements (such as the conductive elements 30 and 30C), a dielectric spacer 45, a buffer layer 60 , passivation layer 70 , conductive structure 80 , and hard mask structure 90 .

The semiconductor substrate 10 may include one or more active regions 110 and one or more isolation structures 130 adjacent to the active regions 110 . In some embodiments, the active region 110 of the semiconductor substrate 10 may be defined by the isolation structure 130 . The semiconductor substrate 10 may comprise or include, for example, silicon, doped silicon, silicon germanium, silicon-on-insulator, silicon-on-sapphire, silicon-germanium-on-insulator, silicon carbide, germanium, gallium arsenide, gallium phosphide, arsenide Gallium phosphide, indium phosphide, gallium indium phosphide or any other Group IV-IV, III-V or I-VI semiconductor material. The isolation structure 130 may comprise or include an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

In some embodiments, the contact structure 20 is disposed or formed on the active region 110 of the semiconductor substrate 10 . In some embodiments, a part of the contact structure 20 is disposed or formed on the isolation structure 130 of the semiconductor substrate 10 .

In some embodiments, the contact structure 20 may include a conductive material, such as doped polysilicon, metal, or metal silicide. The metal can be, for example, aluminum, copper, tungsten, cobalt, or alloys thereof. The metal silicide may be, for example, nickel silicide, platinum silicide, titanium silicide, molybdenum silicide, cobalt silicide, tantalum silicide, tungsten silicide, or the like. In some embodiments, the contact structure 20 includes doped polysilicon. In some embodiments, the contact structure 20 can be used as a bit line contact.

In some embodiments, the conductive element 30 is disposed or formed on the isolation structure 130 of the semiconductor substrate 10 . In some embodiments, a portion of the conductive element 30 is disposed on and spaced apart from the active region 110 of the semiconductor substrate 10 . In some embodiments, the conductive element 30 is spaced apart from the contact structure 20 . In some embodiments, the conductive element 30 is separated from the contact structure 20 by the dielectric spacer substructure 40 and the isolation structure 130 of the semiconductor substrate 10 .

In some embodiments, the conductive element 30C is disposed or formed on the isolation structure 130 of the semiconductor substrate 10 . In some embodiments, the conductive element 30C is separated from the isolation structure 130 of the semiconductor substrate 10 by a dielectric spacer 45 . In some embodiments, the conductive element 30C is disposed or formed on a portion of the active region 110 of the semiconductor substrate 10 . In some embodiments, conductive element 30C is spaced apart from contact structure 20 . In some embodiments, the conductive element 30C is separated from the contact structure 20 by the dielectric spacer substructure 40 and the isolation structure 130 of the semiconductor substrate 10 .

In some embodiments, conductive elements 30 and 30C may comprise or include silicon or metal. Metals may include, for example, aluminum, copper, tungsten or cobalt. In some embodiments, conductive elements 30 and 30C may include doped materials including silicon (Si), germanium (Ge), phosphorus (P), arsenic (As), antimony (Sb), or any combination thereof. In some embodiments, conductive elements 30 and 30C may comprise or include doped polysilicon. In some embodiments, conductive elements 30 and 30C may comprise or include aluminum, copper, tungsten, cobalt, or alloys thereof. In some embodiments, conductive elements 30 and 30C may comprise or include metal nitrides or metal silicides. In some embodiments, each conductive element 30 and 30C can be used as a contact plug to be electrically connected to the capacitor.

Dielectric spacers 45 may be adjacent to contact structures 20 . In some embodiments, the dielectric layer 420 of the dielectric spacer 45 is disposed or formed on the dielectric layer 410 of the dielectric spacer 45 . In some embodiments, the dielectric layer 430 of the dielectric spacer 45 is disposed or formed on the dielectric layer 420 of the dielectric spacer 45 .

The dielectric layer 420 may comprise or include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some embodiments, the dielectric layer 420 includes silicon nitride. The dielectric layer 420 may comprise or include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some embodiments, the dielectric layer 420 includes silicon oxide. The dielectric layer 430 may comprise or include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some embodiments, the dielectric layer 430 includes silicon nitride.

In some embodiments, buffer layer 60 is in direct contact with dielectric spacer 45 . In some embodiments, the buffer layer 60 is in direct contact with the active region 110 and the isolation structure 130 of the semiconductor substrate 10 .

In some embodiments, the passivation layer 70 is disposed or formed on the buffer layer 60 . In some embodiments, passivation layer 70 is in direct contact with buffer layer 60 . The passivation layer 70 can be formed as a stack or a single layer, including silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, fluorine-doped silicate, and the like. In some embodiments, passivation layer 70 includes silicon oxide.

The conductive structure 80 can be disposed on the semiconductor substrate 10 . In some embodiments, one or more portions of conductive structure 80 are disposed on contact structure 20 . In some embodiments, a portion of the conductive structure 80 is disposed on the buffer layer 60 . In some embodiments, a portion of the conductive structure 80 is disposed on the passivation layer 70 .

In some embodiments, the conductive structure 80 includes conductive layers 81 and 82 . In some embodiments, one or more portions of conductive layer 81 are disposed on contact structure 20 . In some embodiments, part of the conductive layer 81 is disposed on the buffer layer 60 . In some embodiments, a portion of the conductive layer 81 is disposed on the passivation layer 70 . In some embodiments, the conductive layer 82 is disposed on the conductive layer 81 . Conductive layer 81 may include, for example, polysilicon or titanium nitride. Conductive layer 82 may include, for example, copper, nickel, cobalt, aluminum, or tungsten. In some embodiments, conductive structure 80 (eg, conductive layers 81 and 82 ) includes a bit line layer.

The hard mask structure 90 can be disposed on the conductive structure 80 . In some embodiments, each portion of hard mask structure 90 is disposed between adjacent dielectric spacer substructures (eg, dielectric spacer substructures 40 and 40C).

According to some embodiments, with the design of the network structure of the dielectric spacers 45, although the contact structure 20 is not formed in the exact predetermined position (for example, most of the conductive element 30C contacts the semiconductor element 1 shown in FIG. 2A The active region 110 , instead of the conductive element 30C most contacts the isolation structure 130 of the semiconductor element, the electrical isolation between the contact structure 20 and the conductive element 30 can be realized by the dielectric spacer 45 .

FIG. 2B is a cross-sectional view illustrating a semiconductor device 1A according to some embodiments of the present disclosure. In some embodiments, FIG. 2B is a cross-sectional view along cross-section line 2-2' in FIG. 1 . The semiconductor element 1A is similar to the semiconductor element 1 shown in FIG. 2A with differences as follows. Descriptions of similar components are omitted.

In some embodiments, the conductive element 30 is disposed or formed on the isolation structure 130 of the semiconductor substrate 10 . In some embodiments, a portion of the conductive element 30 is disposed on and spaced apart from the active region 110 of the semiconductor substrate 10 . In some embodiments, the conductive element 30 is spaced apart from the contact structure 20 . In some embodiments, the conductive element 30 is interposed by the semiconductor substrate 10 The electrical gap substructure 40 is spaced apart from the isolation structure 130 from the contact structure 20 .

In some embodiments, the conductive element 30C is disposed or formed on the isolation structure 130 of the semiconductor substrate 10 . In some embodiments, the conductive element 30C is disposed or formed on a portion of the active region 110 of the semiconductor substrate 10 . In some embodiments, the conductive element 30C is in direct contact with a portion of the isolation structure 130 of the semiconductor substrate 10 . In some embodiments, conductive element 30C is spaced apart from contact structure 20 . In some embodiments, the conductive element 30C is separated from the contact structure 20 by the dielectric interstitial substructure 40 and the isolation structure 130 of the semiconductor substrate 10 . In some embodiments, each of the conductive elements 30 and 30C may serve as a contact plug electrically connected to the capacitor.

According to some embodiments, with the design of the network structure of the dielectric spacers 45, although the contact structure 20 is not formed in the exact predetermined position (for example, only a small part of the conductive element 30C contacts the semiconductor element shown in FIG. 2B 1A, instead of the isolation structure 130 in which the conductive element 30C mostly contacts the semiconductor element), the electrical isolation between the contact structure 20 and the conductive element 30 can be realized by a dielectric spacer 45 .

FIG. 3A to FIG. 7B are various manufacturing stages, illustrating the manufacturing method of the semiconductor device 1 according to some embodiments of the present disclosure.

3A and 3B illustrate one or more fabrication stages, illustrating the fabrication methods of semiconductor devices according to some embodiments of the present disclosure. In some embodiments, FIG. 3A is a top view illustrating a portion of the structure in FIG. 3B.

Referring to FIGS. 3A and 3B , a semiconductor substrate 10 may be provided. The semiconductor substrate 10 may comprise, for example, silicon, doped silicon, silicon germanium, silicon on insulator, silicon on sapphire, silicon germanium on insulator, silicon carbide, germanium, gallium arsenide, gallium phosphide, gallium arsenide phosphide compound, indium phosphide, indium gallium phosphide, or any other group IV-IV, III-V or I-VI semiconductor material.

Still referring to FIGS. 3A and 3B , an isolation structure 130 may be formed in the semiconductor substrate 10 , and the active region 110 of the semiconductor substrate 10 may be defined by the isolation structure 130 . A photolithography process may be performed to pattern the semiconductor substrate 10 to define the positions of the plurality of active regions 110 . An etching process may be performed after the lithography process to form a plurality of trenches in the semiconductor substrate 10 . After the etch process, the trenches may be filled with an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or fluorine-doped silicate by a deposition process. After the deposition process, a planarization process, such as chemical mechanical polishing, may be performed to remove excess material and provide a substantially flat surface for subsequent process steps to conformally form the isolation structure 130 and the active region 110 .

Still referring to FIGS. 3A and 3B , a buffer material 60A may be formed on the semiconductor substrate 10 . The buffer material 60A can be formed as a stack or a single layer, including silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, fluorine-doped silicate, and the like.

Still referring to FIGS. 3A and 3B , a bottom layer 360 may be formed on the buffer material 60A. In some embodiments, bottom layer 360 includes organic materials. In some embodiments, bottom layer 360 includes a polymeric material. In some embodiments, bottom layer 360 acts as a planarization layer. In some embodiments, bottom layer 360 has a thickness of about 200 nm.

Still referring to FIGS. 3A and 3B , an anti-reflection coating 370 may be formed on the bottom layer 360 . In some embodiments, antireflective coating 370 is in direct contact with bottom layer 360 . In some embodiments, antireflective coating 370 includes an inorganic material. In some embodiments, anti-reflective coating 370 includes silicon oxynitride. In some embodiments, the antireflective coating 370 may include two subcoats with different silicon to oxygen (Si/O) atomic ratios. In some embodiments, the antireflective coating 370 has a thickness of about 30 nanometers.

Still referring to FIGS. 3A and 3B , a patterned sacrificial material can be formed on the buffer material 60A. Sacrifice layer 300. In some embodiments, the patterned sacrificial layer 300 is formed on the anti-reflection coating 370 . In some embodiments, the patterned sacrificial layer 300 has an opening 310 to expose the region R2 of the semiconductor substrate 10 . In some embodiments, the region R1 of the semiconductor substrate 10 is covered by the patterned sacrificial layer 300 .

In some embodiments, the patterned sacrificial layer 300 may include an ashable hard mask layer. In some embodiments, the patterned sacrificial layer 300 includes a carbon-based material. In some embodiments, the patterned sacrificial layer 300 includes amorphous carbon. In some embodiments, the thickness of the patterned sacrificial layer 300 is about 60 nm.

4A and 4B illustrate one or more fabrication stages, illustrating the fabrication methods of semiconductor devices according to some embodiments of the present disclosure. In some embodiments, FIG. 4A is a top view illustrating a portion of the structure in FIG. 4B.

Referring to FIGS. 4A and 4B , a mask material may be formed on the patterned sacrificial layer 300 and in the opening 310 . In some embodiments, the mask material 400A includes an oxide, such as silicon oxide. In some embodiments, the mask material 400A covers the patterned sacrificial layer 300 .

FIG. 5A and FIG. 5B illustrate one or more fabrication stages, illustrating the fabrication methods of semiconductor devices according to some embodiments of the present disclosure. In some embodiments, FIG. 5A is a top view illustrating a portion of the structure in FIG. 5B.

Referring to FIGS. 5A and 5B , the patterned sacrificial layer 300 may be removed to form a patterned mask layer 400 . In some embodiments, a portion of the mask material 400A outside the opening 310 of the patterned sacrificial layer 300 is removed, eg, by etching. In some embodiments, after the portion of the masking material 400A outside the openings of the patterned sacrificial layer 300 is removed, the remaining portion of the masking material 400A forms the patterned masking layer 400 in the openings 310 of the patterned sacrificial layer 300 . In some embodiments, the patterned sacrificial layer 300 is removed by heat treatment. In some embodiments, the patterned sacrificial layer 300 includes carbon, and oxygen is introduced under heat treatment to react with carbon to form carbon dioxide gas as a by-product, and the A patterned sacrificial layer 300 is formed on the stamping material 60A.

In some embodiments, the pattern mask layer 400 exposes the region R1 of the semiconductor substrate 10 . In some embodiments, the pattern mask layer 400 includes a plurality of portions 440 to cover the region R2 of the semiconductor substrate 10 .

6A and 6B illustrate one or more fabrication stages, illustrating the fabrication methods of semiconductor devices according to some embodiments of the present disclosure. In some embodiments, FIG. 6B is a cross-sectional view along cross-section line 2-2' in FIG. 6A.

Referring to FIGS. 6A and 6B , a portion of the buffer material 60A can be removed according to the pattern mask layer 400 to form the buffer layer 60 to expose the region R1 of the semiconductor substrate 10 , and the pattern mask layer 400 can be removed.

In some embodiments, one or more contact structures (eg, contact structures 20 , 20A, 20B, 20C, and 20D) are formed on the region R1 of the semiconductor substrate 10 . In some embodiments, a dielectric spacer 45 is formed on the region R1 of the semiconductor substrate 10 . In some embodiments, one or more trenches (eg, trenches 600 , 600A, 600B, 600C, 600D, and 600E) are formed on the region R2 of the semiconductor substrate 10 .

In some embodiments, one or more contact structures (eg, contact structures 20 , 20A, 20B, 20C, and 20D) are formed on the active region 110 of the semiconductor substrate 10 . In some embodiments, dielectric spacers 45 (eg, dielectric spacer structures 40 and 40C) are formed on opposite sides 201 and 202 of at least one of contact structures 20 , 20A, 20B, 20C, and 20D.

7A and 7B illustrate one or more fabrication stages, illustrating the fabrication methods of semiconductor devices according to some embodiments of the present disclosure. In some embodiments, FIG. 7B is a cross-sectional view along cross-section line 2-2' in FIG. 7A.

7A and 7B, on the isolation structure 130 of the semiconductor substrate 10 is formed One or more conductive elements (eg, conductive elements 30 , 30A, 30B, 30C, 30D, and 30E). In some embodiments, the conductive elements 30 , 30A, 30B, 30C, 30D and 30E are formed on the region R2 of the semiconductor substrate 10 . In some embodiments, conductive material may be filled in the trenches 600 , 600A, 600B, 600C, 600D and 600E to form the conductive elements 30 , 30A, 30B, 30C, 30D and 30E. In some embodiments, the conductive material may be polysilicon or doped polysilicon. Thus, the semiconductor element 1 is formed.

FIG. 8 is a flowchart illustrating a method 800 for fabricating a semiconductor device according to some embodiments of the present disclosure.

The fabrication method 800 starts with operation S81, wherein a semiconductor substrate including an active region and an isolation structure is provided.

The fabrication method 800 continues with operation S82, wherein a contact structure is formed on the active region of the semiconductor substrate.

The fabrication method 800 continues with operation S83, wherein a dielectric spacer is formed on opposite sides of the contact structure.

The fabrication method 800 continues with operation S84, wherein a conductive element is formed on the isolation structure of the semiconductor substrate. In some embodiments, the dielectric spacer has a concave surface facing the conductive element.

The preparation method 800 is merely an example, and is not intended to limit the content of the present disclosure beyond what is expressly mentioned in the claims. Additional operations may be provided before, during, or after each operation of manufacturing method 800, and some of the operations described may be replaced, eliminated, or moved for additional embodiments of the manufacturing method. In some embodiments, preparation method 800 may include further operations not depicted in FIG. 8 . In some embodiments, preparation method 800 may include one or more of the operations depicted in FIG. 8 .

One aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate, a contact structure, a first conductive element, and a first dielectric spacer structure. The semiconductor substrate includes an active region and an isolation structure. The contact structure is located on the active region of the semiconductor substrate. The first conductive element is located on the isolation structure of the semiconductor substrate. The first dielectric interstitial substructure is located between the contact structure and the first conductive element. The first dielectric gap substructure has a first concave surface facing the first conductive element.

Another aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate, a contact structure, and a dielectric spacer. The contact structure is located on the semiconductor substrate. The half-contact structure has a first side and a second side opposite to the half-first side. The semi-dielectric spacer is adjacent to the semi-contact structure and has a first concave surface.

Another aspect of the present disclosure provides a method for manufacturing a semiconductor device. The preparation method includes providing a semiconductor base, and the semiconductor base includes an active region and an isolation structure. The manufacturing method also includes forming a contact structure on the active region of the semiconductor substrate. The fabrication method also includes forming a dielectric spacer on opposite sides of the contact structure. The manufacturing method further includes forming a conductive element on the isolation structure of the semiconductor substrate, wherein the dielectric spacer has a concave surface facing the conductive element.

In semiconductor devices, through the network structure design of dielectric spacers, contact structures (such as bit line contacts) and conductive elements (such as contacts with capacitors) can be relatively large by dielectric spacers. The distances are spaced apart so that undesired short circuits between contact structures (eg, bitline contacts) and conductive elements (eg, contacts to capacitors) are effectively prevented.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the present disclosure as defined by the claims. example For example, many of the processes described above can be implemented in different ways and replaced by other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure of this disclosure that existing or future developed processes, machinery, manufacturing, A composition of matter, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patent scope of this application.

1: Semiconductor components

2-2': Cross section line

10: Semiconductor substrate

20: Contact structure

20A: Contact structure

20B: Contact structure

20C: Contact structure

20D: Contact structure

30: Conductive element

30A: conductive element

30B: Conductive element

30C: Conductive elements

30D: Conductive element

30E: Conductive elements

40: Dielectric Interstitial Substructures

40A: Dielectric interstitial substructure

40B: Dielectric Interstitial Substructure

40C: Dielectric interstitial substructure

40D: Dielectric gap substructure

40E: Dielectric Interstitial Substructures

45:Dielectric spacers

50A: Dielectric structure

50B: Dielectric structure

50C: Dielectric structure

50D: Dielectric structure

60: buffer layer

110: active area

130: Isolation structure

201: side

202: side

203: side surface

204: side surface

301: curved surface

401: Concave

401A: Concave

401B: Concave

401C: Concave

402: surface

402C: surface

410: dielectric layer

410A: part

410B: part

420: dielectric layer

420A: part

420B: part

430: dielectric layer

Claims (18)

A method for preparing a semiconductor element, comprising: providing a semiconductor substrate; forming a contact structure on the semiconductor substrate, the contact structure having a first side and a second side opposite to the first side; forming a contact structure with the contact structure a dielectric spacer adjacent to and having a first concave surface; and a first conductive element formed on the semiconductor substrate, wherein the first conductive element is partially surrounded by the first concave surface of the dielectric spacer. The manufacturing method as claimed in claim 1, wherein forming the dielectric spacer comprises: forming a first dielectric spacer structure on the first side of the contact structure and having the first concave surface. The manufacturing method according to claim 2, wherein forming the dielectric spacer further includes: forming a second dielectric spacer structure on the second side of the contact structure, and having a second concave surface, wherein the first The concave surface faces opposite to the second concave surface. The manufacturing method as claimed in claim 3, wherein the first dielectric interstitial substructure and the second dielectric interstitial substructure are formed to have a U-shaped structure viewed from a top view. The manufacturing method according to claim 1, wherein the contact structure has a first side surface extending between the first side and the second side, and the first side surface includes a concave arc-shaped surface. The manufacturing method as claimed in claim 5, wherein the contact structure has a second side surface opposite to the first side surface, and the second side surface includes a concave arc-shaped surface. The preparation method according to claim 6, wherein the first side surface and the second side surface are recessed toward opposite directions. The manufacturing method as claimed in claim 1, wherein the first conductive element has an arc-shaped surface, and a curvature of the arc-shaped surface of the first conductive element is greater than a curvature of the concave surface of the dielectric spacer. The preparation method as claimed in item 1, wherein forming the dielectric spacer includes: forming a first dielectric layer on the first side of the contact structure; and forming a second dielectric layer on the first dielectric layer The electrical layer, wherein the second dielectric layer has a U-shaped structure viewed from a top view. A method for manufacturing a semiconductor element, comprising: providing a semiconductor substrate including an active region and an isolation structure; forming a contact structure on the active region of the semiconductor substrate; forming a dielectric gap on opposite sides of the contact structure and forming a conductive element on the isolation structure of the semiconductor substrate, wherein the dielectric spacer has a concave surface facing the conductive element. The preparation method according to claim 10, further comprising: forming a buffer material on the semiconductor substrate; and forming a pattern mask layer on the buffer material, the pattern mask layer exposing a first region of the semiconductor substrate . The manufacturing method as claimed in claim 11, wherein the pattern mask layer includes a plurality of parts to cover a second region of the semiconductor substrate. The manufacturing method as claimed in claim 12, wherein the conductive element is formed on the second region of the semiconductor substrate. The manufacturing method as claimed in claim 11, further comprising: removing a part of the buffer material according to the pattern mask layer to form a buffer layer to expose the first region of the semiconductor substrate; and removing the pattern mask layer. The manufacturing method as claimed in claim 14, wherein the dielectric spacer is formed on the first region of the semiconductor substrate. The manufacturing method as claimed in claim 14, wherein the contact structure is formed on the first region of the semiconductor substrate. The preparation method as claimed in item 11, wherein forming the pattern mask layer comprises: forming a pattern sacrificial layer on the buffer material, the pattern sacrificial layer having an opening to expose a second region of the semiconductor substrate; forming a mask material on the pattern sacrificial layer and in the opening; and removing the pattern sacrificial layer to form the pattern mask layer. The manufacturing method as claimed in claim 17, wherein the pattern sacrificial layer includes carbon, and the mask material includes oxide.

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