TWI802980B - An apparatus for writing ternary content addressable memory devices and the related method - Google Patents

Abstract

Ternary content-addressable memory (TCAM) devices are described. The TCAMs described herein are designed to perform write operations—including data writes and mask writes—in a single clock cycle. For example, data input is written in a row of the TCAM during the first portion of a clock cycle, and a mask is written in another row of the TCAM during the second portion of the clock cycle. In one implementation, a first bus is used both for data write and key search operations, and a second bus is used both for mask write and search masking operations. In another implementation, a first bus is used both for data write and key search operations, a second bus is used for mask write operations, and a third bus is used for search masking operations.

Description

A device and method for writing tri-state content addressable memory

The present application relates to storage technology, and more particularly, to methods and apparatus for writing to tri-state content-addressable memory.

Content-addressable memory (CAM) is a type of computer memory designed specifically for search-intensive applications. Due to its parallel nature, CAM is much faster at searching than random access memory (RAM) architectures. CAMs are commonly used in Internet routers and switches to increase the speed of route lookup, packet classification, and packet forwarding.

Ternary CAMs, or TCAMs, are designed to store and query data using three different inputs (0, 1, and X). The "X" input, often referred to as a "don't care" or "wildcard" state, enables TCAM to perform broader lookups based on pattern matching, as opposed to binary CAM, which only Use 0 and 1 to perform an exact match lookup.

The present invention provides a method and apparatus for writing a ternary content addressable memory (TCAM), which performs a write operation including a write data input and a write mask in a single clock cycle, thereby, by Increasing the speed at which write operations can be performed significantly increases memory availability.

Some embodiments relate to an apparatus for writing to a tri-state content-addressable memory (TCAM), the apparatus comprising a tri-state content-addressable memory (TCAM) and a control circuit, the tri-state content-addressable memory (TCAM) includes a first multi-column storage unit (first plurality of rows of memory cells) and a second multi-column storage unit (second plurality of rows of memory cells), and the first multi-column storage unit is configured to store a plurality of corresponding Data input; and, the second multi-column storage unit is configured to store a plurality of corresponding masks (mask); the control circuit is configured to: write the data input into the column of the first multi-column storage unit in the first clock cycle (row), and, during the first clock cycle, the mask is written into the columns of the second multi-column memory cell.

In some embodiments, the control circuit is configured to: write the data input into the columns of the first multi-column memory cells in response to the first edge of the first clock cycle, and is further configured to: respond to The mask is written into the columns of the second plurality of columns of memory cells on a second edge of the first clock cycle.

In some embodiments, the columns of the first multi-column memory unit and the columns of the second multi-column memory unit share a common address.

In some embodiments, the columns of the first multi-column of memory cells and the columns of the second multi-column of memory cells are adjacent to each other.

In some embodiments, the TCAM further includes a first bus and a second bus, and the control circuit is configured to: use the first bus to write the data input into a column of the first multi-column memory unit; and , using the second bus to write the mask into the columns of the second multi-column memory unit.

In some embodiments, the control circuit is further configured to use the first bus to look up a key in the first multi-column memory unit.

In some embodiments, the control circuit is further configured to mask one or more rows of the TCAM during a seek operation using the second bus.

In some embodiments, the TCAM further includes a first bus, a second bus, and a third bus, and the control circuit is configured to: use the first bus to write the data input into the first multi-column memory unit using the second bus to write the mask into the columns of the second multi-column memory cell; and using the third bus to mask one or more columns of the TCAM during a lookup operation.

In some embodiments, the control circuit is further configured to use the second bus to look up a key in the first multi-column of memory cells.

In some embodiments, the control circuit is further configured to mask one or more rows of the TCAM during a seek operation using the first bus.

Some embodiments relate to a method for writing to a ternary content addressable memory (TCAM), comprising: writing data input into a column of a first multi-column of memory cells during a first clock cycle, wherein the The first multi-column storage unit is configured to store a plurality of corresponding data inputs; and, During the first clock cycle, a mask is written to a column of a second multi-column of memory cells configured to store a plurality of corresponding masks.

In some embodiments, writing the data input includes: writing the data input in response to a first edge of the first clock cycle; and writing the mask includes: responding to a second edge of the first clock cycle Write to this mask.

In some embodiments, the columns of the first multi-column of memory cells and the columns of the second multi-column of memory cells are adjacent to each other.

In some embodiments, writing the data input includes: writing the data input using a first bus; and writing the mask and: writing the mask using a second bus.

In some embodiments, the method further includes: using the first bus to search for a key in the first multi-column storage unit.

In some embodiments, the method further includes masking one or more rows of the TCAM during a seek operation using the second bus.

In some embodiments, writing the data input includes: writing the data input in response to a first edge of the first clock cycle, and writing the mask includes: writing a predetermined time interval after the first edge into this mask.

This summary is provided by way of example and is not intended to limit the invention. Other embodiments and advantages are described in the detailed description below. The present invention is limited by the scope of the patent application.

The following descriptions are preferred embodiments for implementing the present invention. The following examples are only used to illustrate the technical characteristics of the present invention, and are not intended to limit the scope of the present invention. Certain terms are used throughout the specification and claims to refer to particular components. It should be understood by those skilled in the art that manufacturers may use different terms to refer to the same component. This description and the scope of the patent application do not use the difference in name as the way to distinguish components, but the difference in function of the components as the basis for distinction. The scope of the present invention should be determined with reference to the appended claims. The terms "comprising" and "comprising" mentioned in the following description and scope of patent application are open-ended terms, so they should be interpreted as the meaning of "including, but not limited to...". Also, the term "coupled" means an indirect or direct electrical connection. Therefore, if it is described that a device is coupled to another device, it means that the device may be directly electrically connected to the other device, or indirectly electrically connected to the other device through other devices or connection means. The term "basically" or "approximately" used herein means that within an acceptable range, a person with ordinary knowledge in the technical field can solve the technical problem to be solved and basically achieve the technical effect to be achieved. For example, "approximately equal to" means that there is a certain error from "exactly equal to" that can be accepted by those with ordinary knowledge in the technical field without affecting the correctness of the result.

As modern applications such as artificial intelligence, databases, and network switching drive ever-increasing demands on network bandwidth, there is an increasing need for high-speed memory, and in particular, high-speed TCAM. The architecture of TCAM makes it particularly suitable for computer network equipment, such as switches and routers. Although the operation speed of TCAM has been significantly improved in recent years, it is still not enough to meet the requirements of some network applications.

Applicants have recognized that increasing the speed at which write operations are performed at the TCAM will significantly enhance the applicability of these types of memories. Therefore, the present invention proposes a TCAM architecture designed to increase the speed of write operations. The TCAM architecture proposed by the present invention is designed to perform a write operation in a single clock cycle (single clock cycle), and the write operation includes data (data) write and mask (mask) write. In some embodiments, for example, during the first part of the clock cycle, the data input (data input) is written to the data column (data row) of the TCAM entry (entry), and, during the second part of the same clock cycle During part of the period, the mask is written to the mask column (mask row) of the TCAM entry.

Some embodiments of the present invention relate to a TCAM architecture in which a first bus is used for both data write and key search operations, and a second bus is used for masking Write (mask write) and search masking (search masking) operations. During a write operation, the first bus transfers the data input to the data row of the TCAM entry, and, during this same clock cycle, the second bus transfers the mask (called the "local mask (local mask) mask)") to the corresponding mask row of the TCAM entry. During a lookup operation, the first bus transmits the key to be looked up (key) to the TCAM, and the second bus transmits the bits used to mask the key lookup (these bits are called the "row mask ( column mask)"). Masking a keyword lookup involves returning results (as matched or not matched), independent of the value of the masked row (column). For example, when a particular bit of the mask is asserted, the corresponding row of the TCAM is masked, meaning that the memory is able to return a match whether or not that particular row produced a match.

Optionally, other configurations are also possible, for example, the first bus is used for data writing and lookup mask operations, and the second bus is used for mask writing and key lookup operations. Specifically, the present invention is not limited.

Other embodiments relate to a TCAM architecture in which a first bus is used for data write and key lookup operations, a second bus is used for mask write operations, and a third bus is used for lookup mask operations . During a write operation, the first bus transfers the data input to the data column of the TCAM entry, and, during this same clock cycle, the second bus transfers the mask (called the "local mask") to the TCAM The corresponding mask column for the entry. During a lookup operation, the first bus transmits the key to be looked up to the TCAM, and the third bus transmits the bits used to mask the key lookup (these bits may be referred to as "column masks"). "). Other configurations are also possible. For example, the second bus may be used instead of the first bus to perform keyword search operations.

Figure 1A illustrates a TCAM, according to some embodiments. The TCAM includes an array of memory cells arranged in columns (row) and rows (column). Each cell includes static random access memory (SRAM), alternatively or additionally other types of memory may be used. A TCAM has a number of rows (0, 1, 2, 3, . . . , n-1, n) and a number of columns (0, 1 . . . , 2 ^m-1 ). Each column includes a pair of sub-columns (which includes a first sub-column and a second sub-column). The first sub-column ("data row") is used to store the data, and the second sub-column ("mask row") is used to store the mask. A data bit is identified by the letter "X", and a mask bit is identified by the letter "Y". The data column and mask column of a common (common) TCAM entry are adjacent to each other in the TCAM. For example, for the first TCAM entry, it includes the first data row (such as data row 0) and the first mask row (mask row 0) adjacent to the first data row, and the second TCAM entry includes the second data row (such as data column 1) and a second mask column (masked column 1) adjacent to the second data column. In some embodiments, the data column and mask column of a common TCAM entry (common TCAM entry) share a common memory address, thereby reducing the number of bits required to address the entire memory by one unit. For example, the data row of a single TCAM entry and the mask row corresponding to the data row share a common memory address, for example, the common memory address can point to the data row in the TCAM entry, and, in the An address offset by a preset amount based on the common memory address may point to the corresponding mask column in the TCAM entry.

Each partial mask consists of a number of bits. The value of each partial mask bit determines whether the corresponding data bit is masked or not. Representative logic for partial masking operations is shown in the table of Figure 1B, according to some embodiments. In this example, the state of a particular bit is 1 when the data is set to 1 and the local mask is set to 0. Conversely, when the data is set to 0 and the partial mask is set to 1, the state of the particular bit is 0. When both the local mask and the data are set to 1, the state of the corresponding data bit is "don't care". Finally, combinations where both the local mask and profile are set to 0 are not supported. It should be understood that other logic than that depicted in FIG. 1B may also be used, as the bitmask is not limited to any particular logic.

Figure 2A is a block schematic diagram of a TCAM architecture according to some embodiments. The architecture includes a control circuit 200 and a TCAM 202 . TCAM 202 may be arranged according to the schematic diagram shown in Figure 1A. The architecture is designed to increase the speed of write TCAM operations relative to previous implementations. More specifically, the architecture is designed to write data inputs and local masks in a single clock cycle. For example, data input can be written to data column 0 and a partial mask can be written to mask column 0 in the same clock cycle. The TCAM bus is configured to support data input and mask write operations in a single clock cycle. As shown in Figure 2A, the control circuit 200 communicates with the TCAM 202 using the following buses: CLK, A, SDI, DI, MASKB, CS, WE, RD, SR, and SCU.

The control circuit 200 provides clocks to the TCAM 202 via the bus CLK. Bus A (memory address) is used to provide addresses for write and read operations. For example, during a write operation, if bus A indicates column 5, a write operation is performed on column 5. Similarly, during a read operation, if bus A indicates column 5, the TCAM returns the contents of column 5.

Bus SDI is used for both write and seek operations. During a write operation, bus DI carries the data input to be written to the data column identified by bus A, and bus SDI carries the local mask to be written to the mask column identified by bus A. During a lookup operation, the bus SDI carries the key to be looked up in the entire TCAM.

The bus MASKB is used during seek operations. In particular, bus MASKB includes column mask bits that identify which rows are to be masked and which are not to be masked during lookup.

The bus SCU (single cyle update, single cycle update) is used to enable (enable) single clock cycle operation, for example, when SCU is set to 1, the memory operates in single clock cycle mode (understandably, the opposite logic is also possible of). The bus CS (chip select, chip select) is used to select a specific TCAM chip from a group of multiple TCAM chips. When it is set to 1, bus CS enables operation on a particular TCAM chip (understandably, the reverse logic is also possible). The bus WE (memory write) is used to enable write operations (in some embodiments, with the opposite value relative to SCU). For example, when WE is 0, the single clock cycle write operation is enabled, and when WE is 1, the single clock cycle write operation is disabled (the opposite logic is also feasible, specifically, the present invention does not limit this) . Bus SR is used to enable seek operations. For example, when the SR is 1, the search operation is enabled, and when the SR is 0, the search operation is disabled (the opposite logic is also feasible, and the present invention does not limit this). Bus RD is used to enable read operations. For example, when RD is 1, the read operation is enabled, and when RD is 0, the read operation is disabled (the opposite logic is also feasible, and the present invention is not limited to this).

Output bus DO is used to return the contents of the column identified by bus A during a read operation. The output bus HIT is used during a lookup operation to return the address of the column for which a match has been identified.

Figure 2B shows a schematic diagram of a non-limiting implementation of TCAM 202, according to some embodiments. In this embodiment, TCAM 202 includes flip-flops (flip-flop) 250 (such as DI input latch), 252 (such as SDI input flip-flop) and 254 (such as MASKB input latch), logic unit (logic unit ) 256 and 258, multiplexers (multiplexers) 260 and 262, control unit 264, and TCAM row 270 (in particular, one of the rows in the TCAM array), which includes SRAM (or other type of Memory). TCAM 202 receives signals over buses DI, SDI, MASKB, CLK, WE, SCU, and A (as discussed in connection with Figure 2A).

The flip-flop 250 receives the signal of the bus DI (for example, data, shown as "Data(X-word)" in the figure) as an input, and the flip-flop 252 receives the signal of the bus SDI (for example, a mask, shown as "Mask( Y-word)") as an input, and the flip-flop 254 receives a signal of the bus MASKB (eg, a global mask during a search operation (during search)) as an input. The operation of the clock CLK timing (time) flip-flop. The output of flip-flop 250 is provided as input to multiplexers 260 and 262, respectively. The output of flip-flop 252 is provided as input to logic units 256 and 258, respectively. The state of the logic unit is controlled by the output of flip-flop 254 . The signal on the bus SCU indicates whether a single-clock write operation is to be performed (single-clock write operation), so that, in the case of indicating a single-clock write operation (for example, if the bus SCU is asserted), write in the same clock cycle Both data entry and masking. However, if bus SCU is not asserted, the write operation is performed according to the conventional scheme whereby the data input and corresponding mask are written in a single clock cycle. In this case, the SCU enables multiplexers 260 and 262 . The bus A signal indicates the address of the TCAM entry to be written or read. For a normal write, when WE is 1, multiplexers 260 and 262 select material on the DI bus during a full clock cycle (input S1 on the multiplexer is selected). In the process of writing in a single clock cycle, the ENB signal on the multiplexer is switched according to the timing signal in the same clock cycle, so that S1 or S2 is selected as the input on the multiplexer in the same cycle. Logical units 256 and 258 are used only during lookup operations. During a write operation, logic units 256 and 258 feed through the output of flip-flop 252 . The bus MASKB is used to mask data on a particular row during a seek operation.

Figure 2C illustrates a sequence representative of a write operation, according to some embodiments. The figure shows the bus CLK, SCU (Single Cyle Update, single cycle update), CS (Chip Select, chip selection), WE (memory write, memory write), A (memory address, memory address), DI , the relationship between the signals of SDI and MASKB. When the signal CS is set to 1, the signal CS indicates that the TCAM chip has been selected. When signal SCU is set to 1 and signal WE is set to 0, a single clock write is performed. Conversely, when the signal SCU is set to 0 and the signal WE is set to 1, a multi-clock write will be performed.

Signal A provides the address of the column to be written (labeled "TCAM Address" in the figure). In this example, the address (in hex) is "000". The content of the signal DI represents the data input (marked as "Data/X" in the figure) to be written into the addressed TCAM data row. In this example, the content of DI is "aaaaa". The content of signal SDI represents the mask to be written into the addressed TCAM mask column (labeled "Mask/Y" in the figure). In this example, the content of SDI is "55555". In this sequence, the content of DI and the content of SDI are both written in the same clock cycle (i.e. single clock write). During the write operation, the content of signal MASKB ("fffff" in this example) is not considered.

FIG. 3A is a block diagram illustrating another TCAM architecture according to some embodiments. Similar to the architecture of Figure 2A, this architecture is also designed to write the data inputs and masks in a single clock cycle. However, this architecture involves fewer busses than that of Figure 2A, thereby reducing circuit complexity.

The architecture includes a control circuit 300 and a TCAM 302 . TCAM 302 may be arranged according to the schematic diagram shown in Figure 1A. The TCAM bus is arranged to support data input and mask write operations in a single clock cycle. As shown in Figure 3A, the control circuit 300 communicates with the TCAM 302 using the following buses: CLK, A, SDI, MASKB, CS, WE, RD, SCU, and SR. It should be noted that, unlike the example of Fig. 2A, this architecture does not include the bus DI. In this architecture, both bus SDI and MASKB have dual functions. During a single clock cycle write operation, bus SDI carries the data input to be written, and MASKB carries the local mask to be written. During a lookup operation, bus SDI carries the key to be looked up, and MASKB carries row mask bits which identify which rows are to be masked (optionally, bus MASKB can carry the key to be looked up, and , SDI carries mask bits that identify which rows are masked, specifically, the present invention does not make a limitation). Essentially, both SDI and MASKB are used in a time-division multiplexed manner. The buses CLK, A, CS, WE, RD, SCU and SR have the same functions as described in Fig. 2A. The output buses DO and HIT also have the same function as described in Fig. 2A.

Figure 3B shows a schematic diagram of a non-limiting implementation of TCAM 302, according to some embodiments. In this embodiment, TCAM 302 includes flip-flops 350 , 352 and 354 , logic units 346 , 348 , 356 and 358 , multiplexers 360 and 362 , control unit 364 and TCAM row 370 . For example, TCAM array 370 may include SRAM (or other type of memory) arranged as shown in FIG. 1A. TCAM 302 receives signals over buses SDI, MASKB, CLK, WE, SCU, and A (as discussed in connection with Figure 3A).

Logic unit 346 receives as input the signal of bus SDI, and logic unit 348 receives as input the signal of bus MASKB. The signal on the bus SCU indicates whether to perform a write operation including write data input and mask in a single clock cycle. In this example, the SCU controls the state of logic units 346 and 348 .

Flip-flop 350 receives the signal of bus SDI as input, flip-flop 352 receives the output of logic unit 346 as input, and flip-flop 354 receives the output of logic unit 348 as input. Clock CLK timing flip-flop operation. The output of flip-flop 350 is provided as input to multiplexers 360 and 362, respectively. The output of flip-flop 352 is provided as input to logic units 356 and 358, respectively. The state of logic units 356 and 358 is controlled by the output of flip-flop 354 . The bus A signal indicates the address of the column of the TCAM to be written or read. During the write operation, the signal of the bus WE is asserted, which enables the multiplexers 360 and 362 to be used for the write operation. During a write operation, control unit 364 enables writing to TCAM array 370 , and the output of the flip-flop writes to the TCAM array through transistors 366 and 368 . The bus A signal determines the address of the column to be written. During a lookup operation, logic units 356 and 358 mask the lookup of a particular column according to the value of the corresponding mask bit of MASKB.

Figure 3C illustrates a sequence of representative write operations related to the architecture of Figure 3A, according to some embodiments. This figure illustrates the relationship between the signals of the buses CLK, SCU, WE, A, SDI and MASKB. When SCU is set to 1, CS is set to 1, and WE is set to 0, a write operation of a single clock cycle will be performed in the TCAM chip.

Signal A provides the address of the column to be written. The content of signal SDI represents the data input to be written to the addressed TCAM row. The content of signal MASKB indicates the local mask to be written to the addressed TCAM mask column. In this sequence, both the contents of SDI and the contents of MASKB are written in a single clock cycle.

As mentioned above, according to the present application, different architectures can be used to realize TCAM. Regardless of the specific architecture used, the TCAM described here is configured to perform data writes and mask writes in the same clock cycle. In some embodiments, the data write is performed in a first part of a clock cycle, and the mask write is performed in a second part of the same clock cycle (it will be understood that the reverse order is also possible, and the present invention without any restrictions). For example, data writing can be triggered by the first edge (rising or falling) of a clock cycle, while mask writing can be triggered by the second edge of the same clock cycle. In some embodiments, a decoder is used to enable write operations in this manner.

Figure 4A depicts an exemplary decoder, according to some embodiments. In this example, the TCAM array is arranged as discussed in Figure 1A. Each column (whether data or mask) is coupled to an input register (labeled "WLDRV" in the diagram). The control signals XPZ_EN_EVEN and XPZ_EN_ODD are used to control the timing at which the registers transfer their respective contents to the columns of the TCAM. Decoder (labeled "XDECODER" in the figure), used to select the TCAM entries to be updated. Depending on the value of address bus A, the appropriate WLDRV is selected and then used to enable the odd or even WL bus depending on the state of XPZ_EN_ODD or XPZ_EN_EVEN. The material received on the input buses SDI and MASKB is sent on the signal BL/BLB. Examples of these control signals are shown in Figure 4B, according to some embodiments. In this example, the control signals XPZ_EN_EVEN and XPZ_EN_ODD have the same frequency as the clock CLK. Furthermore, the control signals XPZ_EN_EVEN and XPZ_EN_ODD are phase-shifted relative to each other. The edge (for example, rising edge) of the control signal XPZ_EN_EVEN triggers data writing into a specific data column. Similarly, an edge of the control signal XPZ_EN_ODD (eg, the rising edge immediately following the triggering rising edge of XPZ_EN_EVEN) triggers writing of the partial mask to the corresponding (eg, adjacent) mask column.

The use of ordinal terms such as "first", "second", "third", etc. in a claim to modify a claimed element does not in itself indicate any priority of one claimed element over another claimed element , priority or order, or chronological order in which method actions are performed, but are used only as markers to use ordinal numbers to distinguish one patentable element having the same name from another element element having the same name.

Although the embodiments of the present invention and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made to the present invention without departing from the spirit of the present invention and within the scope defined by the patent scope of the application, for example, New embodiments can be obtained by combining parts of different embodiments. The described embodiments are in all respects for the purpose of illustration only and are not intended to limit the invention. The scope of protection of the present invention should be defined by the scope of the appended patent application. Those skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention.

200,300: control circuit 202,302: TCAM 250,252,254,350,352,354: triggers 256,258,346,348,356,358: logic unit 260,262,360,362: multiplexer 264,364: Control unit 270,370: TCAM row 366,368: Transistor

A more complete understanding of the invention can be obtained by reading the ensuing detailed description and the examples, which are given with reference to the accompanying drawings. FIG. 1A is a schematic block diagram of a tri-state content addressable memory (TCAM) according to some embodiments. Figure 1B is a schematic diagram that may be used to determine the status of the TCAM of Figure 1A, according to some embodiments. Figure 2A is a block schematic diagram of a TCAM architecture according to some embodiments. Figure 2B is a block schematic diagram illustrating a non-limiting implementation of the TCAM architecture of Figure 2A, shown according to some embodiments. Figure 2C is a schematic diagram illustrating control signals used in conjunction with the TCAM architecture of Figure 2A, according to some embodiments. FIG. 3A is a block diagram illustrating another TCAM architecture according to some embodiments. Figure 3B is a block schematic diagram illustrating a non-limiting implementation of the TCAM architecture of Figure 3A, according to some embodiments. Figure 3C is a schematic diagram illustrating control signals used in conjunction with the TCAM architecture of Figure 3A, according to some embodiments. Figure 4A is a block schematic diagram illustrating a TCAM array coupled to a decoder, according to some embodiments. Figure 4B is a schematic diagram illustrating control signals used in conjunction with the TCAM of Figure 4A, according to some embodiments.

In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to enable those skilled in the art to better understand the embodiments of the present invention. It is evident, however, that one or more embodiments may be practiced without these specific details, that different embodiments or different features disclosed in different embodiments may be combined as desired and should not be limited to the drawings Examples of what was done.

200: control circuit

202: TCAM

Claims (15)

An apparatus for writing a tri-state content addressable memory TCAM, comprising the TCAM and a control circuit, the TCAM comprising: a first multi-column memory cell configured to store a plurality of corresponding data inputs; and, a second A multi-column memory unit configured to store a plurality of corresponding masks; the control circuit is configured to: write data input into a column of the first multi-column memory unit in a first clock cycle; and, in the second clock cycle In a clock cycle, the mask is written into the column of the second multi-column storage unit; wherein, the TCAM also includes a first bus and a second bus, and the control circuit is configured to: utilize the first bus to the data input is written into the columns of the first multi-column memory unit; and, using the second bus, the mask is written into the column of the second multi-column memory unit. The device of claim 1, wherein the control circuit is configured to: write the data input into the row of the first multi-row memory unit in response to the first edge of the first clock cycle, and, in response to the The second edge of the first clock cycle writes the mask into the columns of the second multi-column memory cells. The device of claim 1, wherein the columns of the first multi-rank memory unit and the corresponding columns of the second multi-rank memory unit share a common address. The device of claim 1, wherein the columns of the first multi-column memory unit and the corresponding columns of the second multi-column memory unit are adjacent to each other. The device according to claim 1, wherein the control circuit is further configured to use the first bus to search for a key in the first multi-column memory unit. The device of claim 1 or 5, wherein the control circuit is further configured to mask one or more rows of the TCAM during a seek operation using the second bus. The device according to claim 1, wherein the TCAM further includes a third bus, and the The control circuit is configured to mask the row or rows of the TCAM with the third bus during a seek operation. The device according to claim 1, wherein the control circuit is further configured to use the second bus to search for a key in the first multi-column memory unit. The device of claim 1 or 5, wherein the control circuit is further configured to mask one or more rows of the TCAM during a seek operation using the first bus. A method for writing a tri-state content addressable memory (TCAM), comprising: writing data input into columns of a first plurality of columns of memory cells during a first clock cycle, wherein the first plurality of columns the storage unit is configured to store a plurality of corresponding data inputs; and, during the first clock cycle, the mask is written into a column of a second multi-column of storage unit, wherein the second multi-column of storage unit is configured to storing a plurality of corresponding masks; wherein, writing the data input includes: using the first bus to write the data input; and writing the mask includes: using the second bus to write the mask. The method of claim 10, wherein writing the data input includes: writing the data input in response to a first edge of the first clock cycle; and writing the mask includes: responding to a first edge of the first clock cycle The second edge writes the mask. The method of claim 10, wherein the columns of the first multi-column memory unit and the columns of the second multi-column memory unit are adjacent to each other. The method according to claim 10, further comprising: using the first bus to search for a key in the first multi-column storage unit. The method of claim 13, further comprising: masking one or more rows of the TCAM during a seek operation using the second bus. The method of claim 10, wherein writing the data input includes: writing the data input in response to a first edge of the first clock cycle, and writing the mask includes: The mask is written after a predetermined interval of edges.

Images