TWI799034B - Semiconductor package having thin substrate and method of making the same - Google Patents

Abstract

A semiconductor package comprises a semiconductor substrate, a first metal layer, an adhesive layer, a second metal layer, a rigid supporting layer, and a plurality of contact pads. A thickness of the semiconductor substrate is equal to or less than 50 microns. A thickness of the rigid supporting layer is larger than the thickness of the semiconductor substrate. A thickness of the second metal layer is larger than a thickness of the first metal layer. A method comprises the steps of providing a device wafer; providing a supporting wafer; attaching the supporting wafer to the device wafer via an adhesive layer; and applying a singulaton process so as to form a plurality of semiconductor packages.

Description

Semiconductor package with thin substrate and manufacturing method thereof

The present invention generally relates to semiconductor packages having thin semiconductor substrates and methods of manufacturing a plurality of semiconductor packages. More specifically, the present invention relates to a semiconductor package that operates within a sufficient margin of safety and has a substrate with a thickness in the range of 25 microns to 75 microns.

Semiconductor packages typically have a semiconductor substrate thickness of 100 microns or more, such as common-drain metal-oxide-semiconductor field-effect transistor (MOSFET) chip-scale packaging (CSP) and semiconductor power packaging for battery protection applications. The semiconductor substrate provides a large amount of DC resistance. It is advantageous to reduce the thickness of the semiconductor substrate to less than 50 microns, thereby reducing the DC resistance and improving the electrical performance.

Semiconductor substrates provide substantial direct current (DC) resistance. It is advantageous to reduce the thickness of semiconductor substrates to improve electrical performance. For example, when the thickness of the semiconductor substrate is reduced from 50 microns to 25 microns, the on-resistance can be reduced by 24%. When the thickness of the semiconductor substrate is reduced, the mechanical strength of the semiconductor package is reduced. In an example of the present invention, a rigid support layer connected to a metal layer with a Young's modulus of 150 GPa is added to increase mechanical strength. Increasing the thickness of the attached metal layer can further reduce the on-resistance slightly (less sensitive than the effect of changing the thickness of the semiconductor substrate). For example, when the thickness of the attached metal layer is increased from 15 microns to 50 microns, the on-resistance can be reduced by 5%.

A semiconductor package includes a semiconductor substrate, a first metal layer, an adhesive layer, a second metal layer, a rigid support layer and a plurality of contact pads. The thickness of the semiconductor substrate is equal to or less than 75 micrometers. The thickness of the rigid support layer is greater than the thickness of the semiconductor substrate. The thickness of the second metal layer is greater than that of the first metal layer.

A method for manufacturing a plurality of semiconductor packages is disclosed. The method includes the steps of: preparing a device wafer; providing a support wafer; attaching the support wafer to the device wafer through an adhesive layer; and applying a separation process.

FIG. 1 shows a cross-sectional view of a conventional semiconductor package 100 . A conventional semiconductor package 100 includes a plurality of contact pads 102 , a semiconductor substrate 120 , a metal layer 140 and a coating 190 . In one example, substrate 120 is 100 microns thick. Coating 190 does not provide sufficient mechanical strength support for the package. Warpage can occur during surface mount solder reflow.

FIG. 2 shows a cross-sectional view of a conventional semiconductor package 200 . A conventional semiconductor package 200 includes a plurality of contact pads 202 , a semiconductor substrate 220 , a metal layer 240 and a protective tape 294 . In one example, semiconductor substrate 220 is 100 microns thick. The protective tape 294 cannot provide sufficient mechanical strength support for the package. Warpage can occur during surface mount solder reflow.

Figures 3A and 3B of U.S. Patent Application Publication No. 2019/0189569 illustrate a semiconductor package comprising a semiconductor substrate, a metal layer, an adhesive layer, a rigid support layer, and a plurality of contact pads encapsulation. Without an additional metal layer attached to the rigid support layer, the margin of safety included in the mechanical performance requirements of a semiconductor package is not high when the thickness of the semiconductor substrate is reduced to the 50 micron range.

FIG. 3 shows a cross-sectional view of a semiconductor package 300 in an example of the present invention. The semiconductor package 300 includes a semiconductor substrate 320 , a first metal layer 340 , an adhesive layer 360 , a second metal layer 370 , a rigid support layer 380 and a plurality of contact pads 302 .

The semiconductor substrate 320 has a front surface 322 and a back surface 324 . The rear surface 324 is opposite to the front surface 322 . The first metal layer 340 has a front surface 342 and a rear surface 344 . The rear surface 344 is opposite to the front surface 342 . Adhesive layer 360 has a front surface 362 and a rear surface 364 . The rear surface 364 is opposite to the front surface 362 . The second metal layer 370 has a front surface 372 and a rear surface 374 . The rear surface 374 is opposite the front surface 372 . Rigid support layer 380 has a front surface 382 and a rear surface 384 . The rear surface 384 is opposite the front surface 382 .

In an example of the present invention, the front surface 342 of the first metal layer 340 is directly connected to the rear surface 324 of the semiconductor substrate 320 . The front surface 362 of the adhesive layer 360 is directly connected to the rear surface 344 of the first metal layer 340 . The front surface 372 of the second metal layer 370 is directly connected to 364 of the rear surface adhesive layer 360 . The front surface 382 of the rigid support layer 380 is directly connected to the rear surface 374 of the second metal layer 370 . In one example, the plurality of contact pads 302 are connected to the front surface 322 of the semiconductor substrate 320 . In another example, the plurality of contact pads 302 are directly connected to the front surface 322 of the semiconductor substrate 320 .

In one example, the thickness of the semiconductor substrate 320 is equal to or less than 50 microns. In another example, the thickness of the semiconductor substrate 320 is in the range of 25 microns to 35 microns. In an example of the present invention, the thickness of the second metal layer 370 is in the range of 30 microns to 100 microns. The second metal layer 370 provides an electrical path to reduce the on-resistance of the device. The thickness of the first metal layer 340 is in the range of 1 micron to 5 microns. The thickness of the first metal layer 340 is smaller than that of the semiconductor substrate 320 in order to reduce overall warping of the semiconductor package during manufacture. The thickness of the second metal layer 370 is greater than that of the first metal layer 340 . In one example, the edge surfaces of the semiconductor substrate 320 , the second metal layer 370 and the rigid support layer 380 are aligned and coplanar on all sides, respectively. In another example, edge surfaces of the semiconductor substrate 320 , the first metal layer 340 , the second metal layer 370 and the rigid support layer 380 are aligned and coplanar on all sides, respectively. In another example, edge surfaces of semiconductor substrate 320 , first metal layer 340 , adhesive layer 360 , second metal layer 370 , and rigid support layer 380 are aligned and coplanar on all sides, respectively.

In an example of the present invention, the thickness of the supporting layer is 380 microns to 150 microns. The term "rigid" of the rigid support layer 380 refers to a material in the rigid support layer 380 that is harder than the tape material (eg polyimide material or polymer material). The thinner the semiconductor substrate 320, the better the electrical performance of each of the plurality of semiconductor packages. Advantageously, the thickness of the semiconductor substrate 320 is less than 50 microns. If the mechanical performance requirements of the semiconductor package include a safety factor, the rigid support layer 380 has higher strength requirements.

In the example of the present invention, the thickness is measured in a direction parallel to the Z-axis of FIG. 3 . In an example of the invention, the thickness of rigid support layer 380 is the shortest distance between front surface 382 and rear surface 384 . In an example of the present invention, semiconductor substrate 320 includes a silicon material. In an example of the present invention, it is preferred that the semiconductor package (having a planar dimension of 3.05 mm×1.77 mm) be able to withstand more than 5 Newtons without breaking.

In an example of the present invention, adhesive layer 360 includes a conductive adhesive. Rigid support layer 380 is non-conductive. Electric current flows through the semiconductor substrate 320, the first metal layer 340, the adhesive layer 360, the second metal layer 370, the adhesive layer 360, the first metal layer 340 and the semiconductor substrate 320 from the first contact pad in the plurality of contact pads 302. the substrate 320 to the second contact pad of the plurality of contact pads 302 .

In an example of the present invention, the semiconductor package 300 is a common drain metal oxide semiconductor field effect transistor (MOSFET) chip scale package (CSP) for battery protection applications. Two gates and two sources are located on the front surface of the common drain MOSFET CSP. The common drain is located on the backside of the common drain MOSFET CSP.

In an example of the present invention, the entire rigid support layer 380 is made of a material with a relatively high Young's modulus, including single crystal silicon material, polycrystalline silicon material or glass material. In an example of the present invention, the entire rigid support layer 380 is made of a material with a high Young's modulus, including silicon material, glass material or silicon oxide glass material (SiO 2 ). The advantages are cost-effectiveness and lighter semiconductor package weight. In an example of the present invention, the Young's modulus of the entire rigid support layer 380 is in the range of 50% to 150% of the Young's modulus of the semiconductor substrate 320 . The coefficient of thermal expansion (CTE) of the entire rigid support layer 380 is in the range of 50% to 250% of the CTE of the semiconductor substrate 320 .

In an example of the invention, the entirety of the rigid support layer is made of monocrystalline silicon material or polycrystalline silicon material manufactured from recycled silicon wafers. The advantage of using recycled wafers is cost reduction. Recycled silicon wafers are used silicon wafers or recycled silicon wafers. In one example, the silicon wafers used may have been previously used for testing purposes. An etching process and a polishing process are applied to the recycled silicon wafers. The entire first metal layer 340 is made of a material selected from the group consisting of aluminum, nickel, and gold. The entire second metal layer 370 is made of a material selected from the group consisting of titanium, nickel and silver.

FIG. 4 shows a flowchart of a process 400 for fabricating a plurality of semiconductor packages in an example of the present invention. Figures 5A-5D represent cross-sectional views of the corresponding steps. Process 400 may begin at block 402 .

In block 402, referring now to FIG. 5A, a device wafer 502 is prepared. Device wafer 502 may be a 4 inch, 6 inch, 8 inch, 12 inch or 18 inch diameter wafer. The device wafer 502 includes a semiconductor substrate 520 , a first metal layer 540 and a plurality of contact pads 512 . The device wafer 502 may also include a passivation layer 514 (shown in dashed lines). Similar to FIG. 3A of US Patent Application Publication No. 2019/0189569, each of the plurality of contact pads 512 may include a layer of aluminum and a layer of nickel gold. In one example, the first metal layer 540 is directly deposited on the semiconductor substrate 520 .

The semiconductor substrate 520 has a front surface 522 and a rear surface 524 opposite to the front surface 522 of the semiconductor substrate 520 . The first metal layer 540 has a front surface 542 and a rear surface 544 opposite to the front surface 542 of the first metal layer 540 . The front surface 542 of the first metal layer 540 is directly contact-connected to the rear surface 524 of the semiconductor substrate 520 . A plurality of contact pads 512 are connected to the front surface 522 of the semiconductor substrate 520 .

In an example of the present invention, the thickness of the semiconductor substrate 520 is equal to or less than 50 micrometers. The thickness of the semiconductor substrate 520 is in the range of 25 microns to 35 microns. Block 402 may be followed by block 404 .

In block 404, referring now to FIG. 5B, a support wafer 504 is prepared. The support wafer 504 includes a second metal layer 570 and a rigid support layer 580 . The second metal layer 570 has a front surface 572 and a rear surface 574 opposite to the front surface 572 of the second metal layer 570 . The rigid support layer 580 has a front surface 582 opposite the front surface 582 of the second metal layer 570 and a rear surface 584 opposite the front surface 582 of the second metal layer 570 . The front surface 582 of the rigid support layer 580 is directly connected to the rear surface 574 of the second metal layer 570 .

In an example of the present invention, the thickness of the rigid support layer 580 is greater than the thickness of the semiconductor substrate 520 . Rigid support layer 580 is stiffer than the tape material. The thickness of the second metal layer 570 is greater than that of the first metal layer 540 . Rigid support layer 580 is non-conductive. The entire rigid support layer 580 is made of monocrystalline silicon material or polycrystalline silicon material manufactured from recycled silicon wafers. The entire first metal layer 540 is made of a material selected from the group consisting of nickel, copper, titanium, and steel. The entire second metal layer 570 is made of a material selected from the group consisting of nickel, copper, titanium, and steel. Block 404 may be followed by block 406 .

In block 406 , referring now to FIG. 5C , support wafer 504 is attached to device wafer 502 through adhesive layer 560 . The adhesive layer 560 has a front surface 562 and a rear surface 564 opposite to the front surface 562 of the adhesive layer 560 . The front surface 562 of the adhesive layer 560 is directly connected to the rear surface 544 of the first metal layer 540 . Front surface 562 The surface 572 of the second metal layer 570 is directly attached to the rear surface 564 of the adhesive layer 560 .

In an example of the present invention, adhesive layer 560 includes a conductive adhesive. Block 406 may be followed by block 408 .

In block 408 , referring now to FIG. 5D , a separation process is provided to form a plurality of semiconductor packages 599 . In one example, the segmentation process is a laser cutting process. In another example, the separation process is a sawing process. The first package 581 and the second package 583 are separated from the cutting process. Although only two packages are shown in Figure 5D for simplicity, the total number of packages fabricated from a wafer may vary. In an example of the present invention, each of the plurality of semiconductor packages 599 is a common drain metal oxide semiconductor field effect transistor (MOSFET) chip scale package (CSP) for battery protection applications.

Those skilled in the art to which this invention pertains will recognize that modifications of the disclosed embodiments of the invention are possible. For example, the total number of contact pads 302 can vary. Other modifications may be made by those skilled in the art, and all such modifications are considered to belong to the scope of the present invention as defined by the patent claims of the invention.

100: Semiconductor packaging 102: Contact pad 120: Substrate 140: metal layer 190: coating 200: Semiconductor packaging 202: Contact pad 220: Semiconductor substrate 240: metal layer 294: Protective belt 300: semiconductor package 302: contact pad 320: Semiconductor substrate 322: front surface 324: back surface 340: the first metal layer 342: front surface 344: back surface 360: adhesive layer 362: front surface 364: back surface 364: second metal layer 370: second metal layer 372: front surface 374: back surface 380: rigid support layer 382: front surface 384: rear surface 400: process 402: block 404: block 406: block 408: block 502: Equipment Wafer 504: support wafer 512: contact pad 514: passivation layer 520: Semiconductor substrate 522: front surface 524: back surface 540: the first metal layer 542: front surface 544: back surface 560: adhesive layer 562: front surface 564: back surface 570: second metal layer 572: front surface 574: back surface 580: rigid support layer 581: The first package 582: front surface 583:Second package 584: back surface 599: Semiconductor Packaging

Fig. 1 shows a cross-sectional view of a conventional semiconductor package. Fig. 2 shows a sectional view of another conventional semiconductor package. Fig. 3 shows a cross-sectional view of a semiconductor package having a thin substrate in an example of the present invention. FIG. 4 shows a flow chart for preparing a plurality of semiconductor packages in an example of the present invention. Figures 5A-5D show cross-sectional views of corresponding steps in the process shown in Figure 4 in an example of the present invention.

100: Semiconductor packaging

102: Contact pad

120: Substrate

140: metal layer

190: coating

Claims (25)

A semiconductor package with a thin substrate, comprising: a semiconductor substrate having a front surface and a rear surface opposite to the front surface of the semiconductor substrate; a first metal layer having a a front surface and a rear surface opposite to the front surface of the first metal layer, the front surface of the first metal layer is directly connected to the rear surface of the semiconductor substrate; an adhesive layer having a front surface and the adhesive layer a rear surface opposite to the front surface of the adhesive layer, the front surface of the adhesive layer being directly attached to the rear surface of the first metal layer; a second metal layer having a front surface and a The rear surface opposite to the front surface of the second metal layer, the front surface of the second metal layer is directly connected to the rear surface of the adhesive layer; a rigid support layer, the rigid support layer has a front surface and a front surface opposite to the rigid support layer The rear surface of the rigid support layer is directly attached to the rear surface of the second metal layer; and a plurality of contact pads connected to the front surface of the semiconductor substrate; wherein the thickness of the semiconductor substrate is equal to or less than 75 microns; wherein the rigid The thickness of the support layer is greater than the thickness of the semiconductor substrate; and wherein the rigid support layer is harder than the polymer material; wherein the Young's modulus of the entire rigid support layer is in the range of 50% to 150% of the Young's modulus of the semiconductor substrate; And wherein the coefficient of thermal expansion (CTE) of the entire rigid support layer is in the range of 50% to 250% of the CTE of the semiconductor substrate. The semiconductor package as claimed in claim 1, wherein the thickness of the first metal layer ranges from 1 micron to 5 microns. The semiconductor package as claimed in claim 1, wherein the thickness of the second metal layer ranges from 30 microns to 100 microns. The semiconductor package as claimed in item 1, wherein the thickness range of the rigid support layer is 75 microns to 500 microns. The semiconductor package as claimed in claim 1, wherein the adhesive layer is made of conductive adhesive. The semiconductor package as claimed in claim 1, wherein the semiconductor package is a common drain metal oxide semiconductor field effect transistor (MOSFET) chip scale package (CSP) for battery protection applications; wherein two gates and two sources pole on the front surface of the common drain MOSFET CSP; and wherein the common drain is on the rear surface of the common drain MOSFET CSP. The semiconductor package as claimed in claim 1, wherein the entire rigid support layer is made of single crystal silicon material or polycrystalline silicon material produced from recycled silicon wafers. The semiconductor package as claimed in claim 1, wherein the entire rigid support layer is made of amorphous glass material. The semiconductor package as claimed in claim 1, wherein the entire first metal layer is made of a material selected from the group consisting of aluminum, nickel and gold; wherein the entire second metal layer is made of a material selected from the group consisting of titanium, nickel and silver Made of selected materials. A semiconductor package with a thin substrate, comprising: a semiconductor substrate having a front surface and a rear surface opposite to the front surface of the semiconductor substrate; a first metal layer having a a front surface and a rear surface opposite to the front surface of the first metal layer, the front surface of the first metal layer is directly connected to the rear surface of the semiconductor substrate; an adhesive layer having a front surface and the adhesive layer a rear surface opposite to the front surface of the adhesive layer, the front surface of the adhesive layer being directly attached to the rear surface of the first metal layer; a second metal layer having a front surface and a The opposite rear surface of the front surface of the second metal layer, the front surface of the second metal layer is directly connected to the rear surface of the adhesive layer; a rigid support layer, the rigid support layer has a front surface and a front surface with the rigid support layer the opposite rear surface, the front surface of the rigid support layer is directly attached to the rear surface of the second metal layer; and a plurality of contact pads connected to the front surface of the semiconductor substrate; wherein the thickness of the semiconductor substrate is equal to or less than 75 microns; wherein the thickness of the rigid support layer is greater than the thickness of the semiconductor substrate; and wherein the Young's modulus of the entire rigid support layer is in the range of 50% to 150% of the Young's modulus of the semiconductor substrate; and wherein the coefficient of thermal expansion of the entire rigid support layer (CTE) in the range of 50% to 250% of the CTE of the semiconductor substrate; where the semiconductor package is a common-drain metal-oxide-semiconductor field-effect transistor (MOSFET) chip-scale package (CSP) for battery protection applications; two of which a gate and two sources on the front surface of the common drain MOSFET CSP; and wherein the common drain is on the back surface of the common drain MOSFET CSP. The semiconductor package as claimed in claim 10, wherein the thickness of the first metal layer ranges from 1 micron to 5 microns. The semiconductor package as claimed in claim 10, wherein the thickness of the second metal layer ranges from 30 microns to 100 microns. The semiconductor package as claimed in claim 10, wherein the thickness of the rigid support layer ranges from 75 microns to 500 microns. The semiconductor package as claimed in claim 10, wherein the adhesive layer is made of conductive adhesive. The semiconductor package as claimed in claim 10, wherein the entire rigid support layer is made of single crystal silicon material or polycrystalline silicon material produced from recycled silicon wafers. The semiconductor package as claimed in claim 10, wherein the entire rigid support layer is made of amorphous glass material. A method of making a plurality of semiconductor packages having a thin substrate, the method comprising The following steps: preparing a device wafer comprising: a semiconductor substrate having a front surface and a rear surface opposite to the front surface of the semiconductor substrate; a first metal layer having A front surface and a rear surface opposite to the front surface of the first metal layer, the front surface of the first metal layer is directly connected to the rear surface of the semiconductor substrate; and a plurality of contact pads are connected to the front surface of the semiconductor substrate; preparation A support wafer comprising a second metal layer having a front surface and a back surface opposite to the front surface of the second metal layer; and a rigid support layer having a front surface and a rear surface opposite the front surface of the rigid support layer, the front surface of the rigid support layer is directly attached to the rear surface of the second metal layer; the support wafer is connected to the device wafer through an adhesive layer, the adhesive layer has a front surface and a rear surface opposite to the front surface of the adhesive layer, the front surface of the adhesive layer is directly connected to the rear surface of the first metal layer, the front surface of the second metal layer is directly attached to the adhesive and a separation process is applied; wherein the thickness of the semiconductor substrate is equal to or less than 75 micrometers; wherein the thickness of the rigid support layer is greater than the thickness of the semiconductor substrate; and wherein the rigid support layer is harder than the polysilicon material; wherein the entire rigid support The Young's modulus of the layer is in the range of 50% to 150% of the Young's modulus of the semiconductor substrate; wherein the coefficient of thermal expansion (CTE) of the entire rigid support layer is in the range of 50% to 250% of the CTE of the semiconductor substrate. The method according to claim 17, wherein the thickness of the first metal layer ranges from 1 micron to 5 microns. The method according to claim 17, wherein the thickness of the second metal layer ranges from 30 microns to 100 microns. The method as claimed in claim 17, wherein the rigid support layer has a thickness ranging from 75 microns to 500 microns. The method according to claim 17, wherein the adhesive layer is made of a conductive adhesive. The method of claim 17, wherein each of the plurality of semiconductor packages is a common drain metal oxide semiconductor field effect transistor (MOSFET) chip scale package (CSP) for battery protection applications; wherein Two gates and two sources are on the front surface of the common drain MOSFET CSP; and one of the common drains is on the back surface of the common drain MOSFET CSP. The method as claimed in claim 17, wherein the entire rigid support layer is made of single crystal silicon material or polycrystalline silicon material produced from recycled silicon wafers. The method as claimed in claim 17, wherein the entire rigid support layer is made of amorphous glass material. The method as claimed in claim 17, wherein the entire first metal layer is made of a material selected from aluminum, nickel and gold; wherein the entire second metal layer is made of a material selected from titanium, nickel and silver.

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