TWI799034B - Semiconductor package having thin substrate and method of making the same - Google Patents
Semiconductor package having thin substrate and method of making the same Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 137
- 239000000758 substrate Substances 0.000 title claims abstract description 84
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000010410 layer Substances 0.000 claims abstract description 166
- 229910052751 metal Inorganic materials 0.000 claims abstract description 98
- 239000002184 metal Substances 0.000 claims abstract description 98
- 239000012790 adhesive layer Substances 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims abstract description 22
- 235000012431 wafers Nutrition 0.000 claims description 31
- 239000000463 material Substances 0.000 claims description 22
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 16
- 239000002210 silicon-based material Substances 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 229910052759 nickel Inorganic materials 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 239000000853 adhesive Substances 0.000 claims description 6
- 230000001070 adhesive effect Effects 0.000 claims description 6
- 230000005669 field effect Effects 0.000 claims description 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- 239000011521 glass Substances 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 229910044991 metal oxide Inorganic materials 0.000 claims description 4
- 150000004706 metal oxides Chemical class 0.000 claims description 4
- 238000000926 separation method Methods 0.000 claims description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 239000002861 polymer material Substances 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 claims 1
- 238000004806 packaging method and process Methods 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000010959 steel Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 239000000075 oxide glass Substances 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
本發明一般涉及具有薄半導體襯底的半導體封裝和製造複數個半導體封裝的方法。更具體地說,本發明涉及一種半導體封裝,其在足夠的安全系數範圍內工作,具有厚度在25微米到75微米範圍內的襯底。The present invention generally relates to semiconductor packages having thin semiconductor substrates and methods of manufacturing a plurality of semiconductor packages. More specifically, the present invention relates to a semiconductor package that operates within a sufficient margin of safety and has a substrate with a thickness in the range of 25 microns to 75 microns.
如用於電池保護應用的公共汲極金屬氧化物半導體場效應電晶體(MOSFET)晶片級封裝(CSP)和半導體功率封裝等,半導體封裝通常具有100微米或以上的半導體襯底厚度。半導體襯底提供了大量的直流電阻。比較有利的做法是將半導體襯底厚度減小到低於50微米,從而減小直流電阻並提高電性能。Semiconductor packages typically have a semiconductor substrate thickness of 100 microns or more, such as common-drain metal-oxide-semiconductor field-effect transistor (MOSFET) chip-scale packaging (CSP) and semiconductor power packaging for battery protection applications. The semiconductor substrate provides a large amount of DC resistance. It is advantageous to reduce the thickness of the semiconductor substrate to less than 50 microns, thereby reducing the DC resistance and improving the electrical performance.
半導體襯底提供了大量的直流(DC)電阻。減少半導體襯底的厚度以改善電性能是十分有利的做法。例如,當半導體襯底的厚度從50微米減小到25微米時,導通電阻可以減小24%。當半導體襯底厚度減小時,半導體封裝的機械強度降低。在本發明的示例中,添加連接到楊氏模量為150千兆帕斯卡的金屬層的剛性支撐層以增加機械強度。增加所附金屬層的厚度可進一步略微降低導通電阻(比改變半導體襯底厚度的影響敏感度低)。例如,當附著的金屬層的厚度從15微米增加到50微米時,導通電阻可降低5%。Semiconductor substrates provide substantial direct current (DC) resistance. It is advantageous to reduce the thickness of semiconductor substrates to improve electrical performance. For example, when the thickness of the semiconductor substrate is reduced from 50 microns to 25 microns, the on-resistance can be reduced by 24%. When the thickness of the semiconductor substrate is reduced, the mechanical strength of the semiconductor package is reduced. In an example of the present invention, a rigid support layer connected to a metal layer with a Young's modulus of 150 GPa is added to increase mechanical strength. Increasing the thickness of the attached metal layer can further reduce the on-resistance slightly (less sensitive than the effect of changing the thickness of the semiconductor substrate). For example, when the thickness of the attached metal layer is increased from 15 microns to 50 microns, the on-resistance can be reduced by 5%.
一種半導體封裝,包括一個半導體襯底、一個第一金屬層、一個粘合層、一個第二金屬層、一個剛性支撐層和複數個接觸墊。半導體襯底的厚度等於或小於75微米。剛性支撐層的厚度大於半導體襯底的厚度。第二金屬層的厚度大於第一金屬層的厚度。A semiconductor package includes a semiconductor substrate, a first metal layer, an adhesive layer, a second metal layer, a rigid support layer and a plurality of contact pads. The thickness of the semiconductor substrate is equal to or less than 75 micrometers. The thickness of the rigid support layer is greater than the thickness of the semiconductor substrate. The thickness of the second metal layer is greater than that of the first metal layer.
公開了一種用於製造複數個半導體封裝的方法。該方法包括以下步驟:製備一個設備晶圓;提供一個支撐晶圓;透過一個粘合層將支撐晶片連接到設備晶圓;以及應用分離過程。A method for manufacturing a plurality of semiconductor packages is disclosed. The method includes the steps of: preparing a device wafer; providing a support wafer; attaching the support wafer to the device wafer through an adhesive layer; and applying a separation process.
第1圖表示一種傳統的半導體封裝100的剖面圖。傳統的半導體封裝100包括複數個接觸墊102、一個半導體襯底120、一個金屬層140和一個塗層190。在一個示例中,襯底120為100微米厚。塗層190不能為包裝提供足夠的機械強度支撐。在表面貼裝焊料回流過程中會發生翹曲。FIG. 1 shows a cross-sectional view of a
第2圖表示傳統的半導體封裝200的剖面圖。傳統的半導體封裝200包括複數個接觸墊202、一個半導體襯底220、一個金屬層240和一個保護帶294。在一個示例中,半導體襯底220為100微米厚。保護帶294不能為封裝提供足夠的機械強度支撐。在表面安裝焊料回流過程中會發生翹曲。FIG. 2 shows a cross-sectional view of a
美國專利申請公開號2019/0189569的第3A圖和第3B圖表示一種半導體封裝,該半導體封裝包含一個半導體襯底、一個金屬層、一個粘合層、一個剛性支撐層和複數個接觸墊的半導體封裝。如果沒有附加到剛性支撐層的附加金屬層,則當半導體襯底的厚度減小到50微米範圍時,包括在半導體封裝的機械性能要求中的安全系數並不高。Figures 3A and 3B of U.S. Patent Application Publication No. 2019/0189569 illustrate a semiconductor package comprising a semiconductor substrate, a metal layer, an adhesive layer, a rigid support layer, and a plurality of contact pads encapsulation. Without an additional metal layer attached to the rigid support layer, the margin of safety included in the mechanical performance requirements of a semiconductor package is not high when the thickness of the semiconductor substrate is reduced to the 50 micron range.
第3圖表示在本發明的示例中,半導體封裝300的剖面圖。半導體封裝300包括一個半導體襯底320、一個第一金屬層340、一個粘合層360、一個第二金屬層370、一個剛性支撐層380和複數個接觸墊302。FIG. 3 shows a cross-sectional view of a
半導體襯底320具有一個前表面322和一個後表面324。後表面324與前表面322相對。第一金屬層340具有一個前表面342和一個後表面344。後表面344與前表面342相對。粘合層360具有一個前表面362和一個後表面364。所述後表面364與前表面362相對。第二金屬層370具有一個前表面372和一個後表面374。後表面374與前表面372相對。剛性支撐層380具有一個前表面382和一個後表面384。後表面384與前表面382相對。The
在本發明的示例中,第一金屬層340的前表面342直連到半導體襯底320的後表面324。粘合層360的前表面362直接連接到第一金屬層340的後表面344。第二金屬層370的前表面372直接連接到後表面粘合層360的364。剛性支撐層380的前表面382直接連接到第二金屬層370的後表面374。在一個示例中,複數個接觸墊302連接到半導體基板320的前表面322。在另一個示例中,複數個接觸墊302直接連接到半導體襯底320的前表面322。In an example of the present invention, the
在一個示例中,半導體襯底320的厚度等於或小於50微米。在另一示例中,半導體襯底320的厚度在25微米到35微米的範圍內。在本發明的示例中,第二金屬層370的厚度在30微米到100微米的範圍內。第二金屬層370提供電路徑,以便減小器件的導通電阻。第一金屬層340的厚度在1微米到5微米的範圍內。第一金屬層340的厚度小於半導體襯底320的厚度,以便減少半導體封裝在製造期間的整體翹曲。第二金屬層370的厚度大於第一金屬層340的厚度。在一個示例中,半導體襯底320、第二金屬層370和剛性支撐層380的邊緣表面在所有側面分別對齊和共面。在另一示例中,半導體襯底320、第一金屬層340、第二金屬層370和剛性支撐層380的邊緣表面在所有側面分別對齊和共面。在另一個示例中,半導體襯底320、第一金屬層340、粘合層360、第二金屬層370和剛性支撐層380的邊緣表面在所有側面分別對齊和共面。In one example, the thickness of the
本發明的示例中,支撐層的厚度為380微米至150微米。剛性支撐層380的術語“剛性”指剛性支撐層380中比膠帶材料更硬的材料(例如聚醯亞胺材料或聚合物材料)。半導體襯底320越薄,複數個半導體封裝中的每一個的電性能越好。半導體襯底320的厚度小於50微米是十分有利的。如果半導體封裝的機械性能要求中包括安全系數,則剛性支撐層380的強度要求更高。In an example of the present invention, the thickness of the supporting layer is 380 microns to 150 microns. The term "rigid" of the
在本發明的示例中,沿平行於第3圖的Z軸的方向測量厚度。在本發明的示例中,剛性支撐層380的厚度是前表面382和後表面384之間的最短距離。在本發明的示例中,半導體襯底320包括矽材料。在本發明的示例中,優選半導體封裝(具有3.05 mm×1.77 mm的平面尺寸)能夠承受5牛頓以上,而不會斷裂。In the example of the present invention, the thickness is measured in a direction parallel to the Z-axis of FIG. 3 . In an example of the invention, the thickness of
在本發明的示例中,粘合層360包括導電黏合劑。剛性支撐層380是非導電的。電流從複數個接觸墊302中的第一接觸墊,流過半導體襯底320、第一金屬層340、粘合層360、第二金屬層370、粘合層360、第一金屬層340和半導體襯底320,至複數個接觸墊302中的第二接觸墊。In an example of the present invention,
在本發明的示例中,半導體封裝300是用於電池保護應用的公共汲極金屬氧化物半導體場效應電晶體(MOSFET)晶片級封裝(CSP)。兩個閘極和兩個源極位於公共汲極MOSFET CSP的前表面上。公共汲極位於公共汲極MOSFET CSP的背面。In an example of the present invention, the
在本發明的示例中,剛性支撐層380的整體由具有相對較高楊氏模量的材料製成,包括單晶矽材料、多晶矽材料或玻璃材料。在本發明的示例中,剛性支撐層380的整體由具有高楊氏模量的材料製成,包括矽材料、玻璃材料或氧化矽玻璃材料(SiO2)。其優點是具有成本效益和更輕的半導體封裝重量。在本發明的示例中,整個剛性支撐層380的楊氏模量在半導體襯底320楊氏模量的50%到150%範圍內。整個剛性支撐層380的熱膨脹係數(CTE)在半導體襯底320的CTE的50%到250%範圍內。In an example of the present invention, the entire
在本發明的示例中,剛性支撐層的整體由單晶矽材料或由回收矽晶片製造的多晶矽材料製成。使用回收矽片的優點是降低成本。回收的矽片是用過的矽片或再生的矽片。在一個實例中,所使用的矽片可先前用於測試目的。蝕刻工藝和拋光工藝應用於回收的矽片。整個第一金屬層340由從鋁、鎳和金組成的組中選擇的材料製成。整個第二金屬層370由從鈦、鎳和銀組成的組中選擇的材料製成。In an example of the invention, the entirety of the rigid support layer is made of monocrystalline silicon material or polycrystalline silicon material manufactured from recycled silicon wafers. The advantage of using recycled wafers is cost reduction. Recycled silicon wafers are used silicon wafers or recycled silicon wafers. In one example, the silicon wafers used may have been previously used for testing purposes. An etching process and a polishing process are applied to the recycled silicon wafers. The entire
第4圖表示在本發明的示例中,製備複數個半導體封裝的過程400的流程圖。第5A圖-第5D圖表示相應步驟的剖面圖。過程400可以從區塊402開始。FIG. 4 shows a flowchart of a
在區塊402中,現在參考第5A圖,製備一個設備晶圓502。設備晶圓502可以是直徑為4英寸、6英寸、8英寸、12英寸或18英寸的晶圓。設備晶圓502包括半導體襯底520、第一金屬層540和複數個接觸墊512。設備晶圓502還可以包括鈍化層514(以虛線顯示)。類似於美國專利申請公開號2019/0189569的第3A圖,複數個接觸墊512中的每個可包括鋁層和鎳金層。在一個示例中,第一金屬層540直接沉積在半導體襯底520上。In
半導體襯底520具有與半導體襯底520的前表面522相對的前表面522和後表面524。第一金屬層540具有與第一金屬層540的前表面542相對的前表面542和後表面544。第一金屬層540的前表面542直接接觸連接到半導體襯底520的後表面524。複數個接觸墊512連接到半導體襯底520的前表面522。The
在本發明的示例中,半導體襯底520的厚度等於或小於50微米。半導體襯底520的厚度在25微米到35微米的範圍內。區塊402之後可以是區塊404。In an example of the present invention, the thickness of the
在區塊404中,現在參考第5B圖,製備一個支撐晶圓504。支撐晶圓504包括一個第二金屬層570和一個剛性支撐層580。第二金屬層570具有與第二金屬層570的前表面572相對的前表面572和後表面574。剛性支撐層580具有與第二金屬層570的前表面582相對的前表面582和與第二金屬層570的前表面582相對的後表面584剛性支撐層580。剛性支撐層580的前表面582直接連接到第二金屬層570的後表面574。In
在本發明的示例中,剛性支撐層580的厚度大於半導體襯底520的厚度。剛性支撐層580比膠帶材料更硬。第二金屬層570的厚度大於第一金屬層540的厚度。剛性支撐層580不導電。剛性支撐層580的整體由單晶矽材料或由回收矽晶片製造的多晶矽材料製成。整個第一金屬層540由從鎳、銅、鈦和鋼組成的組中選擇的材料製成。整個第二金屬層570由從鎳、銅、鈦和鋼組成的組中選擇的材料製成。區塊404之後可以是區塊406。In an example of the present invention, the thickness of the
在區塊406中,現在參考第5C圖,支撐晶片504透過粘合層560連接到設備晶圓502。粘合層560具有與粘合層560的前表面562相對的前表面562和後表面564。粘合層560的前表面562直接連接到第一金屬層540的後表面544。前表面562第二金屬層570的表面572直接附著到粘合層560的後表面564。In
在本發明的示例中,粘合層560包括導電粘合物。區塊406之後可以是區塊408。In an example of the present invention,
在區塊408中,現在參考第5D圖,提供分離過程以形成複數個半導體封裝599。在一個例子中,分割過程是鐳射切割過程。在另一個例子中,分離過程是鋸切過程。第一封裝581和第二封裝583與切割過程分離。儘管為了簡單起見,第5D圖中僅僅表示出了兩個封裝,但由晶圓製造的封裝的總數可能不同。在本發明的示例中,複數個半導體封裝599中的每一個都是用於電池保護應用的公共汲極金屬氧化物半導體場效應電晶體(MOSFET)晶片級封裝(CSP)。In
本創作所屬技術領域中具有通常知識者可以認識到,本發明公開的實施例的修改是可能的。例如,複數個接觸墊302的總數可以變化。本領域的普通技術人員可以進行其他修改,並且所有該等修改都被認為屬於發明申請專利範圍所定義的本發明的範圍。Those skilled in the art to which this invention pertains will recognize that modifications of the disclosed embodiments of the invention are possible. For example, the total number of
100:半導體封裝 102:接觸墊 120:襯底 140:金屬層 190:塗層 200:半導體封裝 202:接觸墊 220:半導體襯底 240:金屬層 294:保護帶 300:半導體封裝 302:接觸墊 320:半導體襯底 322:前表面 324:後表面 340:第一金屬層 342:前表面 344:後表面 360:粘合層 362:前表面 364:後表面 364:第二金屬層 370:第二金屬層 372:前表面 374:後表面 380:剛性支撐層 382:前表面 384:後表面 400:過程 402:區塊 404:區塊 406:區塊 408:區塊 502:設備晶圓 504:支撐晶圓 512:接觸墊 514:鈍化層 520:半導體襯底 522:前表面 524:後表面 540:第一金屬層 542:前表面 544:後表面 560:粘合層 562:前表面 564:後表面 570:第二金屬層 572:前表面 574:後表面 580:剛性支撐層 581:第一封裝 582:前表面 583:第二封裝 584:後表面 599:半導體封裝 100: Semiconductor packaging 102: Contact pad 120: Substrate 140: metal layer 190: coating 200: Semiconductor packaging 202: Contact pad 220: Semiconductor substrate 240: metal layer 294: Protective belt 300: semiconductor package 302: contact pad 320: Semiconductor substrate 322: front surface 324: back surface 340: the first metal layer 342: front surface 344: back surface 360: adhesive layer 362: front surface 364: back surface 364: second metal layer 370: second metal layer 372: front surface 374: back surface 380: rigid support layer 382: front surface 384: rear surface 400: process 402: block 404: block 406: block 408: block 502: Equipment Wafer 504: support wafer 512: contact pad 514: passivation layer 520: Semiconductor substrate 522: front surface 524: back surface 540: the first metal layer 542: front surface 544: back surface 560: adhesive layer 562: front surface 564: back surface 570: second metal layer 572: front surface 574: back surface 580: rigid support layer 581: The first package 582: front surface 583:Second package 584: back surface 599: Semiconductor Packaging
第1圖表示一種傳統的半導體封裝的剖面圖。 第2圖表示另一種傳統的半導體封裝的剖面圖。 第3圖表示在本發明的示例中,一種具有薄襯底的半導體封裝的剖面圖。 第4圖表示在本發明的示例中,製備複數個半導體封裝的流程圖。 第5A圖-第5D圖表示在本發明的示例中,第4圖所示工藝的相應的步驟剖面圖。 Fig. 1 shows a cross-sectional view of a conventional semiconductor package. Fig. 2 shows a sectional view of another conventional semiconductor package. Fig. 3 shows a cross-sectional view of a semiconductor package having a thin substrate in an example of the present invention. FIG. 4 shows a flow chart for preparing a plurality of semiconductor packages in an example of the present invention. Figures 5A-5D show cross-sectional views of corresponding steps in the process shown in Figure 4 in an example of the present invention.
100:半導體封裝 100: Semiconductor packaging
102:接觸墊 102: Contact pad
120:襯底 120: Substrate
140:金屬層 140: metal layer
190:塗層 190: coating
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US9570295B1 (en) * | 2016-01-29 | 2017-02-14 | International Business Machines Corporation | Protective capping layer for spalled gallium nitride |
US9748353B2 (en) * | 2015-12-31 | 2017-08-29 | International Business Machines Corporation | Method of making a gallium nitride device |
US9831115B2 (en) * | 2016-02-19 | 2017-11-28 | Sunedison Semiconductor Limited (Uen201334164H) | Process flow for manufacturing semiconductor on insulator structures in parallel |
TW201810443A (en) * | 2016-04-29 | 2018-03-16 | 優尼卡塔股份有限公司 | Connecting electronic components to substrates |
TW202010064A (en) * | 2018-08-10 | 2020-03-01 | 南韓商三星電子股份有限公司 | Semiconductor package |
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US9748353B2 (en) * | 2015-12-31 | 2017-08-29 | International Business Machines Corporation | Method of making a gallium nitride device |
US9570295B1 (en) * | 2016-01-29 | 2017-02-14 | International Business Machines Corporation | Protective capping layer for spalled gallium nitride |
US9831115B2 (en) * | 2016-02-19 | 2017-11-28 | Sunedison Semiconductor Limited (Uen201334164H) | Process flow for manufacturing semiconductor on insulator structures in parallel |
TW201810443A (en) * | 2016-04-29 | 2018-03-16 | 優尼卡塔股份有限公司 | Connecting electronic components to substrates |
TW202010064A (en) * | 2018-08-10 | 2020-03-01 | 南韓商三星電子股份有限公司 | Semiconductor package |
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