TWI799029B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A manufacturing process of a semiconductor device includes forming and etching a dielectric layer to form a trench therein. A bottom electrode layer is formed along a bottom portion of a sidewall and a bottom portion of the trench. An insulator layer is formed along an upper portion of the sidewall of the trench and the bottom electrode layer. An upper electrode layer is formed along the insulator. A first contact layer is formed in the trench. A first etching is performed to etch and has a same etching selectivity between the oxide layer, the upper bottom layer, the insulator layer and the dielectric layer. The first etching removes the oxide layer to expose the first contact layer. A second etching is performed to etch the first contact layer, forming a recess over the first contact layer. A second contact layer is formed in the recess.

Description

Semiconductor device and manufacturing method thereof

Some embodiments of the present disclosure include a semiconductor device and a manufacturing method thereof.

In some memories, the memory may include capacitors, channel layers, word lines and bit lines. In some embodiments, the capacitor of the memory may be a Metal-Insulator-Metal (MIM) capacitor element, which is formed by two highly conductive electrode layers and an insulating layer sandwiched between them. MIL capacitors have the advantage of higher capacitance per unit area, so they are widely used in memory.

Some embodiments of the present disclosure provide a method of manufacturing a semiconductor device, including forming a first dielectric layer. Etching the first dielectric layer to form trenches in the first dielectric layer. A bottom electrode layer is formed on the lower portion of the sidewall of the trench and the bottom of the trench. An insulating layer is formed along the upper and bottom electrode layers of the sidewalls of the trench. Along the insulating layer, an upper electrode layer is formed on the insulating layer. A first contact layer is formed in the trench and on the upper electrode layer, wherein an oxide layer is formed on a top surface of the first contact layer. performing a first etching process to etch the oxide layer, the upper electrode layer, the insulating layer, and the first dielectric layer on the top surface of the first contact layer, wherein the first etching process is effective for the oxide layer, the upper electrode layer, the insulating layer, and the first dielectric layer. The first dielectric layer has substantially the same etch selectivity, and the first etch process removes the oxide layer to expose the first contact layer. A second etching process is performed to etch the first contact layer to form a groove on the first contact layer. and forming a second contact layer in the groove.

In some embodiments, the etchant for performing the first etching process includes boron trichloride, chlorine gas or a combination thereof.

In some embodiments, the etchant used to perform the first etching process does not contain fluorine.

In some embodiments, when performing the first etching process, the upper electrode layer, the insulating layer and the first dielectric layer are removed to a thickness substantially the same as that of the oxide layer.

In some embodiments, after the first etching process is completed, the first contact layer, the upper electrode layer, the insulating layer are substantially aligned with the plurality of upper surfaces of the first dielectric layer.

In some embodiments, after the first etching process is completed, there is a vertical height between the upper surface of the insulating layer and the upper surface of the first dielectric layer, and the vertical height is within 3 nm.

In some embodiments, forming the bottom electrode layer on the lower portion of the sidewall of the trench includes forming the electrode layer along the sidewall of the trench and the bottom of the trench, and removing the upper portion of the electrode layer to form the sidewall along the trench. The lower part of the bottom electrode layer.

In some embodiments, some embodiments of the present disclosure provide a semiconductor device including a first dielectric layer, a capacitor structure and a transistor. The capacitor structure is in the first dielectric layer and includes a bottom electrode layer, an insulating layer, an upper electrode layer, a first contact layer and a second contact layer. The bottom electrode layer covers the lower portion of the sidewall of the first dielectric layer. The insulating layer covers the upper portion of the sidewall of the first dielectric layer and the bottom electrode layer. The upper electrode layer covers the insulating layer, and there is a vertical height between the upper surface of the insulating layer and the upper surface of the first dielectric layer, and the vertical height is within 3 nanometers. The first contact layer covers a lower portion of the upper electrode layer. The second contact layer covers the upper portion of the upper electrode layer and the second contact layer is on the first contact layer. The transistor is located on the capacitor structure and is electrically connected with the capacitor structure.

In some embodiments, the semiconductor device further includes a channel layer and a word line. The channel layer is on and contacts the capacitive structure. The word lines wrap around the channel layer.

In some embodiments, the semiconductor device further includes a bit line on and connected to the channel layer.

To sum up, the manufacturing process of some embodiments of the present disclosure can substantially planarize the upper surface of the capacitor structure, so the upper surface of the capacitor structure is substantially flat. In this way, defects caused by uneven top surfaces in the resulting memory can be reduced.

The following will disclose multiple implementations of the present disclosure with diagrams, and for the sake of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present disclosure. That is to say, in some embodiments of the present disclosure, these practical details are unnecessary. In addition, for the sake of simplifying the drawings, some well-known structures and components will be shown in a simple and schematic manner in the drawings.

Some embodiments of the present disclosure relate to processes for fabricating capacitor structures in memory. Using the process of some embodiments of the present disclosure can improve the flatness of the upper surface of the capacitor structure, so that the upper surface of the capacitor structure is substantially flat. In this way, defects caused by uneven top surfaces in the resulting memory can be reduced.

FIG. 1 illustrates a cross-sectional view of a semiconductor device 100 according to some embodiments of the present disclosure. In some embodiments, the semiconductor device 100 is a memory, such as a dynamic random access memory (Dynamic Random Access Memory, DRAM). The semiconductor device 100 may include a first dielectric layer 101 , a capacitor structure CA and a transistor TR. The capacitor structure CA is located in the first dielectric layer 101 . In some embodiments, the first dielectric layer 101 may include a first dielectric sub-layer 102 below and a second dielectric sub-layer 104 on the first dielectric sub-layer 102 . The first dielectric sub-layer 102 and the second dielectric sub-layer 104 can be made of different dielectric materials.

The capacitive structure CA is in the first dielectric layer 101 such that the first dielectric layer 101 surrounds the capacitive structure CA. The capacitor structure CA may include a bottom electrode layer 112 , an insulating layer 114 , an upper electrode layer 116 , a first contact layer 122 and a second contact layer 124 . The bottom electrode layer 112 covers and contacts the lower portion of the sidewall of the first dielectric layer 101 . The insulating layer 114 covers and contacts the upper portion of the sidewall of the first dielectric layer 101 and the bottom electrode layer 112 . The upper electrode layer 116 covers and contacts the insulating layer 114, the upper surface of the insulating layer 114 protrudes from the upper surface of the first dielectric layer 101 and has a vertical height H between the upper surface of the first dielectric layer 101, and the vertical height H within 3 nanometers. The first contact layer 122 covers and contacts the lower portion of the upper electrode layer 116 . The second contact layer 124 covers and contacts the upper portion of the upper electrode layer 116 and is located on the first contact layer 122 .

In the capacitor structure CA, the bottom electrode layer 112, the insulating layer 114, and the upper electrode layer 116 can be collectively regarded as a capacitor, and the first contact layer 122 and the second contact layer 124 are used as contacts to connect the capacitor to the upper Transistor TR.

The transistor TR includes a channel layer 144, a word line 134, a gate dielectric layer 142 and a bit line 164, and the transistor TR is electrically connected to the capacitor structure CA through the first contact layer 122 and the second contact layer 124. Therefore, the first contact layer 122 and the second contact layer 124 can be regarded as one of the source/drain of the transistor TR. The channel layer 144 is on the capacitive structure CA and contacts the second contact layer 124 of the capacitive structure CA. The gate dielectric layer 142 is located on the sidewall of the channel layer 144 . The word line 134 surrounds the channel layer 144 and the gate dielectric layer 142 and contacts the gate dielectric layer 142 . In addition, the word line 134 and the gate dielectric layer 142 can be surrounded by the second dielectric layer 132 and the third dielectric layer 136, so that the word line 134 and the gate dielectric layer 142 are embedded in the second dielectric layer 132 and the third dielectric layer 136 . Bit lines 164 are above channel layer 144 . In some embodiments, the bit line 164 is connected to the channel layer 144 through the transparent conductive layer 162 . Also, the bit line 164 may be surrounded by the fourth dielectric layer 152 such that the bit line 164 is embedded in the fourth dielectric layer 152 . The bit line 164 may further include a structure for connecting to an external circuit, so that the semiconductor device 100 can be further connected to an external circuit.

2 to 12 illustrate cross-sectional views of intermediate stages of the manufacturing process of the semiconductor device 100 according to some embodiments of the present disclosure. Referring to FIG. 2, a first dielectric layer 101 is formed. In some embodiments, although not shown in FIG. 2 , the first dielectric layer 101 may be formed on the interconnect structure with metal lines and vias. In some embodiments, the first dielectric sub-layer 102 may be formed first, and then the second dielectric sub-layer 104 is formed on the first dielectric sub-layer 102 . The first dielectric sub-layer 102 and the second dielectric sub-layer 104 are formed of different dielectric materials, so there is an obvious interface between the first dielectric sub-layer 102 and the second dielectric sub-layer 104 . For example, the first dielectric layer 102 can be formed of silicon oxide, and the second dielectric layer 104 can be formed of silicon nitride.

Referring to FIG. 3 , the first dielectric layer 101 is etched to form a trench T in the first dielectric layer 101 . The trench T can be formed by any suitable method. For example, the trench T may be formed using dry etching, wet etching or a combination thereof. After the trench T is completed, the trench T can expose the metal lines or vias of the underlying interconnection structure, so that the bottom electrode layer 112 of the capacitive structure CA formed in the trench T in the subsequent process (see Section 1 ) can be further connected to the underlying interconnect structure 10.

Referring to FIG. 4 and FIG. 5 , the bottom electrode layer 112 is formed on the lower portion of the sidewall of the trench T. Referring to FIG. Specifically, forming the bottom electrode layer 112 includes forming the electrode layer 111 along the sidewall and bottom of the trench T, as shown in FIG. 4 . The electrode layer 111 is a conformal layer completely covering the sidewall and bottom of the trench T. As shown in FIG. Next, the upper portion of the electrode layer 111 is removed to form the bottom electrode layer 112 along the lower portion of the sidewall of the trench T and the bottom of the trench T, as shown in FIG. 5 . Therefore, in some embodiments, the bottom electrode layer 112 exposes the upper portion of the sidewall of the first dielectric layer 101 . In other embodiments, after the electrode layer 111 is formed along the sidewall and bottom of the trench T, the upper portion of the electrode layer 111 may not be removed. That is, the electrode layer 111 can be directly used as the bottom electrode layer, and the bottom electrode layer will not expose the sidewall of the trench T. Referring to FIG. In some embodiments, the electrode layer 111 and the bottom electrode layer 112 are made of conductive materials, such as titanium nitride (TiN). The electrode layer 111 may be formed using any suitable deposition process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition or the like, and removed by a suitable etching process such as anisotropic etching 111 to form the bottom electrode layer 112 .

Referring to FIG. 6 , next, an insulating layer 114 is formed along the upper portion of the sidewall of the trench T and the bottom electrode layer 112 . The insulating layer 114 is conformally formed along the upper portion of the sidewall of the trench T and the bottom electrode layer 112 , so the insulating layer 114 contacts the upper portion of the sidewall of the first dielectric layer 101 and the bottom electrode layer 112 simultaneously. In addition, the insulating layer 114 also completely covers the top surface, sidewalls and bottom of the bottom electrode layer 112 . In other embodiments where the bottom electrode layer is the electrode layer 111, the insulating layer 114 can completely cover the sidewall and bottom of the electrode layer 111, so that the upper surface of the electrode layer 111 is between the first dielectric layer 101 and the insulating layer 114 exposed. In some embodiments, the insulating layer 114 is made of a material with a high dielectric constant (eg, a dielectric constant higher than 3.9), such as zirconia (ZrOx). The insulating layer 114 may be formed using any suitable deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or the like.

Referring to FIG. 7 , along the insulating layer 114 , an upper electrode layer 116 is formed on the insulating layer 114 . In some embodiments, the upper electrode layer 116 is made of a conductive material, such as titanium nitride (TiN). In some embodiments, the upper electrode layer 116 is made of the same material as the electrode layer 111 , the bottom electrode layer 112 . The upper electrode layer 116 may be formed using any suitable deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or the like.

Referring to FIG. 8 , the first contact layer 122 is formed in the trench T and on the upper electrode layer 116 , wherein the oxide layer 123 is formed on the top surface of the first contact layer 122 . Specifically, after the upper electrode layer 116 is formed, an appropriate contact material can be filled into the trench T so that the contact material completely covers the sidewall and bottom of the upper electrode layer 116 to form the first contact layer 122 . In some embodiments, the first contact layer 122 can be formed of a suitable semiconductor or conductive material, such as polysilicon. In some embodiments, since the top surface of the first contact layer 122 is exposed to air, the top surface of the first contact layer 122 may be oxidized to form the oxide layer 123 . That is, the first contact layer 122 and the oxide layer 123 are formed of different materials, and the oxide layer 123 includes the oxide of the material of the first contact layer 122 .

Referring to FIG. 9 , a first etching process is performed to etch the oxide layer 123 , the upper electrode layer 116 , the insulating layer 114 and the first dielectric layer 101 on the top surface of the first contact layer 122 . Specifically, in some embodiments, a portion of the first contact layer 122 is removed to form the second contact layer (see FIG. 11 ). However, since the first contact layer 122 and the oxide layer 123 on the first contact layer 122 are formed of different materials, if a part of the first contact layer 122 is to be removed, the oxide layer 123 must be removed first. In some embodiments, the oxide layer 123 , the upper electrode layer 116 , the insulating layer 114 and the first dielectric layer 101 can be etched simultaneously in the first etching process. When performing the first etching process, the oxide layer 123 can be completely removed, and the removed thickness of the upper electrode layer 116 , the insulating layer 114 and the first dielectric layer 101 is substantially the same as the thickness of the oxide layer 123 . That is, the first etching process is a planarization etching process, and after the first etching process is completed, the first etching process removes the oxide layer 123 to expose the first contact layer 122 .

Since the oxide layer 123, the upper electrode layer 116, the insulating layer 114, and the first dielectric layer 101 are formed of different materials, the first etching process has a great impact on the oxide layer 123, the upper electrode layer 116, the insulating layer 114, and the first dielectric layer. The layers 101 have substantially the same etch selectivity, so that the first contact layer 122 , the upper electrode layer 116 , and the insulating layer 114 are substantially aligned with the upper surface of the first dielectric layer 101 after the first etching process is completed. The first etching process can be performed using any suitable etchant. In some embodiments, the etchant for performing the first etching process includes boron trichloride, chlorine gas or a combination thereof, and the etchant for performing the first etching process does not contain fluorine. In some embodiments, the bias power of the first etching process is between about 40 watts and 60 watts. In some embodiments, the temperature of the first etching process is between about 40°C and 60°C. Using the disclosed etching gas and conditions can effectively etch the oxide layer 123, the upper electrode layer 116, the insulating layer 114 and the first dielectric layer 101 at substantially the same rate, so that the first contact layer 122, the upper electrode layer 116, The insulating layer 114 is substantially aligned with the upper surface of the first dielectric layer 101 . Therefore, due to the uneven upper surface of the upper electrode layer 116, the insulating layer 114 and the first dielectric layer 101, the subsequent materials used to form the second contact layer 124 will not accumulate on the uneven surface, thereby causing a short circuit. question. In some embodiments, “substantially aligned” means that the maximum vertical distance between the upper surface of the upper electrode layer 116 , the upper surface of the insulating layer 114 and the upper surface of the first dielectric layer 101 is within 3 nm. For example, there is a vertical height H between the upper surface of the insulating layer 114 and the upper surface of the first dielectric layer 101 , and the vertical height H is within 3 nm.

Referring to FIG. 10 , after the first etching process is performed, a second etching process is performed to etch the first contact layer 122 to form the groove R on the first contact layer 122 . Specifically, the second etching process is an etching process with high etching selectivity, so in the second etching process, only part of the first contact layer 122 is removed, and the upper electrode layer 116, the insulating layer 114 and the upper electrode layer 116 are not removed. The first dielectric layer 101. In this way, the removed first contact layer 122 forms a groove R, and the groove R exposes the sidewall of the upper electrode layer 116, that is, the groove R is defined by the first contact layer 122 and the upper electrode layer 116. . In some embodiments, the etchant of the second etching process includes sulfur hexafluoride, argon or a combination thereof. Since the upper electrode layer 116 , the insulating layer 114 are substantially aligned with the surface of the first dielectric layer 101 , the second contact layer 124 will not accumulate on the uneven surface, and the occurrence of short circuits can also be reduced.

Referring to FIG. 11 , the second contact layer 124 is formed in the groove R. Referring to FIG. The resulting second contact layer 124 is on the first contact layer 122 and contacts the sidewalls of the upper electrode layer 116 . In some embodiments, the second contact layer 124 may be formed of a suitable semiconductor or conductive material, such as indium tin oxide (ITO).

After the process of FIG. 11 is completed, the formation of the capacitive structure CA of the semiconductor process is also completed. In the capacitor structure CA, the bottom electrode layer 112, the insulating layer 114 and the upper electrode layer 116 can be collectively regarded as a capacitor, and the first contact layer 122 and the second contact layer 124 are used as contacts for connecting the capacitor and the transistor. channel layer.

Referring to FIG. 12 , after the formation of the capacitive structure CA is completed, other elements, such as the channel layer 144 , can be further formed on the capacitive structure CA. For example, the second dielectric layer 132 , the word line 134 and the third dielectric layer 136 can be sequentially formed on the first dielectric layer 101 and the capacitor structure CA. The second dielectric layer 132 and the third dielectric layer 136 may be formed of any suitable dielectric material. For example, the second dielectric layer 132 and the third dielectric layer 136 may be formed of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride or the like. In some embodiments, the second dielectric layer 132 and the third dielectric layer 136 may be formed of the same dielectric material. Wordlines 134 may be formed of any suitable metal, such as tungsten. Next, an appropriate etching process can be performed to etch the second dielectric layer 132, the word line 134 and the third dielectric layer 136, and form a second dielectric layer 132, the word line 134 and the third dielectric layer 136 The opening of the second contact layer 124 of the capacitive structure CA is exposed. Next, a gate dielectric layer 142 may be formed along sidewalls of the opening. After the gate dielectric layer 142 is formed, a suitable semiconductor material, such as indium gallium zinc oxide (IGZO), is filled in the opening to form a channel layer 144 in the opening. When the channel layer 144 is formed of indium gallium zinc oxide (IGZO), the channel layer 144 may have the advantage of low leakage.

Go back to Figure 1. After the channel layer 144 is formed, other elements, such as bit lines 164 , may then be formed on the channel layer 144 . For example, the fourth dielectric layer 152 can be formed on the third dielectric layer 136 , the gate dielectric layer 142 and the channel layer 144 . The fourth dielectric layer 152 may be formed of any suitable dielectric material. For example, the fourth dielectric layer 152 may be formed of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride or the like. In some embodiments, the second dielectric layer 132 , the third dielectric layer 136 and the fourth dielectric layer 152 may be formed of the same dielectric material. Next, an appropriate etching process may be performed to etch the fourth dielectric layer 152 and form an opening in the fourth dielectric layer 152 exposing the channel layer 144 . Next, a transparent conductive layer 162 can be formed on the bottom surface of the opening and the channel layer 144 , and a metal material is filled in the opening and on the transparent conductive layer 162 to form the bit line 164 . In some embodiments, bitline 164 is formed of tungsten.

In summary, using the etching process according to some embodiments of the present disclosure can improve the flatness of the upper surface of the capacitor structure. Specifically, when using the etching process of the present disclosure to remove the oxide layer on the contact layer, since the etching process of the present disclosure can remove the surrounding oxide with substantially the same etching rate and etch selectivity in the same process. The upper electrode layer, insulating layer and dielectric layer of the layer. In this way, when the oxide layer on the contact layer is removed, the underlying contact layer can be substantially aligned with the upper surfaces of the upper electrode layer, insulating layer, and dielectric layer. Therefore, the formed capacitor structure has a substantially flat top surface, which can reduce defects caused by uneven top surfaces in the resulting semiconductor device, such as short circuit problems caused by contact material accumulated on the uneven surface.

Although this disclosure has been disclosed as above in the form of implementation, it is not intended to limit this disclosure. Anyone who is familiar with this technology can make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, the protection of this disclosure The scope shall be defined by the appended patent application scope.

100: Semiconductor device

101: the first dielectric layer

102: The first dielectric layer

104: The second dielectric layer

111: electrode layer

112: Bottom electrode layer

114: insulation layer

116: Upper electrode layer

122: The first contact layer

123: oxide layer

124: Second contact layer

132: second dielectric layer

134: character line

136: The third dielectric layer

142: gate dielectric layer

144: Channel layer

152: The fourth dielectric layer

162: transparent conductive layer

164: bit line

CA: capacitor structure

H: vertical height

R: Groove

T: Groove

TR: Transistor

FIG. 1 illustrates a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. 2 to 12 illustrate cross-sectional views of intermediate stages in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure.

Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none

100:Semiconductor device

101: the first dielectric layer

102: The first dielectric layer

104: The second dielectric layer

112: Bottom electrode layer

114: insulation layer

116: Upper electrode layer

122: The first contact layer

124: Second contact layer

132: second dielectric layer

134: character line

136: The third dielectric layer

142: gate dielectric layer

144: Channel layer

152: The fourth dielectric layer

162: transparent conductive layer

164: bit line

CA: capacitor structure

H: vertical height

TR: Transistor

Claims (9)

A method of manufacturing a semiconductor device, comprising: forming a first dielectric layer; etching the first dielectric layer to form a trench in the first dielectric layer; forming a bottom electrode layer on a side of the trench A lower part of the sidewall and a bottom of the trench; an insulating layer is formed along an upper part of the sidewall of the trench and the bottom electrode layer; along the insulating layer, an upper electrode layer is formed on the insulating layer ; forming a first contact layer in the trench and on the upper electrode layer, wherein an oxide layer is formed on a top surface of the first contact layer; performing a first etching process to etch the first contact the oxide layer, the upper electrode layer, the insulating layer, and the first dielectric layer on the top surface of the dot layer, wherein the first etching process is effective for the oxide layer, the upper electrode layer, the insulating layer, and The first dielectric layer has substantially the same etch selectivity, and the first etch process removes the oxide layer to expose the first contact layer, wherein after the first etch process is completed, the first contact layer, the upper electrode layer, the insulating layer, and the plurality of upper surfaces of the first dielectric layer are substantially aligned; a second etching process is performed to etch the first contact layer to form contacts on the first contact layer a groove; and forming a second contact layer in the groove. The method according to claim 1, wherein the etchant for performing the first etching process comprises boron trichloride, chlorine gas or a combination thereof. The method as claimed in claim 1, wherein the etchant for performing the first etching process does not contain fluorine. The method as claimed in claim 1, wherein when performing the first etching process, the upper electrode layer, the insulating layer and the first dielectric layer are removed to a thickness substantially the same as a thickness of the oxide layer. The method according to claim 1, wherein after the first etching process is completed, there is a vertical height between an upper surface of the insulating layer and an upper surface of the first dielectric layer, and the vertical height is between 3 within nanometers. The method according to claim 1, wherein forming the bottom electrode layer on the lower portion of the sidewall of the trench comprises: forming an electrode layer along the sidewall of the trench and the bottom of the trench; and displacing An upper portion of the electrode layer is removed to form the bottom electrode layer along the lower portion of the sidewall of the trench. A semiconductor device, comprising: a first dielectric layer; a capacitor structure, in the first dielectric layer, comprising: a bottom electrode layer covering the lower part of the side wall of the first dielectric layer part; an insulating layer covering an upper portion of the sidewall of the first dielectric layer and the bottom electrode layer; an upper electrode layer covering the insulating layer, an upper surface of the insulating layer and the first dielectric layer There is a vertical height between an upper surface, and the vertical height is within 3 nanometers, and an upper surface of the upper electrode layer, the upper surface of the insulating layer and the upper surface of the first dielectric layer are substantially alignment; a first contact layer covering a lower portion of the upper electrode layer; and a second contact layer covering an upper portion of the upper electrode layer and the second contact layer is on the first contact layer; and a transistor located on the capacitive structure and electrically connected with the capacitive structure. The semiconductor device according to claim 7, wherein the transistor comprises: a channel layer on and in contact with the capacitor structure; and a word line surrounding the channel layer. The semiconductor device according to claim 8, wherein the transistor further comprises a bit line on and connected to the channel layer.

Images