TWI798817B - Integrated circuit - Google Patents

Abstract

The present invention provides an integrated circuit that can perform mining algorithms. The integrated circuit includes a memory die and a field programmable gate array (FPGA) die. The memory die includes a memory cell array. The memory die is electrically connected to the FPGA die. The FPGA die includes a memory controller and a memory cell array management circuit. The memory controller outputs an access command signal for accessing the memory die to the memory cell array management circuit, and the memory cell array management circuit outputs a management signal to the memory die based on the access command signal.

Description

integrated circuit

The invention relates to an integrated circuit capable of executing a mining algorithm.

Blockchain technology can be said to be the most disruptive innovative technology since the Internet age. In addition to using cryptography to encrypt data transmitted on the Internet, blockchain technology also uses decentralized algorithms constructed by mathematics to solve the problems of information security and information trust on the Internet at a very low cost, and can be solved in no time. Under the premise of third-party intervention, users can reach a consensus on the value of data. Therefore, the underlying technology of the blockchain can be regarded as a decentralized distributed database. That is to say, the data on each blockchain is stored in different cloud systems, and the accounting and storage are distributed. Each node needs to self-verify, transfer and manage, so that participants do not need to rely on additional management Institutions and hardware equipment, and the data inside the blockchain can be made more reliable through the maintenance of collective participants. During the development of the blockchain, many new types of virtual digital cryptocurrencies are constantly being produced on the network, and mining (mining) is that the participants calculate and generate each block through their respective computing resources on the network. The matching answer of the computing node, and the verification of the network node through the proof of work mechanism (Proof of Work, POW) in the least time is required to establish the transaction.

The development of hardware used in mining, from the earliest central processing unit (Central Processing Unit, CPU) mining, graphics processing unit (Graphics Processing Unit, GPU) mining, to field programmable logic gate array (Field Programmable Gate Array, FPGA) mining and Application Specific Integrated Circuit (ASIC) mining are gradually evolving. In the early days, Bitcoin (Bitcoin) miners used CPU or GPU products to mine. However, since mining is a computing-intensive application, and with the continuous improvement of the number of miners and device performance, the difficulty of mining has gradually increased. Currently, mining with a CPU has little benefit and may even lead to losses.

ASIC mining completes most of the calculations directly through the circuit. When designing the circuit, the circuit is designed to be able to perform corresponding calculations. Through this method, the computing performance is greatly increased and the power consumption is reduced. Therefore, the benefits are much higher than that of the CPU and GPUs also contribute to the centralization of mining hardware. For customized mining using ASIC chips, the algorithm will design the optimal algorithm according to different types of virtual digital currencies to achieve the highest computing power, but the disadvantage is that when the price of a single currency type collapses, the chip will be damaged due to The mining efficiency does not meet expectations and needs to be replaced, which may lead to the risk of ASIC chip development loss.

If FPGA is used for mining, the speed will be faster than CPU and GPU. Users can write programs (mining algorithms) into FPGA according to actual needs. Therefore, FPGA can change the mining algorithm according to the needs of users.

It should be noted that the content of the "Prior Art" paragraph is used to help understand the present invention. Some (or all) of the content disclosed in the "Prior Art" paragraph may not be the prior art known by those skilled in the art. in the "first The content disclosed in the paragraph "Prior Technology" does not mean that the content has been known to those with ordinary knowledge in the technical field before the application of the present invention.

The invention provides an integrated circuit to be applied to block chain technology.

An integrated circuit provided by the present invention includes a first memory chip and a first field programmable logic array (Field Programmable Gate Array, FPGA) chip. The first memory chip includes a memory cell array. The first FPGA chip is electrically connected to the first memory chip. The first FPGA chip includes a memory controller and a memory cell array management circuit. The memory controller outputs an access command signal for accessing the first memory chip to the memory cell array management circuit, and the memory cell array management circuit sends a management signal to the first memory chip according to the access command signal.

Based on the above, the embodiments of the present invention use the memory cell array management circuit of the FPGA chip to execute the access command signal sent by the memory controller. The memory cell array management circuit of the FPGA chip can generate a management signal for managing the memory cell array to the first memory chip according to the access command signal. The algorithm can be written into the FPGA chip according to the actual application, and the FPGA chip can quickly access the memory chip based on the operation of the algorithm. Therefore, the integrated circuit can be applied to blockchain technology.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

100, 200, 300, 500, 700, 800: integrated circuits

101, 201, 301, 410, 501, 701, 801: row address signal

102, 202, 302, 502, 702, 802, 902, 1102, 1202: memory controller

103, 203, 503, 703, 803, 903: memory cell array management circuit

104, 204, 304, 504, 704, 804: access command signal

105, 205, 305, 405, 505, 606, 705, 805, 1103A: memory cell array

107, 207, 307: management signal

108, 208, 308, 408, 508, 708, 808: column address signal

109, 309, 509, 709, 709A, 709B, 809, 809A, 809B: memory bank selection signal

110, 210, 310, 510, 710, 810, 901, 1002, 1004: FPGA chips

120, 220, 320, 400, 520, 720, 820, 900, 1001, 1003, 1103, 1203: memory chip

204a, 304a, 704a, 804a: control signal

204b, 304b, 504b, 704b, 804b: access address signal

211, 311, 511, 711, 811: logic control circuit

212, 312, 512, 712, 812: memory cell array selection circuit

213, 313, 513, 713, 813: address register

214, 314, 414, 514, 714: decoding circuit

415, 515, 715, 815: column address decoding circuit

416, 516, 716, 816: row address decoding circuit

417, 517, 717, 817, 908: input and output circuits

418, 518, 718, 818: drive circuit

519, 719, 819: memory bank selection circuit

521, 721, 821: column address selection circuit

522, 722, 822: refresh counter

523, 723, 823: address counter

524: instruction decoding circuit

904: interface circuit

905: block memory

906:Algorithm module

907:Look-up table (LUT)

909: Embedded algorithm module

1100, 1200: memory wafer

1101, 1201: FPGA wafer

1203A, 1203B, 1203C, 1203D: memory bank group

BL: bit line

BP: micro bump

BUS: Bus

CAP: Capacitance

DB: data bus

GIO: global input and output circuit

LIO: local input and output circuit

MC: memory cell

SIN: write data signal

SOUT: read data signal

SUB: package substrate

TR: Transistor

WF1: first wafer

WF2: second wafer

WF3: third wafer

WF4: fourth wafer

WL, WL': character line

FIG. 1 is a schematic diagram of a circuit block of an integrated circuit according to an embodiment of the present invention.

FIG. 2 is a schematic circuit block diagram of an integrated circuit according to another embodiment of the present invention.

FIG. 3 is a schematic circuit block diagram of an integrated circuit according to yet another embodiment of the present invention.

FIG. 4 is a schematic circuit block diagram of a memory chip according to an embodiment of the invention.

FIG. 5 is a schematic circuit block diagram of an integrated circuit according to an embodiment of the invention.

FIG. 6 is a partially enlarged schematic diagram of a memory bank according to an embodiment of the present invention.

FIG. 7 is a schematic circuit block diagram of an integrated circuit according to an embodiment of the invention.

FIG. 8 is a schematic circuit block diagram of an integrated circuit according to an embodiment of the invention.

FIG. 9 is a block diagram of a part of the connection structure between a programmable logic array chip and a memory chip according to an embodiment of the present invention.

10 to 14 are schematic diagrams illustrating the stacking of a programmable logic array wafer and a memory wafer in an integrated circuit according to different embodiments of the present invention.

Fig. 15 is the input and output circuit in the integrated circuit according to an embodiment of the present invention Block diagram of road configuration.

FIG. 16 is a schematic block diagram of the configuration of the input and output circuits in the integrated circuit according to an embodiment of the present invention.

Features of the inventive concept and methods of achieving the same can be more easily understood by referring to the following detailed description of the embodiments and the accompanying drawings. Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings, in which like reference numerals refer to like elements throughout. However, the invention may be embodied in various different forms and should not be construed as limited to only the embodiments set forth herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the aspects and features of the invention to those skilled in the art. Accordingly, processes, elements and techniques that are not necessary for a person of ordinary skill in the art to fully understand the aspects and features of the invention may not be described. Unless otherwise indicated, like reference numerals denote like elements throughout the accompanying drawings and written description, and thus description thereof will not be repeated. In the drawings, the relative sizes of elements, layers and regions may be exaggerated for clarity.

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments. It is evident, however, that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the various embodiments.

It will be understood that when an element, layer, region or element is referred to as being on another element, When a layer, region or element is "on," "connected to" or "coupled to" another element, layer, region or element, it can be directly on, connected to or coupled to another element, layer, region or element. An element, layer, region or element, or one or more intervening elements, layers, regions or elements may be present. However, "directly connected/directly coupled" means that one element is directly connected or coupled to another element without intervening elements. Meanwhile, other expressions describing the relationship between elements, such as "between", "immediately between", or "adjacent to" and "immediately adjacent to", may be similarly understood. In addition, it will also be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there may also be a or multiple intervening elements or intervening layers.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular form "a/an" is intended to include the plural unless the context clearly dictates otherwise. It will be further understood that the terms "comprises/comprising", "have/having" and "includes/including" when used in this specification mean stated features, integers, steps, operations, The presence of an element and/or an element does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, elements and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

As used herein, the terms "substantially," "about," "approximately," and similar terms are used as terms of approximation and not as terms of degree, and are intended to take into account measured or calculated values that would be recognized by one of ordinary skill in the art inherent bias in . As used herein, "about" or "approximately" is inclusive of the stated value and means a value as determined by an ordinary within an acceptable range of deviation from a specific value as determined by a skilled artisan. For example, "about" can mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value. Additionally, the use of "may" when describing embodiments of the invention means "one or more embodiments of the invention." As used herein, the terms "use", "using", and "used" may be considered in contrast to the terms "utilize", "utilizing", "Utilized" is synonymous. Additionally, the term "exemplary" is intended to mean an example or illustration.

When an embodiment can be implemented differently, a particular order of processing may be executed differently than that described. For example, two consecutively described processes may be performed substantially simultaneously or in an order reverse to the described order.

Various embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of embodiments and/or intermediate structures. As such, variations from the illustrated shapes as a result, for example, of manufacturing techniques and/or tolerances are to be expected. Furthermore, for the purpose of describing embodiments according to the concepts of the present disclosure, specific structural or functional descriptions disclosed herein are merely illustrative. Thus, embodiments disclosed herein should not be construed as limited to the particular illustrated shapes of regions but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration across its edges rather than a binary change from implanted to non-implanted region. Likewise, buried regions formed by implantation can be Some implantation occurs in the region between the buried region and the surface where the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to be limiting.

Electronic or electronic devices according to embodiments of the present invention described herein and/or any other related devices or components may utilize any suitable hardware, firmware (such as application specific integrated circuits), software or software, firmware and Composite implementation of hardware. For example, the various elements of these devices may be formed on one integrated circuit (IC) die or on separate IC dies. In addition, various elements of these devices may be implemented on flexible printed circuit films, tape carrier packages (TCP), printed circuit boards (PCB), or formed on one substrate. In addition, the various elements of these devices may be processes running on one or more processors in one or more computing devices, executing computer program instructions, and interacting with other system elements for performing the various functions described herein or threads of execution. Computer program instructions are stored in memory that can be implemented in a computing device using standard memory devices such as random access memory (RAM). Computer program instructions may also be stored on other non-transitory computer readable media such as CD-ROMs, flash memory drives, or the like. Furthermore, those skilled in the art will recognize that the functionality of various computing devices may be combined or integrated into a single computing device, or that the functionality of a particular computing device may be distributed among one or more other computing devices without departing from the principles of the present invention. spirit and scope of the exemplary embodiments.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs of the same meaning. It will be further understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having meanings consistent with their meanings in the context of the relevant art and/or in this specification, and should not be interpreted in an idealized or overly formalized sense unless otherwise expressly defined herein.

FIG. 1 is a schematic diagram of a circuit block of an integrated circuit 100 according to an embodiment of the present invention. The integrated circuit 100 shown in FIG. 1 at least includes a memory chip 120 and a field programmable logic array (Field Programmable Gate Array, FPGA) chip 110 . According to design requirements, in some application examples, the memory chip 120 includes at least one memory cell array (memory cell array) 105 . The number of memory cell arrays 105 can be determined according to actual design. In some embodiments, the memory cell array 105 may include a plurality of dynamic random access memory (DRAM) cells. One (or more) memory cell arrays 105 can be defined as a memory bank.

The FPGA chip 110 is electrically connected to the memory chip 120 . The FPGA chip 110 at least includes a memory controller (memory controller) 102 and a memory cell array management circuit 103 . Based on the requirements of the algorithm run by the FPGA chip 110 , the memory controller 102 outputs an access command signal 104 for accessing the memory chip 120 to the memory cell array management circuit 103 . The memory cell array management circuit 103 is used for managing the memory cell array 105 of the memory chip 120 . According to the access command signal 104 output by the memory controller 102 , the memory cell array management circuit 103 sends at least one management signal 107 to the memory chip 120 . This embodiment does not limit the specific content of the management signal 107 . For example, according to the actual design, the management signal 107 may include a memory bank Select signal 109 , row address (row address) signal 108 and row address (column address) signal 101 . The memory bank selection signal 109 is used to select the memory bank 108 .

FIG. 2 is a schematic circuit block diagram of an integrated circuit 200 according to another embodiment of the present invention. The integrated circuit 200 includes a memory chip 220 and an FPGA chip 210 . In the application example shown in FIG. 2 , the memory chip 220 includes a memory cell array 205 and a decoding circuit 214 , and the FPGA chip 210 includes a memory controller 202 and a memory cell array management circuit 203 . The integrated circuit 200, FPGA chip 210, memory controller 202, memory cell array management circuit 203, memory chip 220 and memory cell array 205 shown in Figure 2 can refer to the integrated circuit 100, FPGA chip 110, The relevant descriptions of the memory controller 102 , the memory cell array management circuit 103 , the memory chip 120 and the memory cell array 105 are analogous, so they are not repeated here.

In the application example shown in FIG. 2, the access command signal 204 includes a control signal 204a and an access address signal 204b, and the memory cell array management circuit 203 includes a logic control circuit 211, a memory cell array selection circuit 212, and an address register device 213. The address register 213 is electrically connected to the memory controller 202 . The memory cell array selection circuit 212 is electrically connected to the address register 213 . Based on the requirements of the algorithm run by the FPGA chip 210, the programmable memory controller 202 utilizes hardwired control or micro-programmed control to generate signals for accessing the memory chip 220. The control signal 204 a is sent to the logic control circuit 211 of the memory cell array management circuit 203 , and the access address signal 204 b is sent to the address register 213 .

The address register 213 is electrically connected to the memory controller 202 to receive the The address signal 204b in the access command signal 204 is accessed. The address register 213 can provide the access address information corresponding to the access address signal 204 b to the logic control circuit 211 and the memory cell array selection circuit 212 . The logic control circuit 211 can decode the access command signal 204 . The logic control circuit 211 is electrically connected to the memory controller 202 to receive the control signal 204 a (the access command signal 204 ) output by the memory controller 202 . The logic control circuit 211 decodes the control signal 204 a in the access command signal 204 to generate a decoding result, and sends the decoding result to the memory cell array selection circuit 212 .

The memory cell array selection circuit 212 is electrically connected to the address register 213 to receive the access address information corresponding to the access address signal 204b. The memory cell array selection circuit 212 outputs at least one management signal 207 to the decoding circuit 214 in the memory chip 220 according to the decoding result of the logic control circuit 211 and the access address information provided by the reference address register 213 . In the embodiment shown in FIG. 2 , the management signal 207 may include a column address signal 208 and a row address signal 201 . The column address signal 208 and the row address signal 201 shown in FIG. 2 can be analogized with reference to the related description of the column address signal 108 and the row address signal 101 shown in FIG. 1 . Alternatively, the column address signal 108 and the row address signal 101 shown in FIG. 1 can be analogized with reference to the related description of the column address signal 208 and the row address signal 201 shown in FIG. 2 . Since the logic control circuit 211 , the memory cell array selection circuit 212 and the reference address register 213 are configured in the FPGA chip 210 , the access speed of the memory controller 202 to the memory cell array 205 can be improved.

In the embodiment shown in Figure 2, the decoding circuit is electrically connected to the memory cell array At least one word line and at least one bit line of column 205 . The decoding circuit 214 receives the column address signal 208 and the row address signal 201, and performs address decoding on the received column address signal 208 and the row address signal 201, and then drives the word line of the memory cell array 205 according to the decoding result and bit lines for data access. For example, in some application examples, the decoding circuit 214 can write the data from the data bus DB into the memory cell array 205 by driving the word lines and the bit lines. Or in some other application examples, the decoding circuit 214 can read the data of the memory cell array 205 to the data bus DB by driving the word line and the bit line.

FIG. 3 is a schematic circuit block diagram of an integrated circuit 300 according to another embodiment of the present invention. The integrated circuit 300 at least includes a memory chip 320 and an FPGA chip 310 . In the embodiment shown in FIG. 3 , the memory chip 320 includes a plurality of memory cell arrays 305 and a decoding circuit 314 , wherein the memory cell arrays 305 can be defined as a plurality of memory banks. In the embodiment shown in FIG. 3, the FPGA chip 310 includes a memory controller 302 and a memory cell array management circuit 303, and the memory cell array management circuit 303 includes a logic control circuit 311, an address register 313, and a memory cell array selection circuit. 312. The integrated circuit 300 shown in FIG. 3 , the FPGA chip 310 , the memory controller 302 , the memory cell array management circuit 303 , the logic control circuit 311 , the memory cell array selection circuit 312 , the address register 313 , the memory chip 320 , Memory cell array 305 and decoding circuit 314 can refer to integrated circuit 200 shown in Figure 2, FPGA chip 210, memory controller 202, memory cell array management circuit 203, logic control circuit 211, memory cell array selection circuit 212, address Relevant descriptions of temporary register 213, memory chip 220, memory cell array 205 and decoding circuit 214 are added Analogy, so no more details.

The memory controller 302 generates an access command 304 (control signal 304 a and access address signal 304 b ) for accessing the memory chip 320 to the logic control circuit 311 and the address register 313 . The logic control circuit 311 decodes the control signal 304a to generate a decoding result. According to the decoding result provided by the logic control circuit 311 and the access address information provided by the address register 313 , the memory cell array selection circuit 312 outputs the management signal 307 to the decoding circuit 314 in the memory chip 320 . In the embodiment shown in FIG. 3 , the management signal 307 includes a column address signal 308 , a row address signal 301 and a bank select signal 309 . The column address signal 308 and the row address signal 301 shown in FIG. The relevant description of the row address signal 201 is analogized. Alternatively, the column address signal 108 and the row address signal 101 shown in FIG. 1 can be analogized with reference to the relevant description of the column address signal 308 and the row address signal 301 shown in FIG. 3 . The memory bank selection signal 309 shown in FIG. 3 can be analogized with reference to the related description of the memory bank selection signal 109 shown in FIG. 1 . Alternatively, the memory bank selection signal 109 shown in FIG. 1 can be analogized with reference to the related description of the memory bank selection signal 309 shown in FIG. 3 .

In the embodiment shown in FIG. 3, the decoding circuit 314 performs address decoding on the column address signal 308, the address signal 301 and the memory bank selection signal 309, and then drives the word lines and bits of the memory cell array 305 according to the decoding results. line for data access. For example, in some application examples, the decoding circuit 314 can select one of multiple memory banks (memory cell array 305) according to the memory bank selection signal 309, and then by Drive the wordlines and bitlines to write data from the data bus DB into the selected memory bank (memory cell array 305). Or in some other application examples, the decoding circuit 314 can read the data of the selected memory bank (memory cell array 305 ) to the data bus DB by driving the word line and the bit line.

FIG. 4 is a schematic circuit block diagram of a memory chip 400 according to an embodiment of the invention. The memory chip 400 shown in FIG. 4 includes a memory cell array 405 and a decoding circuit 414 . The decoding circuit 414 is electrically connected to at least one word line WL and at least one bit line BL of the memory cell array 405 . The decoding circuit 414 can decode at least one column address signal 408 and at least one row address signal 410 output by the memory cell array management circuit (not shown in FIG. 4 ) of the FPGA chip, so as to drive at least one word line of the memory cell array 405 WL and at least one bit line BL. The memory cell array management circuit can refer to the relevant description of the memory cell array management circuit 103, 203 or 303, the column address signal 408 can refer to the relevant description of the column address signal 108, 208 or 308, and the row position The address signal 410 can refer to the relevant description of the row address signal 101 , 201 or 301 , so it is not repeated here.

The decoding circuit 414 includes a column address decoding circuit 415 , a row address decoding circuit 416 , a driving circuit 418 and an input/output circuit 417 . The column address decoding circuit 415 is electrically connected to the memory cell array management circuit (not shown in FIG. 4 ) to receive the column address signal 408 . The column address decoding circuit 415 decodes the column address signal 408 to drive at least one word line WL of the memory cell array 405 . The row address decoding circuit 416 is electrically connected to the memory cell array management circuit (not shown in FIG. 4 ) to receive the row address signal 410 . The row address decoding circuit 416 decodes the row address signal 410 to generate at least one row of decoding results fruit.

The driving circuit 418 is electrically connected to the row address decoding circuit 416 to receive the row decoding result. The driving circuit 418 can drive at least one bit line BL of the memory cell array 405 according to the row decoding result. The I/O circuit 417 is electrically connected to the driving circuit 418 to provide the write data signal SIN (or receive the read data signal SOUT). The I/O circuit 417 is also electrically connected to the memory controller (not shown in FIG. 4 ) through the data bus DB. For the memory controller, reference may be made to relevant descriptions of the memory controller 102 , 202 or 302 , so details are not repeated here. For example, the I/O circuit 417 can transmit the write data signal SIN input by the data bus DB to the driving circuit 418 . And (or), the drive circuit 418 can read data from the memory cell array 405 through a plurality of bit lines BL, and then the drive circuit 418 can provide the read data to the input and output circuit 417 as the read data signal SOUT . Therefore, the I/O circuit 417 can transmit the read data signal SOUT of the driving circuit 418 to the data bus DB.

FIG. 5 is a schematic circuit block diagram of an integrated circuit 500 according to an embodiment of the present invention. The integrated circuit 500 at least includes a memory chip 520 and an FPGA chip 510 . In the embodiment shown in FIG. 5 , the memory chip 520 includes at least one memory cell array 505 and a decoding circuit 514 , wherein the memory cell array 505 can be defined as at least one memory bank. In the embodiment shown in FIG. 5, the FPGA chip 510 includes a memory controller 502 and a memory cell array management circuit 503, and the memory cell array management circuit 503 includes a logic control circuit 511, an address register 513, and a memory cell array selection Circuit 512. Integrated circuit 500, FPGA chip 510 shown in Figure 5, Memory controller 502, memory cell array management circuit 503, logic control circuit 511, memory cell array selection circuit 512, address register 513, memory chip 520, memory cell array 505 and decoding circuit 514 can refer to FIG. 2 Show integrated circuit 200, FPGA chip 210, memory controller 202, memory cell array management circuit 203, logic control circuit 211, memory cell array selection circuit 212, address register 213, memory chip 220, memory cell array 205 and decoding circuit 214 by analogy, or with reference to the integrated circuit 300 shown in Figure 3, FPGA chip 310, memory controller 302, memory cell array management circuit 303, logic control circuit 311, memory cell array selection circuit 312 , the address register 313 , the memory chip 320 , the memory cell array 305 and the decoding circuit 314 are described by analogy, so they will not be repeated here.

The memory controller 502 generates an access command signal 504 for accessing the memory chip 520 to the logic control circuit 511 and the address register 513 . In the embodiment shown in FIG. 5, the access command signal 504 includes a clock signal (clock signal) CLK, a clock enable signal (clock enable signal) CKE, a chip selection signal (chip selection signal) CS, write enable A signal (write enable) WE, a row address selection signal (column array selection signal) CAS, a column address selection signal (row array selection signal) RAS, and an access address signal 504b. The types and numbers of the access command signal 504 can be modified or added according to design requirements and are not limited thereto. According to the actual design, the access command signal 104, 204 or 304 can refer to the relevant description of the access command signal 504, and (or) the control signal 204a or 304a can refer to the clock signal CLK, clock enable signal CKE, chip selection Signal CS, write enable signal WE, row address selection signal CAS and column address selection signal Instructions for No. RAS.

In the embodiment shown in FIG. 5 , the logic control circuit 511 includes an instruction decoding circuit 524 . The instruction decoding circuit 524 decodes the access command signal 504 provided by the memory controller 502 and the access address information provided by the address register 513 to generate a decoding result, and transmits the decoding result to the memory cell array for selection Circuit 512.

In the embodiment shown in FIG. 5 , the memory cell array selection circuit 512 includes a row address mux circuit 521 , a refresh counter 522 and an address counter 523 . The refresh counter 522 generates refresh count information according to the decoding result output by the command decoding circuit 524 and sends it to the column address selection circuit 521 . According to the access address information provided by the address register 513 and the refresh count information provided by the refresh counter 522, the column address selection circuit 521 can output the column address signal 508 to the column decoding circuit 515 in the memory chip 520 . For the column decoding circuit 515, reference may be made to the relevant description of the column decoding circuit 415, and (or) for the column decoding circuit 415, reference may be made to the relevant description of the column decoding circuit 515.

The address counter 523 generates a row address signal 501 according to the access address information provided by the address register 513 , and transmits the row address signal 501 to the row address decoder 516 in the decoding circuit 514 . For the row address decoder 516 , refer to the relevant description of the row address decoder 416 , and (or) for the row address decoder 416 , refer to the relevant description of the row address decoder 516 .

In the embodiment shown in FIG. 5 , the decoding circuit 514 further includes an input and output circuit 517 , a driving circuit 518 and a memory bank selection circuit 519 . The memory bank selection circuit 519 receives the memory bank selection signal 509 provided by the address register 513, and outputs a record The memory selects information to the column address decoding circuit 515 and the row address decoding circuit 516 . The column address decoding circuit 515 performs address decoding according to the column address signal 508 provided by the column address selection circuit 521 and the memory bank selection information provided by the memory bank selection circuit 519, and drives the words of the memory cell array 505 according to the decoding result. Element Line WL. The row address decoding circuit 516 performs address decoding according to the row address signal 501 provided by the address counter 523 and the bank selection information provided by the bank selection circuit 519 , and sends the decoding result to the driving circuit 518 . The driving circuit 518 drives the bit line BL of the memory cell array 505 according to the decoding result provided by the row address decoding circuit 516 to access data.

In the embodiment shown in FIG. 5 , the I/O circuit 517 and the memory controller 502 transmit data to each other through the data bus DB. For the input-output circuit 517 and the driving circuit 518 , reference may be made to the relevant descriptions of the input-output circuit 417 and the driving circuit 418 , so details are not repeated here.

FIG. 6 is a partially enlarged schematic diagram of a memory cell array 606 according to an exemplary embodiment of the present invention. The memory cell array 606 may include: a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC. Each memory cell MC may include a transistor TR and a capacitor CAP. The memory cell MC shown in FIG. 6 is also called a one transistor, one capacitor (1T1C) type memory cell. In some other embodiments, each memory cell MC may include three transistors and one capacitor, which is a so-called three transistor, one capacitor (3T1C) type memory cell. The design of the memory cell MC can vary depending on the actual application and is not limited thereto.

In the embodiment shown in Fig. 6, the gate electrode of the transistor TR in the memory cell MC Electrically coupled to the word line WL, the drain (or source) of the transistor TR is electrically coupled to the bit line BL, and the source (or drain) of the transistor TR is electrically coupled to the capacitor CAP the first end of . The second end of the capacitor CAP is electrically coupled to another word line WL'.

FIG. 7 is a schematic circuit block diagram of an integrated circuit 700 according to another embodiment of the present invention. The integrated circuit 700 shown in FIG. 7 at least includes a memory chip 720 and an FPGA chip 710 . In the embodiment shown in FIG. 7 , the memory chip 720 includes at least one memory cell array 705 and a decoding circuit 714 , wherein the memory cell array 705 can be defined as at least one memory bank. In the embodiment shown in FIG. 7, the FPGA chip 710 includes a memory controller 702 and a memory cell array management circuit 703, and the memory cell array management circuit 703 includes a logic control circuit 711, an address register 713, and a memory cell array selection circuit 712. Figure 7 shows an integrated circuit 700, an FPGA chip 710, a memory controller 702, a memory cell array management circuit 703, a logic control circuit 711, a memory cell array selection circuit 712, an address register 713, a memory chip 720, Memory cell array 705 and decoding circuit 714 can refer to integrated circuit 200 shown in Figure 2, FPGA chip 210, memory controller 202, memory cell array management circuit 203, logic control circuit 211, memory cell array selection circuit 212, address The relevant descriptions of the temporary register 213, the memory chip 220, the memory cell array 205, and the decoding circuit 214 are analogized, or refer to the integrated circuit 300, FPGA chip 310, memory controller 302, and memory cell array management shown in FIG. Circuit 303, logic control circuit 311, memory cell array selection circuit 312, address register 313, memory chip 320, memory cell array 305, and decoding circuit 314 are described by analogy, or refer to the integrated body shown in Figure 5 Circuit 500, FPGA chip 510, memory controller 502, memory cell array The column management circuit 503, the logic control circuit 511, the memory cell array selection circuit 512, the address register 513, the memory chip 520, the memory cell array 505 and the decoding circuit 514 are analogously described, so they are not repeated here.

The memory controller 702 generates an access command signal 704 for accessing the memory chip 720 to the logic control circuit 711 and the address register 713 . In the embodiment shown in FIG. 7, the access command signal 704 includes a control signal 704a and an access address signal 704b. The access command signal 704 can be deduced by referring to the related description of the access command signal 104, 204 or 304, the control signal 704a can be deduced by referring to the related description of the control signal 204a or 304a, and the access address signal 704b can be deduced by referring to the access bit The relevant description of the address signal 204b or 304b is analogized, so it is not repeated here. According to the actual design, the control signal 704a can refer to the clock signal CLK, clock enable signal CKE, chip select signal CS, write enable signal WE, row address select signal CAS and column address select signal RAS shown in FIG. related instructions.

In the embodiment shown in FIG. 7 , the decoding circuit 714 includes a row address decoding circuit 716 , an input/output circuit 717 and a driving circuit 718 . In the embodiment shown in FIG. 7 , the memory cell array selection circuit 712 includes a column address selection circuit 721 , a refresh counter 722 , an address counter 723 , a column address decoding circuit 715 and a memory bank selection circuit 719 . Column address selection circuit 721, refresh counter 722, address counter 723, column address decoding circuit 715, memory bank selection circuit 719, row address decoding circuit 716, input and output circuit 717 and drive circuit 718 shown in Figure 7 can refer to Column address selection circuit 521 shown in Figure 5, refresh counter 522, address counter 523, column address decoding circuit 515, memory bank selection circuit 519, row address decoding circuit 516, The relevant descriptions of the input-output circuit 517 and the driving circuit 518 are analogized, and thus will not be repeated here. In the embodiment shown in FIG. 7, the memory bank selection circuit 719 in the FPGA chip 710 receives the memory bank selection signal 709 provided by the address register 713, and outputs the memory bank selection signal 709A to the row address decoding circuit 715 , and output the bank select signal 709B to the row address decoding circuit 716 in the memory chip 720 . The column address decoding circuit 715 performs address decoding according to the column address signal 708 provided by the column address selection circuit 721 and the memory bank selection signal 709A provided by the memory bank selection circuit 719, and drives the memory cell array 705 according to the decoding result character line for data access.

Since the column address decoding circuit 715 is integrated into the FPGA chip 710 , the FPGA chip 710 can quickly access the memory cell array 705 of the memory chip 720 .

FIG. 8 is a schematic circuit block diagram of an integrated circuit 800 according to yet another embodiment of the present invention. The integrated circuit 800 at least includes a memory chip 820 and an FPGA chip 810 . In the embodiment shown in FIG. 8 , the memory chip 820 includes at least one memory cell array 805 , wherein the memory cell array 805 can be defined as at least one memory bank. In the embodiment shown in FIG. 8, the FPGA chip 810 includes a memory controller 802 and a memory cell array management circuit 803, and the memory cell array management circuit 803 includes a logic control circuit 811, an address register 813, and a memory cell array selection Circuit 812. Integrated circuit 800 shown in Figure 8, FPGA chip 810, memory controller 802, memory cell array management circuit 803, logic control circuit 811, memory cell array selection circuit 812, address temporary register 813, memory chip 820 and Memory cell array 805 can refer to Fig. 2 The shown integrated circuit 200, FPGA chip 210, memory controller 202, memory cell array management circuit 203, logic control circuit 211, memory cell array selection circuit 212, address register 213, memory chip 220 and memory cell The relevant description of the array 205 is analogized, or referring to the integrated circuit 300 shown in FIG. Address temporary register 313, memory chip 320 and memory cell array 305 are analogized, or refer to the integrated circuit 500, FPGA chip 510, memory controller 502, memory cell array management circuit 503 shown in FIG. The relevant descriptions of the logic control circuit 511 , the memory cell array selection circuit 512 , the address register 513 , the memory chip 520 and the memory cell array 505 are analogous, so they are not repeated here.

The memory controller 802 generates an access command signal 804 for accessing the memory chip 820 to the logic control circuit 811 and the address register 813 . In the embodiment shown in FIG. 8, the access command signal 804 includes a control signal 804a and an access address signal 804b. The access command signal 804 can be deduced by referring to the related description of the access command signal 104, 204 or 304, the control signal 804a can be deduced by referring to the related description of the control signal 204a or 304a, and the access address signal 804b can be deduced by referring to the access bit The relevant description of the address signal 204b or 304b is analogized, so it is not repeated here. According to the actual design, the control signal 804a can refer to the clock signal CLK, clock enable signal CKE, chip select signal CS, write enable signal WE, row address select signal CAS and column address select signal RAS shown in FIG. related instructions.

In the embodiment shown in FIG. 8, the memory cell array selection circuit 812 includes columns Address selection circuit 821 , refresh counter 822 , address counter 823 , at least one column address decoding circuit 815 , at least one row address decoding circuit 816 , input/output circuit 817 , drive circuit 818 and memory bank selection circuit 819 . Column address selection circuit 821, refresh counter 822, address counter 823, column address decoding circuit 815, row address decoding circuit 816, input and output circuit 817, drive circuit 818 and memory bank selection circuit 819 shown in Figure 8 can refer to Column address selection circuit 521, refresh counter 522, address counter 523, column address decoding circuit 515, row address decoding circuit 516, input and output circuit 517, drive circuit 518 and memory bank selection circuit 519 shown in Fig. 5 are related The explanation is analogized, so it will not be repeated.

In the embodiment shown in FIG. 8, the memory bank selection circuit 819 receives the memory bank selection signal 809 provided by the address register 813, and outputs the memory bank selection signal 809A to the column address decoding circuit 815, and outputs the memory bank selection The signal 809B goes to the row address decoding circuit 816 . The column address decoding circuit 815 in the FPGA chip 810 performs address decoding according to the column address signal 808 provided by the column address selection circuit 821 and the memory bank selection signal 809A provided by the memory bank selection circuit 819, and according to the decoding result The word lines WL of the memory cell array 805 in the memory chip 820 are driven.

In addition, the address counter 823 in the FPGA chip 810 generates the row address signal 810 to the row address decoder 816 according to the access address information provided by the address register 813 . The row address decoding circuit 816 performs address decoding according to the row address signal 810 provided by the address counter 823 and the bank selection signal 809B provided by the bank selection circuit 819 , and sends the decoding result to the driving circuit 818 . in FPGA The driving circuit 818 in the chip 810 drives the bit line BL of the memory cell array 805 in the memory chip 820 according to the decoding result to access data.

In the embodiment shown in FIG. 8, since the column address decoding circuit 815, the row address decoding circuit 816, the input and output circuit 817 and the driving circuit 818 have been integrated into the FPGA chip 810, the memory chip 820 is composed of a simple The DRAM array (memory cell array 805 ) can save the manufacturing complexity and process cost of the memory chip 820 . In addition, the FPGA chip 810 can directly drive the word lines WL and bit lines BL of the memory cell array 805 of the memory chip 820 . In some application examples, the word line WL and the bit line BL can be controlled by the driving circuit 818 or by the FPGA chip 810 .

FIG. 9 is a schematic diagram of a partial connection structure of an FPGA chip 901 and a memory chip 900 according to an embodiment of the present invention. The FPGA chip 901 shown in FIG. 9 can be analogized with reference to the relevant descriptions of the FPGA chips 110 , 210 , 310 , 510 , 710 and (or) 810 . Alternatively, any one of the FPGA chips 110 , 210 , 310 , 510 , 710 , and 810 can be analogized with reference to the relevant description of the FPGA chip 901 . The memory chip 900 shown in FIG. 9 can be analogized with reference to the relevant description of the memory chips 120 , 220 , 320 , 400 , 520 , 720 and (or) 820 . Alternatively, any one of the memory chips 120 , 220 , 320 , 400 , 520 , 720 and 820 can be analogized with reference to the relevant description of the memory chip 900 .

In the embodiment shown in FIG. 9 , the integrated circuit may be a DRAM embedded FPGA (DRAM embedded FPGA, deFPGA). The integrated circuit shown in FIG. 9 includes an FPGA chip 901 and a memory chip 900 . The FPGA chip 901 includes an embedded de- Algorithm module 909, adjustable algorithm module, silicon intellectual property core (intellectual property core or IP core), interface circuit 904, bus (BUS), advanced RISC Machine (Advanced RISC Machine, ARM), static Random access memory (static random access memory, SRAM), input and output circuit 908 and memory cell array management circuit 903 . According to design requirements, in the embodiment shown in FIG. 9, the adjustable algorithm module may include a memory controller 902, a block memory 905, an algorithm module 906, and a lookup table (look up table, LUT )907. Wherein, the memory chip 900 is electrically coupled with the memory cell array management circuit 903 of the FPGA chip 901 by forming a through silicon via (TSV) structure and other related process interconnection technologies.

The memory controller 902 shown in FIG. 9 can be analogized with reference to the related descriptions of the memory controllers 102 , 202 , 302 , 502 , 702 and (or) 802 . Alternatively, any one of the memory controllers 102 , 202 , 302 , 502 , 702 , and 802 can be analogized with reference to the relevant description of the memory controller 902 . The memory cell array management circuit 903 shown in FIG. 9 can be analogized with reference to the related descriptions of the memory cell array management circuits 103 , 203 , 303 , 503 , 703 and (or) 803 . Alternatively, any one of the memory cell array management circuits 103 , 203 , 303 , 503 , 703 and 803 can be analogized with reference to the related description of the memory cell array management circuit 903 .

In some application examples, the clock pulse of the interface of the embedded memory chip 900 can save power consumption by increasing the bit line width. In some application examples, the memory cell array management circuit 903 can flexibly adjust and control the embedded memory chip 900 to give consideration to both operation speed and bandwidth. In some application examples, the FPGA The chip 901 can simultaneously (parallel) control any memory cells in the embedded memory chip 900 without being limited by the shared interface bandwidth.

In some application examples, the FPGA chip 901 can be designed to execute at least one algorithm (such as a mining algorithm) through programmed hardware design. In some application examples, the FPGA chip 901 includes hardware for executing at least one mining algorithm, such as an embedded algorithm module 909 . For example, the embedded algorithm module 909 can execute the underlying algorithm of the mining application, such as the hash algorithm (Hash algorithm) and (or) other algorithms. The number of embedded algorithm modules 909 can be determined according to the actual design, and different embedded algorithm modules 909 can execute different mining algorithms according to application requirements, so as to take into account mining speed and bandwidth. In some application examples, the mining algorithm of the embedded algorithm module 909 can be a bottom-level algorithm constructed by using different hash functions, such as SHA, SHA256 and Ethereum and other commonly used mining algorithm hardware . Among them, the mining algorithm used by Ethereum is the Dagger-Hashimoto algorithm, and its mining efficiency has nothing to do with the performance of the processor, but is positively correlated with the bandwidth of the memory. The bandwidth can be defined as the bus width multiplied by the bus frequency times the number of packets exchanged in one clock cycle (ie: bandwidth=bus width*bus frequency*in one clock cycle number of packets exchanged). In some application examples, the bandwidth of the FPGA chip 901 is at least 15 times that of a traditional double data rate (DDR) DDR.

In some embodiments, this underlying algorithm hardware design can be configured in an IP core. The algorithm module 906 can directly call the IP core to execute the underlying algorithm. Users do not need to develop additional underlying algorithms, nor do they need to program additionally on the FPGA (programming) the underlying algorithm, so it can reduce the time to develop mining algorithm hardware. The algorithm module 906 can directly call the embedded algorithm module 909 and (or the IP core) to execute the underlying algorithm to improve mining efficiency.

In some application examples, the number of algorithm modules 906 can be determined according to actual design. Each algorithm module 906 can implement one or more mining algorithms, and different algorithm modules 906 can be used to implement different mining algorithms. In some application examples, mining algorithm hardware can be developed by itself according to different mining needs of users. In addition, this embodiment does not limit the type, implementation and execution details of the mining algorithm hardware. In an embodiment of the present invention, the mining hardware code designed according to the needs of users can be programmed into the algorithm module 906 shown in FIG. 9 to execute the mining algorithm. In one embodiment, when the FPGA chip 901 is configured with multiple mining algorithms (multiple algorithm modules 906), the integrated circuit shown in FIG. 9 can be switched to mining in different currencies at any time according to application requirements. Algorithm does not need to replace the entire set of integrated circuits, so it can reduce the risk of chip development loss and ensure its mining benefits.

In the embodiment shown in FIG. 9 , the interface circuit 904 is used as the internal interface of the FPGA chip 901 for communication. According to actual design, the interface circuit 904 may include an Advanced eXtensible Interface (AXI) bus or other interface circuits. The block memory 905 is used as a temporary storage of internal data of the FPGA chip 901 . The LUT 907 is used as an internal look-up table of the FPGA chip 901 . In some application examples, the input/output circuit 908 includes a low speed input/output (low speed I/O) circuit as an interface circuit for the FPGA chip 901 to communicate with the outside world. For example, in After the algorithm module 906 executes the mining algorithm, the input and output circuit 908 can transmit the operation result of the algorithm module 906 to an external circuit (not shown). Among them, the built-in ARM in the FPGA chip 901 can be used as an independent operating system to perform mining operations without connecting to an external computer for mining.

10 to 14 are schematic diagrams illustrating stacking of FPGA wafers and memory wafers in integrated circuits according to different embodiments of the present invention. The memory wafer means that a plurality of memory chips 1001 (eg, DRAM chips) are formed on the memory wafer (first wafer). The FPGA wafer means that a plurality of FPGA chips 1002 are formed on the FPGA wafer (second wafer). The memory chip (eg 1001 and/or 1003 ) shown in FIGS. 10 to 14 can be analogized with reference to the related description of the memory chip 120 , 220 , 320 , 400 , 520 , 720 , 820 and (or) 900 . Alternatively, any one of the memory chips 120 , 220 , 320 , 400 , 520 , 720 , 820 and 900 can be analogized with reference to the related descriptions of the memory chips 1001 and (or) 1003 shown in FIGS. 10 to 14 . The FPGA chip (eg 1002 and/or 1004 ) shown in FIGS. 10 to 14 can be analogized with reference to the related description of the FPGA chip 110 , 210 , 310 , 510 , 710 , 810 and (or) 901 . Alternatively, any one of the FPGA chips 110 , 210 , 310 , 510 , 710 , 810 and 901 can be analogized with reference to the related descriptions of the FPGA chips 1002 and (or) 1004 shown in FIGS. 10 to 14 . The memory wafer and the FPGA wafer can be electrically bonded to each other by wafer bonding technology.

In the embodiment shown in Figure 10, a plurality of memory chips 1001 (such as DRAM chips) are formed on the first wafer WF1, and the FPGA that can execute the mining hardware algorithm Wafer 1002 is formed on second wafer WF2. In some embodiments, the first wafer WF1 is first bonded to the second wafer WF2 by a heterogeneous wafer bonding (wafer bonding) technique. Then, the first wafer WF1 is electrically connected to the packaging substrate SUB through a connecting structure, such as a micro bump BP. Therefore, the first wafer WF1 is stacked on the packaging substrate SUB, and the second wafer WF2 is stacked on the first wafer WF1.

In some other embodiments, the first wafer WF1 is firstly stacked on the package substrate SUB through a connecting structure, such as a micro bump BP. Then, the second wafer WF2 is stacked on the first wafer WF1 again.

In the embodiment shown in FIG. 11 , a plurality of memory chips 1001 are formed on a first wafer WF1 , and a plurality of memory chips 1003 are formed on a third wafer WF3 . A plurality of FPGA chips 1002 capable of executing mining hardware algorithms are formed on the second wafer WF2.

In some embodiments, the first wafer WF1 is first bonded to the second wafer WF2 by heterogeneous wafer bonding technology, and then the third wafer WF3 is also stacked on the second wafer WF2 by heterogeneous wafer bonding technology. superior. Then, the bonded wafer assembly is electrically connected to the packaging substrate SUB through a connecting structure, such as a micro bump BP. Therefore, the first wafer WF1 is stacked on the packaging substrate SUB, the second wafer WF2 is stacked on the first wafer WF1, and the third wafer WF3 is stacked on the second wafer WF2.

In some other embodiments, the first wafer WF1 is stacked on the package substrate SUB through a connecting structure, such as micro bumps BP, and the second wafer WF2 is then stacked on the first wafer WF1. Next, the third wafer WF3 is stacked on the second wafer on WF2.

In the embodiment shown in FIG. 11 , the second wafer WF2 with the FPGA chip 1002 can simultaneously access the third wafer WF3 with the memory chip 1003 and the first wafer WF1 with the memory chip 1001 . Therefore, the FPGA chip 1002 shown in FIG. 11 can achieve twice the memory access bandwidth.

In the embodiment shown in FIG. 12 , a plurality of memory chips 1001 (such as DRAM chips) are formed on a first wafer WF1, and FPGA chips 1002 capable of executing mining hardware algorithms are formed on a second wafer WF2. In some embodiments, the first wafer WF1 is first bonded to the second wafer WF2 by heterogeneous wafer bonding technology. Then, the second wafer WF2 is electrically connected to the packaging substrate SUB through a connecting structure, such as a micro bump BP. Therefore, the second wafer WF2 is stacked on the package substrate SUB, and the first wafer WF1 is stacked on the second wafer WF2.

In the embodiment shown in FIG. 13 , a plurality of memory chips 1001 are formed on a first wafer WF1 , and a plurality of memory chips 1003 are formed on a third wafer WF3 . A plurality of FPGA chips 1002 capable of executing mining hardware algorithms are formed on the second wafer WF2.

In some embodiments, the first wafer WF1 is first bonded to the second wafer WF2 by heterogeneous wafer bonding technology, and then the third wafer WF3 is also stacked on the first wafer WF1 by heterogeneous wafer bonding technology. superior. Then, the bonded wafer assembly is electrically connected to the packaging substrate SUB through a connecting structure, such as a micro bump BP. Therefore, the second wafer WF2 is stacked on the packaging substrate SUB, the first wafer WF1 is stacked on the second wafer WF2 , and the third wafer WF3 is stacked on the first wafer WF1 .

In the embodiment shown in FIG. 14 , a plurality of memory chips 1001 are formed on a first wafer WF1 , and a plurality of memory chips 1003 are formed on a third wafer WF3 . In addition, a plurality of FPGA chips 1002 capable of executing mining hardware algorithms are formed on the second wafer WF2, and a plurality of FPGA chips 1004 are formed on the fourth wafer WF4.

In some embodiments, the first wafer WF1 is first bonded to the second wafer WF2 by heterogeneous wafer bonding technology, and then the fourth wafer WF4 is also stacked on the first wafer WF1 by heterogeneous wafer bonding technology. Then, the third wafer WF3 is stacked on the fourth wafer WF4 by heterogeneous wafer bonding technology. Then, the bonded wafer assembly is electrically connected to the packaging substrate SUB through a connecting structure, such as a micro bump BP. Therefore, the second wafer WF2 is stacked on the packaging substrate SUB, the first wafer WF1 is stacked on the second wafer WF2, the fourth wafer WF4 is stacked on the first wafer WF1, and the third wafer WF3 is stacked on the on the fourth wafer WF4.

In the embodiment shown in Figure 14, the second wafer WF2 with FPGA chip 1002 and the fourth wafer WF4 with FPGA chip 1004 can access the third wafer WF3 with memory chip 1003 and the third wafer WF3 with memory chip 1001. The first wafer WF1.

FIG. 15 is a schematic block diagram of an input-output circuit configuration in an integrated circuit according to an embodiment of the present invention. The integrated circuit includes a memory wafer 1100 and an FPGA wafer 1101 . The FPGA wafer 1101 includes at least one FPGA chip (not shown) and at least one memory controller 1202 . The memory wafer 1100 includes a plurality of memory chips 1103 , a plurality of local input and output circuits LIO and a global input and output circuit GIO. The memory chip 1103 includes a plurality of memory cell arrays 1103A.

In some applications, the local I/O circuit LIO retrieves information from memory banks in each memory chip 1103 . The global I/O circuit GIO collects the access information of each local I/O circuit LIO, and then transmits the access information to the memory controller 1102 in the FPGA chip 1101 through the shared data bus DB. In some application examples, at least thousands of shared data bus DBs can be provided for the memory controller 1102 to use. In some application examples, the memory controller 1102 is responsible for controlling the reading of the memory chip 1103 and can share a set of DDR communication interfaces.

The memory controller 1102 shown in FIG. 15 can be analogized with reference to the related descriptions of the memory controllers 102 , 202 , 302 , 502 , 702 , 802 and (or) 902 . Alternatively, any one of the memory controllers 102 , 202 , 302 , 502 , 702 , 802 , and 902 can be analogized with reference to the relevant description of the memory controller 1102 . The local input and output circuit LIO and (or) the global input and output circuit GIO shown in FIG. Alternatively, any one of the input-output circuits 417, 517, 717, and 817 can be analogized with reference to the relevant descriptions of the local input-output circuit LIO and (or) the global input-output circuit GIO.

FIG. 16 is a schematic block diagram of an input-output circuit configuration in an integrated circuit according to an embodiment of the present invention. The integrated circuit includes a memory wafer 1200 and an FPGA wafer 1201 . The FPGA chip 1201 includes at least an FPGA chip (not shown), a memory controller 1202 and a global input/output circuit GIO. The memory chip 1200 includes a plurality of memory chips 1203 and a plurality of local input and output Circuit LIO.

In the embodiment shown in FIG. 16, each local input and output circuit LIO accesses information from the memory bank in the corresponding memory chip 1203, and transmits the access information of each local input and output circuit LIO through a separate data bus DB. to the global input/output circuit GIO in the FPGA wafer 1201 . The global I/O circuit GIO collects the access information of each local I/O circuit LIO and then transmits the access information to the memory controller 1202 in the FPGA wafer 1201 through the internal data lines. The memory controller 1202 shown in FIG. 16 can be analogized with reference to the related descriptions of the memory controllers 102 , 202 , 302 , 502 , 702 , 802 and (or) 902 . Alternatively, any one of the memory controllers 102 , 202 , 302 , 502 , 702 , 802 and 902 can be analogized with reference to the relevant description of the memory controller 1202 . The local input and output circuit LIO and (or) the global input and output circuit GIO shown in FIG. Alternatively, any one of the I/O circuits 417, 517, 717, and 817 can be analogized with reference to the relevant descriptions of the local I/O circuit LIO and (or) the global I/O circuit GIO shown in FIG. 16 .

Since the different memory bank groups 1203A, 1203B, 1203C, and 1203D in the memory wafer 1200 can electrically connect their respective data lines to the global input and output circuit GIO of the FPGA wafer 1101 by using a dedicated data bus DB for communication. and access information, so the FPGA chip can individually control the access of the memory bank groups 1203A, 1203B, 1203C, and 1203D according to actual operation requirements, thereby increasing the data transmission bandwidth.

To sum up, the integrated circuit capable of executing the mining algorithm described in the various embodiments of the present invention can flexibly change the mining hardware code according to actual operation needs. For example, the user can change or switch the algorithm module 905 on the FPGA chip 901 to mining algorithms suitable for different currencies (such as Bitcoin, Ethereum, Litecoin, etc.) at any time according to requirements Hardware does not need to replace the entire set of ASIC chips, so it can reduce the risk of chip development loss and ensure its mining benefits. The input and output circuits described in the embodiments of the present invention can be formed in the FPGA chip, or an input and output circuit can be connected externally by using a data bus according to the user's needs, so as to increase the data transmission bandwidth and save the area of the FPGA chip.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

100: integrated circuit

101: row address signal

102: Memory controller

103: Memory cell array management circuit

104: access command signal

105: memory cell array

107:Manage Signals

108: column address signal

109: Memory bank selection signal

110: Field programmable logic array chip

120: memory chip

Claims (14)

An integrated circuit, comprising: a first memory chip, wherein the first memory chip includes at least one memory cell array; and a first field programmable logic array chip electrically connected to the first memory body chip, wherein the first field programmable logic array chip includes a memory controller and a memory cell array management circuit, and the memory cell array management circuit is electrically connected to the memory controller and the second Between a memory chip, the memory controller outputs an access command signal for accessing the first memory chip to the memory cell array management circuit, and the memory cell array management circuit according to the The access command signal sends at least one management signal to the first memory chip. The integrated circuit as claimed in claim 1, wherein the first Field Programmable Logic Array chip is programmed to execute at least one mining algorithm. The integrated circuit according to claim 2, wherein the first Field Programmable Logic Array chip further includes: at least one algorithm module for executing the at least one mining algorithm. The integrated circuit of claim 1, wherein the at least one memory cell array includes a plurality of memory banks, and the at least one management signal includes a memory bank selection signal. The integrated circuit according to claim 1, wherein the at least one management signal includes at least one column address signal and at least one row address signal, and the memory cell array management circuit includes: a logic control circuit electrically connected to The memory controller receives a control signal in the access command signal to decode the control signal to generate a decoding result; an address register is electrically connected to the memory controller device to receive an access address signal in the access command signal; and a memory cell array selection circuit electrically connected to the address register to receive the corresponding access address signal An access address information, wherein the memory cell array selection circuit outputs the at least one column address signal according to the decoding result of the logic control circuit. The integrated circuit according to claim 1, wherein the at least one management signal includes at least one column address signal and at least one row address signal, and the first memory chip further includes: a decoding circuit electrically connected to The at least one word line and the at least one bit line of the at least one memory cell array are used to decode the at least one column address signal and the at least one row address signal output by the memory cell array management circuit to drive the memory cell array. The at least one word line and the at least one bit line. The integrated circuit according to claim 6, wherein the decoding circuit includes: at least one column address decoding circuit electrically connected to the memory cell array management circuit The circuit is used to receive the at least one column address signal for decoding the at least one column address signal to drive the at least one word line; the at least one row address decoding circuit is electrically connected to the memory cell array management circuit for receiving the at least one row of address signals for decoding the at least one row of address signals to generate at least one row of decoding results; and a driving circuit electrically connected to the at least one row of address decoding circuits for receiving the row decoding results , used to drive the at least one bit line according to the row decoding result. The integrated circuit according to claim 7, wherein the decoding circuit further includes: an input and output circuit electrically connected to the memory controller through a data bus, and electrically connected to the driving circuit, Wherein the input and output circuit is used to transmit a write data signal of the data bus to the driving circuit or transmit a read data signal of the driving circuit to the data bus. The integrated circuit according to claim 1, wherein the first memory chip is formed on a first wafer, the first field programmable logic array chip is formed on a second wafer, and the The first wafer is bonded to the second wafer by a wafer bonding technique. The integrated circuit as claimed in claim 9, wherein the first wafer is stacked on a packaging substrate, and the second wafer is stacked on the first wafer. The integrated circuit according to claim 10, further comprising: a second memory chip formed on a third wafer, wherein the third wafer stacked on the second wafer. The integrated circuit as claimed in claim 9, wherein the second wafer is stacked on a packaging substrate, and the first wafer is stacked on the second wafer. The integrated circuit according to claim 12, further comprising: a second memory chip formed on a third wafer, wherein the third wafer is stacked on the first wafer. The integrated circuit as described in claim 12, further comprising: a second memory chip formed on a third wafer; and a second field programmable logic array chip formed on a fourth wafer, wherein The fourth wafer is stacked on the first wafer, and the third wafer is stacked on the fourth wafer.

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