TWI796802B - Display system - Google Patents

Abstract

A display system includes a display panel that includes a plurality of micro-light-emitting diodes (microLEDs), the display panel being divided into a plurality of display blocks; and a plurality of drivers correspondingly driving the plurality of display blocks. Data signals of each driver are provided to a corresponding display block at different times within a horizontal scan period.

Description

display system

The invention relates to a display system, in particular to a micro light emitting diode display system.

A micro LED (microLED, mLED or μLED) display panel is a type of flat panel display panel, which is composed of individual microscopic light emitting diodes with a size range of 1-100 microns. Compared with traditional liquid crystal display panels, micro-light-emitting diode display panels have greater contrast and faster response time, and consume less power. Although micro-light-emitting diodes and organic light-emitting diodes (OLEDs) also have the characteristics of low power consumption, micro-light-emitting diodes use three- to five-group diode technology (such as gallium nitride), so compared Organic light-emitting diodes have higher brightness, higher luminous efficacy and longer lifespan.

A conventional micro-LED display system may use a pulse-width modulation (PWM) mechanism to generate a pulse-width-modulated signal whose duty cycle is proportional to the brightness (or intensity) of the data provided to the micro-LED display panel.

Conventional micro-LED display systems, whether they use PWM or not, suffer from peak current at the beginning of each horizontal scan period, and therefore suffer from peak power problems. In addition, conventional micro-LED display systems are prone to flicker effects, whereby visible brightness changes occur between display cycles of the display panel.

Therefore, it is urgent to propose a novel mechanism to improve the peak power problem and the flicker effect.

In view of the above, one of the objectives of the embodiments of the present invention is to provide a display system that can effectively avoid the peak current generated during each horizontal scanning period and reduce flicker, thereby greatly improving the peak power problem and the flicker effect.

According to one embodiment, a display system includes a display panel and a plurality of drivers. The display panel includes a plurality of micro light emitting diodes, and the display panel is divided into a plurality of display blocks. Multiple drivers respectively drive multiple display blocks. The data signal of each driver is provided to the corresponding display block at different times during the horizontal scanning period.

According to another embodiment, each driver includes a pulse width modulation device for generating a raw pulse width modulated signal, the duty cycle of which is proportional to the brightness of the data. The duty cycle of the original PWM signal is divided into a plurality of sub-duty cycles separated from each other, thereby generating separate PWM signals, which are provided to corresponding display blocks during the horizontal scanning period.

According to yet another embodiment, each driver uses a multi-scan mechanism to reduce flicker effects.

The first figure shows a schematic diagram of the display panel 11 of the embodiment of the present invention, which can be divided into a plurality of display blocks 111 arranged in columns and rows (or channels), and each display block 111 includes a plurality of micro light emitting diodes (microLED). Each display block 111 is driven by a corresponding driver 1111 . In one example, the display panel 11 (for example, a 17-inch display panel) includes 10×8 display blocks 111 , and the resolution of each display block 111 is 48×40 RGB. Therefore, the overall resolution of the display panel 11 is 480x320 RGB (=(48x10)x(40x8) RGB).

The second figure shows a block diagram of a display system 100 according to an embodiment of the present invention. For each display block 111 , the driver 1111 of this embodiment may include a first circuit 1111A for turning on at least one column of micro light emitting diodes in the display block 111 at each time through the scan line 1112 . The driver 1111 may include a second circuit 1111B to provide data to the micro light emitting diodes of the turned-on row of the display block 111 through the data line 1113 (or channel). Wherein, the driver 1111 may include a pulse width modulation (PWM) device 1114 for generating a pulse width modulation signal, and its duty cycle (duty cycle) is proportional to the brightness (or intensity) of the data (provided to the display block 111) . In this embodiment, the first circuit 1111A, the second circuit 1111B and the pulse width modulation device 1114 are fabricated in a single integrated circuit. The display system 100 may include a timing controller 12 for coordinating all drivers 1111 .

The third figure shows a control sequence diagram of the display system 100 according to the first embodiment of the present invention. The horizontal scan signal HDE defines a horizontal scan period (ie, a period of a scan cycle) for scanning a column of the display block 111 . The data signals D1 to D48 respectively represent data, which are provided to the display block 111 (the enabled row) through the data line 1113 (48 channels in this example) during the horizontal scanning period. It is worth noting that the duty cycle of the data signal is proportional to the brightness of the corresponding data. For ease of understanding, the duty cycles of the data signals D1 - D48 shown in the third figure are the same.

According to one of the characteristics of this embodiment, the data signals D1 ˜ D48 of different channels are provided to the display block 111 at different times (during the horizontal scanning period) (by the second circuit 1111B). Wherein, the data signal of the subsequent channel of (any) two adjacent channels lags behind the data signal of the previous channel of the two adjacent channels, and there is a time offset between the two. In one embodiment, all channels have the same time offset. In another alternative embodiment, the time offsets of at least some of the channels are different. For example, the time offsets of all channels are set randomly.

The fourth figure shows a control sequence diagram of the display system 100 according to the second embodiment of the present invention. As illustrated in FIG. 4 , the data signals D1 ˜ D8 have increasing duty cycles (ie, brightness).

According to one of the characteristics of this embodiment, the data signal of the channel is provided to the display block 111 at the reverse time (during the horizontal scanning period) (by the second circuit 1111B). Wherein, the data signal of one of the (any) two adjacent channels is provided at the beginning of the horizontal scanning period, and the data signal of the other of the two adjacent channels is provided at the end of the horizontal scanning period.

FIG. 5A shows a control sequence diagram of the display system 100 according to the third embodiment of the present invention. According to one of the features of this embodiment, the duty cycle of the original PWM signal can be divided into a plurality of sub-duty cycles separated from each other, thus generating separated (divided) PWM signals (in the horizontal Provided to the display block 111 during scanning). As illustrated in FIG. 5A , the duty cycle of the original PWM signal is divided into four sub-duty cycles to generate split PWM signals. In one embodiment, the duty cycle of the original PWM signal is evenly divided. In another alternative embodiment, the time lengths of at least some of the sub-duty cycles are different.

The fifth figure A shows the internal pulse width modulation signals PWM1 ˜ PWM4 of the driver 1111 , and the fifth figure B shows the OR gate 1115 of the second circuit 1111B of the third embodiment of the present invention. In this embodiment, the logical OR gate 1115 performs a logical OR operation on the internal PWM signals PWM1 - PWM4 to generate separate PWM signals.

According to the embodiments described in FIG. 3 to FIG. 5B , since peak current is avoided during each horizontal scan (or synchronization), the problem of power peak can be greatly reduced. Furthermore, due to the reduced power consumption, the driver 1111 can drive the display block 111 with more columns and/or more rows. The mechanism described in the above-mentioned third figure to fifth figure B can be applied to different frames on the temporal axis (temporally). In other words, at different times, two adjacent frames can respectively use the above-mentioned different mechanisms.

According to the fourth embodiment of the present invention, a multiple scan (multi-scan) mechanism may be used to reduce the flicker effect. For example, driver 1111 may use interlaced scanning, which includes two video fields captured consecutively. In another example, triple-laced scanning may be used, which includes three video fields captured consecutively. In yet another example, random scanning may be used to randomly scan scan lines within a video field.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention; all other equivalent changes or modifications that do not deviate from the spirit disclosed by the invention should be included in the following within the scope of the patent application.

100: display system 11: Display panel 111:Display blocks 1111: drive 1111A: First Circuit 1111B: second circuit 1112: scan line 1113: data line 1114: Pulse width modulation device 1115: logic OR gate 12: Timing controller HDE: horizontal scanning signal D1~D8, D16, D32, D47~D48: data signal PWM1~PWM4: internal pulse width modulation signal

The first figure shows a schematic diagram of a display panel according to an embodiment of the present invention, which includes a plurality of display blocks. The second figure shows a block diagram of a display system according to an embodiment of the present invention. The third figure shows a control sequence diagram of the display system according to the first embodiment of the present invention. Figure 4 shows a control timing diagram of the display system according to the second embodiment of the present invention. The fifth figure A shows a control timing diagram of the display system according to the third embodiment of the present invention. The fifth figure B shows the logical OR gate of the second circuit of the third embodiment of the present invention.

HDE: horizontal scanning signal

D1~D2, D16, D32, D47~D48: data signal

Claims (10)

A display system, comprising: a display panel, including a plurality of micro light-emitting diodes, the display panel is divided into a plurality of display blocks; and a plurality of drivers, respectively driving the plurality of display blocks; wherein the data of each driver The signals are provided to the corresponding display blocks at different times during the horizontal scanning period; wherein the data signal of each driver is provided to the corresponding display blocks at the reverse time during the horizontal scanning period. The display system as claimed in claim 1, wherein each driver includes: a first circuit that turns on a row of micro light-emitting diodes at each time; and a second circuit that provides data to the turned-on row of the display block micro light emitting diode. The display system according to claim 2, wherein the driver includes: a pulse width modulation device for generating a pulse width modulation signal, the duty cycle of which is proportional to the brightness of the data. The display system of claim 1 further includes: a timing controller for coordinating the plurality of drivers. The display system according to claim 1, wherein the data signal of one of the two adjacent channels is provided at the beginning of the horizontal scanning period, and the data signal of the other channel of the two adjacent channels is provided at the end of the horizontal scanning period. A display system comprising: A display panel, including a plurality of micro light-emitting diodes, the display panel is divided into a plurality of display blocks; and a plurality of drivers, respectively driving the plurality of display blocks, each driver includes a pulse width modulation device, used To generate an original PWM signal, the duty cycle of which is proportional to the brightness of the data; wherein the duty cycle of the original PWM signal is divided into a plurality of sub-duty cycles separated from each other, thereby generating a separate PWM signal , which are provided to the corresponding display block during the horizontal scanning period; wherein each driver includes a logical OR gate, which performs logical OR operation on a plurality of internal PWM signals to generate the separated PWM signal. Such as the display system of claim 6, wherein each driver includes: a first circuit that turns on a row of micro light-emitting diodes at each time; and a second circuit that provides data to the turned-on row of the display block micro light emitting diode. The display system of claim 6 further includes: a timing controller for coordinating the plurality of drivers. The display system according to claim 6, wherein the duty cycle of the original PWM signal is equally divided. In the display system according to claim 6, at least some of the sub-duty cycles have different time lengths.

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