TWI795901B - Serial link system with an embedded test function - Google Patents

Abstract

The present invention provides a serial link system with an embedded test function. The transmitting end consists of a transmitter and a test symbol generator. The test symbol generator generates a test symbol stream which is constituted by at least a test bit-stream and a golden test bit-stream, and the test bit-stream and the golden test bit-stream are the same except they have a relative delay. The transmitter modulates the test symbol stream and then outputs a serial test signal to the receiving end. The receiving end includes a receiver and an error detector. The receiver recovers a recovered test symbol stream from the serial test signal. The recovered test symbol stream includes a recovered test bit-stream corresponding to the test bit-stream in the test symbol stream, and a recovered golden test bit-stream corresponding to the golden test bit-stream. The error detector first compensates for the relative delay of the recovered test bit-stream and the recovered golden test bit-stream, and then checks if the two resulted delay-compensated bit-streams are the same to obtain a test result. Since the test bit-stream and the golden test bit-stream are combined into a test symbol stream and sent together, there will be no unpredictable timing skew between the recovered test bit-stream and the recovered golden test bit-stream restored after demodulation at the receiving end. The invention uses the recovered golden test bit-stream to replace the golden test bit-stream to greatly simplify the circuit for aligning the recovered test bit-stream with the golden test bit-stream.

Description

Serial transmission system with built-in test function

The present invention relates to a test method, in particular to a serial transmission system with built-in test function.

The serial transmission system (serial links) solves the problem of timing skew (timing skew) between the data and the clock during the high-speed transmission of traditional parallel buses, so it has become the mainstream technology of both wired and wireless data transmission systems . In order to increase the data transmission rate, more advanced serial transmission systems adopt modulation methods such as pulse amplitude modulation (PAM) or quadrature amplitude modulation (QAM) such as multiple bits per symbol. However, testing such advanced serial transmission systems also becomes more complex and expensive. Especially in automotive electronics, aircraft electronic systems and other electronic systems that require high reliability, only built-in testing technology can continuously perform field tests to solve the serious problem of errors caused by component aging after long-term use of the system.

Most of the conventional built-in-test-in-serial-transmission-system (BIST) technologies generate a test symbol stream (test symbol stream) consisting of one or more test bit-stream(s) at the transmitting end. ), after modulation, a series of test signals are generated and sent to the receiving end. At the receiving end, the same control bit-streams (golden test bit-streams) as the test bit-streams sent by the transmitting end are regenerated. After receiving the test bit-stream, the receiver will demodulate and restore a recovered test symbol stream, which includes the recovered test bit-stream corresponding to the test bit-stream (s)), and finally compare the restored test symbol stream with the control symbol stream generated by the receiving end to check whether the two are the same, so as to determine whether the serial transmission system under test passes the test. For example, as shown in FIG. 1 , the prior art serial transmission system includes a transmitting end 22 and a receiving end 24 . The transmitting end 22 includes a test symbol generator 222 and a transmitting circuit 224 . After the test symbol generator 222 generates a test symbol stream, the transmitting circuit 224 modulates it to generate a serial test signal and transmits it to the receiving end 24 . The receiving end 24 includes a receiving circuit 242 and an error detector 244 , wherein the receiving circuit 242 demodulates the received serial test signal to generate a restored symbol stream and then input it into the error detector. However, the test symbol generator 222 only generates a test symbol stream without a control symbol stream. The method for the receiving end 24 to regenerate the comparison symbol flow can be: 1. Another test symbol generator 244 is set at the receiving end 24 to generate the same test symbol flow as the test symbol generator 222 as the comparison symbol flow; or 2. The test symbol generator 222 of the transmitting end 22 directly transmits the same test symbol stream to the error detector 246 as a comparison symbol stream, as shown by the dotted line in the figure. However, the restored test symbol stream demodulated by the receiving end 24 and the generated comparison symbol stream are not synchronized in nature, so complex circuits are required to align the demodulated restored test symbol stream and the generated comparison symbol stream . In a very high-speed (e.g. >10 Gb/s) serial transmission system, the symbol period (symbol period) becomes very short, making this type of circuit design very difficult, and the complex circuit also increases the hardware cost.

Therefore, the present invention proposes a serial transmission system with a built-in test function to effectively solve the above-mentioned problems. The specific structure and its implementation will be described in detail below:

The main purpose of the present invention is to provide a serial transmission system with a built-in test function, which delays one of the same test bit stream and the control bit stream for a relative delay period, and then synthesizes it into a test symbol stream transmitted together, there will be no unpredictable time offset between the restored test bit stream and the restored comparison bit stream in the restored test symbol stream after demodulation at the receiving end, only need to compensate for the restored comparison bit stream and the restored comparison bit stream By restoring the relative delay period between the test bit streams and comparing them with each other, it is possible to know whether there is a bit error. This greatly simplifies the circuitry for aligning the restored test bitstream with the control bitstream.

Another object of the present invention is to provide a serial transmission system with a built-in test function. The error detector at the receiving end only needs a few flip-flops and exclusive OR gate digital circuits, and the required area is extremely small, so it has low cost. , low power consumption and robustness.

Another object of the present invention is to provide a serial transmission system with a built-in test function, in which the error detector adopts a fully digital circuit design, and there is no need to copy the original analog modulation circuit, in addition to reducing the impact caused by mismatched components , can also reduce wafer cost.

For reaching above-mentioned object, the present invention provides a kind of serial transmission system with built-in test function, comprise: a transmission end, comprise: a test symbol generator, produce a test symbol stream, test symbol stream is made up of a test bit stream and Consisting of at least one control bit stream; and a transmission circuit, which modulates the test symbol stream into a serial test signal and then outputs it; and a receiving end, which is connected to the transmitting end signal through a transmission channel, and receives the serial test signal, The receiving end includes: a receiving circuit, which restores the test symbol stream in the serial test signal into a restored test bit stream corresponding to the test bit stream and a restored control bit stream corresponding to the control bit stream; and a The error detector compares whether an error code is generated in the restoration test bit stream and the restoration comparison bit stream, and obtains a test result.

According to an embodiment of the present invention, the test bit stream and the control bit stream have the same data sequence and a fixed relative delay period. When the receiving circuit restores the test bit stream and the control bit stream, the relative delay period is simultaneously restored.

According to an embodiment of the present invention, the test symbol generator includes: a pseudo-random binary sequence (PRBS) generator for generating a test bit stream and a control bit stream with a relative delay period.

According to an embodiment of the present invention, the pseudo-random bit stream generator includes a plurality of first flip-flops, and the outputs of two of the first flip-flops are selected as the control bit stream and the test bit stream respectively, so that the control bit stream The metastream is delayed by a fixed relative delay period from the test bitstream.

According to the embodiment of the present invention, in the test symbol stream composed of the output of the selected first flip-flop, all symbols (symbols) will appear, and the probability of each symbol appearing is almost the same, and the conversion between each symbol The number of times is almost the same.

According to an embodiment of the present invention, the error detector includes a delay line for delaying the restoration test bit stream by a relative delay period to generate a delayed restoration test bit stream, delaying the restoration test bit stream and the restoration comparison bit stream Bits of the same data are aligned one by one under error-free conditions.

According to the embodiment of the present invention, the error detector includes a mutual exclusive OR gate, receives and compares the restoration control bit stream and the restoration test bit stream after a delay of a relative delay period, and obtains the test result.

According to an embodiment of the present invention, the transmitting end and the receiving end are located in different test chips.

According to the embodiment of the present invention, when the symbol of the test symbol stream produced by the test symbol generator is a unit cell, the number of comparison bit streams is one group, and the test symbol stream is combined by the test bit stream and the comparison bit stream in an interleaved manner. produced in a manner.

According to an embodiment of the present invention, the test symbol generator includes a multiplexer for interleaving and combining the test bit stream and the control bit stream to generate a unit-bit test symbol stream.

According to an embodiment of the present invention, the symbols of the test symbol stream generated by the test symbol generator are multi-bit symbols, and when the number of bits of each multi-bit symbol is greater than or equal to three bits, the number of bit streams is compared There are at least two groups, and the test symbol stream is composed of the test bit stream and the at least two sets of control bit streams.

The invention provides a serial transmission system with a built-in test function, which allows the serial transmission system to complete the built-in test only by adding a very simplified circuit on the chip. The present invention does not require complex built-in data and bit stream synchronization circuits, nor does it need to use expensive high-end test machines, so the test time and cost of the chip can be greatly reduced. Since the built-in test circuit (Built-in Self Test, BIST) is built inside the chip, the test can be completed at full speed and under the influence of the actual channel, improving the test coverage and the reliability of the test results.

Please refer to FIG. 2A, which is a block diagram of the serial transmission system 10 with built-in test function of the present invention. The serial transmission system 10 with built-in testing function includes a transmitting end 12 and a receiving end 14. The transmitting end 12 and the receiving end 14 can be set on the same chip or on different chips. The receiving end 14 is connected to the transmitting end 12 through a transmission channel 16 . The transfer channel 16 can be located inside or outside the chip. The transmitting end 12 includes a test symbol generator 122 and a transmitting circuit 124 . Wherein, the test symbol generator 122 is used to generate a test symbol stream, the test symbol stream is composed of a test bit stream and at least one comparison bit stream, and the data content of the test bit stream and the comparison bit stream are exactly the same, but There is a relative delay of a fixed clock cycle between the two. The transmission circuit 124 is used for modulating the test symbol stream formed by combining the test bit stream and the comparison bit stream into a serial test signal, and then output the serial test signal to the receiving end 14 . The receiving end 14 includes a receiving circuit 142 and an error detector 144 , and the receiving circuit 142 is connected to the error detector 144 . In this embodiment, the receiving circuit 142 is used to restore the test symbol stream in the serial test signal into a restored test symbol stream, including a restored test bit stream corresponding to the test bit stream and a test bit stream corresponding to the control bit stream. A restore control bitstream. At the same time, the receiving circuit 142 also restores the recovery clock rclk. Then, after first compensating the relative delay of the test bit stream and the comparison bit stream by the error detector 144, then comparing whether an error code occurs between the restoration test bit stream and the restoration comparison bit stream, a test result (BIST) is obtained. result). If any error code is generated in the restoration test bit stream or the restoration comparison bit stream, the test result output by the error detector 144 will generate a pulse immediately to provide subsequent error processing defined by the designer.

Please refer to FIG. 2B, which is a block diagram of an embodiment of the serial transmission system 10 with built-in test function of the present invention. This embodiment uses QPSK modulation/demodulation. The serial transmission system 10 with built-in testing function includes a transmitting end 12 and a receiving end 14. The transmitting end 12 and the receiving end 14 can be set on the same chip or on different chips. The receiving end 14 is connected to the transmitting end 12 through a transmission channel 16 . The transfer channel 16 can be located inside or outside the chip. The transmitting end 12 includes a test symbol generator 122 and a transmission circuit 124, wherein the test symbol generator 122 is used to generate a test symbol stream, and the data bit streams data _I and data _Q in the test symbol stream are respectively used as test bits The data contents of the test bit stream data _I and the control bit stream data _Q are exactly the same, but there is a relative delay of two clock cycles between the two. The transmitting circuit 124 is used for converting the test symbol stream formed by combining the test bit stream and the comparison bit stream into a serial test signal by QPSK modulation, and then output the serial test signal to the receiving end 14 . The receiving end 14 includes a receiving circuit 142 and an error detector 144 , and the receiving circuit 142 is connected to the error detector 144 . In this embodiment, the receiving circuit 142 is used to restore the test symbol stream in the serial test signal into the restored test bit stream rdata _I and the restored control bit corresponding to the test bit stream data _I and the comparison bit stream data _Q respectively. Yuan stream rdata _Q and restore the recovery clock rclk at the same time. Next, the error detector 144 first compensates the relative delay of two clock cycles between the restoration test bit stream rdata _I and the restoration comparison bit stream rdata _Q , and then compares the restoration test bit stream rdata after the compensation for the relative delay Whether _I and the reduction control bit stream rdata _Q are the same, a test result (BIST result) is obtained. If any error code is generated in the restoration test bit stream rdata _I or the restoration comparison bit stream rdata _Q , the test result output by the error detector 144 will immediately generate a pulse to provide subsequent error handling functions defined by the designer. deal with.

In one embodiment, the transmitting circuit 124 includes a modulator (not shown in the figure), and the receiving circuit 142 includes a demodulator (not shown in the figure). The demodulator may be a Clock and Data Recovery (CDR) circuit.

The biggest difference between the present invention and the prior art is that in the prior art, the transmitting end 20 only transmits the test symbol stream, while the control symbol stream is generated by setting another test symbol generator at the receiving end 20 . Therefore, when the restored test symbol stream is compared with the reference symbol stream, the restored test symbol stream is transmitted through the transmission channel, and a signal delay occurs. However, the control symbol stream does not pass through the transmission channel, and the same delay will not be generated, which will make it difficult to align the restored test symbol stream and the control symbol stream. In the present invention, the test bit stream and the control bit stream are combined into a test symbol stream and transmitted simultaneously, so even if signal delay occurs, the two still maintain the same relative delay, so it is not an unpredictable time offset, and it is quite easy to restore Test bitstream and restore control bitstream alignment.

The present invention also provides an embodiment. In this embodiment, there is a fixed relative delay period between the test bit stream and the control bit stream. As shown in the embodiment of Fig. 3, the test bit stream data _I is ahead of the control bit stream data _Q by two cycles, therefore, the third bit T[2] of the test bit stream data _I and the control bit The first bit G[0] of the stream data _Q is combined into a 2-bit symbol as a test symbol. . The key point of the design of this embodiment is that since the transmitting end 12 simultaneously transmits the test symbol streams including the test bit stream and the comparison bit stream, and one of the bit streams has a relative delay, therefore, if there is a clutter in the data transmission process If the signal affects the test symbols of a certain clock cycle, then when the receiving end 14 restores the serial test signal back to the restored test bit stream and the restored control bit stream, and after the error detector 144 compensates for the relative delay period, both The erroneous bits do not occur in the same clock cycle. For example, if an error occurs in T[3], the parallel G[1] will also make an error, but G[3] located in a different cycle is correct. Therefore, when the restoration test bit stream rT[i] is aligned with the restoration control bit stream rG[i], it can be seen that one of rT[3] and rG[3] generates an error. In this way, the error detector 144 can compare the generation of error codes to achieve the effect of built-in testing.

One of the methods for the test symbol generator to generate the test bit stream data _I and the comparison bit stream data _Q with a relative delay period, for example, is to set a pseudo-random bit stream (pseudo- random binary sequence, PRBS) generator 123, as shown in Figure 4. FIG. 4 shows an embodiment of the pseudo-random bitstream generator 123 . The pseudo-random bit stream generator 123 includes a plurality of first flip-flops 1232. In this embodiment, a PRBS7 generator is used as an example. The number of first flip-flops 1232 is 7, and the data is output cyclically. Select the output of two of the first flip-flops as the test bit stream data _I and the comparison bit stream data _Q respectively. The data content of the test bit stream data _I and the comparison bit stream data _Q are exactly the same but have fixed relative delay period. In this embodiment, the output data _I of the first first flip-flop and the output data _Q of the third first flip-flop are respectively taken as the comparison bit stream and the test bit stream, so that the comparison bit stream Delayed from the test bit stream, the relative delay period is two periods. The modulator in the transmitting circuit 124 is a QPSK modulator, and the modulated signal is the serial test signal. Since the pseudo-random bit stream generator 123 is essentially a linear shift register (LSFR) and the two selected signals are separated by two first flip-flops 1232, it can be determined that data _I always leads data _Q by two hours The pulse cycle and the data sequence of the two are exactly the same.

If there is already a test bit stream, the test symbol generator 122 in Fig. 3 can also use the test bit stream to generate the required fixed The comparison bitstream relative to the delay period without using the pseudo-random bitstream generator 123.

Correspondingly, the error detector 144 needs to align the restoration test bit stream rdata _I with the restoration comparison bit stream rdata _Q delayed by a relative delay period, so a delay line (not shown in the figure) must be used to align the test bit streams flow for compensatory shifting. As shown in FIG. 5, the error detector 144 includes a delay line 1442 and a mutually exclusive OR gate 1444, and the delay line 1442 is formed by two second flip-flops. The clock period difference between the two second flip-flops is the relative delay period, and is used to delay the restored test bit stream rdata _I by the relative delay period. Since the output of the first flip-flop and the third flip-flop of PRBS7 were selected as the test bit stream and the control bit stream respectively when the test symbol stream was generated, after the receiving circuit restores the test symbol stream, only The restoration test bit stream rdata _I needs to be delayed by two clock cycles, and then the restoration test bit stream rdata _I and the restoration control bit stream rdata _Q can be aligned to generate a delayed restoration test bit stream. Therefore, the output and input of the delay line 1442 are also designed to have a difference of two clock cycles. In this way, when the restoration test bit stream rdata _I passes through the delay line 1442, the same data bits of the restoration comparison bit stream rdata _Q and the restoration test bit stream can be aligned under the condition of no transmission error. Then, the aligned restored test bit stream and restored comparison bit stream rdata _Q are sent to the exclusive OR gate 1444 to compare whether they are the same to obtain the test result. The exclusive OR gate (XOR) 1444 of the error detector 144 can also be replaced by a non-exclusive OR gate (XNOR). In addition, additional accumulators or other circuits can be added to process the test results according to the needs of designers.

In the present invention, the basic condition of the test bit stream and the comparison bit stream is that the two have the same data sequence and a fixed relative delay period, so the receiving circuit 142 restores the test bit stream and the comparison bit stream in the serial test signal. When meta-streaming, the relative delay period of the two can be restored at the same time. In fact, selecting any two outputs of the first to sixth first flip-flops 1232 of the PRBS7 generator can satisfy this basic condition.

In addition, in order to ensure test coverage and test quality, in addition to the above two basic conditions, the test bit stream and control bit stream selected to form the test symbol stream must also meet two conditions as much as possible, including Condition 1: In the test symbol stream, all symbols (symbols) will appear and the probability of occurrence of each symbol is almost the same, and Condition 2: the number of transitions between symbols is also almost the same. As shown in the constellation diagram in Fig. 6, among the total 2 ⁷ -1=127 symbols in each cycle of the embodiment, the four symbols 00, 01, 11, and 10 appear almost the same number of times, of which 00 appears 31 times, and 01 , 11, and 10 all appear 32 times, meeting the above-mentioned condition one. The number of conversions between 00, 01, 11, and 10 is also the same, 16 times. In addition, the number of times of maintaining the same symbol is 8 times except for 00 which is 7 times, which also meets the second condition above. Therefore, when the test signal is modulated by QPSK, the best test effect can be achieved by delaying the control bit stream by two clock cycles. If the modulator in the transmitter is not QPSK, then there is no delay in comparing the bit stream.

The present invention can be applied to the built-in test of any serial transmission system, such as PAM4 and QAM. Taking PAM4 as an example, its test symbol stream is composed of two bit streams, so the above embodiments can be directly applied. Taking the 16-QAM used by Blue Tooth 2 as an example, its test symbol stream can be composed of four sets of test bit streams with fixed relative delay periods between them, for example, simply select four positive The output of the inverter generates a test signal. At the receiving end, it is only necessary to compare the decoded four restored bits through an appropriate number of flip-flops to compensate for the fixed relative delay periods between each other, and check whether there is an error code. Or take the outputs of the two flip-flops as the control bit stream and the test bit stream as in the embodiment in FIG. 4, and then convert it into a four-bit test symbol stream with a coding circuit customized by the designer. Then, the receiving end only needs to restore the restored test symbol stream to the corresponding decoding circuit to restore the restored control bit stream and the restored test bit stream, and use an appropriate number of flip-flops to compensate for the relative delay period. Compare and check whether there is any bit error.

The present invention can also be applied to serial transmission systems for testing units per symbol. It is only necessary to intersperse the control bit stream and the test bit stream to generate a single bit test symbol stream, and input it into the serial transmission system under test with built-in test function.

As shown in Fig. 7a to Fig. c, it is a schematic diagram of an embodiment of the test symbol generator generating a unit test symbol stream. The ith bit of each test bitstream T[i] and control bitstream G[i] are the same. In Fig. 7a, the test bit stream T[i] and the reference bit stream G[i-2] delayed by two cycles are interleaved and merged into a unit test symbol stream. In Figure 7b, two consecutive bits of the test bit stream T[i] and two consecutive bits of the control bit stream G[i-2] delayed by two periods are interleaved and combined into a unit test symbol flow. In Figure 7c, the test bit stream T[i] has m consecutive bits and the control bit stream G[i-2] with two cycles of delay. The m consecutive bits are interleaved and merged into a unit test symbol stream . This embodiment is applicable to two-phase shift modulation (BPSK), non-return-to-zero coding (NRZ), two-frequency shift modulation (BFSK), etc.

Figure 8a is a block diagram for generating the unit test symbol stream in Figure 7a, wherein the clock frequency of the test symbol generator 122 is only half of the frequency of the symbol clock CLK _ref , and still outputs the test bit stream T[i] and the comparison bit stream G[i−2] delayed by two clock cycles, and the test symbol generator 122 includes a multiplexer 125 . The multiplexer 125 takes a bit from the test bit stream T[i] and the control bit stream G[i] every 1/2 symbol clock period, and can generate the unit cell as shown in Fig. 7a The test symbol stream is sent to the transmission circuit to generate a serial test signal. Figure 8b is the timing diagram of Figure 8a.

FIG. 9 is a schematic diagram of an embodiment in which the test symbol generator generates a test symbol stream greater than or equal to three bits. The data of the test bit stream data ₁ is T[i], the data of the two control bit streams data ₂ and data ₃ are G[i] and A[i] respectively, and T[i] and G[i] , same as A[i] three-bit stream. In this embodiment, the first comparison bit stream data ₂ is delayed by two clock cycles, and the second comparison bit stream data ₃ is delayed by three clock cycles. Therefore, the first symbol of the test symbol stream can be combined in the fourth clock cycle, which is a three-bit signal composed of T[3], G[1], A[0], which can be 000, 001 , 010, 011, 100, 101, 110, 111 etc. one of the eight symbols.

The present invention has the following advantages: 1. By synthesizing the test bit stream and the control bit stream generated by the same test bit stream delayed by a fixed period into a test symbol stream and transmitting them together, the receiver demodulates and restores the restored test symbol stream There will be no unpredictable time offset between the restored test bit stream in the restored test symbol stream and the restored control bit stream, only the restored test bit stream in the restored restored test symbol stream is delayed by the fixed period, and then By comparing with the restored control bit stream, it is possible to know whether there is an error code. This greatly simplifies the circuitry required to align and restore the test bitstream and the control bitstream. 2. Very few circuits are required, reducing chip cost. The common BIST method needs to install a control bit stream generator and circuits required for aligning and restoring the test bit stream and the control bit stream in the receiving end of the serial transmission system to be tested, which greatly increases the chip area and increases the cost of the chip , the present invention does not need to set a test symbol generator at the receiving end. 3. The test symbol generation circuit at the transmitting end does not need to be located in the same chip as the receiving end, so it allows on-site built-in testing at the system level. 4. Able to test channel loss and errors caused by the front-end circuit at the receiving end. If the test symbol generator is independent from the chip to be tested, or loopback is used, the test symbol stream can pass through the actual transmission environment, making the test condition setting more complete and pragmatic, and the test result more reliable. 5. Full digitization. The error detector can be composed of all digital circuits, without duplicating the original analog demodulation circuit in the receiving end, reducing the influence caused by mismatched components, and improving the robustness of the built-in test circuit itself. 6. The circuit and environment under test are not changed. The built-in test circuit does not affect the performance of the serial transmission system under test, so at-speed tests can be realized to test the actual performance of the serial transmission system under test.

To sum up, the serial transmission system with built-in test function provided by the present invention generates a plurality of comparison bit streams and test bit streams with fixed relative delay periods at the transmission end without increasing any hardware cost. The error detector at the receiving end only needs a few flip-flops and exclusive OR gate digital circuits, and the required area is very small, so it has the characteristics of low cost, low power consumption and robustness. In addition, the present invention allows the receiving end and the transmitting end to not be located on the same chip, not only covering the output driver (output driver) of the transmitting end, the transmission channel, and the response of the analog front-end circuit of the receiving end, but also allowing the system level to test the in-situ (in -situ field tests) built-in tests. Therefore, the present invention is more practical in use than the built-in test functions of other serial transmission systems. In addition to being applicable to the test of larger-scale chip mass production, it is especially suitable for testing systems that require high reliability, such as Automotive electronics, avionics, satellite communication systems, etc.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the scope of the present invention. Therefore, all equivalent changes or modifications based on the features and spirit described in the scope of the application of the present invention shall be included in the scope of the patent application of the present invention.

10: Serial transmission system with built-in test function 12:Transmitter 122: Test symbol generator 123: Pseudo-random bit stream generator 1232: The first flip-flop 124: transmission circuit 125: multiplexer 14: Receiver 142: Receiving circuit 144:Error detector 1442: delay line 16: Transmission channel 22: Transmitter 222: Test symbol generator 224: transmission circuit 24: Receiver 242: Receiving circuit 244: Test symbol generator 246: Error detector

FIG. 1 is a block diagram of a serial transmission system with a built-in test function in the prior art. FIG. 2A is a block diagram of the serial transmission system with built-in test function of the present invention. FIG. 2B is a block diagram of an embodiment of the serial transmission system with built-in test function of the present invention. Fig. 3 is a schematic diagram of the present invention combining the test bit stream and the control bit stream to form a test symbol stream. FIG. 4 is a schematic diagram of an embodiment of the present invention using a pseudo-random bit stream generator to generate a test bit stream and a control bit stream. Fig. 5 is a logic circuit diagram of an embodiment of the error detector of the present invention. Fig. 6 is a state machine diagram of data transitions in the test symbol generator when the system and method of the present invention are used for the embodiment test. Figures 7a to 7c are examples of the test symbol generator generating a bit test symbol stream. Fig. 8a is a block diagram of an embodiment of generating the test symbol flow in Fig. 7a, and Fig. 8b is a timing diagram of Fig. 8a. FIG. 9 is an embodiment of a test symbol generator generating a test symbol stream larger than three bits.

10: Serial transmission system with built-in test function

12:Transmitter

122: Test symbol generator

124: transmission circuit

14: Receiver

142: Receiving circuit

144:Error detector

16: Transmission channel

Claims (11)

A serial transmission system with a built-in test function, comprising: a transmitting end, including: a test symbol generator, which generates a test symbol stream, and the test symbol stream is formed by a test bit stream and at least one comparison bit stream Composition, the test bit stream and the at least one comparison bit stream have the same data sequence; and a transmission circuit, which modulates the test symbol stream into a serial test signal and outputs it; and a receiving end, through a transmission channel and The transmitting end is signal-connected to receive the serial test signal, and the receiving end includes: a receiving circuit for restoring the test symbol stream in the serial test signal into a restored test bit stream corresponding to the test bit stream and at least one restoration control bit stream corresponding to the at least one comparison bit stream; and an error detector for comparing whether an error code is generated between the restoration test bit stream and the restoration comparison bit stream to obtain a test result . The serial transmission system with built-in test function as described in Claim 1, wherein the test bit stream and the at least one control bit stream have a fixed relative delay period, and the receiving circuit restores the restored test bit stream When restoring the at least one comparison bit stream, the relative delay period is simultaneously restored. The serial transmission system with built-in test function as described in claim item 2, wherein the test symbol generator includes: A pseudo-random binary sequence (PRBS) generator is used to generate the test bit stream and the at least one control bit stream with the relative delay period. The serial transmission system with built-in test function as described in claim 3, wherein the pseudo-random bit stream generator includes a plurality of first flip-flops, and the outputs of at least two of the first flip-flops are selected as For the at least one control bitstream and the test bitstream, delaying the at least one control bitstream relative to the test bitstream by the relative delay period. As the serial transmission system with built-in test function described in claim 4, in the test symbol stream formed by the output of the two first flip-flops, all symbols (symbol) will appear, and each The symbols appear almost equally often, and the number of transitions between each symbol is almost the same. The serial transmission system with built-in test function as described in claim item 4, wherein the error detector includes a delay line for delaying the recovery test bit stream by the relative delay period to generate a delayed recovery test bit In the bit stream, the delayed recovery test bit stream is aligned one by one with the same data bits of the at least one recovery control bit stream under error-free conditions. The serial transmission system with built-in test function as described in claim 1 or 6, wherein the error detector further includes an exclusive OR gate (XOR gate), receiving the at least one restoration control bit stream and the delay The test bit stream is restored and compared to obtain the test result. The serial transmission system with built-in test function as described in claim 1, wherein the transmitting end and the receiving end are located in different test chips. The serial transmission system with built-in test function as described in claim item 1, when the symbols of the test symbol stream generated by the test symbol generator are units, the at least one comparison The number of bit streams is one group, and the test symbol stream is generated by interleaving and merging the test bit stream and the set of control bit streams. The serial transmission system with built-in test function as described in claim item 9, wherein the test symbol generator includes a multiplexer for interleaving and combining the test bit stream and the set of comparison bit streams to generate Unity of the test symbol stream. The serial transmission system with built-in test function as described in claim 1, wherein the symbols of the test symbol stream produced by the test symbol generator are multi-bit symbols, and the number of bits of each multi-bit symbol When it is greater than or equal to three bits, the quantity of the at least one comparison bit stream is at least two sets, and the test symbol stream is composed of the test bit stream and the at least two sets of comparison bit streams.

Images