TWI794427B - Semiconductor device and adjusting method thereof - Google Patents

Abstract

The semiconductor device includes: a first vertical Hall element disposed on a first region of a semiconductor substrate, having a plurality of first electrodes arranged at predetermined intervals on a first straight line; a second vertical Hall element disposed on A second region of the semiconductor substrate different from the first region has a plurality of second electrodes arranged at predetermined intervals on a second straight line parallel to the first straight line, the same number as the plurality of first electrodes; the first drive power supply , to drive the first vertical Hall element; and a second drive power supply, set separately from the first drive power supply, to drive the second vertical Hall element.

Description

Semiconductor device and adjusting method thereof

The present invention relates to a semiconductor device and its adjustment method, in particular to a semiconductor device with a vertical Hall element for detecting the horizontal magnetic field and its adjustment method.

Hall elements are used in various applications because they can be used as magnetic sensors for non-contact position detection or angle detection. Among them, a magnetic sensor using a horizontal Hall element that detects a magnetic field component (vertical magnetic field) perpendicular to the surface of a semiconductor substrate is generally known, but various methods using a magnetic field component parallel to the semiconductor substrate have also been proposed. A magnetic sensor with a vertical Hall element that detects the magnetic field component (horizontal magnetic field) of the surface.

In the vertical Hall element, since it is difficult to obtain a structure with high geometric symmetry, it is easier to generate a so-called offset (offset) voltage that is output even when no magnetic field is applied, compared to the horizontal Hall element. Therefore, when used as a magnetic sensor, it is necessary to remove the offset voltage, and a spin current method is known as a method for this.

As a method of removing the offset voltage using the spinning current method, for example, Patent Document 1 discloses that, as shown in FIG. The elements 400 are arranged in parallel, and the electrodes 311 to 315 of the vertical Hall element 300 are connected to the electrodes 411 to 415 of the vertical Hall element 400 as shown in the figure through the wiring W1 to W6 to perform the spinning current method . Thereby, when the rotating current method is performed, the resistance of the current path becomes equal in any of the phases after the direction of the current is switched, so that the accuracy of removing the offset voltage can be improved. [Prior art literature] [Patent Document]

[Patent Document 1] Specification of European Patent No. 1438755

[Problem to be Solved by the Invention]

However, in the method of Patent Document 1, the following problems occur.

When the characteristics of the plurality of vertical Hall elements are completely the same, as described above, the resistance of the current path is equal in any of the phases when the rotating current method is performed, so that the offset voltage can be removed with high precision.

However, although a plurality of vertical Hall elements are simultaneously formed on the same substrate through a semiconductor manufacturing process, it is extremely difficult to make the concentration distribution of impurities etc. identical among the plurality of vertical Hall elements. Therefore, characteristic variation occurs among a plurality of vertical Hall elements. Therefore, in each phase when the rotating current method is performed, the resistances of the current paths are not completely equal, so the accuracy of offset cancel cannot be greatly improved.

Therefore, an object of the present invention is to provide a semiconductor device having a vertical Hall element capable of achieving offset cancellation by the spinning current method with higher accuracy. [Means to solve the problem]

The semiconductor device of the present invention is characterized in that it comprises: a first vertical Hall element disposed in a first region of a semiconductor substrate, having a plurality of first electrodes arranged at predetermined intervals on a first straight line; a second vertical Hall element The Hall element is provided in a second region of the semiconductor substrate that is different from the first region, and has a plurality of Hall elements arranged at a predetermined interval on a second straight line parallel to the first straight line. A plurality of second electrodes with the same number of first electrodes; a first driving power supply, driving the first vertical Hall element; and a second driving power supply, set separately from the first driving power supply, driving the second vertical Hall element Type Hall element. [Effect of the invention]

According to the present invention, since the first vertical Hall element and the second vertical Hall element are independently driven by different drive power sources, by properly adjusting the first drive power source and the second drive power source, the semiconductor manufacturing process can be compensated. The resulting characteristic error of the first vertical Hall element and the second vertical Hall element. Therefore, since the spinning current method can be performed with the characteristics of the first vertical Hall element and the second vertical Hall element being substantially the same, high-precision offset cancellation can be performed.

Hereinafter, modes for implementing the present invention will be described in detail with reference to the drawings.

1 and 2 are schematic diagrams for explaining a semiconductor device having a vertical Hall element according to an embodiment of the present invention. When the direction is set to the first state (phase 1), FIG. 2 shows the case where the direction of the current flowing in the vertical Hall element is set to the second state (phase 2) when the rotating current method is performed.

As shown in FIG. 1 and FIG. 2 , the semiconductor device of this embodiment includes: a vertical Hall element 100 and a vertical Hall element 200 , and a drive current is supplied to the vertical Hall element 100 and the vertical Hall element 200 respectively. The current source 120 and the current source 220 of the drive power supply, the amplifier 110 and the amplifier 210 that amplify the signals obtained by the free-standing Hall element 100 and the vertical Hall element 200, and the amplifiers 110 and 210 for driving the vertical Hall element 100 and Switches S10 to S19 and switches S20 to S29 switch the direction of the current of the vertical Hall element 200 .

The vertical Hall element 100 and the vertical Hall element 200 respectively include five electrodes 111 to 115 and electrodes 211 to 215 arranged at predetermined intervals on the straight line L1-L1 and the straight line L2-L2 shown in FIG. , and have approximately the same structure as each other. Furthermore, vertical Hall element 100 and vertical Hall element 200 are arranged such that straight line L1 - L1 and straight line L2 - L2 are parallel to each other.

The current source 120 is configured to be connected to the vertical Hall element 100 via switches S10 to S14 . That is, the input terminal of the current source 120 is connected to the electrode 111 via the switch S10, connected to the electrode 112 via the switch S11, connected to the electrode 115 via the switch S14, and the output terminal of the current source 120 is connected to the electrode 113 via the switch S12, It is connected to the electrode 114 via the switch S13.

On the other hand, the current source 220 is configured to be connected to the vertical Hall element 200 through the switches S20 - S24 . That is, the input terminal of the current source 220 is connected to the electrode 213 via the switch S22, and connected to the electrode 214 via the switch S23, and the output terminal of the current source 220 is connected to the electrode 211 via the switch S20, and connected to the electrode 212 via the switch S21, It is connected to the electrode 215 via the switch S24.

Furthermore, the amplifier 110 is configured to be connected to the vertical Hall element 100 via the switches S15 - S19 . That is, the non-inverting input terminal of the amplifier 110 is connected to the electrode 112 via the switch S16, and connected to the electrode 113 via the switch S17, and the inverting input terminal of the amplifier 110 is connected to the electrode 111 via the switch S15, and connected to the electrode 111 via the switch S18. The electrode 114 is connected to the electrode 115 via the switch S19.

On the other hand, amplifier 210 is configured to be connected to vertical Hall element 200 via switches S25 to S29 . That is, the non-inverting input terminal of the amplifier 210 is connected to the electrode 211 via the switch S25, connected to the electrode 214 via the switch S28, and connected to the electrode 215 via the switch S29, and the inverting input terminal of the amplifier 210 is connected to the electrode 215 via the switch S26. The electrode 212 is connected to the electrode 213 via the switch S27.

The vertical Hall element 100 and the vertical Hall element 200 are simultaneously formed on the same semiconductor substrate through a semiconductor manufacturing process. Here, an example of the configuration of the vertical Hall element 100 and the vertical Hall element 200 will be described with reference to FIG. 3 . FIG. 3 is a diagram corresponding to a cross-section taken along line L-L of the semiconductor device shown in FIG. 1 .

As shown in FIG. 3 , the vertical Hall element 100 and the vertical Hall element 200 are respectively formed in the region RA and the region RB of the P-type (first conductivity type) semiconductor substrate 101 . The region RA and the region RB are electrically separated from each other by the P-type element isolation diffusion layer 103 formed on the N-type (second conductivity type) semiconductor layer 102 provided on the semiconductor substrate 101 . The electrodes 111 to 115 of the vertical Hall element 100 and the electrodes 211 to 215 of the vertical Hall element 200 are arranged adjacent to the surface of the semiconductor layer 102 in each of the region RA and the region RB than the concentration of the semiconductor layer 102. A high N-type impurity region constitutes.

Although not shown in FIG. 3, the current source 120 and the current source 220, the amplifier 110 and the amplifier 210, the switch S10 to the switch S19 and the switch S20 to the switch S29 shown in FIG. 1 and FIG. The region different from the region RB is formed so as to be electrically separated from the vertical Hall element 100 and the vertical Hall element 200 by the element isolation diffusion layer 103 .

In addition, in FIG. 3 , it is shown that the vertical Hall element 100 and the vertical Hall element 200 are aligned in the lateral direction, that is, the straight line L1-L1 and the straight line L2-L2 shown in FIG. 1 become the same straight line. As an example of disposing the vertical Hall element 100 and the vertical Hall element 200 as long as the straight line L1-L1 is parallel to the straight line L2-L2, the vertical Hall element 100 and the vertical Hall element 200 may be arranged in any way. For example, the vertical Hall element 100 and the vertical Hall element 200 can also be arranged vertically, that is, in FIG. 1 and FIG. Hall element 200 is arranged on the lower side of the drawing. Furthermore, the vertical Hall element 100 and the vertical Hall element 200 do not necessarily need to be arranged adjacent to each other. For example, the current source 120, the current source 220, or Amplifier 110, amplifier 210, etc.

Next, a description will be given of a method of offset cancellation by the spinning current method using the vertical Hall element 100 and the vertical Hall element 200 in the semiconductor device of the present embodiment. The magnetic field is applied in the direction of arrow B shown in FIGS. 1 and 2 .

First, as shown in FIG. 1 , as phase 1, switches S10, S12, S14, S16, and S18 connected to the vertical Hall element 100, and switches S20, S20, and Switch S22, switch S24, switch S26, and switch S28 are set to be connected (ON), and the switch S11, switch S13, switch S15, switch S17, switch S19 connected to the vertical Hall element 100, and the vertical Hall element connected to The switch S21, the switch S23, the switch S25, the switch S27, and the switch S29 of the Seoul element 200 are turned off (OFF).

Thereby, a driving current is supplied from the current source 120 to the vertical Hall element 100 so that the current flows from the electrode 113 to the electrodes 111 and 115 at both ends (the direction of the current at this time is referred to as "the first current direction") , thereby generating a potential difference between the electrode 112 and the electrode 114 . Since the switch S16 and the switch S18 are turned on, and the non-inverting input terminal of the amplifier 110 is connected to the electrode 112, and the inverting input terminal is connected to the electrode 114, the amplifier 110 amplifies the potential difference between the electrode 112 and the electrode 114 and outputs it to the summing device 130.

A drive current is supplied from the current source 220 to the vertical Hall element 200 in such a manner that current flows from the electrodes 211 and 215 at both ends to the electrode 213 (the direction of the current at this time is referred to as "the second current direction"), thereby A potential difference is generated between the electrode 212 and the electrode 214 . Since the switch S26 and the switch S28 are turned on, and the non-inverting input terminal of the amplifier 210 is connected to the electrode 214, and the inverting input terminal is connected to the electrode 212, the amplifier 210 amplifies the potential difference between the electrode 214 and the electrode 212 and outputs it to the summing device 130.

The adder 130 adds the output signal of the amplifier 110 and the output signal of the amplifier 210 , and outputs the output voltage VOUT1 to the output terminal 131 as the output voltage of phase 1 . The output voltage VOUT1 is held by a sample hold circuit or the like (not shown).

Next, as shown in FIG. 2 , as phase 2, switch S11, switch S13, switch S15, switch S17, switch S19 connected to the vertical Hall element 100, and switches S21, Switch S23, switch S25, switch S27, and switch S29 are set to be connected, and the switch S10, switch S12, switch S14, switch S16, switch S18 connected to the vertical Hall element 100, and the vertical Hall element 200 are connected. The switch S20, the switch S22, the switch S24, the switch S26, and the switch S28 are set to off.

In this way, a drive current is supplied from the current source 120 to the vertical Hall element 100 in such a manner that a current flows from the electrode 114 to the electrode 112 (the direction of the current at this time is referred to as “the third current direction”), and the electrode 113 A potential difference is generated between the electrode 111 and the electrode 115 . Since the switch S15, the switch S17, and the switch S19 are turned on, and the non-inverting input terminal of the amplifier 110 is connected to the electrode 113, and the inverting input terminal is connected to the electrode 111 and the electrode 115, the amplifier 110 connects the electrode 113 to the electrode 111 and the electrode 115. The potential difference between is amplified and output to the adder 130 .

A driving current is supplied from the current source 220 to the vertical Hall element 200 in such a manner that the current flows from the electrode 212 to the electrode 214 (the direction of the current at this time is referred to as "the fourth current direction"), thereby generating A potential difference is generated with the electrode 213 . Since the switch S25, the switch S27, and the switch S29 are turned on, and the non-inverting input terminal of the amplifier 210 is connected to the electrode 211 and the electrode 215, and the inverting input terminal is connected to the electrode 213, the amplifier 210 connects the electrode 211 and the electrode 215 to the electrode 213. The potential difference between is amplified and output to the adder 130 .

The adder 130 adds the output signal of the amplifier 110 and the output signal of the amplifier 210 , and outputs the output voltage VOUT2 to the output terminal 131 as the output voltage of the phase 2 .

And, by performing a process of subtracting the output voltage VOUT1 obtained in the phase 1 from the output voltage VOUT2 obtained in the phase 2, the final output voltage from which the offset voltage has been removed can be obtained.

In addition, in the above description, it was shown that in phase 1, the driving current in the first current direction is supplied to the vertical Hall element 100 , and the driving current in the second current direction is supplied to the vertical Hall element 200 . 2, the driving current in the third current direction is supplied to the vertical Hall element 100, and the driving current in the fourth current direction is supplied to the vertical Hall element 200, but the supply direction of the driving current is not limited to this. Change the switching mode of the switch, for example, in phase 1, supply the driving current in the first current direction to the vertical Hall element 100, supply the driving current in the fourth current direction to the vertical Hall element 200, and in phase 2, supply the driving current in the fourth current direction to the vertical Hall element 200. The vertical Hall element 100 supplies the driving current in the third current direction, and supplies the driving current in the second current direction to the vertical Hall element 200. The voltages are added or subtracted as appropriate, thereby canceling the offset voltage.

Here, the vertical Hall element 100 and the vertical Hall element 200 are formed simultaneously on the same semiconductor substrate through a semiconductor manufacturing process, but it is very difficult to make the concentration distribution of impurities and the like between them exactly the same. Therefore, a characteristic deviation occurs between the vertical Hall element 100 and the vertical Hall element 200 .

Therefore, in this embodiment, a configuration is adopted in which the vertical Hall element 100 and the vertical Hall element 200 are driven by using different current sources 120 and 220 , respectively. With the above configuration, the driving currents of the vertical Hall element 100 and the vertical Hall element 200 can be separately adjusted.

That is, the current value of the current source 120 and the current value of the current source 220 are set to the same current value in advance (referred to as the initial current value), and it is measured that the opposing Hall element 100 and the vertical Hall element 200 respectively supply the same direction, The respective output voltages at the drive current of the same current value. Then, based on the measured difference between the two output voltages, the current value of the current source 120 and the current value of the current source 220 are adjusted to correct the difference. Thereby, the characteristic deviation between the vertical Hall element 100 and the vertical Hall element 200 can be substantially compensated. Therefore, offset cancellation by the rotating current method can be performed with high precision. In addition, the adjustment of each current value of the current source 120 and the current source 220 is, for example, preferably to increase the current value of the current source 120 from the initial current value by α, and decrease the current value of the current source 220 from the initial current value by α, And make the total current value (drive current) be adjusted in a certain way. Thereby, it is no longer necessary to adjust circuits such as the amplifier 110 and the amplifier 210 on the output side of the vertical Hall element 100 and the vertical Hall element 200 .

Furthermore, in the present embodiment, by adopting a configuration in which the outputs of the vertical Hall element 100 and the vertical Hall element 200 are amplified by different amplifiers 110 and 210 , it is also possible to adjust the amplifier 110 and the amplifier 210 . 210 to compensate the characteristic deviation between the vertical Hall element 100 and the vertical Hall element 200 .

On the other hand, although not shown in the figure, the output side of the vertical Hall element 100 and the vertical Hall element 200 may be appropriately connected, and the output voltage may be amplified by a single amplifier. In this case, although it becomes impossible to compensate the characteristic deviation between the vertical Hall element 100 and the vertical Hall element 200 by adjusting the gains of the two amplifiers 110 and 210 as described above, since the Since one amplifier is used, the circuit scale can be reduced.

Furthermore, according to the present embodiment, by appropriately adjusting the drive current supplied to each of the vertical Hall element 100 and the vertical Hall element 200, that is, the current values of the current source 120 and the current source 220, according to the detection state of the magnetic field, It is also possible to add a hysteresis characteristic to the final output voltage. Therefore, a specific configuration example in which a hysteresis characteristic is added to the final output voltage by adjusting the current values of the current source 120 and the current source 220 will be described below using FIG. 4 .

FIG. 4 is a diagram showing a specific configuration example when a hysteresis characteristic is added to the final output voltage of the semiconductor device shown in FIGS. 1 and 2 . In addition, FIG. 4 shows the same phase 1 state as FIG. 1 , but the illustration of the phase 2 state is omitted since it is the same as FIG. 2 . Furthermore, FIG. 5 is a diagram for explaining the magnetoelectric conversion characteristics of the semiconductor device shown in FIG. 4 .

The semiconductor device shown in FIG. 4 further includes a sample-and-hold circuit 140 and a comparator 150 in addition to the configuration of the semiconductor device shown in FIG. 1 .

The sample-and-hold circuit 140 holds the output voltage VOUT1 in phase 1, subtracts the held output voltage VOUT1 from the output voltage VOUT2 in phase 2, and outputs the subtraction result as the final output voltage VOUT.

The output voltage VOUT of the sampling and holding circuit 140 is input to the non-inverting input terminal of the comparator 150, and the ground voltage of the ground terminal 151 is input to the inverting input terminal of the comparator 150 as a reference voltage, and the voltage VOUT is compared with the ground voltage to obtain The result of is output as the output signal CMPOUT. The output signal CMPOUT of the comparator 150 is input to the current source 120 and the current source 220 .

As described above, the current source 120 and the current source 220 have their current values adjusted in advance in order to compensate for the characteristic deviation between the vertical Hall element 100 and the vertical Hall element 200 , and are configured so as to respond to the output signal of the comparator 150 CMPOUT is based on the current value of the adjusted state, and the current value is switched between two values respectively.

Here, since the ground voltage (0 V) is input to the inverting input terminal of the comparator 150 , the output signal CMPOUT corresponding to the voltage value of the voltage VOUT of the non-inverting input terminal is output as follows. When VOUT>0, CMPOUT="H" When VOUT<0, CMPOUT="L"

Next, the operation of this embodiment will be described using FIG. 5 . The X-axis represents the applied magnetic flux density B, and the Y-axis represents the output voltage of the sample-and-hold circuit 140 (the input voltage of the non-inverting input terminal of the comparator 150 ) VOUT.

When the current value before the adjustment of the current source 120 and the current source 220 is I, the adjusted current value of the current source 120 and the current source 220 is respectively I1 and I2, and when α and β are constants, by When CMPOUT=“H”, I1=I(1+α+β), I2=I(1-α-β) When CMPOUT=“L”, I1=I(1+α-β), I2=I(1-α+β) In this way, according to the output signal CMPOUT of the comparator 150, the current values of the current source 120 and the current source 220 are switched between binary values, so that the output voltage VOUT of the sample-and-hold circuit 140 has the same slope and the Y-axis intercept is only biased. Shift ± VOS magnetoelectric conversion characteristics.

Here, α is a value adjusted in advance in such a manner as to compensate for a characteristic deviation between the vertical Hall element 100 and the vertical Hall element 200 . The straight line corresponding to β=0 represents the magnetoelectric conversion characteristic whose characteristic deviation is compensated by adding and subtracting the α to obtain the current value I1 of the current source 120 and the current value I2 of the current source 220 respectively. β is arbitrarily set according to the desired hysteresis width BHYS.

When the applied magnetic flux density B increases from zero to positive (S pole), along the line corresponding to CMPOUT=“L”, the output voltage VOUT of the sample and hold circuit 140 increases (corresponding to the arrow O in the figure). When VOUT>0, the output signal CMPOUT of the comparator 150 changes from "L" to "H", and the magnetoelectric conversion characteristic for the applied magnetic flux density B is switched to a straight line corresponding to CMPOUT="H" (corresponding to the arrow in the figure P). The applied magnetic flux density B at this time is the operating point BOP.

Secondly, when the applied magnetic flux density B increases toward the negative (N pole), along the line corresponding to CMPOUT=“H”, the output voltage VOUT of the sample and hold circuit 140 decreases (corresponding to the arrow Q in the figure). When VOUT<0, the output signal CMPOUT of the comparator 150 changes from "H" to "L", and the magnetoelectric conversion characteristic for the applied magnetic flux density B is switched to a straight line corresponding to CMPOUT="L" again (corresponding to arrow R). The applied magnetic flux density B at this time is the reset point BRP.

In this way, by making the magnetoelectric conversion characteristic hysteresis, it is possible to realize the alternating detection characteristic having the hysteresis width BHYS. Therefore, it is no longer necessary to add a circuit for switching the signal transmission polarity of the signal path, which is usually provided to add a hysteresis characteristic to the output of the sample-and-hold circuit 140, and it is only necessary to add a comparator with a simple configuration, so that the occupied area can be reduced. .

In addition, instead of the ground voltage, a predetermined reference voltage VREF may be input to the inverting input terminal of the comparator 150 . In this case, the inversion level of the magnetoelectric conversion characteristic of the output voltage VOUT of the sample-and-hold circuit 140 in FIG. 5 is not 0 but VREF, and thus becomes When VOUT>VREF, CMPOUT="H" When VOUT<VREF, CMPOUT=“L”, The operating point BOP and the reset point BRP are shifted according to the absolute value and polarity of the prescribed reference voltage VREF. That is, if VREF (>0) is input so that both the operating point BOP and the reset point BRP are positive, the S pole detection characteristic having the operating point BOP and the reset point BRP on the S pole side can be realized. Furthermore, if VREF (<0) is input so that both the operating point BOP and the reset point BRP are negative, the N pole detection characteristic having the operating point BOP and the reset point BRP on the N pole side can also be realized.

FIG. 4 shows an example in which the current values of both the current source 120 and the current source 220 are switched by the output signal CMPOUT of the comparator 150, but only any one of the current source 120 and the current source 220 may be switched. The composition of the current value.

As described above, according to the present embodiment, the current source 220 for driving the vertical Hall element 200 is provided separately from the current source 120 for driving the vertical Hall element 100. Therefore, by properly adjusting the current source 120 and the current source The current value of 220 can compensate the characteristic error of the vertical Hall element 100 and the vertical Hall element 200 produced in the semiconductor manufacturing process, and can make the characteristics of the vertical Hall element 100 and the vertical Hall element 200 substantially the same The rotating current method is performed under the state. Therefore, high-precision offset cancellation can be performed. Furthermore, by switching and controlling the current values of the current source 120 and the current source 220 based on the output signal CMPOUT of the comparator 150 , it is also possible to add a hysteresis characteristic to the final output voltage VOUT. Therefore, it is no longer necessary to add a circuit for adding a special hysteresis characteristic, which is usually provided after the final output voltage VOUT, so that the area of the entire semiconductor device can be reduced.

As mentioned above, although embodiment of this invention was described, this invention is not limited to the said embodiment, Of course, various changes are possible in the range which does not deviate from the summary of this invention.

For example, in the above-described embodiments, an example in which a current source is used as the driving power source is illustrated, but a voltage source may be used instead of the current source. In this case, the driving current of the vertical Hall element is adjusted by adjusting the voltage value of the voltage source.

In the above-described embodiments, a semiconductor device having two vertical Hall elements has been described as an example, but the present invention is also applicable to a semiconductor device having three or more vertical Hall elements. In this case, as in the above-mentioned embodiment, the same number of driving power sources as the number of vertical Hall elements is provided, and each vertical Hall element is driven separately by using an independent driving power source, thereby correcting the number of vertical Hall elements. The characteristic error of a vertical Hall element in the semiconductor manufacturing process. In particular, if four vertical Hall elements are provided, the drive currents in the first current direction to the fourth current direction can be supplied to each vertical Hall element at one time, so the offset cancellation time can be shortened. time. Furthermore, if a configuration in which eight vertical Hall elements are provided, since drive currents in four directions can be supplied to two vertical Hall elements, offset cancellation can be performed with higher precision.

In the embodiment, it is shown that the amplifier 110 and the amplifier 210 are respectively connected to the vertical Hall element 100 and the vertical Hall element 200, and the output signal of the amplifier 110 and the output of the amplifier 210 are combined by the adder 130 Example of signal addition, but can also be set as follows. That is, one amplifier may also be used. First, the difference in the output voltage obtained by driving the vertical Hall element 100 in the state shown in FIG. Next, the difference of the output voltage obtained by driving the vertical Hall element 200 in the state shown in FIG. 1 is amplified by the same amplifier as the second output signal. The difference of the output voltage obtained by driving the vertical Hall element 100 in the state shown in FIG. The difference of the obtained output voltages is amplified as the fourth output signal, and the addition and subtraction calculation is performed on the first output signal to the fourth output signal. Thereby, since one amplifier is required, the circuit scale can be reduced. However, due to the time-division processing, the time required for offset cancellation becomes longer. Therefore, when high speed is required, it is preferable to provide amplifiers corresponding to each of the vertical Hall elements as in the above-mentioned embodiment.

In the above-described embodiment, the directions of the currents supplied to the vertical Hall element 100 and the vertical Hall element 200 are respectively set as two directions, that is, the first current direction and the third current direction are supplied to the vertical Hall element 100. , the vertical Hall element 200 is supplied with driving currents in the second current direction and the fourth current direction, but it is also possible to apply the first current direction to the fourth current direction to each of the vertical Hall element 100 and the vertical Hall element 200 direction for offset cancellation. In this case, since four phases are required, the time required for offset cancellation increases, but the accuracy of offset cancellation can be improved.

In the above-described embodiment, an example in which the vertical Hall element 100 and the vertical Hall element 200 each have five electrodes is shown, but it is not limited thereto, as long as the vertical Hall element 100 and the vertical Hall element The number of electrodes of 200 is the same, and it is only necessary to have three or more electrodes. This point is also the same when the semiconductor device has three or more vertical Hall elements.

In the above-described embodiment, the first conductivity type is described as P-type, and the second conductivity type is N-type. type as P type.

100, 200, 300, 400‧‧‧Vertical Hall element 101‧‧‧semiconductor substrate 102‧‧‧semiconductor layer 103‧‧‧Component separation diffusion layer 110, 210‧‧‧amplifier 111～115, 211～215, 311～315, 411～415‧‧‧electrodes 120, 220‧‧‧current source 130‧‧‧adder 131‧‧‧Output terminal 140‧‧‧sample and hold circuit 150‧‧‧comparator 151‧‧‧Earth terminal B‧‧‧applied magnetic flux density/arrow BHYS‧‧‧Hysteresis Width BOP‧‧‧Operation point BRP‧‧‧reset point CMPOUT‧‧‧Comparator output signal RA, RB‧‧‧area S10～S29‧‧‧Switch VOS‧‧‧Offset VOUT1, VOUT2‧‧‧output voltage VOUT‧‧‧Final output voltage W1～W6‧‧‧Wiring L, L1, L2‧‧‧Line

FIG. 1 is a schematic diagram illustrating a semiconductor device including a vertical Hall element according to an embodiment of the present invention. 2 is a schematic diagram illustrating a semiconductor device including a vertical Hall element according to an embodiment of the present invention. 3 is a cross-sectional view showing an example of the structure of a vertical Hall element according to an embodiment of the present invention, corresponding to a cross-section taken along line L-L of the semiconductor device shown in FIG. 1 . FIG. 4 is a schematic diagram illustrating a specific configuration example when a hysteresis characteristic is added to the semiconductor device shown in FIG. 1 . FIG. 5 is a graph for explaining magnetoelectric conversion characteristics of the semiconductor device shown in FIG. 4 . FIG. 6 is a schematic diagram illustrating a semiconductor device including a conventional vertical Hall element.

100, 200‧‧‧Vertical Hall element

110, 210‧‧‧amplifier

111~115, 211~215‧‧‧electrodes

120, 220‧‧‧current source

130‧‧‧adder

131‧‧‧Output terminal

B‧‧‧applied magnetic flux density/arrow

S10~S29‧‧‧Switch

VOUT1‧‧‧Output voltage

L, L1, L2‧‧‧Line

Claims (8)

A semiconductor device, characterized by comprising: a first vertical Hall element disposed on a first region of a semiconductor substrate and having a plurality of first electrodes arranged at predetermined intervals on a first straight line; a second vertical Hall element The Er element is provided in a second region of the semiconductor substrate different from the first region, and has the plurality of first and second straight lines arranged at the predetermined interval on a second straight line parallel to the first straight line. A plurality of second electrodes with the same number of electrodes; a first drive power supply, which drives the first vertical Hall element; and a second drive power supply, which is set separately from the first drive power supply, and drives the second vertical Hall element. The Hall element, the first driving power supply and the second driving power supply are configured to be independently regulated by independent power supplies. The semiconductor device according to claim 1, wherein the first driving power supply and the second driving power supply are current sources. The semiconductor device according to claim 1, wherein the first driving power supply and the second driving power supply are voltage sources. The semiconductor device according to claim 1 of the patent application, wherein the first vertical Hall element and the second vertical Hall element have substantially the same structure. The semiconductor device described in any one of items 1 to 4 of the scope of the patent application further includes: a first amplifier for amplifying the output voltage from the first vertical Hall element; a second amplifier, provided separately from the first amplifier, amplifying the output voltage from the second vertical Hall element; and an adder, combining the output signal of the first amplifier with the output signal of the second amplifier add up. The semiconductor device as described in item 5 of the scope of the patent application further includes: a sample-and-hold circuit, which maintains the current in the first vertical Hall element and The direction of the current flowing in each of the second vertical Hall elements is set to the first output voltage output from the adder when it is in the first state, and the first output voltage will be output by the first driving power supply and the first driving power supply. The second output voltage output from the adder when the direction of the current flowing in each of the first vertical Hall element and the second vertical Hall element is set to a second state by driving the power supply and The first output voltages are added or subtracted, and the addition result or subtraction result is output as a final output voltage. The semiconductor device as described in claim 6 of the scope of the patent application, which further includes: a comparator, wherein the final output voltage is input into one input terminal, and a prescribed reference voltage is input into the other input terminal, and the final output voltage will be compared A result obtained from the reference voltage is output as an output signal, and according to the output signal of the comparator, a current value or a voltage value of at least one of the first driving power supply and the second driving power supply is obtained switch. A method for adjusting a semiconductor device, characterized by comprising: in the semiconductor device described in item 1 of the scope of the patent application, combining the current value or voltage value of the first driving power supply with the value of the second driving power supply The first step of measuring the output voltages of the first vertical Hall element and the second vertical Hall element when driving currents in the same direction and with the same amount of current are respectively supplied to the first vertical Hall element and the second vertical Hall element. ; and based on the difference between the two output voltages measured in the first step, to increase the current value or voltage value of the first driving power supply by α from the initial value, and to increase the current value or voltage value of the second driving power supply The second step of adjusting the current value or voltage value by decreasing α from the initial value to correct the difference.

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