TWI794318B - Methods and apparatuses for increasing reactor processing batch size - Google Patents

Abstract

Certain embodiments herein relate to methods of increasing a reaction chamber batch size. A portion of a batch of wafers is processed within the chamber. The processing results in at least some off-target deposition of material on interior surfaces of the reaction chamber. A mid-batch chamber processing is conducted to stabilize the off-target deposition materials accumulated on the chamber interior surfaces. Another portion of the batch of wafers is processed within the chamber. In various embodiments, processing of the chamber (e.g., mid-batch) and subsequent portion of the batch of wafers is repeated until processing of all wafers is complete. Batch size refers to the number of wafers that may be processed in the reaction chamber between chamber clean cycles. Chamber interior surfaces are seasoned prior to batch processing. Seasoning of the chamber interior surfaces involves applying a coating of the same material that may be used for deposition on the wafers during processing of the same.

Description

Method and apparatus for increasing reactor batch size

The present invention relates to methods and apparatus for increasing reactor batch sizes.

Semiconductor processing is typically performed in dedicated processing facilities where optimized and efficient throughput is often required. Such equipment may include a reaction chamber that houses a batch of wafers during processing. The reaction chamber may also contain various hardware (eg, substrate supports, showerheads, etc.) used in semiconductor processing. In some cases, the reaction chamber may be treated, or seasoned, before the reaction chamber is used to process substrates. Reaction chamber processing can take a number of different forms and can be performed for a variety of reasons. Furthermore, in some cases, reactions between cleaning cycles have required the process to be stopped and the chamber shut down for cleaning due to the buildup of off-target films deposited on various internal components of the reaction chamber. The total number of wafers that a chamber can process may be limited.

Certain embodiments herein relate to methods of increasing the processing batch size of a reaction chamber involving: (a) processing a portion of a batch of wafers within the reaction chamber, wherein the processing step results in off-target deposition of at least some material on the surface; (b) performing batch intermediate reaction chamber processing to stabilize the off-target deposited material accumulated on interior surfaces of the reaction chamber; and (c) processing the reaction chamber within the reaction chamber Another part of the batch of wafers.

The method further involves repeating (b)-(c) until processing of the batch of wafers is complete.

In some embodiments, the chamber batch size is the number of wafers that can be processed in the chamber between chamber cleaning cycles.

The method may further involve aging the interior surfaces of the reaction chamber prior to batch processing in the reaction chamber.

In some embodiments, the step of aging the interior surfaces of the reaction chamber involves applying a coating of a material that is compatible with the wafers deposited on the batch of wafers during (a) or (c). The material is the same.

In some embodiments, (a) or (c) may involve depositing a material on wafers of the wafer lot.

In some embodiments, the step of aging includes applying a coating to interior surfaces of the reaction chamber by atomic layer deposition (ALD) while no wafer is present in the reaction chamber.

The method may further involve: cleaning interior surfaces of the reaction chamber after (c) is completed.

The method may further involve: (d) cleaning interior surfaces of the reaction chamber after processing of the batch of wafers is complete.

In some embodiments, (b) is performed every specified interval of the total lot accumulation limit of the lot of wafers. Again, the specified interval may be empirically determined. Additionally, the specified interval may occur prior to material buildup on interior surfaces of the reaction chamber to a deleterious level that results in material spalling and wafer defects and/or particles produce.

In some embodiments, the total batch accumulation is limited to the thickness of accumulated material on the interior surfaces of the reaction chamber beyond which processing is compromised such that cleaning of the reaction chamber is required prior to further processing.

In some embodiments, wherein (b) involves depositing a thin film that adheres to material that accumulates on an interior surface of the reaction chamber. Furthermore, the compressibility of the deposited film can be enhanced by adjusting any one or more of the group consisting of: radio frequency (RF) power level, reaction chamber pressure, or RF processing time.

In some embodiments, (b) involves: exposing the material accumulated on the interior surface of the reaction chamber to a plasma after the material has accumulated to a specified thickness. Furthermore, plasma exposure can be performed at pressures in the range of 1 Torr to 10 Torr to facilitate diffusion of plasma into materials accumulated on the interior surfaces of the reaction chamber. Additionally, the plasma can be ignited on the faceplate of the showerhead within the reaction chamber. Additionally, the plasma can be derived from any one of the group consisting of hydrogen, helium, argon, or a source containing nitrogen. In addition, the step of exposing to the plasma can deposit a thin film of about 200 Å on the material accumulated on the interior surfaces of the reaction chamber. Also, a purge gas can be disabled to allow the plasma to disperse evenly throughout the reaction chamber. In some embodiments, the plasma has a frequency of 400 kHz.

In some embodiments, the deposited film stabilizes materials on interior surfaces of the reaction chamber. Furthermore, the step of exposing to the plasma densifies the deposited film to stabilize the material on the interior surfaces of the reaction chamber. In addition, the compressibility of the film can be increased by a method selected from the group consisting of: applied radio frequency (RF) power in the range of 2 kw - 7 kw, applied in the range of 2 torr - 10 torr range, or use an RF plasma time of 0.2 s - 10 s.

The method may further involve: (d) grounding the reaction chamber. Furthermore, grounding the reaction chamber can facilitate plasma diffusion to the outside of the reaction chamber. In some embodiments, a showerhead that may be configured to deliver a deposition gas to the batch of wafers is powered. Also, in some embodiments, a pedestal configured to support the batch of wafers is powered. Furthermore, the plasma used to perform (d) can be supplied by a remote plasma cleaning unit. The remote plasma cleaning unit can be installed in the reaction chamber.

Another aspect relates to a plasma processing apparatus for processing a substrate. The apparatus may further include a reaction chamber comprising: interior chamber surfaces, a substrate support for supporting a substrate within the reaction chamber, and a substrate for removing material from the reaction chamber exhaust port; a remote plasma chamber comprising: a plasma generator for generating plasma in the remote plasma chamber for delivering gas to an inlet of the remote plasma chamber for providing plasma generated in the remote plasma chamber to an outlet of the reaction chamber; and a controller configured to execute instructions for: processing a batch within the reaction chamber a portion of the wafer; performing a batch intermediate reaction chamber process to stabilize material accumulated on interior surfaces of the reaction chamber from batch processing; and processing another portion of the wafer batch within the chamber.

In some embodiments, the plasma processing apparatus is remote from the reaction chamber.

In some embodiments, the controller is further configured to execute instructions for: cleaning an interior surface of the reaction chamber after (c) is complete.

These and other implementations are further described below with reference to the drawings.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail in order not to obscure the present invention. Additionally, while the invention has been described in connection with specific embodiments, it should be understood that the specific embodiments are not intended to limit the invention.

In this application, the terms "wafer" and "substrate" are used interchangeably. Wafers or substrates used in the semiconductor device industry typically have a diameter of 200 mm, or 300 mm, or 450 mm. Unless otherwise stated, processing details (e.g., flow rates, power levels, etc.) described herein relate to processing 300 mm diameter substrates, or to processing chambers configured to process 300 mm diameter substrates, and may Scale as appropriate for other sizes of substrates or chambers. The chambers described herein can be used to process workpieces that can be of various shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces that may be processed in chambers prepared in accordance with certain embodiments include various items such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, micro machinery etc. foreword

In semiconductor manufacturing, efficient reaction chamber productivity is desired. Conventionally, a batch of wafers is supplied to a reaction chamber to be processed (eg deposited) therein on the wafer(s). However, inadvertent off-target deposition of materials on various internal chamber surfaces (eg, sidewalls of the reaction chamber) may result in eventual particle generation, eg, via exfoliation of such materials onto wafers being processed in the chamber. Such exfoliation of off-target material is undesirable because it may contaminate the wafer being processed, thereby degrading the overall quality of the batch of wafers being processed.

Conventionally, a complete cleaning of the interior of the reaction chamber is performed immediately after reaching the batch size of the reaction chamber, which is such that the reaction chamber can be processed before the wafers being processed can be substantially contaminated by particle generation. The maximum number of wafers processed in a chamber where particle generation is due to off-target deposition accumulating in the chamber. Performing such cleaning requires removal of the reaction chamber contents contained therein for processing, thereby potentially reducing throughput and preventing larger batches of wafer processing within a given time period.

Increasing the reaction chamber batch size increases productivity (or throughput) by allowing additional wafers to be processed in the reaction chamber between required cleaning cycles. These increases can be accomplished through one or more of the methods disclosed herein, namely the application of batch-increasing accumulation procedures (BIAS) related processes, which describe the process using intermediary (or batch-intermediate) chamber processing to briefly interrupt conventional wafer processing. Circular processing to stabilize off-target materials deposited on internal reaction chamber components (such as chamber interior sidewalls) to prevent these materials from peeling off or generating particles that would contaminate the processed wafers.

Flaking (as used here and elsewhere throughout this disclosure) can refer to a form of particle generation resulting from partial or complete disintegration of off-target deposited material on interior surfaces of a reaction chamber to On a batch of wafers being processed in a reaction chamber. Spalling is an undesirable condition and can compromise the quality of the lot being processed by introducing defects and/or other particles to the wafer. In addition to exfoliation, "peeling" may be observed. Lift-off describes a specific type of lift-off in which the top exposed surface of the off-target deposited material is uniformly detached from the inner walls to which it is attached during processing and falls onto the wafer. reaction chamber

Figure 1 presents a simplified illustration of a reaction or processing chamber for which processes and apparatus in accordance with the present disclosure may be implemented. The processing chamber 102 includes chamber walls 103 , a chamber floor 104 , and a chamber ceiling 105 . The substrate holder 106 is positioned in the processing chamber 102 and the substrate 107 is seated on the substrate holder 106 . The processing chamber 102 also includes an inlet 108 and a discharge outlet 109 . In some embodiments, the remote plasma source 110 is disposed above the processing chamber 102 . The remote plasma source 110 includes a plasma generator (not shown) for generating plasma in the remote plasma source. The plasma generator includes hardware (eg, coils, electrodes, etc.) for generating plasma, which can be inductively coupled plasma (ICP), capacitively coupled plasma (CCP), or microwave-generated plasma, etc. . The remote plasma source 110 is separated from the processing chamber 102 by a showerhead 111 having a plurality of showerhead holes 112 . The remote plasma source 110 has an inlet 113 for providing a gas used to generate the remote plasma.

Typically, a batch of wafers (eg, one, two to four wafers) are sequentially processed (eg, deposited on the wafers) within the processing chamber 102 . For example, four wafers enter processing chamber 102, undergo processing, and then be removed. Next, an additional four unprocessed wafers may be sent into the processing chamber 102 for processing. Such an approach of transferring collections of wafers until a total target volume or "batch" is reached between required chamber cleaning cycles may be referred to as "batch processing." Wafers are sequentially processed at one or more stations (eg, 1, 2, or 4 stations) until the reaction chamber batch size (eg, limit) is reached. The application of BIAS enables chamber batch sizes to be expanded by intermediary processing of off-target deposited materials to avoid such materials interfering with subsequent wafer processing. Thus, by applying BIAS, a large number of wafers can be processed before wafer processing is temporarily interrupted to process or clean residue buildup on the inner surfaces of the reaction chamber due to Off-target deposition on inner surfaces.

FIG. 2 illustrates the device shown in FIG. 1 after the surface of its internal components has been coated, for example "aged" by applying an undercoat layer (UCT) such as coating 220, as further described below. In general, "aging treatment" refers to a treatment that prepares the interior surfaces of a reaction chamber for processing wafers therein. In some embodiments, the aging treatment may involve applying a coating of silicon oxide (SiO ₂ ) or UCT to the interior surfaces. In other embodiments, silicon oxide ( _SiOx ), nitride, tungsten, or other suitable materials (eg, dielectric materials) may be used in the aging process, depending on what is being deposited in the reaction chamber.

The depicted coating 220 may also represent the accumulation of off-target material deposition during wafer processing in the reaction chamber. The term "accumulation" as used here and elsewhere in this disclosure generally describes the growth of off-target deposited material on the interior surfaces of the reaction chamber. Likewise, the term "normal build-up" describes the conventional build-up procedure during processing of batches of wafers in a chamber that is cleared when the maximum chamber batch size is reached. Substrate 107 (eg, a wafer) is not shown in this figure, and the thickness of coating 220 is exaggerated for illustrative purposes. Additionally, coating 220 may be present in areas not visible in FIG. 2 , such as on the interior surface of showerhead aperture 112 . In some embodiments, the low recombination coating 220 covers only the surfaces inside the processing chamber 102 .

Processing of the substrate 107, such as a semiconductor wafer, may involve deposition thereon by various processes, such as atomic layer deposition (ALD). During wafer processing, a specified number of wafers (eg, one, two, or four wafers) may undergo processing in the processing chamber 102 and then be cycled out to allow entry of new unprocessed wafers. After a certain amount of time spent processing a large number of wafers, material to be deposited on the wafers may begin to accumulate in unintended locations, such as on the chamber walls 103 . As a result, such off-target deposited material may begin to generate particles, eg, flake off the chamber walls 103 and fall (or migrate) onto the substrate 107 to contaminate wafer processing.

Thus, performing the processes further described in FIGS. 4 and 5A-5B can fix or stabilize such off-target deposited material on the chamber walls. Such stabilization of the off-target deposition material may allow additional continued processing of the substrate 107 until a final chamber wall 103 cleaning cycle is necessary to remove and remove the off-target deposition material. In general, a cleaning cycle refers to the removal of undesired off-target deposited material from various internal reactor elements such as sidewalls. The reaction chamber is typically cleaned to allow wafer processing in the reaction chamber to resume. Chamber cleaning can be wet (using liquid phase chemicals) or dry (eg, using plasma). Also, chamber cleaning (commonly referred to as "plasma cleaning") may be performed by providing a plasma to the reaction chamber to clean off-target deposited material on the interior surfaces of the reaction chamber. Plasma cleaning can be performed using in situ or remote plasma.

FIG. 3 shows an exemplary process flow 300 for addressing problems caused by off-target deposition on interior surfaces of reaction chambers during wafer batch processing. Process 300 begins at operation 302 , which involves providing one or more wafers to a reaction chamber, such as a processing chamber, as shown in FIG. 1 .

In some embodiments, multiple wafers may enter the reaction chamber for sequential processing at multiple stations and then be removed from the reaction chamber after processing is complete. In other embodiments, the chamber may be configured to process one wafer at a time. These multiple wafer processes may be collectively referred to as "batch processing," where a "batch" of wafers refers to the processing of wafers that can be processed in the reaction chamber between chamber cleaning cycles before requiring the reactor to be shut down for complete cleaning. Total number of wafers processed where reactors were shut down for full cleaning in order to continue processing wafers without risk of process drift and/or wafer contamination due to particle generation , such as accumulative off-target deposition material exfoliation on internal reactor elements (especially sidewalls), which is attributable to wafer processing in the reaction chamber. In general, a cleaning cycle involves completely deactivating the reaction chamber to provide complete cleaning before continuing to process wafers without risk of contamination due to particle generation, for example, deposition on internal reactor components (especially Cumulative off-target deposition material on the sidewalls) was ablated due to previous wafer processing in the reaction chamber.

During a typical batch process, desired process throughput may be limited due to the continued accumulation of off-target material on the interior surfaces of the reaction chamber during batch wafer processing. Operation 306 (performed after initial processing of a portion of a batch of wafers) addresses the issue of off-target deposition by performing batch intermediate reaction chamber processing to stabilize off-target material deposited, for example, on the sidewalls of the reaction chamber. Any wafers within the reaction chamber may be removed from the reaction chamber before the batch mid-processing at operation 306 begins to avoid undesirable contamination due to batch mid-processing. In some embodiments, batch intermediate processing may involve one or more different program variations, which are further described in FIGS. 4A-4B . After batch intermediate processing in the reaction chamber at operation 306 is complete, another portion of the batch of wafers may be processed in the reaction chamber at operation 308 before process 300 is terminated at operation 310 .

Thus, implementing batch intermediate reaction chamber processing at operation 306 can increase the total number of wafers that can be processed in the reaction chamber between required cleaning cycles, thereby effectively increasing the batch size of wafers to be processed. Therefore, the procedure 300 including operation 306 (also referred to as the batch increasing accumulation procedure (BIAS)) is needed to extend the usability or lifetime of the reaction chamber (e.g., where off-target deposited material will accumulate) between required cleaning cycles. removed to prevent adhesion to the sidewalls of the reaction chamber), thereby increasing the overall operating throughput of wafers being processed in a given reaction chamber.

FIG. 4A shows a comprehensive program flow 400 describing BIAS according to a specific embodiment of the general process described with reference to FIG. 4 . FIG. 4B will be discussed and described in conjunction with FIG. 4A and shows several specific types of batch intermediate reaction chamber processing, such as that performed at operation 306 in process flow 300, and likewise at operation 412 in process flow 400. Implementer. After beginning at operation 402, those skilled in the art will appreciate that the interior surfaces of the reaction chamber may be prepared or aged by depositing thin films thereon by conventional deposition methods, or by atomic layer deposition (ALD). . The film deposited in aging operation 404 may be referred to as a "precoat," or "undercoat" (UCT), and in some embodiments may include a dielectric such as silicon oxide (SiO ₂ )), or other oxides suitable for deposition. In addition, silicon oxide can be deposited by ALD as a UCT in a relatively short period of time to control the thickness of the deposited film over the course of 500 to 1,200 ALD cycles, for example, at a minimum of 100 Å to a maximum of 2,000 Å range, typically within the range of 700Å to 1,400Å.

ALD is a cyclic process with nominally self-limiting steps, which results in small and numerical changes in film thickness. The process is characterized by smoothness and shape retention. The concept of an "ALD cycle" is relevant to the discussion of many of the embodiments herein. In general, an ALD cycle is the minimum set of operations to perform a surface deposition reaction. One cycle results in at least part of a silicon-containing thin film layer eg on the surface of the substrate. Typically, an ALD cycle includes operations to transport and adsorb at least one reactant to a substrate surface, and then react the adsorbed reactant with one or more reactants to form part of the thin film layer. The cycle may include certain ancillary operations, such as removal of either reactants or by-products, and/or treatment of a portion of the deposited film. In general, a loop contains one instance of a unique sequence of operations. For example, an ALD cycle may include the following operations: (i) delivery/adsorption of a silicon-containing precursor, (ii) purging of the silicon-containing precursor from the chamber, (iii) delivery of a second reactant and plasma , and (iv) draining the plasma from the chamber. Various flow rate ranges for precursors, process gases, and/or reagents suitable for generating and coating various types of UCTs by ALD are shown in FIG. 5A, where the column is labeled "UCT." The flow rates (provided in standard cubic centimeters per minute (sccm)) for the ALD process for coating UCT, and additionally various batches of intermediate process coatings, may encompass the specific ranges shown in FIG. 5A. For example, it can be selected from BTBAS (bis(tert-butylamino)silane), BDEAS (bis(diethylamino)silane) ((Et ₂ N) ₂ SiH ₂ ), or DIPAS (bis(isopropylamino)silane) ) silane) precursors flow into the reaction chamber at a volumetric flow rate of 500-3,000 sccm, so that UCT such as silicon oxide (SiO ₂ ) (such as silicate glass) is generated and coated on the interior of the reaction chamber surface. Other suitable exemplary precursors (or reactants) for forming silicon-containing UCTs may include various other bis(alkylamino)silanes, wherein the alkyl group thereof may contain 1-6 carbon groups. Also, each amine group may be individually or monosubstituted with an alkyl group. Additionally, in some embodiments, alkenyl and alkynyl variants can be used as precursors or reactants for the formation of silicon-containing UCTs. In some cases or configurations, different alkyl groups can be used on the molecule (eg, one or more amines can be substituted with methyl groups and one or more other amines can be substituted with ethyl groups). In certain embodiments, one or more alkyl groups may provide steric hindrance to the silane core. Likewise, a carrier gas such as argon (Ar) gas can also be flowed into the reaction chamber to generate UCT as required.

Next, after aging the reaction chamber to coat the UCT at operation 404 as described above, a portion of the batch of wafers is provided to the reaction chamber for processing therein. As previously described for process flow 300, a batch size may refer to the maximum number of wafers that can be processed by the reaction chamber between desired chamber cleaning cycles. A portion of the batch can be any amount less than the entire batch. In some embodiments, a batch can be divided into plural equal parts, such as representing one-half, one-third, one-fourth, etc. The limit is just below the limit at which wafers being processed can substantially become contaminated by particle generation due to off-target deposition accumulating in the chamber. In a specific example, the batch may be divided into quarters, after completing its processing, the batch is 25%, 50%, 75%, and 100% complete. Operation 408 involves processing a portion of a batch of wafers, and may involve (as previously described) sequentially processing groups of wafers (eg, groups of one, two to four wafers) that are cycled in and out of the reaction chamber room for processing. In some embodiments, the processing at operation 408 may involve performing one or more techniques on a portion of the wafer lot, including deposition via an ALD process.

After the processed wafers are removed from the reaction chamber, the portion of the process is temporarily interrupted at operation 412 to allow batch intermediate processing of the reaction chamber. Batch intermediate processing stabilizes off-target material that is inadvertently deposited on the interior surfaces of the reaction chamber during processing of the portion at operation 408 .

One of the advantages of BIAS is that the net capacity of the reaction chamber is increased by increasing the maximum batch size that can be processed by the reaction chamber between mandatory cleaning cycles. The relatively large batch size means that more reaction chamber time can be spent processing wafers therein rather than frequently interrupting processing to complete comprehensive housekeeping operations such as chamber cleaning. Thus, implementing BIAS results in increased throughput, as well as reduced defectivity observed in batches (eg, that may result from frequent process interruptions to clean reaction chambers).

FIG. 4B shows several variations of the particular type of processing that may be performed at operation 412 . For example, the off-target deposition material attached to the side wall of the reaction chamber can be fixed or sealed in place through modification A, for example, by coating (e.g., deposition) to bind the off-target deposition material to the surface to which it is attached (eg, sidewalls and/or other reaction chamber interior components) highly compressible films, while preventing future exfoliation or decomposition of off-target deposited materials, which could interfere with batch wafer processing.

During batch processing, such films may be deposited at every other set of pre-specified intervals, eg, at 25%, 50%, or 75% of the total batch limit, which intervals may be determined empirically. Alternatively, batch intermediate processing may be performed at regular time intervals (eg, per unit of time elapsed from the start of processing). Furthermore, given that off-target material buildup on the interior surfaces of the reaction chamber tends to be proportional to the number of wafers processed therein since the most recent cleaning cycle, a choice may be made based on the measurement of off-target material buildup. Intervals for applying batch intermediate chamber coatings. Such measurements may be performed in addition to, or instead of, applying the batch midchamber coating at a specified fraction of the total batch limit.

Exemplary methods of increasing the compressibility of films or coatings applied to confine off-target deposited material by batch intermediate processing of Variation A (subset of operation 412) include, but are not limited to, under the following conditions Coating thin films by ALD: high radio frequency (RF) power of 2 kw – 7kW, high voltage of 2 T – 10 T, long RF time (0.2 s – 10 s), or through other methods to coat thin films. Furthermore, in some embodiments, one or more of the mentioned techniques may be combined in any combination as desired to increase the compressibility of the film.

A more comprehensive list of exemplary processing conditions is provided in Figure 5A (under the header "Batch Middle - 1/2"). For example, suitable batch mid-processing conditions for applying compressible thin film coatings at, eg, 50% of the total batch build-up limit, may include precursor flow at a volumetric flow rate of 500 to 3,000 sccm. Suitable precursors for forming and applying silicon oxide coatings may comprise silicon-containing species selected from the group comprising: BTBAS (bis(tert-butylamino)silane), BDEAS (bis(diethylamino)silane), Amino)silane) ((Et ₂ N) ₂ SiH ₂ ), or DIPAS (di(isopropylamino)silane), which can be flowed into the reaction chamber at a volumetric flow rate of 500 – 3,000 sccm so that UCTs such as silicon oxide (SiO ₂ ), such as silicate glass, are formed and coated on the interior surfaces of the reaction chamber. Other suitable exemplary precursors (or reactants) for forming silicon-containing UCTs may include various other bis(alkylamino)silanes, wherein the alkyl group thereof may contain 1-6 carbon groups. Also, each amine group may be individually or monosubstituted with an alkyl group. Additionally, in some embodiments, alkenyl and alkynyl variants can be used as precursors or reactants for the formation of silicon-containing UCTs. In some cases or configurations, different alkyl groups can be used on the molecule (eg, one or more amines can be substituted with methyl groups and one or more other amines can be substituted with ethyl groups). In certain embodiments, one or more alkyl groups may provide steric hindrance to the silane core. A carrier gas such as argon (Ar) gas can also be flowed into the reaction chamber to generate UCT as needed. Also, in certain embodiments, the oxygen-containing species can be selected from the group comprising: nitrous oxide ( _N2O ) gas and/or oxygen ( _O2 ) gas, and can be flowed into the reaction chamber .

A subsequent purge operation using nitrogen ( _N2 ) gas in the range shown (eg, 5,000 - 50,000 sccm) can be used to optionally evacuate process reagents from the reaction chamber. In certain embodiments, the second purging operation may be performed at a similar flow rate range as the first purging. The total reaction chamber pressure can be maintained between 1T and 10T during deposition (eg, ALD) and purge operations.

Likewise, the sequence of steps for deposition and associated purge operations is shown below the approximate flow rate range. The dosing sequence indicates the precursor dosing time in seconds; the PDP indicates the post-dosing purge time such as the flow of inert gas used to remove the deposition precursor from the reaction area of the wafer in the reaction chamber; RF time refers to the period of time when radio frequency (RF) plasma power is on in the presence of reactants during a deposition operation; and RF drain time refers to the absence of reactants or plasma power after RF plasma driven deposition duration of purging. Additional chamber process parameters that may be used for adjustment during ALD and purge operations include chamber temperature and power settings. For example, ampoule temperature refers to the temperature of the reactants as they enter the chamber and can range from 20°C to 80°C; gas line temperature refers to the temperature at which the process gas is delivered to the reaction chamber through the gas line , and can be in the range of 20°C-85°C; the base temperature refers to the temperature of the base holding the (plural) wafers to be processed, and can be in the range of 20°C-550°C, depending on The process application and the requirements of the deposited film; the chamber temperature refers to the internal temperature of the reaction chamber during the ALD and related purging process, and can be set in the range of 20°C-85°C; and the top plate temperature can be It is set in the range of 20°C-85°C.

Allowable power settings include those shown in FIG. 5A within specific ranges for various reaction chamber components such as the showerhead and base, both of which can be within the range shown. available in the frequency range below. Additionally, in some embodiments, post-processing processes may be combined with ALD and associated purge processes shown in Figure 5A for batch mid-1/2 processing, at the approximate power levels shown, between flow into the reaction chamber Gas species, frequency and time interval are applied.

In some embodiments, rather than coating a compressible film as described above to coat and seal the off-target deposition material, the accumulated off-target deposition material on the interior surfaces of the reaction chamber may be exposed to the plasma, e.g., As shown in Modification B. Plasma exposure can be performed at a low pressure at desired intervals (e.g., 25%, 50%, or 75%) of the total batch build-up limit, e.g., to allow easier diffusion of the plasma into the off-target deposited material to remove this and other materials are held in place to prevent them from falling onto the batch of wafers during processing. For example, suitable reaction chamber processing conditions and optional post-processing for Modification B may be shown as "batch middle-3" in FIG. 5B. Plasma can be generated in the same manner as shown for deposition (shown in the "Process" column of Figure 5A), and can be delivered to the space between the showerhead (which can be powered) and The processing chamber between the bases (which may be grounded). Furthermore, in some embodiments, the plasma generated as described above can diffuse to improve the quality of material deposited on the carrier ring, which can be positioned within the reaction chamber to hold the wafer during processing. The carrier ring may be made of high impedance ceramic configured or used to focus plasma power onto a grounded base.

In some embodiments, after the plasma treatment described in Variation B, a thin film (e.g., less than 200 Å) can be deposited on the plasma-treated off-target deposition material on the interior surface of the reaction chamber, such as Shown in Modification C. Also, Variation C may involve initial coating with a non-dosing (eg, no flow of reactive precursors or deposition reagents) oxidative plasma treatment at low pressure. In addition, the plasma for first stabilizing the off-target deposited material can be generated by argon (Ar) or a mixture of argon and oxygen (O ₂ ), which can be generated from the showerhead 111 behind the shower head 111 as shown in FIGS. 1 and 2 . location lit. Thus, Variation C can be accomplished by selecting and applying certain process parameters (as previously shown in the "Batch Middle - 1/2" column in FIG. ALD to deposit thin films. These ALD processes may involve short reactant flow times to deposit thinner films (eg, less than 200 Å).

In the conventional processing procedure of Variation C, chemicals (eg, reactive species) for deposition on the substrate 107 may flow out of the showerhead 111 . The inert gas used to generate the plasma used in Modification C is generally difficult to ignite. Accordingly, electrical power may be provided to ignite the inert gas on the faceplate of the showerhead 111 . Also, in such cases, the secondary exhaust (eg, to exhaust gas and/or other species from the reaction chamber) is turned off so that the plasma can be uniformly dispersed outward throughout the process chamber .

Next, after exposing the off-target deposition material to the plasma as described above, a thin film (eg, less than 200 Å) can be deposited thereon to fix or cure the off-target deposition material in place. Such coatings may comprise silicon oxide or another suitable oxide. Additionally, in some embodiments, additional post-deposition film treatments, such as annealing or plasma treatment, may be performed.

Modification D shown in FIG. 5B can be implemented together with Modifications A, B, and C, and Modification D involves grounding the reaction chamber so that the plasma ignited therein eventually diffuses to the outer region of the reaction chamber ( For example, towards the side wall). Conventionally, the pedestal or pedestal that holds the substrate, such as substrate 107 shown in Figures 1 and 2, is grounded, while the showerhead that transports the species toward the substrate for deposition thereon is powered. Here, according to variant D and contrary to the known arrangement, the base can be powered while the showerhead is grounded. For example, the parameters shown in the column "Batch Intermediate - 4" shown in FIG. 5B may optionally be used to cause grounding of the reaction chamber, for example, at power levels in the range of 500W - 7kW Operating base. These configurations provided by Variation D can assist in targeting regions within the reaction chamber for plasma activation, directionality of coating, and bombardment; for example, towards the side walls of the reaction chamber on which off-target material is deposited . These plasmas, after being used to treat or dispose of off-target deposited material on the chamber sidewalls and other chamber components, may then diffuse toward the outer regions of the reaction chamber.

After successful completion of one or more of Variations A-D and/or combinations of Variations A-D (which together constitute batch intermediate reaction chamber processing at operation 412), another portion of the batch of wafers is placed into the reaction chamber at operation 414 chamber to perform processing in the reaction chamber at operation 416 . A decision operation 420 determines whether the reaction chamber batch size limit has been reached during operations 408 and 416 for processing the initial portion of the wafer lot and processing any additional portions. For example, if the determination is "No," the process flow 400 returns to operation 412 for additional batch intermediate processing and deposition so that another portion of the batch of wafers is processed. Accordingly, those skilled in the art will appreciate that the use of BIAS and batch intermediate processing at operation 412 in program workflow 400 enables batch size expansion that allows additional wafers to be processed between mandatory chamber cleaning cycles.

Finally, the total batch accumulation limit will be reached at operation 420, possibly after multiple executions of the batch intermediate reaction chamber processing operation 412, in which there will be (or may be exceeded) deposition on the interior surfaces of the reaction chamber The threshold amount of off-target material is obtained such that the result in operation 420 is "Yes". Accordingly, programmatic workflow 400 proceeds to terminal operation 422, where chamber cleaning is performed.

As previously mentioned, FIGS. 5A and 5B show graphs providing various exemplary process parameter data values corresponding to various wafer processing and batch intermediate chamber processing operations. These values shown are intended to represent parameters used in the various BIAS-related processes described above, but are not exhaustive and are not limiting. Process values and/or parameters may be adjusted as required to achieve specific wafer processing throughput goals.

The various individual parameters are listed vertically in the "Parameter" column in both Figures 5A and 5B. Also, as previously described, flow is provided in sccm for the volumetric flow rate of precursor, reactant, and/or inert exhausting species entering and/or exiting the reaction chamber. The timing of the steps shown in Figures 5A and 5B is as previously described, such as dosing timing and the like. Likewise, the remaining temperature, power level, and optional post-processing settings include parameters as previously described, for example, corresponding to one or more of the following: coating of UCT, or through Variations A-D Batch intermediate processing for any one or more of them.

FIG. 5A also shows an approximate parameter setting range suitable for batch wafer processing, which is listed under the "Process" column. Batch processing can be performed by using ALD techniques as previously described to deposit films of desired thickness thereon, and can involve the flow of precursor and reagent species in the amounts and/or combinations shown.

The remaining columns for UCT, Lot Mid-1/2, Lot Mid-3, and Lot Mid-4 represent the primer coating during pre-treatment aging in the reaction chamber, and Variations A-D, respectively. That is, the column header "UCT" indicates the operating conditions, or settings, for generating and applying a pre-treatment aging primer layer on the inner reaction chamber surface. Likewise, in some embodiments, the field header "Batch Middle - 1/2" indicates the setting of Variation A; the field header "Lot Middle - 3" indicates the setting of Variation B; and, the field The header "batch middle-4" indicates the setting of Modification D. Variation C can be implemented by optionally combining the setting ranges provided in the field headers "Lot Middle - 1/2" and "Lot Middle - 3".

6 shows another graph of exemplary process parameters for a remote cleaning recipe that may be used to perform remote cleaning of the reaction chamber at operation 422 at the end of program workflow 400, for example. The abbreviations HP and LP stand for "high pressure" and "low pressure" respectively (and are also reflected in their respective pressure ranges shown in Figure 6). Various formulations of species for generating plasmas for cleaning are available. After successful removal of off-target deposited material from the interior surfaces of the reaction chamber by a complete cleaning cycle, the BIAS process as shown in program workflow 300, or 400 may be restarted to process additional batches of wafers as needed . equipment

FIG. 7 depicts a schematic diagram of an embodiment of an atomic layer deposition (ALD) processing station 700 having a processing chamber 702 . Processing station 700 may be used to perform certain disclosed embodiments. For example, while processing station 700 may typically be used to deposit thin films on substrates by atomic layer deposition (ALD), processing station 700 may be used in certain configurations to perform atomic layer etching (ALE) or atomic layer cleaning (ALC), for example. ) to etch or clean the carbonaceous material in the patterned framework, respectively. In some embodiments, processing station 700 may be used for ALE, ALC, and ALD, or in some embodiments, several processing stations in a multi-station tool may include a station for ALE or ALC, and a station for ALD, So that the substrate can be transferred between the ALC station and the ALD station without breaking the vacuum.

The processing chamber 702 may be used to maintain low pressure processing. A plurality of processing stations may be included in a common low pressure processing tool environment. For example, FIG. 8 depicts an embodiment of a multi-station processing tool 800 . In some embodiments, one or more hardware parameters of processing station 700 (including those discussed in detail below) may be programmatically adjusted by one or more computer controllers 750 .

The processing station 700 is in fluid communication with a reactant delivery system 701 a for delivering process gases to a distribution showerhead 706 . The reactant delivery system 701 a includes a mixing vessel 704 for mixing and/or conditioning process gases (eg, oxygen-containing gases, or inert gases) for delivery to the showerhead 706 . One or more mixing vessel inlet valves 720 may control the introduction of process gases into the mixing vessel 704 .

For example, the embodiment of FIG. 7 includes a vaporization point 703 for vaporizing liquid reactants to be supplied to a mixing vessel 704 . In some embodiments, deposition chemicals may be provided as vaporized liquid reactants. After performing ALE or ALC in the processing chamber 702, a deposition chemistry may be used to form a patterned carbonaceous material such that a conformal thin film may be deposited on the patterned carbonaceous material by ALD. In some embodiments, vaporization point 703 may be a heated vaporizer. Saturated reactant vapors from this vaporizer may condense in downstream transfer lines. Exposure of incompatible gases to condensed reactants may generate small particles. These small particles may clog pipelines, impede valve operation, contaminate substrates, and the like. Some approaches to address these issues include purging and/or emptying transfer lines to remove residual reactants. However, clearing transfer lines may increase processing station cycle times, which reduces throughput. Thus, in some embodiments, the transfer line downstream of vaporization point 703 may be heat traced. In some embodiments, mixing vessel 704 may also be heated. In a non-limiting example, the line downstream of vaporization point 703 has an increasing temperature profile extending from about 100°C to about 150°C at mixing vessel 704 .

In some embodiments, liquid precursors or liquid reactants may be vaporized at a liquid injector (not shown in FIG. 7 ). For example, a liquid injector may inject a pulse of liquid reactant into the carrier gas stream upstream of mixing vessel 704 . In one embodiment, the liquid injector can vaporize the reactants by flash vaporizing the liquid from high pressure to low pressure. In another example, a liquid injector may atomize a liquid into discrete droplets, which are then vaporized in a heated delivery line. Smaller droplets can vaporize faster than larger droplets, which reduces the delay between liquid injection and complete vaporization. The faster vaporization allows the length of the pipeline downstream of vaporization point 703 to be reduced. In one case, the liquid injector may be mounted directly to the mixing vessel 704 . In another case, the liquid injector can be directly mounted on the shower head 706 .

In some embodiments, a liquid flow controller (LFC) upstream of vaporization point 703 may be provided to control the mass flow of liquid for vaporization and delivery to processing chamber 702 . For example, the LFC may include a thermal mass flow meter (MFM) located downstream of the LFC. The plunger valve of the LFC can then be adjusted in response to feedback control signals provided by a proportional-integral-derivative (PID) controller in electrical communication with the MFM. However, it may take more than a second to stabilize the liquid flow with feedback control. This may prolong the dosing time of the liquid reactant. Therefore, in some embodiments, the LFC can dynamically switch between feedback control mode and direct control mode. In some embodiments, this can be performed by disabling the sense tubes of the LFC and PID controllers.

Showerhead 706 distributes process gas to substrate 712 . In the embodiment shown in FIG. 7 , the substrate 712 is positioned below the showerhead 706 and is shown seated on a chuck or pedestal 708 . Showerhead 706 may be positioned at a distance between 350 mils (0.35 in.) to 700 mils (0.7 in.) to achieve ion directionality provided (or spread) by showerhead 706 toward substrate 712 the degree of expectation. In some embodiments, a lower, or smaller, gap between the showerhead 706 and the pedestal 708 may be employed in order to maintain the directionality of the ions dispersed from the showerhead 706 . However, under low pressure conditions (eg, below 10 mT, or 0.01 Torr), higher, or larger, gaps may be required to achieve a stable spread of ionized plasma from the showerhead 706 . In some embodiments, a chamber may contain multiple chucks or mounts. Showerhead 706 may have any suitable shape and may have any suitable number and configuration of ports for distributing process gases to substrate 712 .

In some embodiments, the base 708 can be raised or lowered to expose the substrate 712 to the volume between the substrate 712 and the showerhead 706 . In some embodiments, the base 708 may be temperature controlled via a heater 710 . During operation of the various disclosed embodiments, base 708 may be set to any suitable temperature, such as between about 25°C to about 650°C, or between about 35°C to about 100°C. It should be appreciated that in some embodiments the base height can be adjusted programmatically by a suitable computer controller 750 .

In another instance, adjusting the height of pedestal 708 may result in a change in plasma density during plasma activation as performed in certain disclosed embodiments. For example, the plasma may be ignited while an inert gas is flowing through the showerhead 706 to the substrate 712 to remove modified core material after exposure of the core material to an oxygen-containing gas. After the processing stage is complete, the pedestal 708 may be lowered during another substrate transfer stage to allow the substrate 712 to be removed from the pedestal 708 .

In some embodiments, the position of the showerhead 706 can be adjusted relative to the base 708 to change the volume between the substrate 712 and the showerhead 706 . Furthermore, it should be understood that the vertical position of base 708 and/or showerhead 706 may be changed by any suitable mechanism within the scope of the present disclosure. In some embodiments, the base 708 may include a rotational axis for rotating the orientation of the substrate 712 . It should be appreciated that in some embodiments one or more of these example adjustments may be performed programmatically by one or more suitable computer controllers 750 . Computerized controller 750 may include any of the features described below for controller 750 of FIG. 7 .

In some embodiments using plasma as discussed above, showerhead 706 and base 708 are in electrical communication with radio frequency (RF) power supply 714 and matching network 716 for energizing the plasma. In some embodiments, plasma energy can be controlled by controlling one or more of: processing station pressure, gas concentration, RF source power, RF source frequency, and plasma power pulse timing. For example, RF power supply 714 and matching network 716 may be operated at any suitable power to form a plasma having a desired free radical species composition. Likewise, RF power supply 714 may provide RF power at any suitable frequency. In some embodiments, the RF power supply 714 may be configured to independently control the high and low frequency RF power sources. Example low frequency RF frequencies may include, but are not limited to, frequencies between 0 kHz and 500 kHz. Example high frequency RF frequencies may include, but are not limited to, frequencies between 1.8 MHz and 2.45 GHz, or greater than about 13.56 MHz, or greater than 27 MHz, or greater than 40 MHz, or greater than 60 MHz. It should be understood that any suitable parameter may be modulated discretely or continuously to provide plasmonic energy for surface reactions.

In some embodiments, the plasma can be monitored in situ by one or more plasma monitors. In one case, plasma power can be monitored by one or more voltage and current sensors (eg, VI probes). In another instance, the plasma density and/or process gas concentration may be measured by one or more optical emission spectrometer sensors (OES). In some embodiments, one or more plasma parameters can be programmatically adjusted based on measurements from the in situ plasma monitor. For example, an OES sensor may be used in a feedback loop for providing programmable control of plasma power. In some embodiments, using certain disclosed embodiments, an OES sensor can be used to set an endpoint to stop etching after a certain amount of time. It should be understood that in some embodiments other monitors may be used to monitor plasma and other process characteristics. Such monitors may include, but are not limited to, infrared (IR) monitors, acoustic monitors, and pressure transducers.

In some embodiments, instructions to controller 750 may be provided via input/output control (IOC) sequence instructions. In one example, instructions for setting conditions for processing stages may be included in corresponding recipe stages of the processing recipe. In some cases, processing recipe stages may be configured sequentially so that all instructions for a processing stage are executed concurrently with that processing stage. In some embodiments, instructions for setting one or more reactor parameters may be included in the recipe phase. For example, a first recipe stage may include: instructions for setting the flow rate of an inert and/or reactant gas (e.g., an oxygen-containing gas), instructions for setting a flow rate of a carrier gas (e.g., argon), and timing for the first recipe stage. delay order. A subsequent second recipe stage may include instructions to modulate or suspend flow rates of inert and/or reactant gases, instructions to modulate flow rates of carrier or purge gases, and time delay instructions for the second recipe stage. The third recipe stage may include: instructions to modulate the flow rate of the second gas (e.g., argon) for the third recipe stage, instructions to modulate the flow rate of the carrier or purge gas, between about 250 W to Instructions for igniting plasma at low plasma powers between about 750W and time delay instructions. A subsequent fourth recipe stage may include instructions to modulate or discontinue flow rates of inert and/or reactant gases, instructions to modulate flow rates of carrier or purge gases, and time delay instructions for the fourth recipe stage. Such formulations can be used to etch carbonaceous materials (eg, core materials) on a substrate to produce vertical sidewalls that contact the underlying surface to be etched at about 90° ± 5°. Additional formulations can also follow and can be used to deposit conformal thin films on patterned core materials by ALD. For example, for depositing a conformal thin film of silicon oxide on a patterned core material, one additional recipe stage may include instructions for setting the flow rate of a silicon-containing precursor, while another additional recipe stage may include: Instructions for flow rates of oxygenated reactants, and time delay instructions. It should be understood that the formulation stages may be further subdivided and/or iterated in any suitable manner within the scope of the present disclosure.

Additionally, in some embodiments, pressure control of the processing station 700 may be provided through a butterfly valve 718 . As shown in the embodiment of FIG. 7, butterfly valve 718 throttles the vacuum provided by a downstream vacuum pump (not shown in FIG. 7). However, in some embodiments, the pressure control of the processing station 700 may also be adjusted by varying the flow rate of one or more gases introduced into the processing station 700 .

As noted above, one or more processing stations may be included in a multi-station processing tool. 8 shows a schematic diagram of an embodiment of a multi-station processing tool 800 having an inbound load gate 802 and an outbound load gate 804, either or both of which may include a remote plasma source (not shown in Figure 8). Robotic arm 806 is configured to move wafers from pods loaded by FOUP 808 into inbound loadgate 802 via atmospheric port 810 at atmospheric pressure. A wafer (not shown in FIG. 8 ) is placed by robot arm 806 on pedestal 812 in inbound load gate 802 , atmospheric port 810 is closed, and inbound load gate 802 is evacuated. Where inbound loadgate 802 includes a remote plasma source, wafers may be exposed to remote plasma processing in inbound loadgate 802 before the wafer is introduced into processing chamber 814 . Furthermore, the wafer may also be heated in the inbound loadgate 802, for example, to remove moisture and sorbed gases. Next, the chamber transfer port 816 to the processing chamber 814 is opened and another robotic arm (not shown) places the wafer into the reactor on the base of the first station shown in the reactor for processing . While the embodiment depicted in FIG. 8 includes a load gate, it should be understood that in some embodiments, direct access of wafers to a processing station may be provided.

In the embodiment shown in FIG. 8, the depicted processing chamber 814 includes four processing stations, numbered 1-4. Each station has a heated base (shown at 818 for station 1), and gas line inlets. It should be understood that in some embodiments, each processing station may serve different or multiple purposes. For example, in some embodiments, a processing station is switchable between ALC, ALD, and plasma-assisted ALD processing modes. In some embodiments, exposure to the deposition precursor and exposure to the second reactant and plasma are performed in the same station. Alternatively or even further, in some embodiments, the processing chamber 814 may contain one or more pairs of matched ALD and plasma assisted ALD processing stations. Although processing chamber 814 is depicted as including four stations, it should be understood that processing chambers in accordance with the present disclosure may have any suitable number of stations. For example, in some embodiments, a processing chamber may have five or more stations, while in other embodiments a processing chamber may have three or fewer stations.

FIG. 8 depicts an embodiment of a wafer handling system 890 for transferring wafers within a processing chamber 814 . In some embodiments, the wafer handling system 890 can transfer wafers between various processing stations and/or between a processing station and a load gate. It should be understood that any suitable wafer handling system may be used. Non-limiting examples include wafer carousels and wafer handling robots. FIG. 8 also depicts an embodiment of a system controller 850 used to control the processing conditions and hardware status of the processing tool 800 . System controller 850 may include one or more memory devices 856 , one or more mass storage devices 854 , and one or more processors 852 . Processor 852 may include a CPU or computer, analog, and/or digital input/output connections, stepper motor controller board, and the like.

In some embodiments, system controller 850 controls all actions of processing tool 800 . System controller 850 executes system control software 858 that is stored in mass storage device 854 , loaded into memory device 856 , and executed on processor 852 . Alternatively, the control logic may be hardcoded in the controller 850 . Application specific integrated circuits, programmable logic devices (eg, field programmable gate arrays, or FPGAs), etc. may be used for such purposes. In the following discussion, whenever "software" or "code" is used, functionally equivalent hard-coded logic may be used there. System control software 858 may include the following commands: control timing, gas mixing, gas flow rates, chamber and/or station pressure, chamber and/or station temperature, wafer temperature, target power level, RF power level The alignment, the position of the substrate mount, chuck and/or pedestal, and other parameters for the particular process performed by the processing tool 800. System control software 858 may be configured in any suitable manner. For example, subroutines or control objects of various processing tool components may be written to control the operation of the processing tool components used to perform the processing of the various processing tools. System control software 858 may be encoded in any suitable computer readable programming language.

In some embodiments, the system control software 858 may include an input/output control (IOC) sequence of commands to control the various parameters described above. In some embodiments, other computer software and/or programs stored on mass storage device 854 and/or memory device 856 associated with system controller 850 may be employed. Examples of programs or portions of programs for this purpose include substrate positioning programs, process gas control programs, pressure control programs, heater control programs, and plasma control programs.

The substrate positioning program may include code for process tool elements used to load substrates on pedestal 818 and to control spacing between substrates and other components of process tool 800 .

The process gas control program may include code to control gas composition (e.g., silicon-containing gas, oxygen-containing gas, and purge gas as described herein) and flow rate and optionally to flow the gas into a or more processing stations to stabilize the pressure in the processing stations. The pressure control program may include code to control the pressure within the processing station by adjusting, for example, a throttle valve in the discharge system of the processing station, the air flow into the processing station, and the like.

The heater control program may include code for controlling the current of the heating unit for heating the substrate. Alternatively, the heater control program may control the delivery of a heat transfer gas, such as helium, to the substrate.

The plasma control program may include code to set the RF power level applied to the processing electrodes in one or more processing stations according to embodiments herein.

The pressure control program may include code for maintaining the pressure in the reaction chamber according to embodiments herein.

In some embodiments, there may be a user interface associated with the system controller 850 . The user interface may include a display screen, a graphical software display of the device and/or processing station, and user input devices (eg, pointing device, keyboard, touch screen, microphone, etc.).

In some embodiments, the parameters adjusted via the system controller 850 may relate to processing conditions. Non-limiting examples include process gas composition and flow rate, temperature, pressure, plasma state (eg, RF bias power level), and the like. These parameters can be provided to the user in the form of a recipe, which can be entered using the user interface.

Signals to monitor the process may be provided via analog and/or digital input connections to the system controller 850 from various process tool sensors. Signals controlling the processing may be output on analog and digital output connections of the processing tool 800 . Non-limiting examples of process tool sensors that may be monitored include mass flow controllers, pressure sensors (eg, manometers), thermocouples, and the like. Appropriately programmed feedback and control algorithms can be used with data from the sensors to maintain process conditions.

The system controller 850 may provide programmed instructions for performing the deposition process described above. These program instructions can control various process parameters, such as DC power level, RF bias power level, pressure, temperature and so on. The instructions may control parameters to operate in situ deposition of thin film stacks in accordance with various embodiments described herein.

System controller 850 will typically include one or more memory devices and one or more processors configured to execute instructions such that the apparatus performs methods in accordance with the disclosed embodiments. A machine-readable medium containing instructions to control processing operations in accordance with the disclosed embodiments may be coupled to the system controller 850 .

In some embodiments, system controller 850 is part of a system that may be part of the examples described above. Such systems may include semiconductor processing equipment including one or more processing tools, one or more chambers, one or more work stations for processing, and/or specific processing elements (wafer bases, gas flow systems, etc.). These systems can be integrated with electronic devices to control the operation of semiconductor wafers or substrates before, during, and after processing. These electronic devices may be referred to as "controllers" which control various elements or subcomponents of a system or systems. Depending on the conditions of the process and/or the type of system, the system controller 850 can be programmed to control any of the processes disclosed herein, including process gas delivery, temperature setting (e.g., heating and/or cooling), Pressure setting, vacuum setting, power setting, radio frequency (RF) generator setting, radio frequency (RF) matching circuit setting, frequency setting, flow rate setting, fluid delivery setting, position and operation setting, access to tools and connection to specific systems or with Additional transfer tools and/or load gate wafer transfer for specific system interface.

Broadly speaking, the system controller 850 refers to an electronic device having various integrated circuits, logic, memory, and/or software for receiving commands, sending commands, controlling operations, enabling cleaning operations, enabling endpoint measurements, and the like. The integrated circuit may comprise one of chips in the form of firmware storing program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and/or executing program instructions (such as software) or More microprocessors or microcontrollers. Program instructions may be instructions transmitted to system controller 850 in the form of various individual settings (or program files) that define operating parameters for performing specific processes on or for semiconductor wafers or for the system. In some implementations, the operating parameters may be part of a recipe defined by a process engineer for one or more thin film layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, During the fabrication of circuits and/or dies, one or more processing steps are performed.

In some implementations, the system controller 850 can be part of or coupled to a computer that is integrated with the system, coupled to the system, or connected to the system through a network, or a combination thereof. For example, system controller 850 may reside in the "cloud," or be all or part of the fab's mainframe computer system, which may allow remote access for substrate processing. The computer can achieve remote access to the system to monitor the current progress of manufacturing operations, view the history of past manufacturing operations, view trends or performance indicators from multiple manufacturing operations, so as to change the parameters of the current processing to set the processing step to continue the current process, or start a new process. In some examples, a remote computer (eg, a server) may provide the processing recipe to the system over a network, which may include a local area network or the Internet. The remote computer may include a user interface that enables input or programming of parameters and/or settings that are then transmitted from the remote computer to the system. In some examples, system controller 850 receives instructions in the form of data specifying parameters for each of the processing steps to be performed during one or more operations. It should be understood that these parameters may be specific to the type of process to be performed, and the type of tool with which the system controller 850 is configured to interface or control the tool. Thus, as noted above, system controller 850 may be decentralized, such as by including one or more separate controllers that are networked together and work toward a common goal, such as the processes and processes described herein. control. An example of a separate controller for such purposes could be one or more integrated circuits on the housing, which is connected to one or more remote (eg, at platform level, or part of a remote computer) location. Multiple integrated circuits communicate, which combine to control the processing on the chamber.

Example systems may include, but are not limited to, plasma etch chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, clean chambers or modules, beveled Etching chamber or module, physical vapor deposition (PVD) chamber or module, chemical vapor deposition (CVD) chamber or module, ALD chamber or module, atomic layer cleaning (ALC) chamber or module Groups, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing systems that may be associated with or used in the fabrication and/or production of semiconductor wafers.

As noted above, depending on the process step(s) to be performed by the tool, the system controller 850 may communicate with one or more of the following in the semiconductor fabrication plant: other tool circuits or modules, other tool components, cluster tools , other tool interface, adjoining tool, adjacent tool, tool throughout the factory, host computer, another controller, or tool used in material transportation that transports wafer containers to and from Tool location and/or loadport.

Suitable apparatus for carrying out the methods disclosed herein are further discussed and described in the following U.S. patent application: U.S. Patent Application No. 13/2011, filed April 11, 2011, entitled "PLASMA ACTIVATED CONFORMAL FILM DEPOSITION" 084,399 (now U.S. Patent No. 8,728,956); and U.S. Patent Application No. 13/084,305, filed April 11, 2011, entitled "SILICON NITRIDE FILMS AND METHODS," the full texts of which are hereby incorporated introduce.

The apparatus/processes described herein may be used with, for example, lithographic patterning tools or processes for the fabrication of semiconductor elements, displays, LEDs, photovoltaic panels, and the like. Typically, though not necessarily, such tooling/processing will be used or performed together in a common manufacturing facility. Photolithographic patterning of thin films typically includes some or all of the following operations, each of which is provided in several possible tools: (1) Coating of photoresist on the workpiece (ie, substrate), using spin-coating or spray-on tools; (2) curing of photoresist using a hot plate or oven or UV curing tool; (3) exposing photoresist to visible or UV light or x-rays with a tool (eg, wafer stepper) (4) developing the photoresist to selectively remove and thereby pattern it using a tool (e.g., a wet clean station); (5) using a dry or plasma-assisted etch tool to The pattern is transferred into the underlying film or workpiece; and (6) the photoresist is removed using a tool (eg, RF or microwave plasma resist stripper). in conclusion

While the foregoing embodiments have been described in detail for purposes of clarity of understanding, it will be appreciated that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and devices of the present invention. Accordingly, the invention should be considered illustrative rather than restrictive, and the examples should not be limited to the details provided herein.

102‧‧‧processing chamber 103‧‧‧chamber wall 104‧‧‧Chamber floor 105‧‧‧cavity ceiling 106‧‧‧substrate support 107‧‧‧substrate 108‧‧‧Entrance 109‧‧‧Emission outlet 110‧‧‧Remote plasma source 111‧‧‧Sprinkler 112‧‧‧sprinkler hole 113‧‧‧Entrance 220‧‧‧coating 300‧‧‧Program flow 302‧‧‧Operation 304‧‧‧Operation 306‧‧‧Operation 308‧‧‧Operation 310‧‧‧Operation 400‧‧‧Program flow 402‧‧‧Operation 404‧‧‧Operation 406‧‧‧Operation 408‧‧‧Operation 412‧‧‧Operation 414‧‧‧Operation 416‧‧‧Operation 420‧‧‧Operation 422‧‧‧Operation 700‧‧‧processing stations 701a‧‧‧Reactant delivery system 702‧‧‧Processing chamber 703‧‧‧vaporization point 704‧‧‧mixing container 706‧‧‧Sprinkler 708‧‧‧base 710‧‧‧heater 712‧‧‧substrate 713‧‧‧ampule box 714‧‧‧RF Power Supply 716‧‧‧Matching network 718‧‧‧butterfly valve 720‧‧‧Inlet valve for mixing vessel 750‧‧‧Controller 800‧‧‧processing tool 802‧‧‧Inbound Load Gate 804‧‧‧outbound load gate 806‧‧‧Robot Arm 808‧‧‧Wafer transfer box 810‧‧‧atmospheric port 812‧‧‧base 814‧‧‧processing chamber 816‧‧‧Chamber delivery port 818‧‧‧base 850‧‧‧Controller 852‧‧‧processor 854‧‧‧mass storage device 856‧‧‧memory device 858‧‧‧System control software 890‧‧‧Wafer handling system

Figure 1 shows a simplified diagram of a reaction chamber for processing substrates with plasma delivered from a remote source.

Figure 2 shows the reaction chamber of Figure 1 with a coating covering the interior surfaces of the chamber.

FIG. 3 is a process flow diagram illustrating operations of a method in accordance with disclosed embodiments.

4A-4B are process flow diagrams illustrating operations of methods in accordance with disclosed embodiments.

5A-5B are exemplary graphs representing sample operating conditions according to the methods of the disclosed embodiments.

FIG. 6 is an exemplary graph representing sample operating conditions according to the method of the disclosed embodiments.

Figure 7 is a schematic diagram of an example processing tool for implementing certain disclosed embodiments.

Figure 8 is a schematic diagram of another example processing tool for implementing certain disclosed embodiments.

300‧‧‧Program flow

302‧‧‧Operation

304‧‧‧Operation

306‧‧‧Operation

308‧‧‧Operation

310‧‧‧Operation

Claims (34)

A method of increasing the batch size of a reaction chamber, the method comprising: (a) processing a portion of a batch of wafers within a reaction chamber, wherein the processing step results in off-target deposition of at least some material on interior surfaces of the reaction chamber; (b) performing batch intermediate reaction chamber processing to stabilize off-target deposited material that has accumulated on interior surfaces of the reaction chamber; and (c) processing another portion of the batch of wafers within the reaction chamber. For example, the method of increasing the batch size of the reaction chamber in item 1 of the scope of the patent application further includes: Repeat (b)-(c) until processing of the batch of wafers is complete. A method of increasing a reaction chamber batch size as claimed in claim 1, wherein the reaction chamber batch size is the number of wafers that can be processed in the reaction chamber between reaction chamber cleaning cycles. For example, the method of increasing the batch size of the reaction chamber in item 1 of the scope of the patent application further includes: The internal surfaces of the reaction chamber are seasoned prior to batch processing in the reaction chamber. The method of increasing the batch size of a reaction chamber as claimed in claim 4, wherein the step of aging the internal surface of the reaction chamber involves applying a coating of a material that is compatible with the one used in (a) or The materials deposited on the batch of wafers during (c) are the same. A method of increasing batch size of a reaction chamber as claimed in claim 1, wherein (a) or (c) involves depositing a material on a wafer of the batch of wafers. A method for increasing the batch size of a reaction chamber as claimed in claim 4, wherein the step of aging treatment comprises: applying a coating by atomic layer deposition (ALD) when no wafer is present in the reaction chamber distributed on the interior surface of the reaction chamber. For example, the method of increasing the batch size of the reaction chamber in item 1 of the scope of the patent application further includes: (d) After (c) is completed, cleaning the interior surfaces of the reaction chamber. For example, the method of increasing the batch size of the reaction chamber in item 2 of the scope of the patent application further includes: (d) cleaning interior surfaces of the reaction chamber after processing of the batch of wafers is complete. The method for increasing the batch size of the reaction chamber as claimed in claim 1, wherein (b) is implemented at a specified interval of the total batch accumulation limit of the batch of wafers. A method of increasing the batch size of a reaction chamber as claimed in claim 10, wherein the total batch accumulation is limited to the thickness of accumulated material on the interior surface of the reaction chamber beyond which processing is compromised such that further processing Cleaning of the reaction chamber is required prior to processing. The method for increasing the batch size of a reaction chamber as claimed in claim 10, wherein the specified interval is empirically determined. The method of increasing the batch size of a reaction chamber as claimed in claim 10, wherein the specified interval occurs before the accumulation of material on the internal surface of the reaction chamber is harmful to the extent that the material on the internal surface of the reaction chamber accumulates detrimental levels leading to material delamination and wafer defect and/or particle generation. A method of increasing the batch size of a reaction chamber as claimed in claim 1, wherein (b) involves depositing a thin film that adheres to material accumulated on the interior surface of the reaction chamber. The method of increasing the batch size of a reaction chamber as claimed in claim 14, wherein the compressibility of the film is enhanced by adjusting any one or more of the group consisting of: radio frequency ( RF) power level, reaction chamber pressure, or RF processing time. The method of increasing the batch size of a reaction chamber as claimed in claim 1, wherein (b) involves: exposing the material accumulated on the inner surface of the reaction chamber to a plasma after the material has accumulated to a specified thickness. A method of increasing the batch size of a reaction chamber as claimed in claim 16, wherein plasma exposure is performed at a pressure in the range of 1 Torr to 10 Torr to facilitate the diffusion of plasma to accumulate on the internal surface of the reaction chamber in the above material. The method of increasing the batch size of a reaction chamber as claimed in claim 16, wherein the plasma is ignited on the faceplate of the shower head in the reaction chamber. For example, the method for increasing the batch size of the reaction chamber in item 16 of the scope of the patent application further includes: A purge gas is disabled to allow the plasma to disperse evenly throughout the reaction chamber. A method of increasing the batch size of a reaction chamber as claimed in claim 16, wherein the plasma is derived from any one of the group consisting of hydrogen, helium, argon, or a source containing nitrogen. The method of increasing the batch size of a reaction chamber as claimed in claim 16, wherein the step of exposing to the plasma deposits a thin film of about 200 Å on the material accumulated on the interior surface of the reaction chamber. The method of increasing the batch size of a reaction chamber as claimed in claim 21, wherein the thin film deposited stabilizes the material on the inner surface of the reaction chamber. The method of increasing the batch size of a reaction chamber as claimed in claim 21, wherein the step of exposing to the plasma densifies the deposited film to stabilize the material on the inner surface of the reaction chamber. A method of increasing the batch size of a reaction chamber as claimed in claim 15, wherein the compressibility of the film is increased by a method selected from the group consisting of: applied in the range of 2 kw - 7 kw Use radio frequency (RF) power within the range of 2 torr - 10 torr, or use an RF plasma time of 0.2 s - 10 s. For example, the method of increasing the batch size of the reaction chamber in item 15 of the scope of the patent application further includes: (d) Ground the reaction chamber. The method of increasing the batch size of a reaction chamber as claimed in claim 25, wherein grounding the reaction chamber facilitates plasma diffusion to the outside of the reaction chamber. A method of increasing batch size of a reaction chamber as claimed in claim 26, wherein a shower head configured to deliver a deposition gas to the batch of wafers is powered. The method for increasing the batch size of a reaction chamber as claimed in claim 26, wherein a base configured to support the batch of wafers is powered. The method for increasing the batch size of a reaction chamber as claimed in claim 9, wherein the plasma used to implement (d) is supplied by a remote plasma cleaning unit. The method for increasing the batch size of a reaction chamber as claimed in claim 29, wherein the remote plasma cleaning unit is installed in the reaction chamber. The method of increasing the batch size of a reaction chamber as claimed in claim 16, wherein the plasma has a frequency of 400 kHz. A plasma processing device for processing a substrate, the device comprising: A reaction chamber comprising: internal chamber surfaces, a substrate holder for supporting a substrate within the reaction chamber, and a discharge port for removing material from the reaction chamber; a remote plasma chamber comprising: a plasma generator for generating plasma in the remote plasma chamber, an inlet for delivering gas to the remote plasma chamber, an outlet for providing plasma generated in the remote plasma chamber to the reaction chamber; and A controller configured to execute instructions for: (a) processing a portion of a batch of wafers within the reaction chamber, wherein the processing step results in off-target deposition of at least some material on interior surfaces of the reaction chamber; (b) performing batch intermediate reaction chamber processing to stabilize off-target deposited material that has accumulated on interior surfaces of the reaction chamber; and (c) processing another portion of the batch of wafers within the reaction chamber. The plasma processing equipment for processing substrates as claimed in claim 32, wherein the plasma processing equipment is far away from the reaction chamber. A plasma processing apparatus for processing a substrate as claimed in claim 32, wherein the controller is further configured to execute instructions for: (d) After (c) is completed, cleaning the interior surfaces of the reaction chamber.

Images