TWI793360B - Bridge embedded interposer, and package substrate and semiconductor package comprising the same - Google Patents

Abstract

A bridge embedded interposer and a package substrate and a semiconductor package including the same includes: a connection structure including one or more redistribution layers, a first bridge disposed on the connection structure and including one or more first circuit layers electrically connected to the one or more redistribution layers, a frame disposed around the first bridge on the connection structure and including one or more wiring layers electrically connected to the one or more redistribution layers, and an encapsulant disposed on the connection structure and covering at least a portion of each of the first bridge and the frame.

Description

Bridge embedded interposer and package substrate and semiconductor package including same [CROSS-REFERENCE TO RELATED APPLICATIONS]

This application claims Korean Patent Application No. 10-2019-0009366 filed with the Korean Intellectual Property Office on January 24, 2019 and Korean Patent Application No. 10 filed with the Korean Intellectual Property Office on April 5, 2019 - The benefit of priority of No. 2019-0040072, the disclosure of said application is hereby incorporated by reference in its entirety.

The present disclosure relates to a bridge embedded interposer, a package substrate and a semiconductor package including the same.

The intermediary market has grown in accordance with improvements in specifications of high-end sets and the use of high bandwidth memory (HBM). Currently, silicon is generally mainly used as an intermediary material. For example, in the case of a semiconductor package using an interposer, the die may be surface mounted on a silicon-based interposer and have been fabricated by molding with a molding material.

At the same time, compared with the prior art, the amount of high-bandwidth memory is With recent improvements in the specifications of devices, intermediaries with high performance have been realized, which makes the process more difficult and lowers the yield rate making it high risk.

The aspect of the present disclosure is to provide an intermediary, a packaging substrate containing it, and a semiconductor package. The intermediary, the packaging substrate and the semiconductor package including it can reduce the difficulty of the process, improve the efficiency and yield of the process, and solve the warpage problem. Complement and improve power characteristics, as well as reduce size, and also manufacture in large area.

Aspects of the present disclosure use a frame including one or more wiring layers to embed bridges in interposers and electrically connect connection structures including one or more redistribution layers.

According to aspects of the present disclosure, a bridge-embedded intermediary may include: a connection structure including one or more redistribution layers; a first bridge disposed on the connection structure and electrically connected to the One or more first circuit layers of one or more redistribution layers; a frame, disposed on the connection structure around the first bridging member, and including electrical connections to the one or more redistribution layers one or more wiring layers; and an encapsulation body configured on the connection structure and covering at least part of each of the first bridging member and the frame.

In addition, a package substrate according to an example may include: a printed circuit board; and a bridge embedded interposer disposed on the printed circuit board. The bridge-embedded intermediary may include: a connection structure including one or more redistribution layers; a bridge member disposed on the connection structure and including one or more redistribution layers electrically connected to the one or more redistribution layers. a circuit layer; a frame, disposed on the connection structure around the bridge, and including one or more wiring layers electrically connected to the one or more redistribution layers; and an encapsulation body configured on the connection structure and covering each of the bridge member and the frame at least part of the The one or more circuit layers may be electrically connected via the one or more redistribution layers and the one or more wiring layers.

In addition, a semiconductor package according to an example may include: a bridge embedded interposer including: a connection structure having a first side and a second side opposite to the first side, and including one or more redistribution layers; a bridge, configured on the first side of the connection structure, and including one or more circuit layers electrically connected to the one or more redistribution layers; a frame, disposed on the bridge around the bridge on the first side of the connection structure, and includes one or more wiring layers electrically connected to the one or more redistribution layers; and an encapsulation body configured on the first side of the connection structure side, and covering at least part of each of the bridge and the frame; a first semiconductor chip, configured on the second side of the connecting structure, and has an electrical connection to the one or a plurality of first connection pads of a plurality of redistribution layers; and a second semiconductor chip configured on the second side of the connection structure and having a pad electrically connected to the one or more redistribution layers a plurality of second connection pads. At least part of the plurality of first connection pads and at least part of the plurality of second connection pads may be electrically connected to each other via the one or more circuit layers.

100A, 100B, 100C, 100D, 100E, 100F: intermediary embedded in the bridge

100A1: Embedded intermediary in the first bridge piece

100A2: Embedded intermediary in the second bridge piece

100A3: Embedded intermediary in the third bridge piece

110: frame

110H: Penetrating part

110H1: The first penetration

110H2: Second penetration

110H3: The third penetration

111: insulating layer

111a: first insulating layer

111b: second insulating layer

112a: wiring layer/first wiring layer

112b: wiring layer/second wiring layer

112c: wiring layer/third wiring layer

113: Wiring through hole

113a: first wiring through hole

113b: second wiring through hole

120a: base layer

120b: insulating layer

120c: circuit layer

120d: pad layer

120e: through hole

120f: pad layer

120g: insulating layer

120h: pattern layer

120i: via layer

121: The first bridge piece

122: The second bridge piece

130: Encapsulation

132: Back side wiring layer

133: Back side through hole

140: Connection structure

141: insulation layer

142:Rewiring layer

143: Connection through hole

150: The first passive component

160: Second passive component

170: passivation layer

180: the first electrical connection bump

195: Tape

210: Underfill resin

221: The first semiconductor wafer

221a:1-1 Semiconductor wafer/semiconductor wafer

221b:1-2 Semiconductor wafer/semiconductor wafer

221B: The first electrical connection metal

221c:1-3 Semiconductor Wafer/Semiconductor Wafer

221P: first connection pad

222: second semiconductor wafer

222a:2-1 Semiconductor Wafer/Semiconductor Wafer

222b:2-2 Semiconductor Wafer/Semiconductor Wafer

222B: the second electrical connection metal

222c: 2-3 Semiconductor Wafer/Semiconductor Wafer

222P: Second connection pad

300: printed circuit board

310: The third passive component

320: the second electrical connection bump

400A, 400B, 400C, 400D, 400E, 400F: package substrate

500A, 500B, 500C, 500D, 500E, 500F: semiconductor package

1000: electronic device

1010:Motherboard/Mainboard

1020: Chip-related components

1030: Network related components

1040: other components

1050: camera

1060: Antenna

1070: display

1080: battery

1090: signal line

1100: smart phone

1101: Ontology

1110: printed circuit board

1120: Electronic components

1130: Camera module

2110: Motherboard

2210: Ball Grid Array (BGA) Substrate

2220: Graphics Processing Unit/Semiconductor Chip

2230: Intermediary

2240: High bandwidth memory/semiconductor chip

2250: Silicon intermediary

2260: Organic Intermediaries/Intermediaries

2310: Semiconductor packaging

2320: Semiconductor packaging

I-I': section line

The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, wherein in the accompanying drawings:

FIG. 1 is a block diagram illustrating an example of an electronic device system.

FIG. 2 is a schematic perspective view illustrating an example of an electronic device.

FIG. 3 is a schematic cross-sectional view illustrating a situation where a 3D ball grid array (BGA) package is mounted on a motherboard of an electronic device.

FIG. 4 is a schematic cross-sectional view showing a situation where a 2.5D silicon interposer package is mounted on a motherboard.

FIG. 5 is a schematic cross-sectional view showing a situation where a 2.5D organic interposer package is mounted on a motherboard.

FIG. 6 is a schematic cross-sectional view showing an example of a semiconductor package.

FIG. 7 is a schematic plan view of a top view of the semiconductor package shown in FIG. 6 .

FIG. 8 is a schematic plan view taken along the section line I-I' of the semiconductor package shown in FIG. 6 .

FIG. 9 is a schematic plan view showing a modified example of the top view shown in FIG. 7 .

FIG. 10 is a schematic diagram of a cutting plane showing a modified example of the cutting plane diagram shown in FIG. 8 .

FIG. 11 is a schematic cross-sectional view showing an example of a first bridge member of the semiconductor package shown in FIG. 6 .

FIG. 12 is a schematic cross-sectional view showing an example of a second bridge member of the semiconductor package shown in FIG. 6 .

13 is a schematic cross-sectional view illustrating another example of the first bridge and/or the second bridge of the semiconductor package shown in FIG. 6 .

14 to 17 are schematic process diagrams showing a manufacturing example of the semiconductor package shown in FIG. 6 .

FIG. 18 is a schematic cross-sectional view showing another example of a semiconductor package.

FIG. 19 is a schematic cross-sectional view showing another example of a semiconductor package.

FIG. 20 is a schematic cross-sectional view showing another example of a semiconductor package.

FIG. 21 is a schematic cross-sectional view showing another example of a semiconductor package.

FIG. 22 is a schematic cross-sectional view showing another example of a semiconductor package.

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings as follows. In the drawings, the size and shape of elements will be exaggerated or reduced for clarity of description.

electronic device

FIG. 1 is a block diagram illustrating an example of an electronic device system.

Referring to FIG. 1 , an electronic device 1000 may receive a motherboard 1010 . The motherboard 1010 may include chip-related components 1020 , network-related components 1030 and other components 1040 that are physically or electrically connected to the motherboard 1010 . These components can be connected to other components described below to form various signal lines 1090 .

Chip-related components 1020 may include: memory chips, such as volatile memory (such as dynamic random access memory (dynamic random access memory, DRAM)), non-volatile memory (such as read only memory (read only memory, ROM)), flash memory, etc.; application processor chip, such as central processing unit (for example: central processing unit (central processing unit, CPU)), graphics processor (for example: graphics processing unit (graphic processing unit, GPU) ), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (analog-to-digital converter), application-specific integrated circuit (application-specific integrated circuit, ASIC), etc. However, the chip-related components 1020 are not limited thereto, and may also include other types of chip-related components. In addition, wafer related components 1020 may be combined with each other.

The network-related components 1030 may include, for example, the following protocols: Wireless Fidelity (Wireless Fidelity, Wi-Fi) (Institute of Electrical and Electronics Engineers (Institute of Electrical And Electronics Engineers, IEEE) 802.11 family, etc.), Worldwide Interoperability for Microwave Access (worldwide interoperability for microwave access, WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, long term evolution (long term evolution, LTE), evolution data only (evolution data only, Ev-DO), high-speed packet access + (high speed packet access+, HSPA+), high speed downlink packet access+ (HSDPA+), high speed uplink packet access+ (HSUPA+), enhanced data GSM environment (EDGE ), global system for mobile communications (GSM), global positioning system (global positioning system, GPS), general packet radio service (general packet radio service, GPRS), code division multiple access (code division multiple access) , CDMA), time division multiple access (time division multiple access, TDMA), digital enhanced cordless telecommunications (digital enhanced cordless telecommunications, DECT), ^Bluetooth® , 3G protocol, 4G protocol and 5G protocol, and designated after the above agreements any other wireless and wired protocols. However, the network-related component 1030 is not limited thereto, but may also include various other wireless standards or protocols or wired standards or protocols. In addition, the network-related component 1030 may be combined with each other together with the above-mentioned chip-related component 1020 .

Other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramics, LTCC), electromagnetic interference (electromagnetic interference, EMI) filter, multilayer ceramic capacitor (multilayer ceramic capacitor, MLCC), etc. However, the other components 1040 are not limited thereto, but may also include passive components and the like for various other purposes. Additionally, other components 1040 may be combined with each other along with the wafer-related components 1020 or the network-related components 1030 described above.

Depending on the type of the electronic device 1000 , the electronic device 1000 includes other components that may be physically or electrically connected to the motherboard 1010 , or may not be physically or electrically connected to the motherboard 1010 . These other components may include, for example, camera 1050, antenna 1060, display 1070, battery 1080, audio codec (not shown), video codec (not shown), power amplifier (not shown), out), compass (not shown in figure), accelerometer (not shown in figure), gyroscope (not shown in figure), speaker (not shown in figure), mass storage unit (such as hard disk drive machine) (not shown in the figure), a compact disk (CD) drive (not shown in the figure), a digital versatile disc (digital versatile disk, DVD) drive (not shown in the figure), etc. However, these other components are not limited thereto, but may also include other components for various purposes depending on the type of the electronic device 1000 and the like.

The electronic device 1000 can be a smart phone, a personal digital assistant (personal digital assistant, PDA), digital camera, digital still camera (digital still camera), network system, computer, monitor, tablet PC (tablet PC), laptop PC, portable easy-to-network personal computer (netbook PC), TV, video game machine (video game machine), smart watch or car components, etc. However, the electronic device 1000 is not limited thereto, and can be any other electronic device capable of processing data.

FIG. 2 is a schematic perspective view illustrating an example of an electronic device.

Referring to FIG. 2, the semiconductor package may be used for various purposes in the various electronic devices 1000 described above. For example, the printed circuit board 1110 can be accommodated in the body 1101 of the smartphone 1100 , and various electronic components 1120 can be physically and/or electrically connected to the printed circuit board 1110 . In addition, other components that may be physically or electrically connected to the printed circuit board 1110 or may not be physically or electrically connected to the printed circuit board 1110 (such as the camera module 1130 ) may be accommodated in the body 1101 . Some of the electronic components in the electronic component 1120 may be chip-related components, such as the semiconductor package 1121 , but not limited thereto. The electronic device is not necessarily limited to the smartphone 1100, but may be other electronic devices as described above.

semiconductor package

Generally speaking, many sophisticated circuits are integrated in a semiconductor chip. However, the semiconductor wafer itself may not function as a completed semiconductor product and may be damaged by external physical or chemical influences. Therefore, the semiconductor wafer cannot be used alone, but it can be packaged and used in an electronic device or the like in the packaged state.

Here, due to the electrical connection between the semiconductor chip and the motherboard of the electronic device Differences in circuit width in connection, thus requiring semiconductor packaging. Specifically, the size of the connection pads of the semiconductor chip and the spacing between the connection pads of the semiconductor chip are extremely precise, but the size of the component mounting pads of the main board used in the electronic device and the spacing between the component mounting pads of the main board are significantly larger than The size and spacing of the connection pads of the semiconductor wafer. Therefore, it may be difficult to directly mount the semiconductor die on the motherboard, requiring packaging techniques for buffering the difference in circuit width between the semiconductor die and the motherboard.

Hereinafter, an intermediary using a semiconductor package manufactured by such a packaging technique will be explained in more detail with reference to the drawings.

FIG. 3 is a schematic cross-sectional view illustrating a situation where a 3D ball grid array (BGA) package is mounted on a motherboard of an electronic device.

Application specific integrated circuits (ASICs) such as graphics processing units (GPUs) in semiconductor wafers are extremely expensive, and therefore it is extremely important to perform packaging on application specific integrated circuits with high yield. of. To this end, prepare a ball grid array (BGA) substrate 2210 that can redistribute thousands to hundreds of thousands of connection pads before mounting the semiconductor chip, and use surface mounting technology (surface mounting technology, SMT) to place the expensive semiconductor Chips (eg, graphics processing unit 2220 , etc.) are mounted and packaged on the BGA substrate 2210 , and then the semiconductor chips are finally mounted on the motherboard 2110 .

Meanwhile, in the case of the GPU 2220, the signal path between the GPU 2220 and a memory such as a high bandwidth memory (HBM) needs to be significantly reduced. For this, the following product is used: In said product, for example, a high bandwidth A semiconductor chip such as a memory 2240 is mounted and then packaged on the interposer 2230, and then the semiconductor chip is stacked in a package-on-package (POP) form on the package in which the graphics processing unit 2220 is mounted. However, in this case, the thickness of the device is excessively increased, and there is a limit in significantly reducing the signal path.

FIG. 4 is a schematic cross-sectional view showing a situation where a 2.5D silicon interposer package is mounted on a motherboard.

As a method for solving the above-mentioned problems, it may be considered to manufacture the semiconductor package 2310 including the organic intermediary by 2.5D intermediary technology including the following steps: connecting the first semiconductor wafer (such as the graphics processing unit 2220) and the second semiconductor wafer (eg high bandwidth memory 2240 ) are surface mounted side by side and then packaged on silicon interposer 2250 . In this case, the GPU 2220 and the high bandwidth memory 2240 with thousands to hundreds of thousands of connection pads can be redistributed through the silicon interposer 2250 and can be electrically connected to each other through the shortest path. In addition, when the semiconductor package 2310 including the silicon interposer is mounted again and redistributed on the ball grid array substrate 2210 or the like, the semiconductor package 2310 may be finally mounted on the main board 2110 . However, it is extremely difficult to form through-silicon vias (TSVs) in the silicon interposer 2250, and the cost required to manufacture the silicon interposer 2250 is quite high, and therefore the silicon interposer 2250 is increasing the area and reducing the cost aspect is disadvantageous.

FIG. 5 is a schematic cross-sectional view showing a situation where a 2.5D organic interposer package is mounted on a motherboard.

As a solution to the above problems, the use of organic intermediaries 2260 may be considered To replace the silicon interposer 2250. For example, it can be considered to manufacture the semiconductor package 2320 including the organic interposer by 2.5D interposer technology including the following steps: combining a first semiconductor die (such as a graphics processing unit 2220 ) with a second semiconductor die (such as a high bandwidth memory 2240) side by side with each other and then packaged on the organic interposer 2260. In this case, the GPU 2220 and the high bandwidth memory 2240 with thousands to hundreds of thousands of connection pads can be redistributed through the organic intermediary 2260 and can be electrically connected to each other through the shortest path. In addition, when the semiconductor package 2320 including the organic intermediary is mounted again and redistributed on the ball grid array substrate 2210 or the like, the semiconductor package 2320 may be finally mounted on the main board 2110 . In addition, organic intermediaries may be advantageous in terms of increased area and reduced cost. However, in the case of a semiconductor package including an organic interposer, warpage of the package may occur when the molding process is performed, fillability of the underfill resin may deteriorate, and due to the coefficient of thermal expansion of the interposer 2260 expansion, CTE) and the coefficient of thermal expansion of the molding material of the semiconductor wafers 2220 and 2240 may generate cracks between the die and the molding material, as described above. Furthermore, organic intermediaries may be disadvantageous in achieving precise patterns.

As a method for solving the above-mentioned problems, although not shown in detail in the drawings, a silicon-based interconnection bridge with a fine pattern can be formed separately, and the silicon-based interconnection bridge can be inserted into a ball grid array substrate. embedded in the cavity. However, in this case, it is difficult to form cavities and achieve corresponding precise patterns in the BGA substrate, which may lead to process problems and lower yield. Therefore, there is a need for a new type of semiconductor package that can solve all the above-mentioned problems.

FIG. 6 is a schematic cross-sectional view showing an example of a semiconductor package.

FIG. 7 is a schematic plan view showing a top view of the semiconductor package shown in FIG. 6 .

FIG. 8 is a schematic plan view taken along the section line I-I' of the semiconductor package shown in FIG. 6 .

Referring to the drawings, a semiconductor package 500A according to an example may include a package substrate 400A including: a printed circuit board 300 ; and a bridge embedded interposer 100A disposed on the printed circuit board 300 . In addition, the semiconductor package 500A may include: a first semiconductor chip 221 configured on the interposer 100A embedded in the bridge member and including a plurality of first connection pads 221P; and a plurality of second semiconductor chips 222 respectively configured in the bridge member embedded The interposer 100A respectively includes a plurality of second connection pads 222P.

In this case, the bridge embedded intermediary 100A according to the example may include: a connection structure 140 having a first side and a second side opposite to the first side; a plurality of first bridges 121 respectively configured to connect On the first side of the structure 140; a plurality of second bridges 122, respectively configured on the first side of the connecting structure 140; frame 110, surrounding the plurality of first bridges 121 and the plurality of second bridges 122 is disposed on the first side of the connection structure 140; and the encapsulation body 130 is disposed on the first side of the connection structure 140 and covers the plurality of first bridges 121 and the plurality of second bridges 122 and at least part of each of the frames 110 . The connection structure 140 may include one or more redistribution layers 142 . Each of the plurality of first bridges 121 and the plurality of second bridges 122 can be electrically connected to one or more redistribution layers respectively 142. The frame 110 may include one or more wiring layers 112 a , 112 b , and 112 c electrically connected to one or more redistribution layers 142 . At the same time, the plurality of first connection pads 221P of the first semiconductor chip 221 and the plurality of second connection pads 222P of each second semiconductor chip 222 can pass through the plurality of first bridge members 121 and the plurality of connection pads 222P. The two second bridging elements 122 are electrically connected to each other in various relationships, as shown in FIG. 7 and FIG. 8 . For example, the second connection pads 222P of each second semiconductor chip 222 can be electrically connected to the first connection pads 221P of the first semiconductor chip 221 via the first bridges 121 or the second bridges 122 respectively.

As described above, in the semiconductor package 500A according to the example, the bridge embedded interposer 100A according to the example may include the frame 110, and the plurality of first bridges 121 and the plurality of second bridges may be configured using the frame 110. bridge piece 122 . Specifically, in an example, the frame 110 may have a plurality of first through portions 110H1 and a plurality of second through portions 110H2, and a plurality of first bridging members 121 may be respectively arranged in the plurality of first through portions 110H1, and a plurality of The second bridging elements 122 can be respectively disposed in the plurality of second through portions 110H2. After such configuration, the plurality of first bridging elements 121 and the plurality of second bridging elements 122 can be respectively encapsulated by the encapsulating body 130 . In this case, only good products among the plurality of first bridges and the plurality of second bridges manufactured separately may be selected and configured. In addition, the bridge-embedded interposer 100A of a good product manufactured as described above can be connected to the printed circuit board 300, the first semiconductor wafer 221, and the plurality of second semiconductor wafers 222 without a separate carrier, so that expensive second semiconductor wafers 222 can be reduced. The loss of the first semiconductor chip 221 and the second semiconductor chip 222 and the expensive printed circuit board 300 . In addition, due to the plurality of first bridging members 121 And the plurality of second bridges 122 can be manufactured to have a compact size, so the size of the ultra-fine wiring area can be reduced, and interposer yield can be prevented from being lowered. In addition, since the printed circuit board 300 , the first semiconductor chip 221 and the plurality of second semiconductor chips 222 can be connected without a separate carrier as described above, the manufacturing process can be simplified. Furthermore, the frame 110 controls process warpage so that warpage control is also possible.

Meanwhile, the intermediary 100A embedded in the bridge according to the example may further include the first passive component 150 and/or the second passive component 160 . Specifically, in an example, the first passive component 150 may be disposed in the third through portion 110H3 of the frame 110 . In addition, the second passive component 160 having a smaller size than the first passive component 150 may be embedded in the frame 110 . The first passive component 150 and the second passive component 160 may be known passive components, such as capacitors or inductors, respectively. As described above, when the first passive component 150 and the second passive component 160 are disposed at various positions in the bridge embedded interposer 100A, the electrical paths to the first semiconductor chip and/or the second semiconductor chip are relatively small. The short electrical path to the third passive component 310 disposed on the printed circuit board 300 complements and improves power integrity.

Meanwhile, the bridge-embedded interposer 100A according to the example may further include: a backside wiring layer 132 disposed on the side of the encapsulation body 130 opposite to the side in which the connection structure 140 is disposed; and a backside via hole 133 , penetrate through the encapsulation body 130 and electrically connect one or more wiring layers 112 a , 112 b , 112 c of the frame 110 and the backside wiring layer 132 . In this case, the pads for the first electrical connection bump 180 can be arranged at various positions via the backside wiring design. Therefore, by increasing the number of the first electrical connection bumps 180, the electrical properties of the printed circuit board 300 can be improved. path. The backside wiring layer 132 may be disposed on a side of the encapsulation body 130 opposite to the side in which the connection structure 140 is disposed, and may be protected by a passivation layer 170 covering at least part of the backside wiring layer 132 .

The passivation layer 170 may have openings exposing at least part of each of the backside wiring layers 132, and the first electrical connection bumps 180 may be respectively disposed in the openings to be electrically connected to the exposed backside wirings. Layer 132.

Hereinafter, each configuration included in the semiconductor package 500A according to the example will be explained in more detail with reference to the drawings.

First, as described above, the bridge-embedded intermediary 100A according to the example may include a frame 110 , a plurality of first bridges 121 , a plurality of second bridges 122 , an encapsulation 130 , and a connection structure 140 . In addition, if necessary, the bridge embedded intermediary 100A may further include the first passive component 150 and/or the second passive component 160 . In addition, if necessary, the bridge-embedded interposer 100A may further include a backside wiring layer 132 , a backside via hole 133 and/or a first electrical connection bump 180 .

The frame 110 can improve the rigidity of the bridge-embedded intermediary 100A depending on the specific material, and can be used to ensure the thickness uniformity of the encapsulation body 130 . The frame 110 may have a first penetrating portion 110H1 , a second penetrating portion 110H2 , and a third penetrating portion 110H3 penetrating through the first insulating layer 111 a and the second insulating layer 111 b. In addition to the first insulating layer 111a and the second insulating layer 111b, the frame 110 may further include a first wiring layer 112a, a second wiring layer 112b, a third wiring layer 112c, and a first wiring through hole 113a and a second wiring through hole. 113b. Therefore, the frame 110 may serve as an electrical connection member providing a vertical electrical connection path. If desired, the frame 110 may be composed of a plurality of frame units. each The frame unit may independently include a first insulating layer 111a and a second insulating layer 111b, a first wiring layer 112a, a second wiring layer 112b, and a third wiring layer 112c, and a first wiring through hole 113 and a second wiring through hole 113b . Each frame unit can be configured around the plurality of first bridges 121 and the plurality of second bridges 122 .

According to the design, the first bridging part 121 , the second bridging part 122 and/or the first passive component 150 can be respectively disposed in the first through part 110H1 , the second through part 110H2 and the third through part 110H3 of the frame 110 . For example, the first bridging elements 121 can be respectively configured in the first through portions 110H1 . However, the present disclosure is not limited thereto, and a plurality of first bridging elements 121 may be configured together in one first through portion 110H1 . The same is true for the second through portion 110H2 and the second bridge piece 122 . The second bridging element 122 can replace the first bridging element 121 and be disposed in the first through portion 110H1 . The first bridging element 121 can replace the second bridging element 122 disposed in the second through portion 110H2 . The first passive components 150 can be respectively disposed in the third through portion 110H3 , or the plurality of first passive components 150 can be arranged in the third through portion 110H3 . The first bridge member 121, the second bridge member 122 and the first passive component 150 can be respectively disposed in the first through portion 110H1, the second through portion 110H2 and the third through portion 110H3, and can be continuously surrounded by the inner wall of the frame 110 , but not limited to. For example, the frame 110 itself may comprise a plurality of unit frames, and in this case, the frame 110 may be discontinuously surrounded.

The frame 110 may include: a first insulating layer 111a in contact with the first side of the connection structure 140; a first wiring layer 112a in contact with the first side of the connection structure 140 and embedded in the first insulating layer 111a; a second wiring layer 112a in contact with the first side of the connection structure 140; Layer 112b, configured in and embedded in On the side opposite to the side with the first wiring layer 112a; the second insulating layer 111b is disposed on the first insulating layer 111a and covers at least part of the second wiring layer 112b; and the third wiring layer 112c is disposed on the On the side opposite to the side in which the second wiring layer 112b is embedded. Respectively, the first wiring layer 112a and the second wiring layer 112b can be electrically connected through the first wiring via hole 113a penetrating through the first insulating layer 111a, while the second wiring layer 112b and the third wiring layer 112c can be electrically connected through the through hole 113a. The second wiring of the second insulating layer 111b is electrically connected through the hole 113b. The first wiring layer 112 a , the second wiring layer 112 b and the third wiring layer 112 c can be electrically connected to the first bridge 121 and the second bridge 122 through the redistribution layer 142 and the connection via 143 of the connection structure 140 .

Materials of the first insulating layer 111 a and the second insulating layer 111 b are not particularly limited, and for example, insulating materials may be used as materials of the first insulating layer and the second insulating layer. In this case, the insulating material may be thermosetting resins such as epoxy resins; thermoplastic resins such as polyimide resins; resins in which thermosetting resins and thermoplastic resins are mixed with inorganic fillers. Ajinomoto build-up film (ABF) and the like are used as insulating materials. Alternatively, a resin in which a thermosetting resin or a thermoplastic resin is impregnated into a core material such as glass fiber (or glass cloth, or glass cloth) together with an inorganic filler (for example, a prepreg, etc.) may also be used as the insulating material.

The first wiring layer 112 a , the second wiring layer 112 b and the third wiring layer 112 c together with the first wiring via hole 113 a and the second wiring via hole 113 b provide a vertical electrical connection path of the bridge embedded interposer 100A. The formation material of the first wiring layer 112a, the second wiring layer 112b and the third wiring layer 112c can be a metal material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or alloys thereof. The first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c may perform various functions depending on the design of the corresponding layers. For example, the first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c may include ground (GND) patterns, power supply (PWR) patterns, signal (S) patterns, and the like. Here, the signal (S) pattern may include various signals other than a ground (GND) pattern, a power (PWR) pattern, etc., such as a data signal, and the like. The ground (GND) pattern and the power (PWR) pattern may be the same pattern. In addition, the first wiring layer 112 a , the second wiring layer 112 b and the third wiring layer 112 c may respectively include various types of via pads and the like.

The thickness of each of the first wiring layer 112 a , the second wiring layer 112 b and the third wiring layer 112 c may be thicker than that of each rewiring layer 142 . Specifically, since the frame 110 selects the material of the first insulating layer 111a and the second insulating layer 111b as a prepreg or the like to maintain rigidity, the first wiring layer 112a, the second wiring layer 112b and the third wiring layer formed on it The thickness of the wiring layer 112c may be relatively thick. On the other hand, the connection structure 140 may need to have a precise circuit and a high-density design. Therefore, since a photosensitive insulating material (PID) or the like is used as a material of the insulating layer 141 , the thickness of the redistribution layer 142 formed thereon may be relatively thin.

The first wiring layer 112a may be recessed inside the first insulating layer 111a. In this case, the first wiring layer 112a may be recessed inside the first insulating layer 111a such that the first surface of the first insulating layer 111a in contact with the first side of the connection structure 140 and the first side of the connection structure 140 The surface of the contacted first wiring layer 112a may have a mesa order. Therefore, when the frame 110 and the first bridges 121 and the second bridges 122 are covered by the encapsulation 130, the formation material of the first wiring layer 112a of the frame 110 can be prevented from being polluted due to the seepage of the formation material of the encapsulation 130. .

The first wiring via hole 113a and the second wiring via hole 113b can electrically connect the first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c formed on different layers to each other, thereby forming an electrical connection in the frame 110. sexual access. The forming material of the first wiring through hole 113a and the second wiring through hole 113b can be a metal material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni ), lead (Pb), titanium (Ti) or their alloys. The first wiring via hole 113 a and the second wiring via hole 113 b may include a signal via hole, a power supply via hole, a ground via hole, and the like. The power via and the ground via may be the same via. The first wiring via hole 113 a and the second wiring via hole 113 b may be a filling type via hole filled with a metal material, or a conformal-type via hole in which a metal material is formed along a wall surface of a via hole, respectively. In addition, the first wiring via hole 113a and the second wiring via hole 113b may have a tapered shape, respectively.

Some pads of the first wiring layer 112a may serve as termination elements when forming the holes of the first wiring via 113a. In this regard, since the first wiring via hole 113a has a tapered shape in which the width of the upper surface is smaller than that of the lower surface, it may be advantageous in the manufacturing process. In this case, the first wiring via hole 113a may be integrated with the pad pattern of the second wiring layer 112b. In addition, some pads of the second wiring layer 112b may serve as termination elements when forming the hole of the second wiring via hole 113b. In this regard, since the second wiring via hole 113b has a tapered shape in which the width of the upper surface is smaller than that of the lower surface, it may be advantageous in the manufacturing process. In this case, the second wiring The via hole 113b may be integrated with the pad pattern of the third wiring layer 112c.

The first bridge member 121 and the second bridge member 122 may include precision circuit wires for electrically interconnecting the first connection pads 221P and the second connection pads 222P of the first semiconductor chip 221 and the second semiconductor chip 222 respectively. For this, as shown in FIGS. 7 and 8 , the first bridge 121 and the second bridge 122 may be configured such that at least a portion thereof overlaps the first semiconductor wafer 221 and the second semiconductor wafer 222 , respectively. Since the first bridge 121 and the second bridge 122 include precise circuit wiring, the circuits (not shown) in the first bridge 121 and the second bridge 122 can be compared with the redistribution layer 142 of the connection structure 140. Thin. In addition, circuits (not shown in the figure) may be vertically electrically connected via via holes (not shown in the figure) having a pitch smaller than that between the connection via holes 143 of the connection structure 140 . The first bridge 121 and the second bridge 122 can be Si interconnect bridges, glass interconnect bridges, ceramic interconnect bridges or organic interconnect bridges, but not limited thereto. Different from the first bridge 121 , the second bridge 122 may additionally have a design for vertical electrical connection therein. For example, compared with the first bridge 121 , when the second bridge 122 is a silicon interconnection bridge, through-silicon vias (TSVs) can be further formed.

The encapsulation body 130 may cover at least part of the frame 110 and each of the first bridge 121 and the second bridge 122 . In addition, the encapsulation body 130 may fill at least part of each of the first through portion 110H1 , the second through portion 110H2 , and the third through portion 110H3 . The encapsulation body 130 may include an insulating material. In this case, the insulating material may be a non-photosensitive insulating material, more specifically, a non-photosensitive material including inorganic filler and insulating resin. For example, the insulating material may be: thermoset Resins such as epoxy resins; thermoplastic resins such as polyimide resins; or resins containing reinforcing materials such as inorganic fillers in thermosetting resins or thermoplastic resins, in detail, non-photosensitive insulating materials such as Ajinomoto Component film (ABF) and epoxy molding compound (epoxy molding compound, EMC). If necessary, a material in which an insulating resin such as a thermosetting resin or a thermoplastic resin is impregnated into glass fiber or the like together with an organic filler, such as a prepreg or the like, may be used. In this way, void and waviness problems can be improved and warpage control can be more easily performed.

The connection structure 140 may redistribute the first connection pads 221P and the second connection pads 222P of each of the first semiconductor die 221 and the second semiconductor die 222 . In addition, the first connection pad 221P and the second connection pad 222P of each of the first semiconductor chip 221 and the second semiconductor chip 222 can be electrically connected to the first bridge member 121 and/or the second bridge member 122 according to the configuration. . The connection structure 140 may include: an insulation layer 141 ; a redistribution layer 142 disposed on the insulation layer 141 ; and a connection via 143 penetrating through the insulation layer 141 and connected to the redistribution layer 142 . The connection vias 143 can electrically connect the redistribution layers 142 disposed on different layers to each other. In addition, the connection structure 140 can electrically connect the redistribution layer 142 to the first bridge 121 and/or the second bridge 122 or the first wiring layer 112 a , the second wiring layer 112 b and the third wiring layer 112 c of the frame 110 . The insulating layer 141 , the redistribution layer 142 and the connection via 143 of the connection structure 140 may be larger or smaller than those shown in the drawing, respectively.

The material of the insulating layer 141 may be an insulating material. In this case, a photosensitive insulating material (PID) may be used as the insulating material. In this case, the precision pitch can be introduced through the photo via, which is very important for precision circuit and high density design is advantageous. When the insulating layer 141 has multiple layers, the boundaries may be separated from each other, and the boundaries between the multiple layers may also be indistinct.

The redistribution layer 142 may perform substantial redistribution functions. The material of the redistribution layer 142 can also be a metal material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium ( Ti) or its alloys. The redistribution layer 142 can also perform various functions depending on the design. The ground (CND) pattern and the power (PWR) pattern may be the same pattern. In addition, the redistribution layer 142 may include various types of via pads, electrical connection metal pads, and the like.

The connection vias 143 can electrically connect the redistribution layers 142 formed on different layers to each other. In addition, the connection vias 143 can electrically connect the redistribution layer 142 to the first bridge 121 and/or the second bridge 122 or the first wiring layer 112a, the second wiring layer 112b and the third wiring layer 112c of the frame 110 . The connecting vias 143 may include signal vias, power vias, ground vias, etc., and the power vias and the ground vias may be the same vias. The connection vias 143 may also be filled vias filled with a metal material, or conformal vias in which a metal material is formed along the wall surface of the via hole, respectively. In addition, the connection via hole 143 may have a tapered shape opposite to that of the first wiring via hole 113a and the second wiring via hole 113b.

The first passive component 150 and the second passive component 160 can be inductors (for example, high-frequency inductors, ferrite inductors, power inductors, etc.) independently, capacitors, etc. (for example, LTCC and MLCC), As well as ferrite beads, EMI filters, etc. The first passive component 150 can be disposed in the third through portion 110H3 , and the second passive component 160 can be disposed in the frame 110 . Dimensions of the first passive component 150 It may be larger than the size of the second passive component 160 . For example, the first passive component 150 may be thicker than the second passive component 160 and may have a larger installation area.

A backside wiring layer 132 may be introduced for backside wiring design. The material of the backside wiring layer 132 can also be a metal material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or its alloys. The backside wiring layer 132 can also perform various functions depending on the design. For example, the backside wiring layer 132 may include ground (GND) pattern pads, power supply (PWR) pattern pads, signal (S) pattern pads, and the like. The ground (GND) pattern pad and the power (PWR) pattern pad may have the same pattern. If desired, the backside wiring layer 132 can be evenly distributed on the entire area of the lower surface of the encapsulation body 130 . When at least a portion of the backside wiring layer 132 is configured to overlap the first bridge 121 and/or the second bridge 122, the heat generated from the first bridge 121 and/or the second bridge 122 can be more easily passed through. The first electrical connection bump 180 and the like are discharged.

The backside via hole 133 can provide an electrical connection path between the first wiring layer 112 a , the second wiring layer 112 b , the third wiring layer 112 c and the backside wiring layer 132 . The forming material can be a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloy. The backside via hole 133 may be a filling type via hole filled with a metal material, or a conformal type via hole in which a metal material is formed along a wall surface of the via hole. In addition, the backside via hole 133 may have the same tapered shape as the first wiring via hole 113a and the second wiring via hole 113b. The backside vias 133 may also include signal vias, ground vias, power vias, etc., and the power vias and the ground vias may be the same vias.

With additional configuration, the passivation layer 170 can protect the backside wiring layer from external physical or chemical damage. The passivation layer 170 may include a thermosetting resin. For example, the passivation layer 170 can be a film made of Ajinomoto, but it is not limited thereto. The passivation layer 170 may have an opening to expose at least a portion of the backside wiring layer 132 . The number of openings can be tens to thousands, and can be set to a greater or lesser number. Each opening may consist of a plurality of holes. If necessary, a surface mount component (not shown), such as a land side capacitor (LSC), may be disposed on the lower surface of the passivation layer 170 .

The first electrical connection bump 180 can physically and/or electrically connect the bridge embedded interposer 100A to the printed circuit board 300 . The first electrical connection bumps 180 can be disposed on the opening of the passivation layer 170 and can be electrically connected to the backside wiring layer 132 respectively. The first electrical connection bumps 180 may be respectively formed of low melting point metals such as tin (Sn) or an alloy containing tin (Sn). More specifically, the first electrical connection bump 180 may be formed by solder or the like. However, this is only for illustration, and the material of the first electrical connection bump 180 is not particularly limited thereto. The first electrical connection bump 180 can be a land, a ball, or a pin. The first electrical connection bump 180 may be formed of multiple layers or a single layer. When the first electrical connection bump includes multiple layers, the first electrical connection bump 180 may include copper pillars and solder. When the first electrical connection bump 180 includes a single layer, the first electrical connection bump 180 may include tin-silver solder or copper, but this is for illustration only, and the disclosure is not limited thereto. The quantity, spacing, and configuration of the first electrical connection bumps 180 are not particularly limited, but can be fully modified according to design specifications.

The package substrate 400A according to the example may include the printed circuit board 300 and the bridge embedded interposer 100A mounted on the printed circuit board 300 according to the above example. According to an example, the third passive component 310 may be mounted on the printed circuit board 300 around the bridge-embedded interposer 100A as necessary. Passive components (not shown in the figure) can also be embedded in the printed circuit board 300 . The printed circuit board 300 can be mounted on the main board of the electronic device or the like via the second electrical connection bumps 320 (eg, solder balls, etc.). That is, the printed circuit board 300 may be a BGA substrate as described above, but not limited thereto.

According to an example, in the semiconductor package 500A according to an example, the first semiconductor wafer 221 and the plurality of second semiconductor wafers 222 may be arranged parallel to each other on the second side of the bridge-buried interposer 100A. The plurality of first connection pads 221P of the first semiconductor chip 221 and the plurality of second connection pads 222P of each of the plurality of second semiconductor chips 222 can be electrically connected to the bridge according to the example according to their functions. One or more redistribution layers 142 of the connection structure 140 of the interposer 100A are buried. Specifically, the plurality of first connection pads 221P of the first semiconductor chip 221 can be respectively electrically connected to one or more protruding contacts of the redistribution layer 142 via the plurality of first electrical connection metals 221B. pad. Similarly, the plurality of second connection pads 222P of each of the plurality of second semiconductor chips 222 can be electrically connected to one or more via the plurality of second electrical connection metals 222B respectively. Protruding pads of the redistribution layer 142 . Therefore, the connection pads can also be electrically connected to the plurality of first bridges 121 and the plurality of second bridges 122 via one or more redistribution layers 142 . The first electrical connection metal 221B and the second electrical connection metal 222B can be respectively formed of low melting point metals such as tin (Sn) or an alloy containing tin (Sn). More specifically, the first The electrical connection metal 221B and the second electrical connection metal 222B can be formed by solder or the like, but not limited thereto.

The first semiconductor chip 221 may be an integrated circuit (IC) with hundreds to millions or more components integrated into a single chip. In this case, the base material of the body can be silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. Various circuits can be formed on the body. The first connection pads 221P of the first semiconductor chip 221 can electrically connect the first semiconductor chip 221 to other components. The material of the first connection pad 221P may be a metal material such as copper (Cu), aluminum (Al), and the metal material may be used without any particular limitation. A passivation layer (not shown in the figure) exposing the first connection pad 221P can be formed on the body, and the passivation layer (not shown in the figure) can be an oxide layer, a nitride layer, etc., or an oxide layer and a nitride layer. A double layer of layers.

The second semiconductor chip 222 may be an integrated circuit (IC) provided with hundreds to millions of components integrated into a single chip. If necessary, the second semiconductor wafer 222 may have the form of a stacked integrated circuit (IC). Stacked circuits (ICs) can also be electrically connected to other components through through-silicon vias (TSVs). The second semiconductor chip 222 can also have a second connection pad 222P for electrically connecting the second semiconductor chip 222 to other components, and in this case, the second connection pad 222P can be configured on the second semiconductor chip 222. On the lowermost side facing the bridge-embedded intermediary 100A.

The first semiconductor chip 221 may be an Application Specific Integrated Circuit (ASIC). Alternatively, the first semiconductor chip 221 may be a Field Programmable Gate Array (field programmable gate array, FPGA). Alternatively, the first semiconductor chip 221 may be a chip set composed of Application Specific Integrated Circuits (ASIC) and Field Programmable Gate Array (FPGA). Alternatively, the first semiconductor chip 221 may be a graphics processing unit (GPU). Alternatively, the first semiconductor chip 221 may be a chip set composed of Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) and Graphics Processing Units (GPUs). In addition, the second semiconductor chip 222 can be a stacked memory, such as a high bandwidth memory (HBM). That is, the first semiconductor chip 221 and the second semiconductor chip 222 may be expensive chips with tens to millions of I/Os or more, but not limited thereto. The second semiconductor wafers 222 may be arranged in a larger number than the first semiconductor wafers 221 and may be arranged around the first semiconductor wafers 221 . For example, as shown in FIG. 7 , two second semiconductor chips 222 may be disposed on both sides of the first semiconductor chip 221 , but it is not limited thereto.

Meanwhile, in the semiconductor package 500A according to the example, the underfill resin 210 covering at least part of the underside of each of the first semiconductor wafer 221 and the plurality of semiconductor wafers 222 may be further configured in the bridge according to the example. On the second side of the embedded interposer 100A. The underfill resin 210 may fill a space between each of the first semiconductor wafer 221 and the second semiconductor wafer 222 and the second side of the bridge-buried interposer 100A according to the example. In addition, the underfill resin 210 can cover a plurality of first electrical connection metals 221B and a plurality of second electrical connection metals 222B. The first semiconductor chip 221 and the plurality of second semiconductor chips 222 may be fixed by the underfill resin 210 . In addition, if necessary, on the second side of the bridge-embedded interposer 100A according to the example, further configurations covering the first semiconductor wafer 221 and At least part of the molding material (not shown in the figure) of each of the plurality of second semiconductor wafers 222, and if necessary, the molding material (not shown in the figure) may be exposed due to grinding. A surface of each of a semiconductor wafer 221 and the plurality of second semiconductor wafers 222 .

FIG. 9 is a schematic plan view showing a modified example of the top view shown in FIG. 7 .

FIG. 10 is a cut plan view showing a modified example of the cut plan view shown in FIG. 8 .

Referring to FIGS. 9 and 10 , a semiconductor package as a modified example may be one in which a plurality of bridge-embedded interposers 100A1, bridge-embedded interposers 100A2, and bridge-embedded interposers 100A3 are independently arranged on a printed circuit board 300, respectively. on the semiconductor package. For example, the first bridging member embedded intermediary 100A1 may include the first bridging member 121 or the second bridging member 122 disposed in the penetrating portion 110H, and may provide the 1-1 Electrical connection between the semiconductor chip 221a and 2-1 semiconductor chip 222a. Similarly, the second bridge embedded interposer 100A2 can provide an electrical connection between the 1-2 semiconductor chip 221b and the 2-2 semiconductor chip 222b. Similarly, the third bridge embedded interposer 100A3 can provide an electrical connection between the 1-3 semiconductor chip 221c and the 2-3 semiconductor chip 222c. Each of the semiconductor wafer 221a, the semiconductor wafer 222a, the semiconductor wafer 221b, the semiconductor wafer 222b, the semiconductor wafer 221c, and the semiconductor wafer 222c may be different from each other. That is, various designs can be performed by the plurality of bridge-embedded intermediaries 100A1 , bridge-embedded intermediaries 100A2 , and bridge-embedded intermediaries 100A3 . Other descriptions are substantially the same as those described above, and will not be repeated here.

FIG. 11 is a schematic cross-sectional view showing an example of a first bridge member of the semiconductor package shown in FIG. 6 .

Referring to FIG. 11, the first bridge member 121 according to the example may include: a base layer 120a; an insulating layer 120b disposed on the base layer 120a; a circuit layer 120c disposed on the insulating layer 120b; and a pad layer 120d disposed on the insulating layer 120b. on the upper side of layer 120b. The base layer 120a can control warpage, and thus can include silicon (Si), glass, ceramics, and the like. The insulating layer 120b may include an insulating material. The circuit layer 120c and the pad layer 120d may include metal materials. The circuit layer 120c may include a wiring portion and a via portion. The pad layer 120d can be connected to the connection via hole 143 of the connection structure 140 . That is, according to the example, the first bridge 121 may be a silicon interconnect bridge, a glass interconnect bridge, or a ceramic interconnect bridge or the like.

FIG. 12 is a schematic cross-sectional view showing an example of a second bridge member of the semiconductor package shown in FIG. 6 .

12, according to the first bridge member 121 of the above example, the second bridge member 122 according to the example may further include: a through hole 120e penetrating through the base layer 120a; and a pad layer 120f configured in the second bridge member 122 on the underside of the base layer 120a. The through hole 120e and the pad layer 120f may also include metal materials. The pad layer 120f may be connected to the backside via. That is, the second bridge 122 according to the example may have the pad layers 120d and 120f on the upper and lower sides thereof, and the second bridge 122 may be a silicon interconnection bridge electrically connected to each other through the through hole 120e or the like. parts, glass interconnection bridges or ceramic interconnection bridges, etc.

FIG. 13 is a diagram illustrating a first bridge member and/or a first bridge member of the semiconductor package shown in FIG. A schematic cross-sectional view of another example of the two bridges.

13, according to another example, the first bridge member 121 and/or the second bridge member 122 may include: one or more insulating layers 120g; a pattern layer 120h, respectively configured on one or more insulating layers 120g; or a plurality of insulating layers 120g; and one or more via layers 120i, respectively penetrating through one or more insulating layers 120g and electrically connecting the pattern layers 120h disposed on different levels. The pattern layer 120h and the via layer 120i can be used as a circuit layer. The uppermost and lowermost pattern layers 120h can be used as pad layers, and can be connected to the connection vias 143 and the backside vias 133, respectively. That is, the first bridge 121 and/or the second bridge 122 according to another example may be an organic interconnection bridge.

14 to 17 are schematic process diagrams showing a manufacturing example of the semiconductor package shown in FIG. 6 .

Referring to FIG. 14 , the frame 110 having the first penetrating portion 110H1 , the second penetrating portion 110H2 , and the third penetrating portion 110H3 is prepared. The specific configuration of the frame 110 is as described above. Next, the first bridging part 121 , the second bridging part 122 and the first passive component 150 are respectively arranged on the first through part 110H1 , the second through part 110H2 and the third through part 110H3 by using the adhesive tape 195 . The first bridge 121 and the second bridge 122 can be configured by selecting only good products. Next, the frame 110 , the first bridging element 121 , the second bridging element 122 and the first passive component 150 are encapsulated by the encapsulating body 130 .

Referring to FIG. 15 , next, the tape 195 is removed, and the insulating layer 141 is disposed in the area where the tape 195 is removed. In addition, openings are formed in the insulating layer 141 using lithography. Next, the redistribution layer 142 and the connection via hole 143 are formed by a plating process. Next, if necessary, further form an insulating layer 141, a redistribution layer 142, and connection via holes. 143 to form the connecting structure 140.

Referring to FIG. 16 , next, openings are formed in the encapsulation 130 in desired locations using mechanical drilling and/or laser drilling. Next, the backside wiring layer 132 and the backside via hole 133 are formed by a plating process. Next, a passivation layer 170 is formed, an opening is formed at a desired position of the passivation layer 170 , and then a first electrical connection bump 180 is formed using a low melting point metal or the like. The bridge-embedded interposer 100A according to the above example can be manufactured through a series of processes. A series of processes can be performed at the panel level with a large area size, and each bridge-embedded interposer 100A can be obtained through a singulation process.

Referring to FIG. 17 , next, the manufactured bridge embedded interposer 100A is mounted on the printed circuit board 300 . Specifically, only good bridge-embedded interposers 100A are selected and mounted on the more expensive printed circuit board 300 . The third passive component 310 may be configured on the printed circuit board 300 as required. The printed circuit board 300 may be a ball grid array substrate having the second electrical connection bumps 320 , but is not limited thereto. The packaging substrate 400A according to the above example can be manufactured through a series of processes. Next, after selecting a good packaging substrate 400A, use the first electrical connection metal 221B and the second electrical connection metal 222B to mount the more expensive first semiconductor chip 221 and the second semiconductor chip 222 on the bridge of the good packaging substrate 400A The interposer 100A is embedded and fixed with an underfill resin 210 . Accordingly, the semiconductor package 500A according to the above-described example can be manufactured. Meanwhile, the semiconductor package 500A according to the example may have a form in which the printed circuit board 300 is omitted, as necessary.

FIG. 18 is a schematic cross-sectional view showing another example of a semiconductor package.

Referring to FIG. 18 , a semiconductor package 500B according to another example may have a bridge embedded interposer 100B of a package substrate 400B in a different form. Specifically, in the bridging-embedded intermediary 100B according to another example, the frame 110 may include: an insulating layer 111; a first wiring layer 112a disposed on one surface of the insulating layer 111; a second wiring layer 112b, It is disposed on the other surface of the insulating layer 111 ; and a wiring through hole 113 penetrates through the insulating layer and electrically connects the first wiring layer 112 a and the second wiring layer 112 b. That is, the frame 110 may have a more simplified form. Meanwhile, although only the first bridging member 121 is shown in another example, there is no doubt that the second bridging member 122 can be used instead of the first bridging member 121 . Other descriptions are substantially the same as those described above, and will not be repeated here.

FIG. 19 is a schematic cross-sectional view showing another example of a semiconductor package.

Referring to FIG. 19 , a semiconductor package 500C according to another example may have a bridge embedded interposer 100C of a package substrate 400C in a different form. Specifically, the second passive component 160 replaces the first passive component 150 and is configured in the bridge-embedded intermediary 100C according to another example or in the bridge-embedded intermediary 100B according to the above-mentioned another example. The second passive component 160 is embedded in the frame 110 . Other descriptions are substantially the same as those described above, and will not be repeated here.

FIG. 20 is a schematic cross-sectional view showing another example of a semiconductor package.

Referring to FIG. 20 , a semiconductor package 500D according to another example may have a bridge embedded interposer 100D of a package substrate 400D in a different form. Specifically, in the bridge embedded intermediary 100D according to another example, the third penetrating portion 110H3 is omitted in the frame 110 . In addition, the first wiring layer 112a, the second The wiring design of the wiring layer 112 b and the third wiring layer 112 c as well as the first wiring through hole 113 a and the second wiring through hole 113 b replaces the configuration of the first passive component 150 and the second passive component 160 . Other descriptions are substantially the same as those described above, and will not be repeated here.

FIG. 21 is a schematic cross-sectional view showing another example of a semiconductor package.

Referring to FIG. 21 , a semiconductor package 500E according to another example may have a bridge embedded interposer 100E of a package substrate 400E in a different form. Specifically, the bridge embedded intermediary 100E according to another example is mainly designed for the second bridge 122 so as to significantly reduce the vertical electrical connection path. Other descriptions are substantially the same as those described above, and will not be repeated here.

FIG. 22 is a schematic cross-sectional view showing another example of a semiconductor package.

Referring to FIG. 22 , a semiconductor package 500F according to another example may have a bridge embedded interposer 100F of a package substrate 400F in a different form. Specifically, in the bridge-embedded interposer 100F according to another example, the backside wiring layer 132 , the backside via hole 133 , and the passivation layer 170 are omitted for further thinning. Other descriptions are substantially the same as those described above, and will not be repeated here.

As described above, according to the exemplary embodiments of the present disclosure, there can be provided an interposer, a packaging substrate including the same, and a semiconductor package, the interposer, the packaging substrate and the semiconductor package including the same can reduce the process difficulty and improve the process efficiency and yield, solve warpage problems, supplement and improve power characteristics, reduce size, and also manufacture in large size.

In this article, for the convenience of explanation, for example, "over...", "on Spatially relative terms such as "square", "under" and "beneath" are used to describe the relationship of one element to another one or more other elements shown in the drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "on" or "over" other elements would then be oriented "below" or "beneath" the other elements or features. Thus, the term "over" can encompass both an orientation of above and below, depending on the particular orientation in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Throughout this specification, it should be understood that when an element (eg, layer, region, or wafer (substrate)) is referred to as being "on," "connected to," or "coupled to" another element, the An element may be directly on, directly "connected to," or directly "coupled to" the other element or there may be other intervening elements therebetween. In contrast, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element, there may be no intervening elements or layers present. Like numbers refer to like elements throughout. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Hereinafter, embodiments of the inventive concept will be described with reference to schematic diagrams illustrating embodiments of the inventive concept. In the drawings, modifications to the shapes shown may be expected, for example, as a result of manufacturing techniques and/or tolerances. Thus, embodiments of the inventive concept should not be construed as limited to the particular shaped regions illustrated herein but are to include, for example, variations in shapes that result in manufacturing. The following embodiments can also be formed independently, in combination or in part Subgroup composition.

The terminology used herein is for describing particular embodiments only and the inventive concepts are not limited thereto. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the term "comprises and/or comprising" when used in this specification specifies the existence of stated features, integers, steps, operations, components, elements and/or groups thereof, But it does not exclude the existence or addition of one or more other features, integers, steps, operations, components, elements and/or groups thereof.

While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the invention as defined by the appended claims .

100A: Embedded intermediary in the bridging piece

110: frame

110H1: The first penetration

110H2: Second penetration

110H3: The third penetration

111a: first insulating layer

111b: second insulating layer

112a: wiring layer/first wiring layer

112b: wiring layer/second wiring layer

112c: wiring layer/third wiring layer

113a: first wiring through hole

113b: second wiring through hole

121: The first bridge piece

122: The second bridge piece

130: Encapsulation

132: Back side wiring layer

133: Back side through hole

140: Connection structure

141: insulation layer

142:Rewiring layer

143: Connection through hole

150: The first passive component

160: Second passive component

170: passivation layer

180: the first electrical connection bump

210: Underfill resin

221: The first semiconductor wafer

221B: The first electrical connection metal

221P: first connection pad

222: second semiconductor wafer

222B: the second electrical connection metal

222P: Second connection pad

300: printed circuit board

310: The third passive component

320: the second electrical connection bump

400A: package substrate

500A: Semiconductor package

I-I': section line

Claims (20)

A bridge embedded intermediary, comprising: a connection structure including one or more insulating layers and one or more redistribution layers disposed on or in the one or more insulating layers The first bridge is configured on the connection structure and includes one or more first circuit layers electrically connected to the one or more redistribution layers; the frame is configured around the first bridge On the connection structure, including one or more wiring layers electrically connected to the one or more redistribution layers; and an encapsulation body, configured on the connection structure, and covering the first bridge member and at least a portion of each of the frames, wherein one insulating layer of the one or more insulating layers of the connection structure extends continuously to contact the frame and the first bridge. The bridge-embedded intermediary described in item 1 of the scope of the patent application, wherein the frame has a first through portion, the first bridge is disposed in the first through portion, and the encapsulation body is filled At least part of the first through portion. The bridging part embedded intermediary as described in item 2 of the scope of the patent application further includes: a second bridging part, arranged on the connection structure in parallel with the first bridging part, and electrically connected to the One or more second circuit layers of one or more redistribution layers, and wherein the encapsulation body covers at least part of the second bridge member. The embedded intermediary of the bridging member as described in item 3 of the scope of the patent application, wherein The frame further has a second penetrating portion spaced apart from the first penetrating portion, the second bridging member is disposed in the second penetrating portion, and the enclosing body fills the second penetrating portion At least partially. The bridge-embedded intermediary described in item 2 of the scope of the patent application further includes: a first passive component disposed on the connection structure in parallel with the first bridge and electrically connected to the one or a plurality of redistribution layers, and wherein the encapsulation body covers at least part of the first passive component. The bridge-embedded intermediary as described in item 5 of the scope of the patent application, wherein the frame further has a third penetration portion spaced apart from the first penetration portion, and the first passive component is disposed on the third penetration portion. the through portion, and the encapsulation fills at least part of the third through portion. The intermediary embedded in the bridging member as described in item 1 of the patent claims further includes: a second passive component embedded in the frame and electrically connected to the one or more redistribution layers. The bridge-embedded intermediary described in item 1 of the patent scope of the application, wherein the encapsulation body has a plurality of openings, and the plurality of openings respectively expose the lowermost wiring layer among the one or more wiring layers At least part of the package, and a plurality of electrical connection bumps are respectively disposed on the plurality of openings of the encapsulation body, and are electrically connected to the exposed lowermost wiring layer. The bridge member embedded intermediary described in item 1 of the scope of the patent application further includes: a backside wiring layer arranged on the lower side of the encapsulation body; a plurality of first backside through holes respectively penetrating through the encapsulation body, and respectively the back a side wiring layer electrically connected to a lowermost wiring layer of the one or more wiring layers; a passivation layer disposed on the lower side of the encapsulation to cover at least part of the backside wiring layer, And the passivation layer has a plurality of openings respectively exposing at least part of the backside wiring layer; and a plurality of electrical connection bumps, arranged on the plurality of openings of the passivation layer, and electrically connected to the exposed backside wiring layer. The intermediary embedded in the bridging member as described in item 9 of the patent scope of the application, wherein the first bridging member includes: a base layer; an insulating layer disposed on the base layer; a first circuit layer disposed on the insulating layer; and a first pad layer disposed on the upper side of the insulating layer and electrically connected to the first circuit layer. The intermediary embedded in the bridging member as described in item 10 of the scope of the patent application, wherein the first bridging member further includes: a second pad layer disposed on the underside of the base layer; and a through hole penetrating through the base layer The base layer is electrically connected to the second pad layer to the first circuit layer. The intermediary embedded in the bridging member as described in item 11 of the scope of the patent application further includes: a plurality of second backside through holes respectively penetrating through the encapsulation body and electrically connecting the backside wiring layers to the the second pad layer. The bridging member embedded intermediary as described in item 9 of the patent scope of the application, wherein the first bridging member includes: a plurality of insulating layers; a plurality of pattern layers, arranged on the plurality of insulating layers or on the plurality of In the insulating layer; and a plurality of via layers, which respectively penetrate through the plurality of insulating layers and electrically connect the plurality of pattern layers located on different levels, and The first circuit layer includes at least part of the plurality of pattern layers and at least part of the plurality of via layers. The bridge member embedded intermediary described in item 13 of the scope of the patent application further includes: a plurality of second backside through holes respectively penetrating through the encapsulation body and electrically connecting the backside wiring layers to the The lowest wiring layer of the plurality of pattern layers. The bridge member embedded intermediary described in item 1 of the scope of the patent application further includes: a back side wiring layer disposed on the lower side of the encapsulation body; and a back side through hole penetrating the encapsulation body, and electrically connect the backside wiring layer to the lowermost wiring layer of the one or more wiring layers, wherein the connection structure includes a connection via, and the connection via connects the one or more repeated The lowest redistribution layer of the wiring layers is electrically connected to the uppermost wiring layer of the one or more wiring layers, and the connection vias and the backside vias taper gradually in opposite directions. A packaging substrate, comprising: a printed circuit board; and a bridge embedded intermediary disposed on the printed circuit board, wherein the bridge embedded intermediary includes: a connection structure, including one or more insulating layers and a configuration One or more redistribution layers on the one or more insulating layers or in the one or more insulating layers; bridges, configured on the connection structure and including electrically connected to the one or more One or more circuit layers of a redistribution layer; a frame, disposed on the connection structure around the bridge, and including an electrical connection to the one one or more wiring layers of one or more redistribution layers; and an encapsulation body configured on the connection structure and covering at least part of each of the bridge member and the frame, wherein the one or a plurality of circuit layers are electrically connected to the printed circuit board through the one or more redistribution layers and the one or more wiring layers, wherein the number of the one or more circuit layers of the bridge different from the number of the one or more wiring layers of the frame, and one insulating layer of the one or more insulating layers of the connection structure extends continuously to contact the frame and the bridge member . A semiconductor package, comprising: a bridge embedded interposer, having: a connection structure, having a first side and a second side opposite to the first side, and including one or more insulating layers and disposed on the one or One or more redistribution layers on a plurality of insulating layers or in the one or more insulating layers; bridges, configured on the first side of the connection structure, and including electrically connected to the one One or more circuit layers of one or more redistribution layers; a frame, disposed on the first side of the connection structure around the bridge, and including electrically connected to the one or more redistribution layers one or more wiring layers; and an encapsulation disposed on the first side of the connection structure and covering at least part of each of the bridge and the frame, the first semiconductor wafer , configured on the second side of the connection structure, and having a plurality of first connection pads electrically connected to the one or more redistribution layers; and a second semiconductor chip, configured on the connection structure and having a plurality of second connection pads electrically connected to the one or more redistribution layers, Wherein at least part of the plurality of first connection pads and at least part of the plurality of second connection pads are electrically connected to each other via the one or more circuit layers, wherein the one or more of the bridge members The number of circuit layers is different from the number of the one or more wiring layers of the frame, and one insulating layer of the one or more insulating layers of the connection structure extends continuously to the frame and the wiring layers. contact with the bridge. The semiconductor package as described in claim 17 of the scope of the patent application further includes: a plurality of first electrical connection metals disposed on the second side of the connection structure, and electrically connecting the plurality of first connection pads connected to the one or more redistribution layers; a plurality of second electrical connection metals, configured on the second side of the connection structure, and electrically connected to the plurality of second connection pads The one or more redistribution layers; and an underfill resin disposed on the second side of the connection structure and covering the plurality of first electrical connection metals and the plurality of second electrical connections At least a portion of each of the metals is connected. The semiconductor package as described in item 17 of the scope of the patent application further includes: a printed circuit board disposed on one of the intermediaries embedded in the bridge member, in which the first semiconductor chip and the second semiconductor chip are disposed. on the opposite side, and wherein the plurality of first connection pads and the plurality of second connection pads are electrically connected to the the printed circuit board. The semiconductor package as described in item 17 of the scope of application, wherein the The first semiconductor chip and the second semiconductor chip partially overlap the bridge member, and one of the plurality of first connection pads and one of the plurality of second connection pads pass through the one The one or more redistribution layers and the one or more circuit layers are electrically connected to each other.

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