TWI792805B - Buck converter and operating method of buck converter, maximum quick response signal generator and operating method of maximum quick response signal generator - Google Patents
Buck converter and operating method of buck converter, maximum quick response signal generator and operating method of maximum quick response signal generator Download PDFInfo
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本發明係關於一種降壓轉換器,特別是指一種具快速響應機制的降壓轉換器及其操作方法。 The present invention relates to a step-down converter, in particular to a step-down converter with a fast response mechanism and an operation method thereof.
在應用於微處理器核心電壓控制的現代電壓調節系統中,多相控制是一種普遍的控制方法,其符合高功率密度及高電流扭轉率(slew rate)的要求。然而,習知的多相控制方法仍不足以應付現代電壓調節器規範中所制訂的超高負載暫態,特別是在負載施加暫態(load application transient)期間的規範要求。因此,一種被稱為快速響應(quick response)的開迴路控制機制(open-loop control mechanism)被發明出來,以克服下衝(undershoot)的問題。在負載施加暫態期間,快速響應機制將會立即開啟所有相的高位側開關,以全力供應重負載電流需求,且輸出電壓下垂(droop)能夠因而受控進入正確的負載線規範(load line specification)。即使如此,快速響應機制仍然有些缺點,例如,不精準的快速響應開啟和關閉可能導致非預期的震盪(ringback)或輸出電壓持續上升造成電路過載。 In modern voltage regulation systems applied to microprocessor core voltage control, multiphase control is a common control method, which meets the requirements of high power density and high current slew rate. However, conventional multiphase control methods are still insufficient to cope with the ultra-high load transients specified in modern voltage regulator specifications, especially during load application transients. Therefore, an open-loop control mechanism called quick response was invented to overcome the undershoot problem. During load application transients, the fast response mechanism will immediately turn on the high-side switches of all phases to fully supply the heavy load current demand, and the output voltage droop can thus be controlled into the correct load line specification ). Even so, the fast-response mechanism still has some disadvantages. For example, inaccurate fast-response turn-on and turn-off may lead to unexpected ringback or circuit overload due to continuous rise of the output voltage.
為了更清楚說明,第9圖示意了先前技術之具有快速響應電路的降壓轉換器900。降壓轉換器900包含複數個對應各相位的脈寬調變訊號產生器
Ton1~TonN,複數個或閘OR1~ORN耦接於對應的脈寬調變訊號產生器Ton1~TonN,複數個功率級PS1~PSN耦接於對應的或閘OR1~ORN,複數個電感L1~LN耦接於對應的功率級PS1~PSN及輸出端OUT之間,輸出電容Co,負載Lo耦接於輸出端OUT及接地端GND之間。快速響應電路910耦接於輸出端OUT及或閘OR1~ORN之間。每一功率級,例如功率級PS1,包含緩衝器903耦接於或閘OR1,反向器904耦接於或閘OR1,第一電晶體901及第二電晶體902。第一電晶體901包含第一端,用以接收輸入電壓Vin,第二端耦接於電感L1,及控制端耦接於緩衝器903。第二電晶體902包含第一端耦接於第一電晶體901的第二端及電感L1,第二端耦接於接地端GND,及控制端耦接於反向器904。快速響應電路910根據輸出電壓Vo產生快速響應訊號QR。各相位的脈寬調變訊號產生器Ton1~TonN根據輸入電壓Vin及輸出電壓Vo輸出脈寬調變產生訊號PM1~PMN。或閘OR1~ORN根據脈寬調變產生訊號PM1~PMN及快速響應訊號QR產生各相位的脈寬調變訊號PWM1~PWMN。脈寬調變訊號PWM1~PWMN推動功率級PS1~PSN提供輸出電壓Vo以及負載電流ILo。
For clarity, FIG. 9 illustrates a prior
第10圖係為第9圖之降壓轉換器的操作訊號時序圖。在時間t1,當負載Lo的電能需求提高,負載電流ILo會上升至高電流,使輸出電壓Vo開始下降至小於閾值(threshold)。此時,快速響應電路910可產生快速響應訊號QR,QR訊號與脈寬調變產生訊號PM1~PMN經過或閘產生脈寬調變訊號PWM1~PWMN,用於推動功率級PS1~PSN提供輸出電壓Vo以及負載電流ILo。詳細而言,快速響應訊號QR的前緣可導通第一電晶體901並截止第二電晶體902,第一電晶體901的第一端提供負載電流ILo至負載Lo。第一電晶體901導通後,電感L1~LN開始充電,總電感電流Isum上升。同時,部分電流流至輸出電容Co使其充電,另一部分流至負載Lo,為提供負載Lo電能。在快速響應訊號QR拉至低準位後,第一電晶體
901截止且第二電晶體902導通,電感L開始放電,總電感電流Isum下降。輸出電容Co開始放電至負載Lo,使負載電流ILo維持在高電流。在時間t2,負載電流ILo降至低電流,使輸出電壓Vo開始上升,而總電感電流Isum持續下降。在時間t3,負載電流ILo再度上升至高電流,使輸出電壓Vo下降至小於閾值(threshold)。此時,快速響應訊號QR再度產生並推動功率級PS1~PSN提供輸出電壓Vo以及負載電流ILo,其餘的運作過程同時間t1。在時間t4,負載電流ILo再降至低電流,輸出電壓V6開始上升,其餘的運作過程同時間t2。在時間t5至t6之間,整個電路運作過程再度重複。然而,時間t3至t6的負載頻率高於時間t1至t2的負載頻率,總電感電流Isum以及輸出電壓Vo在降回原來的準位之前就會再被拉高。總電感電流Isum以及輸出電壓Vo會隨著時間愈來愈被拉高,最後造成電壓過載的情況。
Fig. 10 is a timing diagram of operation signals of the step-down converter in Fig. 9. At time t1, when the power demand of the load Lo increases, the load current I Lo rises to a high current, so that the output voltage Vo begins to drop below the threshold (threshold). At this time, the
一種降壓轉換器,包含快速響應電路、補償器、交錯邏輯電路、複數個脈寬調變訊號產生器、複數個或閘、複數個功率級、複數個電感及輸出電容。補償器耦接於輸出端。交錯邏輯電路耦接於補償器。複數個功率級耦接於對應的複數個或閘。每一脈寬調變訊號產生器分別耦接於交錯邏輯電路、輸出端及輸入端。每一或閘分別耦接於對應的脈寬調變訊號產生器。每一電感耦接於對應的功率級及輸出端之間。輸出電容耦接於輸出端及接地端之間。快速響應電路包含電壓下垂感測器、負載頻率感測器、快速響應訊號產生器、最大快速響應訊號產生器、及閘。電壓下垂感測器耦接於輸出端。負載頻率感測器耦接於輸出端。快速響應訊號產生器耦接於電壓下垂感測器。最大快速響應訊號產生器耦接於電壓下垂感測器、負載頻率感測器輸出端及輸入端。及閘耦接於快速響應訊號產生器、最大快速響應訊號產生器及複數個或閘。電壓下垂感測器用以根據輸出電壓的電壓下垂產生觸發訊號。負載頻率感測器用以根據負載 的頻率輸出負載頻率訊號,快速響應訊號產生器用以根據觸發訊號產生起始快速響應訊號。最大快速響應訊號產生器用以根據輸入電壓、觸發訊號、負載頻率訊號及輸出電壓產生最大快速響應訊號。及閘用以根據起始快速響應訊號及最大快速響應訊號產生快速響應訊號。補償器用以根據輸出電壓及參考電壓產生補償訊號。交錯邏輯電路用以根據補償訊號產生交錯訊號,每一脈寬調變訊號產生器用以根據交錯訊號、輸出電壓及輸入電壓產生脈寬調變產生訊號。每一或閘用以根據快速響應訊號及對應的脈寬調變產生訊號產生脈寬調變訊號。複數個功率級用以根據複數個脈寬調變訊號產生輸出電壓。 A step-down converter includes a fast response circuit, a compensator, an interleaving logic circuit, a plurality of pulse width modulation signal generators, a plurality of OR gates, a plurality of power stages, a plurality of inductors and an output capacitor. The compensator is coupled to the output end. The interleaving logic circuit is coupled to the compensator. The plurality of power stages are coupled to the corresponding plurality of OR gates. Each PWM signal generator is respectively coupled to the interleaved logic circuit, the output terminal and the input terminal. Each OR gate is respectively coupled to a corresponding PWM signal generator. Each inductor is coupled between the corresponding power stage and the output end. The output capacitor is coupled between the output terminal and the ground terminal. The quick response circuit includes a voltage droop sensor, a load frequency sensor, a quick response signal generator, a maximum quick response signal generator, and a gate. The voltage droop sensor is coupled to the output end. The load frequency sensor is coupled to the output end. The fast response signal generator is coupled to the voltage droop sensor. The maximum fast response signal generator is coupled to the output terminal and the input terminal of the voltage droop sensor and the load frequency sensor. The AND gate is coupled to the quick response signal generator, the maximum quick response signal generator and a plurality of OR gates. The voltage droop sensor is used to generate a trigger signal according to the voltage droop of the output voltage. The load frequency sensor is used according to the load The frequency output load frequency signal, the quick response signal generator is used to generate the initial quick response signal according to the trigger signal. The maximum fast response signal generator is used to generate the maximum fast response signal according to the input voltage, trigger signal, load frequency signal and output voltage. The AND gate is used for generating the quick response signal according to the initial quick response signal and the maximum quick response signal. The compensator is used for generating a compensation signal according to the output voltage and the reference voltage. The interleaving logic circuit is used to generate interleaved signals according to the compensation signal, and each PWM signal generator is used to generate pulse width modulated signals according to the interleaved signals, the output voltage and the input voltage. Each OR gate is used for generating a PWM signal according to the fast response signal and the corresponding PWM generating signal. A plurality of power stages are used to generate an output voltage according to a plurality of PWM signals.
一種降壓轉換器的操作方法。降壓轉換器包含快速響應電路、補償器、交錯邏輯電路、複數個脈寬調變訊號產生器、複數個或閘、複數個功率級、複數個電感及輸出電容。補償器耦接於輸出端。交錯邏輯電路耦接於補償器。每一脈寬調變訊號產生器分別耦接於交錯邏輯電路、輸出端及輸入端。每一或閘分別耦接於對應的脈寬調變訊號產生器。複數個功率級耦接於對應的複數個或閘。每一電感耦接於對應的功率級及輸出端之間。輸出電容耦接於該輸出端及接地端之間。快速響應電路包含電壓下垂感測器、負載頻率感測器、快速響應訊號產生器、最大快速響應訊號產生器、及閘。電壓下垂感測器耦接於輸出端。負載頻率感測器耦接於輸出端。快速響應訊號產生器耦接於電壓下垂感測器。最大快速響應訊號產生器耦接於電壓下垂感測器、負載頻率感測器、輸出端及輸入端。及閘耦接於快速響應訊號產生器、最大快速響應訊號產生器及複數個或閘。操作方法包含電壓下垂感測器根據輸出電壓的電壓下垂產生觸發訊號,負載頻率感測器根據負載的頻率輸出負載頻率訊號,快速響應訊號產生器根據觸發訊號產生起始快速響應訊號,最大快速響應訊號產生器根據輸入電壓、觸發訊號、負載頻率訊號及輸出電壓產生最大快速響應訊號,及閘根據起 始快速響應訊號及最大快速響應訊號產生快速響應訊號,補償器根據輸出電壓及參考電壓產生補償訊號,交錯邏輯電路根據補償訊號產生交錯訊號,複數個脈寬調變訊號產生器中每一脈寬調變訊號產生器根據交錯訊號、輸出電壓及輸入電壓產生脈寬調變產生訊號,複數個或閘中每一或閘根據快速響應訊號及對應的脈寬調變產生訊號產生脈寬調變訊號,及複數個功率級根據複數個脈寬調變訊號產生輸出電壓。 A method of operating a buck converter. The buck converter includes a fast response circuit, a compensator, an interleaved logic circuit, a plurality of pulse width modulation signal generators, a plurality of OR gates, a plurality of power stages, a plurality of inductors and an output capacitor. The compensator is coupled to the output end. The interleaving logic circuit is coupled to the compensator. Each PWM signal generator is respectively coupled to the interleaved logic circuit, the output terminal and the input terminal. Each OR gate is respectively coupled to a corresponding PWM signal generator. The plurality of power stages are coupled to the corresponding plurality of OR gates. Each inductor is coupled between the corresponding power stage and the output end. The output capacitor is coupled between the output terminal and the ground terminal. The quick response circuit includes a voltage droop sensor, a load frequency sensor, a quick response signal generator, a maximum quick response signal generator, and a gate. The voltage droop sensor is coupled to the output end. The load frequency sensor is coupled to the output end. The fast response signal generator is coupled to the voltage droop sensor. The maximum fast response signal generator is coupled to the voltage droop sensor, the load frequency sensor, the output terminal and the input terminal. The AND gate is coupled to the quick response signal generator, the maximum quick response signal generator and a plurality of OR gates. The operation method includes that the voltage droop sensor generates a trigger signal according to the voltage droop of the output voltage, the load frequency sensor outputs a load frequency signal according to the frequency of the load, and the quick response signal generator generates an initial quick response signal and a maximum quick response signal according to the trigger signal The signal generator generates the maximum fast response signal according to the input voltage, trigger signal, load frequency signal and output voltage, and the gate is based on the The initial fast response signal and the maximum fast response signal generate a fast response signal. The compensator generates a compensation signal according to the output voltage and the reference voltage. The interleaved logic circuit generates an interleaved signal according to the compensation signal. Each pulse width in a plurality of pulse width modulation signal generators The modulation signal generator generates a pulse width modulation signal according to the interleaved signal, output voltage and input voltage, and each OR gate in a plurality of OR gates generates a pulse width modulation signal according to the fast response signal and the corresponding pulse width modulation signal , and a plurality of power stages generate output voltages according to a plurality of PWM signals.
一種最大快速響應訊號產生器,包含電流源、電容、開關、比較器及正反器。電容耦接於電流源及接地端之間。開關包含第一端耦接於電流源及電容,第二端耦接於接地端,及控制端。比較器包含正輸入端耦接於電流源、電容及開關的第一端,負輸入端及輸出端。正反器包含輸入端,時序端,輸出端,反輸出端耦接於開關的控制端,重置端耦接於比較器的輸出端。電流源用以根據輸入電壓及負載頻率訊號產生電流。比較器用以根據正輸入端接收之響應電壓及負輸入端接收之輸出電壓於比較器之輸出端輸出重置訊號。正反器用以根據輸入端接收之固定電壓,時序端接收之觸發訊號,及重置端接收之重置訊號於正反器的輸出端輸出最大快速響應訊號。 A maximum fast response signal generator, including a current source, a capacitor, a switch, a comparator and a flip-flop. The capacitor is coupled between the current source and the ground. The switch includes a first terminal coupled to the current source and a capacitor, a second terminal coupled to the ground terminal, and a control terminal. The comparator includes a positive input terminal coupled to the current source, a capacitor and the first terminal of the switch, a negative input terminal and an output terminal. The flip-flop includes an input terminal, a timing terminal, and an output terminal. The inverting output terminal is coupled to the control terminal of the switch, and the reset terminal is coupled to the output terminal of the comparator. The current source is used to generate current according to the input voltage and the load frequency signal. The comparator is used for outputting a reset signal at the output terminal of the comparator according to the response voltage received by the positive input terminal and the output voltage received by the negative input terminal. The flip-flop is used to output the maximum fast response signal at the output of the flip-flop according to the fixed voltage received by the input terminal, the trigger signal received by the timing terminal, and the reset signal received by the reset terminal.
一種最大快速響應訊號產生器的操作方法。最大快速響應訊號產生器包含電流源、電容、開關、比較器及正反器。電容耦接於電流源及接地端之間。開關包含第一端耦接於電流源及電容,第二端耦接於接地端,及控制端。比較器包含正輸入端耦接於電流源、電容及開關的第一端,負輸入端及輸出端。正反器包含輸入端,時序端,輸出端,反輸出端耦接於開關的控制端,重置端耦接於比較器的輸出端。操作方法包含電流源根據輸入電壓及負載頻率訊號產生電流,比較器根據正輸入端接收之響應電壓及負輸入端接收之輸出電壓於比 較器之輸出端輸出重置訊號,正反器根據輸入端接收之固定電壓,時序端接收之觸發訊號,及重置端接收之重置訊號於正反器的輸出端輸出最大快速響應訊號。 A method of operating a maximum fast response signal generator. The maximum fast response signal generator includes current sources, capacitors, switches, comparators and flip-flops. The capacitor is coupled between the current source and the ground. The switch includes a first terminal coupled to the current source and a capacitor, a second terminal coupled to the ground terminal, and a control terminal. The comparator includes a positive input terminal coupled to the current source, a capacitor and the first terminal of the switch, a negative input terminal and an output terminal. The flip-flop includes an input terminal, a timing terminal, and an output terminal. The inverting output terminal is coupled to the control terminal of the switch, and the reset terminal is coupled to the output terminal of the comparator. The operation method includes the current source generating current according to the input voltage and the load frequency signal, and the comparator according to the response voltage received by the positive input terminal and the output voltage received by the negative input terminal. The output terminal of the comparator outputs a reset signal, and the flip-flop outputs the maximum quick response signal at the output terminal of the flip-flop according to the fixed voltage received by the input terminal, the trigger signal received by the timing terminal, and the reset signal received by the reset terminal.
100,900:降壓轉換器 100,900: buck converter
10,910:快速響應電路 10,910: Quick response circuit
12:電壓下垂感測器 12: Voltage droop sensor
14:負載頻率感測器 14: Load frequency sensor
16:快速響應訊號產生器 16: Quick response signal generator
18:最大快速響應訊號產生器 18: Maximum fast response signal generator
20:補償器 20: Compensator
30:交錯邏輯電路 30:Interleaved logic circuit
901,902:電晶體 901,902: Transistor
903:緩衝器 903: buffer
904:反向器 904: Inverter
Ton1~TonN:脈寬調變訊號產生器 Ton1~TonN: PWM signal generator
OR1~ORN:或閘 OR1~ORN: OR gate
PS1~PSN:功率級 PS1~PSN: power stage
L1~LN:電感 L1~LN: Inductance
AND:及閘 AND: and gate
Vo:輸出電壓 Vo: output voltage
Vin:輸入電壓 Vin: input voltage
Vsen:觸發訊號 Vsen: trigger signal
Lo:負載 Lo: load
Co:輸出電容 Co: output capacitance
Fs:負載頻率訊號 Fs: load frequency signal
ILo:負載電流 I Lo : load current
Isum:總電感電流 Isum: total inductor current
QRi:起始快速響應訊號 QRi: initial quick response signal
QRmax:最大快速響應訊號 QRmax: maximum quick response signal
QR:快速響應訊號 QR: Quick Response Signal
Vref:參考電壓 Vref: reference voltage
Vcomp:補償訊號 Vcomp: compensation signal
Vint:交錯訊號 Vint: interlaced signal
PM1~PMN:脈寬調變產生訊號 PM1~PMN: pulse width modulation signal generation
PWM1~PWMN:脈寬調變訊號 PWM1~PWMN: pulse width modulation signal
OUT:輸出端 OUT: output terminal
IN:輸入端 IN: input terminal
181:電流源 181: Current source
182:比較器 182: Comparator
C:電容 C: Capacitance
S:開關 S: switch
SR:正反器 SR: flip-flop
GND:接地端 GND: ground terminal
D:輸入端 D: input terminal
R:重置端 R: reset terminal
CK:時序端 CK: timing terminal
Q:輸出端 Q: output terminal
Qb:反輸出端 Qb: Inverse output terminal
Iqr:響應電流 Iqr: response current
Vqr:響應電壓 Vqr: response voltage
t1~t8:時間 t1~t8: time
T1~T4:週期 T1~T4: period
700,800:方法 700,800: method
S702~S720,S802~S806:步驟 S702~S720, S802~S806: steps
第1圖係為本發明實施例之降壓轉換器的示意圖。 FIG. 1 is a schematic diagram of a buck converter according to an embodiment of the present invention.
第2圖係為第1圖之最大快速響應訊號產生器的示意圖。 Figure 2 is a schematic diagram of the maximum fast response signal generator in Figure 1.
第3圖係為第2圖之最大快速響應訊號產生器的操作訊號時序圖。 Figure 3 is a timing diagram of the operating signals of the maximum fast response signal generator in Figure 2.
第4圖係為第1圖之降壓轉換器的操作訊號時序圖。 Figure 4 is a timing diagram of the operation signals of the step-down converter in Figure 1.
第5圖係為第1圖之降壓轉換器的另一操作訊號時序圖。 Fig. 5 is another operation signal timing diagram of the step-down converter in Fig. 1.
第6圖係為第1圖之降壓轉換器的另一操作訊號時序圖。 Fig. 6 is another operation signal timing diagram of the step-down converter in Fig. 1.
第7圖係為第1圖之降壓轉換器的操作方法的流程圖。 FIG. 7 is a flowchart of the operation method of the step-down converter in FIG. 1 .
第8圖係為第2圖之最大快速響應訊號產生器的操作方法的流程圖。 FIG. 8 is a flowchart of the operation method of the maximum fast response signal generator in FIG. 2 .
第9圖係為先前技術之具有快速響應電路的降壓轉換器的示意圖。 FIG. 9 is a schematic diagram of a prior art buck converter with a fast response circuit.
第10圖係為第9圖之降壓轉換器的操作訊號時序圖。 Fig. 10 is a timing diagram of operation signals of the step-down converter in Fig. 9.
第1圖係為本發明實施例之降壓轉換器(buck converter)100的示意圖。降壓轉換器100是一種會降低電壓的直流-直流轉換器,輸出端OUT的電壓會比輸入端IN的輸入電壓Vin要低。降壓轉換器100可包含快速響應電路10、補償器20、交錯邏輯電路30、複數個脈寬調變訊號產生器Ton1~TonN、複數個或閘OR1~ORN、複數個功率級PS1~PSN、複數個電感L1~LN、輸出電容Co及負載Lo。補償器20耦接於輸出端OUT。交錯邏輯電路30耦接於補償器20。脈寬調變訊號
產生器Ton1~TonN耦接於交錯邏輯電路30、輸入端IN及輸出端OUT。或閘OR1~ORN耦接於對應的脈寬調變訊號產生器Ton1~TonN。功率級PS1~PSN耦接於對應的或閘OR1~ORN。電感L1~LN耦接於對應的功率級PS1~PSN及輸出端OUT之間。輸出電容Co耦接於輸出端OUT及接地端GND之間。負載Lo耦接於輸出端OUT及接地端GND之間。其中每一脈寬調變訊號產生器以及功率級對應一相位,例如脈寬調變訊號產生器Ton1及功率級PS1對應第一相位,脈寬調變訊號產生器Ton2及功率級PS2,對應第二相位,依此類推。
FIG. 1 is a schematic diagram of a
快速響應電路10包含電壓下垂感測器12、負載頻率感測器14、快速響應訊號產生器16、最大快速響應訊號產生器18、及閘AND。電壓下垂感測器12耦接於輸出端OUT。負載頻率感測器14耦接於輸出端OUT。快速響應訊號產生器16耦接於電壓下垂感測器12。最大快速響應訊號產生器18耦接於電壓下垂感測器12、負載頻率感測器14、輸入端IN及輸出端OUT。及閘AND耦接於快速響應訊號產生器16、最大快速響應訊號產生器18及或閘OR1~ORN。
The fast response circuit 10 includes a
電壓下垂感測器12用以根據輸出電壓Vo的電壓下垂產生觸發訊號Vsen。負載頻率感測器14用以根據負載Lo的頻率輸出負載頻率訊號Fs。快速響應訊號產生器16用以根據觸發訊號Vsen產生起始快速響應訊號QRi。最大快速響應訊號產生器18用以根據輸入電壓Vin、觸發訊號Vsen、負載頻率訊號Fs及輸出電壓Vo產生最大快速響應訊號QRmax。及閘AND用以根據起始快速響應訊號QRi及最大快速響應訊號QRmax產生快速響應訊號QR。補償器20用以根據輸出電壓Vo及參考電壓Vref產生補償訊號Vcomp。交錯邏輯電路30用以根據補償訊號Vcomp產生交錯訊號Vint。脈寬調變訊號產生器Ton1~TonN用以根據交錯訊號Vint、輸出電壓Vo及輸入電壓Vin產生脈寬調變產生訊號PM1~PMN。或閘
OR1~ORN用以根據快速響應訊號QR及對應的脈寬調變產生訊號PM1~PMN產生脈寬調變訊號PWM1~PWMN。功率級PS1~PSN用以根據脈寬調變訊號PWM1~PWMN產生輸出電壓Vo及提供負載電流ILo至負載Lo,同時在電感L1~LN產生總電感電流Isum。脈寬調變產生訊號PM1~PMN以及脈寬調變訊號PWM1~PWMN分別對應第一相位至第N相位。
The
舉例而言,降壓轉換器100的負載Lo的頻率範圍可介於300Hz至1MHz之間,輸入電壓Vin可介於6V至24V,輸出電壓Vo可介於0.2V至3.05V,快速響應訊號QR可為5V,負載電流ILo可介於50A至300A之間。
For example, the frequency range of the load Lo of the
第2圖係為第1圖之最大快速響應訊號產生器18的示意圖。最大快速響應訊號產生器18包含電流源181、電容C、開關S、比較器182及正反器SR。電容C耦接於電流源181及接地端GND之間。開關S包含第一端耦接於電流源181及電容C,第二端耦接於接地端GND,及控制端。比較器182包含正輸入端耦接於電流源181、電容C及開關S的第一端,負輸入端耦接於輸出端OUT。正反器SR包含輸入端D,重置端R耦接於比較器182的輸出端,時序端CK,輸出端Q,及反輸出端Qb耦接於開關S的控制端。電流源181用以根據輸入電壓Vin及負載頻率訊號Fs產生響應電流Iqr。比較器182用以根據正輸入端接收之響應電壓Vqr及負輸入端接收之輸出電壓Vo產生重置訊號Vrst。正反器SR用以根據輸入端D接收之固定電壓VHD,時序端CK接收之觸發訊號Vsen,及重置端R接收之重置訊號Vrst於輸出端Q輸出最大快速響應訊號QRmax。電流源181可用任何半導體電流鏡(current mirror)實現,開關S可用場效電晶體(field-effect transistor)實現。
FIG. 2 is a schematic diagram of the maximum fast
第3圖係為第2圖之最大快速響應訊號產生器18的操作訊號時序圖。
以下說明最大快速響應訊號產生器18產生最大快速響應訊號QRmax的過程。在時間t1,觸發訊號Vsen拉至高準位,使正反器SR的輸出端Q所輸出的最大快速響應訊號QRmax也拉至高準位。響應電流Iqr開始對電容C充電,響應電壓Vqr開始上升。在時間t2,當響應電壓Vqr上升至超過輸出電壓Vo的準位,比較器182會將重置訊號Vrst拉至高準位。高準位的重置訊號Vrst會將正反器SR的輸出端Q所輸出的最大快速響應訊號QRmax拉至低準位,並將反輸出端Qb所輸出的訊號拉至高準位。反輸出端Qb的高準位訊號將開關S打開,引導響應電流Iqr流至接地端GND,將響應電壓Vqr拉至低準位,重置訊號Vrst也會回到低準位。因電路反應時間皆在奈秒級數,所以重置訊號Vrst呈現脈衝波。
FIG. 3 is a timing diagram of operating signals of the maximum fast
在時間t3,觸發訊號Vsen再度拉至高準位,整個電路運作過程重複,依此類推。整個電路運作過程可依據需要一直重複。最大快速響應訊號QRmax的開啟時間皆為響應電壓Vqr由低準位上升至輸出電壓Vo的準位所需的時間。需注意的是,輸出電壓Vo的振幅比響應電壓Vqr小很多,因此在圖中輸出電壓Vo的準位看起來是固定的。 At time t3, the trigger signal Vsen is pulled to the high level again, and the whole circuit operation process is repeated, and so on. The entire circuit operation process can be repeated as required. The turn-on time of the maximum quick response signal QRmax is the time required for the response voltage Vqr to rise from the low level to the level of the output voltage Vo. It should be noted that the amplitude of the output voltage Vo is much smaller than the response voltage Vqr, so the level of the output voltage Vo appears to be fixed in the figure.
此外,電流源181可根據負載頻率訊號Fs以及輸入電壓Vin調整響應電流Iqr。固定電壓VHD可為直流電壓,例如5V,並可用以使正反器SR輸出的最大快速響應訊號QRmax的高準位等於固定電壓VHD。而最大快速響應訊號QRmax的寬度可由以下公式表示:
其中QRmax為最大快速響應訊號寬度,C為電容值,Vo為輸出電壓,Vin為輸入電壓,Rs為電流源181之電阻值,Fs為負載頻率。
Wherein QRmax is the maximum fast response signal width, C is the capacitance value, Vo is the output voltage, Vin is the input voltage, Rs is the resistance value of the
最大快速響應訊號QRmax的寬度為降壓轉換器100所能承受最大的脈寬調變訊號寬度。脈寬調變訊號超過此寬度會使輸出電壓Vo持續上升而造成電壓過載(overvoltage)的情況。最大快速響應訊號產生器18的應用可避免電壓過載情況。
The width of the maximum fast response signal QRmax is the maximum width of the PWM signal that the
第4圖係為第1圖之降壓轉換器100的操作訊號時序圖。以下說明快速響應電路10產生快速響應訊號QR及其應用於降壓轉換器100提供輸出電壓Vo和負載電流ILo的過程。在時間t1,負載電流ILo上升至高電流,使輸出電壓Vo開始下降至小於閾值(threshold)。此時,電壓下垂感測器12可產生觸發訊號Vsen,並將觸發訊號Vsen傳送至快速響應訊號產生器16以及最大快速響應訊號產生器18以分別產生起始快速響應訊號QRi及最大快速響應訊號QRmax。快速響應訊號產生器16可根據觸發訊號Vsen的斜率調整起始快速響應訊號QRi的寬度。起始快速響應訊號QRi及最大快速響應訊號QRmax會輸入及閘AND。及閘AND對最大快速響應訊號QRmax及起始快速響應訊號QRi進行及邏輯運算產生快速響應訊號QR。快速響應訊號QR及脈寬調變產生訊號PM1~PMN會分別輸入對應的或閘OR1~ORN。或閘OR1~ORN會將快速響應訊號QR及對應的脈寬調變產生訊號PM1~PMN進行或邏輯運算產生脈寬調變訊號PWM1~PWMN。脈寬調變訊號PWM1~PWMN同時推動功率級PS1~PSN產生輸出電壓Vo,並且電感L1~LN產生的總電感電流Isum開始上升。同時,總電感電流Isum的部分電流流至輸出電容Co為輸出電容Co充電,並且另一部分電流成為流至負載Lo的負載電流ILo,提供負載Lo所需的電能。功率級PS1~PSN的運作方式為本技術領域中具有通常知識者所習知,在此不贅述。
FIG. 4 is a timing diagram of operation signals of the
在時間t1和時間t2之間,一開始由快速響應訊號QR訊號快速提供電能使總電感電流Isum能迅速拉高,之後因輸出電壓Vo仍小於閾值,補償器20輸出補償訊號Vcomp使交錯邏輯電路30產生交錯訊號Vint,推動脈寬調變訊號產生器Ton1~TonN以交錯的方式產生脈寬調變產生訊號PM1~PMN,脈寬調變產生訊號PM1~PMN即為脈寬調變訊號PWM1~PWMN。脈寬調變訊號PWM1~PWMN推動功率級PS1~PSN持續提供部分負載電流ILo。同時,輸出電容Co放電以提供另一部分的負載電流ILo。
Between time t1 and time t2, at the beginning, the fast response signal QR signal quickly provides power to make the total inductor current Isum rise rapidly, and then because the output voltage Vo is still lower than the threshold value, the
在時間t2,負載電流1Lo降至低電流,輸出電壓Vo開始回升,電感L1~LN開始放電,總電感電流Isum開始下降至低電流,直到時間t3,負載電流ILo再度提高。在時間t3至t4的電路運作過程重複時間t1至t2。 At time t2, the load current 1 Lo drops to a low current, the output voltage Vo starts to rise, the inductors L1~LN start to discharge, and the total inductor current Isum starts to drop to a low current, until time t3, the load current I Lo increases again. The circuit operation from time t3 to t4 is repeated for time t1 to t2.
在時間t5至t6,負載頻率提高,此時,快速響應訊號QR即為脈寬調變訊號PWM1~PWMN,脈寬調變訊號PWM1~PWMN同時推動功率級PS1~PSN產生輸出電壓Vo並提供負載電流ILo。由於快速響應訊號QR所產生之脈寬調變訊號PWM1~PWMN已經提供足夠電能,因此補償器20不需要再輸出補償訊號Vcomp來使脈寬調變訊號產生器Ton1~TonN另外輸出脈寬調變產生訊號PM1~PMN來推動功率級PS1~PSN提供額外的電流。在快速響應訊號QR拉至低準位後,電感L1~LN即開始放電,總電感電流Isum即開始下降。之後,負載電流ILo降至低電流,使輸出電壓Vo開始上升,而總電感電流Isum持續下降,直到時間t7,負載電流ILo再度提高。時間t7至t8以及其後的運作週期雖然頻率可不同,但電路運作過程基本上重複時間t5至t6,依此類推。因本發明之快速響應電路10可以控制快速響應訊號QR的寬度,總電感電流Isum可在降回原來的準位之後才會再被拉高,所以不會造成額外的能量累積,輸出電壓Vo就不會隨著時間而愈
來愈被拉高,如此即可避免電壓過載的情況。
From time t5 to t6, the load frequency increases. At this time, the quick response signal QR is the pulse width modulation signal PWM1~PWMN, and the pulse width modulation signal PWM1~PWMN simultaneously drives the power stage PS1~PSN to generate the output voltage Vo and provide the load Current I Lo . Since the pulse width modulation signals PWM1~PWMN generated by the quick response signal QR have already provided sufficient power, the
第5圖係為第1圖之降壓轉換器100的另一操作訊號時序圖。第5圖示意了總電感電流Isum以及快速響應訊號QR以輔助說明如何導出最大快速響應訊號QRmax的寬度。說明如下:電感L1~LN在一週期中充電的總電能為:
電感L1~LN在一週期中電感放電的總電能為:
根據能量守恆定律,在一週期中電感L1~LN充電的總電能等於電感L1~LN放電的總電能:
因此降壓轉換器100所能承受最大的脈寬調變訊號寬度可由下列算式導出:
其中QRmax為最大快速響應訊號的寬度,Vo為輸出電壓,Vin為輸入電壓,Fs為負載頻率,Ts為負載週期,N為相數,L為電感的感值。由公式可見,最大快速響應訊號的寬度可根據輸入電壓Vin,輸出電壓Vo,以及負載頻率決定。 Among them, QRmax is the width of the maximum quick response signal, Vo is the output voltage, Vin is the input voltage, Fs is the load frequency, Ts is the load cycle, N is the number of phases, and L is the inductance value. It can be seen from the formula that the width of the maximum fast response signal can be determined according to the input voltage Vin, the output voltage Vo, and the load frequency.
第6圖係為第1圖之降壓轉換器100的另一操作訊號時序圖。最大快速響應訊號QRmax的高準位時間皆為響應電壓Vqr由低準位上升至輸出電壓Vo所需的時間。在週期T1,起始快速響應訊號QRi的寬度小於最大快速響應訊號QRmax的寬度,因此快速響應電路10輸出的快速響應訊號QR為起始快速響應訊號QRi。在週期T2,起始快速響應訊號QRi的寬度大於最大快速響應訊號QRmax的寬度,因此快速響應電路10輸出的快速響應訊號QR為最大快速響應訊號QRmax。在週期T3,負載頻率提高,最大快速響應訊號產生器18因為負載頻率上升而將最大快速響應訊號QRmax的寬度下調,因此快速響應電路10輸出的快速響應訊號QR為最大快速響應訊號QRmax,以避免降壓轉換器100發生電路過載。在週期T4,負載頻率降低,最大快速響應訊號產生器18因為負載頻率下降而將最大快速響應訊號QRmax的寬度上調,因此快速響應電路10輸出的快速響應訊號QR為起始快速響應訊號QRi。藉此方法可根據負載頻率及時調整快速響應訊號QR的寬度以避免電壓過載,並達到最好的能源效率。
FIG. 6 is another timing diagram of operation signals of the
第7圖係為第1圖之降壓轉換器100的操作方法700的流程圖。方法700包含以下步驟:S702:電壓下垂感測器12根據輸出電壓Vo的電壓下垂產生觸發訊號Vsen;S704:負載頻率感測器14根據負載Lo的頻率輸出負載頻率訊號Fs;S706:快速響應訊號產生器16根據觸發訊號Vsen產生起始快速響
應訊號QRi;S708:最大快速響應訊號產生器18根據輸入電壓Vin、觸發訊號Vsen、負載頻率訊號Fs及輸出電壓Vo產生最大快速響應訊號QRmax;S710:及閘AND根據起始快速響應訊號QRi及最大快速響應訊號QRmax產生快速響應訊號QR;S712:補償器20根據輸出電壓Vo及參考電壓Vref產生補償訊號Vcomp;S714:交錯邏輯電路30根據補償訊號Vcomp產生交錯訊號Vint;S716:脈寬調變訊號產生器Ton1~TonN根據交錯訊號Vint、輸出電壓Vo及輸入電壓Vin產生對應的脈寬調變產生訊號PM1~PMN;S718:或閘OR1~ORN根據快速響應訊號QR及對應的脈寬調變產生訊號PM1~PMN產生對應的脈寬調變訊號PWM1~PWMN;及S720:功率級PS1~PSN根據脈寬調變訊號PWM1~PWMN產生輸出電壓Vo。
FIG. 7 is a flowchart of a
降壓轉換器100的操作方法700的詳細說明可於見於前面段落,在此不贅述。
The detailed description of the
第8圖係為第2圖之最大快速響應訊號產生器18的操作方法800的流程圖。方法800包含以下步驟:S802:電流源181根據輸入電壓Vin及負載頻率訊號Fs產生響應電流Iqr;S804:比較器182根據正輸入端接收之響應電壓Vqr及負輸入端接收之輸出電壓Vo輸出重置訊號Vrst;及
S806:正反器SR根據輸入端D接收之固定電壓VHD,時序端CK接收之觸發訊號Vsen,及重置端R接收之重置訊號Vrst於正反器SR的輸出端Q輸出最大快速響應訊號QRmax。
FIG. 8 is a flowchart of a
最大快速響應訊號產生器18的操作方法800的詳細說明可於見於前面段落,在此不贅述。
The detailed description of the
綜上所述,本發明之具快速響應電路的降壓轉換器可有效避免一般快速響應電路在負載施加暫態期間可能產生的電壓過載問題,總電感電流可在降回原來的準位之後才會再被拉高,因此不會產生額外的能量累積。輸出電壓就不會隨著時間而愈來愈被拉高,如此即可避免電壓過載的情況,並提升了降壓轉換器的能源效率。 To sum up, the step-down converter with fast response circuit of the present invention can effectively avoid the voltage overload problem that may occur in the general fast response circuit during the transient state of the load, and the total inductor current can be recovered after the total inductor current is reduced to the original level. will be pulled high again, so there will be no additional energy buildup. The output voltage will not be pulled higher and higher over time, thus avoiding voltage overload and improving the energy efficiency of the buck converter.
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。 The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.
100:降壓轉換器 100: Buck converter
10:快速響應電路 10: Quick response circuit
12:電壓下垂感測器 12: Voltage droop sensor
14:負載頻率感測器 14: Load frequency sensor
16:快速響應訊號產生器 16: Quick response signal generator
18:最大快速響應訊號產生器 18: Maximum fast response signal generator
20:補償器 20: Compensator
30:交錯邏輯電路 30:Interleaved logic circuit
Ton1~TonN:脈寬調變訊號產生器 Ton1~TonN: PWM signal generator
OR1~ORN:或閘 OR1~ORN: OR gate
PS1~PSN:功率級 PS1~PSN: power stage
L1~LN:電感 L1~LN: Inductance
AND:及閘 AND: and gate
Vo:輸出電壓 Vo: output voltage
Vin:輸入電壓 Vin: input voltage
Vsen:觸發訊號 Vsen: trigger signal
Lo:負載 Lo: load
Co:輸出電容 Co: output capacitance
Fs:負載頻率訊號 Fs: load frequency signal
ILo:負載電流 I Lo : load current
Isum:總電感電流 Isum: total inductor current
QRi:起始快速響應訊號 QRi: initial quick response signal
QRmax:最大快速響應訊號 QRmax: maximum quick response signal
QR:快速響應訊號 QR: Quick Response Signal
Vref:參考電壓 Vref: reference voltage
Vcomp:補償訊號 Vcomp: compensation signal
Vint:交錯訊號 Vint: interlaced signal
PM1~PMN:脈寬調變產生訊號 PM1~PMN: pulse width modulation signal generation
PWM1~PWMN:脈寬調變訊號 PWM1~PWMN: pulse width modulation signal
OUT:輸出端 OUT: output terminal
IN:輸入端 IN: input terminal
Claims (20)
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Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7301314B2 (en) * | 2002-03-22 | 2007-11-27 | International Rectifier Corporation | Multi-phase buck converter |
CN103208915A (en) * | 2012-01-17 | 2013-07-17 | 快捷半导体(苏州)有限公司 | Active Droop Power Supply With Improved Step-load Transient Response |
JP5967871B2 (en) * | 2011-06-27 | 2016-08-10 | トランスフォーム・ジャパン株式会社 | Power supply |
JP6010570B2 (en) * | 2014-02-26 | 2016-10-19 | 株式会社豊田中央研究所 | Power conversion circuit system |
TW201824719A (en) * | 2016-12-27 | 2018-07-01 | 京三製作所股份有限公司 | Power apparatus, and control method of power apparatus |
TW201935833A (en) * | 2018-02-19 | 2019-09-01 | 美商微晶片科技股份有限公司 | Multi-phase parallelable constant on time buck controller with phase interleaving ensured by ripple injection |
US10439497B2 (en) * | 2015-07-20 | 2019-10-08 | Texas Instruments Incorporated | Time-interleaved current feedback droop function for multiphase buck converters |
CN110429812A (en) * | 2015-09-22 | 2019-11-08 | 意法半导体股份有限公司 | For manage multiple sluggishness DC-DC buck converters method and corresponding DC-DC buck converter |
-
2021
- 2021-12-24 TW TW110148641A patent/TWI792805B/en active
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7301314B2 (en) * | 2002-03-22 | 2007-11-27 | International Rectifier Corporation | Multi-phase buck converter |
US7477045B2 (en) * | 2002-03-22 | 2009-01-13 | International Rectifier Corporation | Multi-phase buck converter |
JP5967871B2 (en) * | 2011-06-27 | 2016-08-10 | トランスフォーム・ジャパン株式会社 | Power supply |
CN103208915A (en) * | 2012-01-17 | 2013-07-17 | 快捷半导体(苏州)有限公司 | Active Droop Power Supply With Improved Step-load Transient Response |
JP6010570B2 (en) * | 2014-02-26 | 2016-10-19 | 株式会社豊田中央研究所 | Power conversion circuit system |
US10439497B2 (en) * | 2015-07-20 | 2019-10-08 | Texas Instruments Incorporated | Time-interleaved current feedback droop function for multiphase buck converters |
CN110429812A (en) * | 2015-09-22 | 2019-11-08 | 意法半导体股份有限公司 | For manage multiple sluggishness DC-DC buck converters method and corresponding DC-DC buck converter |
TW201824719A (en) * | 2016-12-27 | 2018-07-01 | 京三製作所股份有限公司 | Power apparatus, and control method of power apparatus |
TW201935833A (en) * | 2018-02-19 | 2019-09-01 | 美商微晶片科技股份有限公司 | Multi-phase parallelable constant on time buck controller with phase interleaving ensured by ripple injection |
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