TWI792805B - Buck converter and operating method of buck converter, maximum quick response signal generator and operating method of maximum quick response signal generator - Google Patents

Abstract

A buck converter includes a quick response circuit, a compensator coupled to an output node, an interleaving logic circuit coupled to the compensator, a plurality of pulse width modulation signal generators, a plurality of OR gates coupled to the corresponding pulse width modulation signal generator, a plurality of power stages coupled to the corresponding OR gates, a plurality of inductors and an output capacitor. Each pulse width modulation signal generator is coupled to the interleaving logic circuit, an input node and the output node.. The quick response circuit includes a voltage droop sensor coupled to the output node, a load frequency sensor coupled to the output node, a quick response signal generator coupled to the voltage droop sensor, a maximum quick response signal generator coupled to the voltage droop sensor and the load frequency sensor, an AND gate coupled to the quick response signal generator, the maximum quick response signal generator and the plurality of OR gates.

Description

Buck Converter and Buck Converter Operation Method, Maximum Fast Response Signal Production Generator and the operation method of the maximum fast response signal generator

The present invention relates to a step-down converter, in particular to a step-down converter with a fast response mechanism and an operation method thereof.

In modern voltage regulation systems applied to microprocessor core voltage control, multiphase control is a common control method, which meets the requirements of high power density and high current slew rate. However, conventional multiphase control methods are still insufficient to cope with the ultra-high load transients specified in modern voltage regulator specifications, especially during load application transients. Therefore, an open-loop control mechanism called quick response was invented to overcome the undershoot problem. During load application transients, the fast response mechanism will immediately turn on the high-side switches of all phases to fully supply the heavy load current demand, and the output voltage droop can thus be controlled into the correct load line specification ). Even so, the fast-response mechanism still has some disadvantages. For example, inaccurate fast-response turn-on and turn-off may lead to unexpected ringback or circuit overload due to continuous rise of the output voltage.

For clarity, FIG. 9 illustrates a prior art buck converter 900 with a fast response circuit. The buck converter 900 includes a plurality of PWM signal generators Ton1~TonN corresponding to each phase, a plurality of OR gates OR1~ORN coupled to the corresponding PWM signal generators Ton1~TonN, and a plurality of power stages PS1~PSN are coupled to the corresponding OR gates OR1~ORN, a plurality of inductors L1~LN are coupled between the corresponding power stages PS1~PSN and the output terminal OUT, the output capacitor Co and the load Lo are coupled to the output terminal OUT and Between the ground terminal GND. The fast response circuit 910 is coupled between the output terminal OUT and the OR gates OR1˜ORN. Each power stage, such as the power stage PS1 , includes a buffer 903 coupled to the OR gate OR1 , an inverter 904 coupled to the OR gate OR1 , a first transistor 901 and a second transistor 902 . The first transistor 901 includes a first terminal for receiving the input voltage Vin, a second terminal coupled to the inductor L1 , and a control terminal coupled to the buffer 903 . The second transistor 902 includes a first terminal coupled to the second terminal of the first transistor 901 and an inductor L1 , a second terminal coupled to the ground terminal GND, and a control terminal coupled to the inverter 904 . The quick response circuit 910 generates a quick response signal QR according to the output voltage Vo. The PWM signal generators Ton1~TonN of each phase output PWM signals PM1~PMN according to the input voltage Vin and the output voltage Vo. The OR gates OR1˜ORN generate the signals PM1˜PMN according to the PWM and the quick response signal QR generate the PWM1˜PWMN of each phase. The pulse width modulation signals PWM1˜PWMN drive the power stages PS1˜PSN to provide the output voltage Vo and the load current I _Lo .

Fig. 10 is a timing diagram of operation signals of the step-down converter in Fig. 9. At time t1, when the power demand of the load Lo increases, the load current I _Lo rises to a high current, so that the output voltage Vo begins to drop below the threshold (threshold). At this time, the quick response circuit 910 can generate the quick response signal QR, and the QR signal and the pulse width modulation signal PM1~PMN generate the pulse width modulation signal PWM1~PWMN through the OR gate, which is used to drive the power stage PS1~PSN to provide the output voltage Vo and the load current I _Lo . In detail, the leading edge of the quick response signal QR can turn on the first transistor 901 and turn off the second transistor 902 , and the first terminal of the first transistor 901 provides the load current I _Lo to the load Lo. After the first transistor 901 is turned on, the inductors L1 ˜ LN start to charge, and the total inductor current Isum increases. At the same time, part of the current flows to the output capacitor Co to charge it, and the other part flows to the load Lo to provide electrical energy for the load Lo. After the quick response signal QR is pulled to a low level, the first transistor 901 is turned off and the second transistor 902 is turned on, the inductor L starts to discharge, and the total inductor current Isum decreases. The output capacitor Co starts to discharge to the load Lo, so that the load current I _Lo maintains a high current. At time t2, the load current I _Lo drops to a low current, so that the output voltage Vo begins to increase, while the total inductor current Isum continues to decrease. At time t3, the load current I _Lo rises to a high current again, causing the output voltage Vo to drop below the threshold (threshold). At this time, the quick response signal QR is generated again and drives the power stages PS1˜PSN to provide the output voltage Vo and the load current I _Lo , and the rest of the operation process is at the same time as time t1. At time t4, the load current I _Lo drops to a low current again, the output voltage V6 starts to rise, and the rest of the operation process is the same as time t2. Between time t5 and t6, the entire circuit operation process is repeated again. However, the load frequency from time t3 to t6 is higher than the load frequency from time t1 to t2, the total inductor current Isum and the output voltage Vo will be pulled up again before falling back to the original level. The total inductor current Isum and the output voltage Vo will be pulled up more and more over time, eventually causing voltage overload.

A step-down converter includes a fast response circuit, a compensator, an interleaving logic circuit, a plurality of pulse width modulation signal generators, a plurality of OR gates, a plurality of power stages, a plurality of inductors and an output capacitor. The compensator is coupled to the output end. The interleaving logic circuit is coupled to the compensator. The plurality of power stages are coupled to the corresponding plurality of OR gates. Each PWM signal generator is respectively coupled to the interleaved logic circuit, the output terminal and the input terminal. Each OR gate is respectively coupled to a corresponding PWM signal generator. Each inductor is coupled between the corresponding power stage and the output end. The output capacitor is coupled between the output terminal and the ground terminal. The quick response circuit includes a voltage droop sensor, a load frequency sensor, a quick response signal generator, a maximum quick response signal generator, and a gate. The voltage droop sensor is coupled to the output end. The load frequency sensor is coupled to the output end. The fast response signal generator is coupled to the voltage droop sensor. The maximum fast response signal generator is coupled to the output terminal and the input terminal of the voltage droop sensor and the load frequency sensor. The AND gate is coupled to the quick response signal generator, the maximum quick response signal generator and a plurality of OR gates. The voltage droop sensor is used to generate a trigger signal according to the voltage droop of the output voltage. The load frequency sensor is used according to the load The frequency output load frequency signal, the quick response signal generator is used to generate the initial quick response signal according to the trigger signal. The maximum fast response signal generator is used to generate the maximum fast response signal according to the input voltage, trigger signal, load frequency signal and output voltage. The AND gate is used for generating the quick response signal according to the initial quick response signal and the maximum quick response signal. The compensator is used for generating a compensation signal according to the output voltage and the reference voltage. The interleaving logic circuit is used to generate interleaved signals according to the compensation signal, and each PWM signal generator is used to generate pulse width modulated signals according to the interleaved signals, the output voltage and the input voltage. Each OR gate is used for generating a PWM signal according to the fast response signal and the corresponding PWM generating signal. A plurality of power stages are used to generate an output voltage according to a plurality of PWM signals.

A method of operating a buck converter. The buck converter includes a fast response circuit, a compensator, an interleaved logic circuit, a plurality of pulse width modulation signal generators, a plurality of OR gates, a plurality of power stages, a plurality of inductors and an output capacitor. The compensator is coupled to the output end. The interleaving logic circuit is coupled to the compensator. Each PWM signal generator is respectively coupled to the interleaved logic circuit, the output terminal and the input terminal. Each OR gate is respectively coupled to a corresponding PWM signal generator. The plurality of power stages are coupled to the corresponding plurality of OR gates. Each inductor is coupled between the corresponding power stage and the output end. The output capacitor is coupled between the output terminal and the ground terminal. The quick response circuit includes a voltage droop sensor, a load frequency sensor, a quick response signal generator, a maximum quick response signal generator, and a gate. The voltage droop sensor is coupled to the output end. The load frequency sensor is coupled to the output end. The fast response signal generator is coupled to the voltage droop sensor. The maximum fast response signal generator is coupled to the voltage droop sensor, the load frequency sensor, the output terminal and the input terminal. The AND gate is coupled to the quick response signal generator, the maximum quick response signal generator and a plurality of OR gates. The operation method includes that the voltage droop sensor generates a trigger signal according to the voltage droop of the output voltage, the load frequency sensor outputs a load frequency signal according to the frequency of the load, and the quick response signal generator generates an initial quick response signal and a maximum quick response signal according to the trigger signal The signal generator generates the maximum fast response signal according to the input voltage, trigger signal, load frequency signal and output voltage, and the gate is based on the The initial fast response signal and the maximum fast response signal generate a fast response signal. The compensator generates a compensation signal according to the output voltage and the reference voltage. The interleaved logic circuit generates an interleaved signal according to the compensation signal. Each pulse width in a plurality of pulse width modulation signal generators The modulation signal generator generates a pulse width modulation signal according to the interleaved signal, output voltage and input voltage, and each OR gate in a plurality of OR gates generates a pulse width modulation signal according to the fast response signal and the corresponding pulse width modulation signal , and a plurality of power stages generate output voltages according to a plurality of PWM signals.

A maximum fast response signal generator, including a current source, a capacitor, a switch, a comparator and a flip-flop. The capacitor is coupled between the current source and the ground. The switch includes a first terminal coupled to the current source and a capacitor, a second terminal coupled to the ground terminal, and a control terminal. The comparator includes a positive input terminal coupled to the current source, a capacitor and the first terminal of the switch, a negative input terminal and an output terminal. The flip-flop includes an input terminal, a timing terminal, and an output terminal. The inverting output terminal is coupled to the control terminal of the switch, and the reset terminal is coupled to the output terminal of the comparator. The current source is used to generate current according to the input voltage and the load frequency signal. The comparator is used for outputting a reset signal at the output terminal of the comparator according to the response voltage received by the positive input terminal and the output voltage received by the negative input terminal. The flip-flop is used to output the maximum fast response signal at the output of the flip-flop according to the fixed voltage received by the input terminal, the trigger signal received by the timing terminal, and the reset signal received by the reset terminal.

A method of operating a maximum fast response signal generator. The maximum fast response signal generator includes current sources, capacitors, switches, comparators and flip-flops. The capacitor is coupled between the current source and the ground. The switch includes a first terminal coupled to the current source and a capacitor, a second terminal coupled to the ground terminal, and a control terminal. The comparator includes a positive input terminal coupled to the current source, a capacitor and the first terminal of the switch, a negative input terminal and an output terminal. The flip-flop includes an input terminal, a timing terminal, and an output terminal. The inverting output terminal is coupled to the control terminal of the switch, and the reset terminal is coupled to the output terminal of the comparator. The operation method includes the current source generating current according to the input voltage and the load frequency signal, and the comparator according to the response voltage received by the positive input terminal and the output voltage received by the negative input terminal. The output terminal of the comparator outputs a reset signal, and the flip-flop outputs the maximum quick response signal at the output terminal of the flip-flop according to the fixed voltage received by the input terminal, the trigger signal received by the timing terminal, and the reset signal received by the reset terminal.

100,900: buck converter

10,910: Quick response circuit

12: Voltage droop sensor

14: Load frequency sensor

16: Quick response signal generator

18: Maximum fast response signal generator

20: Compensator

30:Interleaved logic circuit

901,902: Transistor

903: buffer

904: Inverter

Ton1~TonN: PWM signal generator

OR1~ORN: OR gate

PS1~PSN: power stage

L1~LN: Inductance

AND: and gate

Vo: output voltage

Vin: input voltage

Vsen: trigger signal

Lo: load

Co: output capacitance

Fs: load frequency signal

I _Lo : load current

Isum: total inductor current

QRi: initial quick response signal

QRmax: maximum quick response signal

QR: Quick Response Signal

Vref: reference voltage

Vcomp: compensation signal

Vint: interlaced signal

PM1~PMN: pulse width modulation signal generation

PWM1~PWMN: pulse width modulation signal

OUT: output terminal

IN: input terminal

181: Current source

182: Comparator

C: Capacitance

S: switch

SR: flip-flop

GND: ground terminal

D: input terminal

R: reset terminal

CK: timing terminal

Q: output terminal

Qb: Inverse output terminal

Iqr: response current

Vqr: response voltage

t1~t8: time

T1~T4: period

700,800: method

S702~S720, S802~S806: steps

FIG. 1 is a schematic diagram of a buck converter according to an embodiment of the present invention.

Figure 2 is a schematic diagram of the maximum fast response signal generator in Figure 1.

Figure 3 is a timing diagram of the operating signals of the maximum fast response signal generator in Figure 2.

Figure 4 is a timing diagram of the operation signals of the step-down converter in Figure 1.

Fig. 5 is another operation signal timing diagram of the step-down converter in Fig. 1.

Fig. 6 is another operation signal timing diagram of the step-down converter in Fig. 1.

FIG. 7 is a flowchart of the operation method of the step-down converter in FIG. 1 .

FIG. 8 is a flowchart of the operation method of the maximum fast response signal generator in FIG. 2 .

FIG. 9 is a schematic diagram of a prior art buck converter with a fast response circuit.

Fig. 10 is a timing diagram of operation signals of the step-down converter in Fig. 9.

FIG. 1 is a schematic diagram of a buck converter 100 according to an embodiment of the present invention. The buck converter 100 is a DC-DC converter that reduces voltage, and the voltage at the output terminal OUT is lower than the input voltage Vin at the input terminal IN. The buck converter 100 may include a fast response circuit 10, a compensator 20, an interleaving logic circuit 30, a plurality of pulse width modulation signal generators Ton1~TonN, a plurality of OR gates OR1~ORN, a plurality of power stages PS1~PSN, A plurality of inductors L1˜LN, an output capacitor Co and a load Lo. The compensator 20 is coupled to the output terminal OUT. The interleaving logic circuit 30 is coupled to the compensator 20 . PWM signal The generators Ton1˜TonN are coupled to the interleave logic circuit 30, the input terminal IN and the output terminal OUT. The OR gates OR1˜ORN are coupled to the corresponding PWM signal generators Ton1˜TonN. The power stages PS1˜PSN are coupled to the corresponding OR gates OR1˜ORN. The inductors L1 -LN are coupled between the corresponding power stages PS1 -PSN and the output terminal OUT. The output capacitor Co is coupled between the output terminal OUT and the ground terminal GND. The load Lo is coupled between the output terminal OUT and the ground terminal GND. Wherein each PWM signal generator and power stage correspond to a phase, for example, the PWM signal generator Ton1 and the power stage PS1 correspond to the first phase, and the PWM signal generator Ton2 and the power stage PS2 correspond to the second phase. Two-phase, and so on.

The fast response circuit 10 includes a voltage droop sensor 12 , a load frequency sensor 14 , a fast response signal generator 16 , a maximum fast response signal generator 18 , and a gate AND. The voltage droop sensor 12 is coupled to the output terminal OUT. The load frequency sensor 14 is coupled to the output terminal OUT. The fast response signal generator 16 is coupled to the voltage droop sensor 12 . The maximum fast response signal generator 18 is coupled to the voltage droop sensor 12, the load frequency sensor 14, the input terminal IN and the output terminal OUT. The AND gates AND are coupled to the fast response signal generator 16 , the maximum fast response signal generator 18 and the OR gates OR1˜ORN.

The voltage droop sensor 12 is used for generating the trigger signal Vsen according to the voltage droop of the output voltage Vo. The load frequency sensor 14 is used for outputting a load frequency signal Fs according to the frequency of the load Lo. The quick response signal generator 16 is used for generating an initial quick response signal QRi according to the trigger signal Vsen. The maximum quick response signal generator 18 is used for generating the maximum quick response signal QRmax according to the input voltage Vin, the trigger signal Vsen, the load frequency signal Fs and the output voltage Vo. The AND gate AND is used for generating the quick response signal QR according to the initial quick response signal QRi and the maximum quick response signal QRmax. The compensator 20 is used for generating a compensation signal Vcomp according to the output voltage Vo and the reference voltage Vref. The interleave logic circuit 30 is used for generating the interleave signal Vint according to the compensation signal Vcomp. The pulse width modulation signal generators Ton1~TonN are used to generate pulse width modulation signals PM1~PMN according to the interleaving signal Vint, the output voltage Vo and the input voltage Vin. The OR gates OR1˜ORN are used for generating the PWM signals PWM1˜PWMN according to the quick response signal QR and the corresponding PWM generating signals PM1˜PMN. The power stages PS1~PSN are used to generate the output voltage Vo and provide the load current I _Lo to the load Lo according to the pulse width modulation signals PWM1~PWMN, and generate the total inductor current Isum in the inductors L1~LN. The pulse width modulation generating signals PM1˜PMN and the pulse width modulation signals PWM1˜PWMN respectively correspond to the first phase to the Nth phase.

For example, the frequency range of the load Lo of the buck converter 100 can be between 300Hz and 1MHz, the input voltage Vin can be between 6V and 24V, the output voltage Vo can be between 0.2V and 3.05V, and the fast response signal QR It can be 5V, and the load current I _Lo can be between 50A and 300A.

FIG. 2 is a schematic diagram of the maximum fast response signal generator 18 in FIG. 1 . The maximum fast response signal generator 18 includes a current source 181 , a capacitor C, a switch S, a comparator 182 and a flip-flop SR. The capacitor C is coupled between the current source 181 and the ground terminal GND. The switch S includes a first terminal coupled to the current source 181 and the capacitor C, a second terminal coupled to the ground terminal GND, and a control terminal. The comparator 182 includes a positive input terminal coupled to the current source 181 , the capacitor C and the first terminal of the switch S, and a negative input terminal coupled to the output terminal OUT. The flip-flop SR includes an input terminal D, a reset terminal R coupled to the output terminal of the comparator 182 , a timing terminal CK, an output terminal Q, and an inverted output terminal Qb coupled to the control terminal of the switch S. The current source 181 is used for generating a response current Iqr according to the input voltage Vin and the load frequency signal Fs. The comparator 182 is used for generating the reset signal Vrst according to the response voltage Vqr received by the positive input terminal and the output voltage Vo received by the negative input terminal. The flip-flop SR is used to output the maximum quick response signal QRmax at the output terminal Q according to the fixed voltage VHD received by the input terminal D, the trigger signal Vsen received by the timing terminal CK, and the reset signal Vrst received by the reset terminal R. The current source 181 can be realized by any semiconductor current mirror, and the switch S can be realized by a field-effect transistor.

FIG. 3 is a timing diagram of operating signals of the maximum fast response signal generator 18 in FIG. 2 . The process of generating the maximum quick response signal QRmax by the maximum quick response signal generator 18 is described below. At time t1, the trigger signal Vsen is pulled to a high level, so that the maximum fast response signal QRmax output by the output terminal Q of the flip-flop SR is also pulled to a high level. The response current Iqr starts to charge the capacitor C, and the response voltage Vqr starts to rise. At time t2, when the response voltage Vqr rises above the level of the output voltage Vo, the comparator 182 pulls the reset signal Vrst to a high level. The reset signal Vrst at a high level pulls the maximum rapid response signal QRmax output from the output terminal Q of the flip-flop SR to a low level, and pulls the signal output from the inverted output terminal Qb to a high level. The high level signal of the inverting output terminal Qb turns on the switch S, guides the response current Iqr to flow to the ground terminal GND, pulls the response voltage Vqr to a low level, and the reset signal Vrst also returns to a low level. Since the response time of the circuit is on the order of nanoseconds, the reset signal Vrst presents a pulse wave.

At time t3, the trigger signal Vsen is pulled to the high level again, and the whole circuit operation process is repeated, and so on. The entire circuit operation process can be repeated as required. The turn-on time of the maximum quick response signal QRmax is the time required for the response voltage Vqr to rise from the low level to the level of the output voltage Vo. It should be noted that the amplitude of the output voltage Vo is much smaller than the response voltage Vqr, so the level of the output voltage Vo appears to be fixed in the figure.

In addition, the current source 181 can adjust the response current Iqr according to the load frequency signal Fs and the input voltage Vin. The fixed voltage VHD can be a DC voltage, such as 5V, and can be used to make the high level of the maximum quick response signal QRmax output by the flip-flop SR equal to the fixed voltage VHD. The width of the maximum quick response signal QRmax can be expressed by the following formula:

Wherein QRmax is the maximum fast response signal width, C is the capacitance value, Vo is the output voltage, Vin is the input voltage, Rs is the resistance value of the current source 181, and Fs is the load frequency.

The width of the maximum fast response signal QRmax is the maximum width of the PWM signal that the buck converter 100 can withstand. If the pulse width modulation signal exceeds this width, the output voltage Vo will continue to rise and cause voltage overload (overvoltage). The application of the maximum fast response signal generator 18 can avoid the voltage overload situation.

FIG. 4 is a timing diagram of operation signals of the buck converter 100 in FIG. 1 . The process of generating the quick response signal QR by the quick response circuit 10 and applying it to the step-down converter 100 to provide the output voltage Vo and the load current I _Lo will be described below. At time t1, the load current I _Lo rises to a high current, causing the output voltage Vo to drop below the threshold. At this time, the voltage sag sensor 12 can generate the trigger signal Vsen, and send the trigger signal Vsen to the quick response signal generator 16 and the maximum quick response signal generator 18 to generate the initial quick response signal QRi and the maximum quick response signal respectively. QRmax. The quick response signal generator 16 can adjust the width of the initial quick response signal QRi according to the slope of the trigger signal Vsen. The initial quick response signal QRi and the maximum quick response signal QRmax are input into the AND gate. The AND gate AND performs an AND logic operation on the maximum quick response signal QRmax and the initial quick response signal QRi to generate a quick response signal QR. The quick response signal QR and the PWM generation signals PM1~PMN are respectively input into the corresponding OR gates OR1~ORN. The OR gates OR1~ORN perform an OR logic operation on the quick response signal QR and the corresponding pulse width modulation signal PM1~PMN to generate the pulse width modulation signal PWM1~PWMN. The pulse width modulation signals PWM1~PWMN simultaneously drive the power stages PS1~PSN to generate the output voltage Vo, and the total inductor current Isum generated by the inductors L1~LN starts to rise. At the same time, part of the total inductor current Isum flows to the output capacitor Co to charge the output capacitor Co, and another part of the current becomes the load current I _Lo flowing to the load Lo to provide the electric energy required by the load Lo. Operations of the power stages PS1 -PSN are well known to those skilled in the art, and will not be repeated here.

Between time t1 and time t2, at the beginning, the fast response signal QR signal quickly provides power to make the total inductor current Isum rise rapidly, and then because the output voltage Vo is still lower than the threshold value, the compensator 20 outputs a compensation signal Vcomp to make the interleaved logic circuit 30 Generate the interleaved signal Vint, and push the pulse width modulation signal generator Ton1~TonN to generate the pulse width modulation signal PM1~PMN in an interleaved manner, and the pulse width modulation signal PM1~PMN is the pulse width modulation signal PWM1~ PWMN. The pulse width modulation signals PWM1~PWMN drive the power stages PS1~PSN to continuously provide part of the load current I _Lo . At the same time, the output capacitor Co is discharged to provide another part of the load current I _Lo .

At time t2, the load current 1 _Lo drops to a low current, the output voltage Vo starts to rise, the inductors L1~LN start to discharge, and the total inductor current Isum starts to drop to a low current, until time t3, the load current I _Lo increases again. The circuit operation from time t3 to t4 is repeated for time t1 to t2.

From time t5 to t6, the load frequency increases. At this time, the quick response signal QR is the pulse width modulation signal PWM1~PWMN, and the pulse width modulation signal PWM1~PWMN simultaneously drives the power stage PS1~PSN to generate the output voltage Vo and provide the load Current I _Lo . Since the pulse width modulation signals PWM1~PWMN generated by the quick response signal QR have already provided sufficient power, the compensator 20 does not need to output the compensation signal Vcomp to enable the pulse width modulation signal generators Ton1~TonN to output pulse width modulation. Signals PM1~PMN are generated to drive power stages PS1~PSN to provide extra current. After the quick response signal QR is pulled to a low level, the inductors L1~LN start to discharge, and the total inductor current Isum starts to drop. Afterwards, the load current I _Lo drops to a low current, so that the output voltage Vo begins to rise, while the total inductor current Isum continues to drop until time t7, when the load current I _Lo increases again. Although the frequency of the operation period from time t7 to t8 and thereafter may be different, the operation process of the circuit basically repeats the operation period from time t5 to t6, and so on. Because the quick response circuit 10 of the present invention can control the width of the quick response signal QR, the total inductor current Isum can be pulled up again after falling back to the original level, so no extra energy accumulation will be caused, and the output voltage Vo will be It will not be pulled up more and more over time, so that the voltage overload situation can be avoided.

FIG. 5 is another timing diagram of operation signals of the buck converter 100 in FIG. 1 . FIG. 5 shows the total inductor current Isum and the quick response signal QR to help explain how to derive the width of the maximum quick response signal QRmax. The description is as follows: the total electric energy charged by inductors L1~LN in one cycle is:

The total electric energy discharged by the inductors L1~LN in one cycle is:

According to the law of energy conservation, the total electric energy charged by inductors L1~LN in one cycle is equal to the total electric energy discharged by inductors L1~LN:

Therefore, the maximum width of the PWM signal that the buck converter 100 can withstand can be derived from the following formula:

Among them, QRmax is the width of the maximum quick response signal, Vo is the output voltage, Vin is the input voltage, Fs is the load frequency, Ts is the load cycle, N is the number of phases, and L is the inductance value. It can be seen from the formula that the width of the maximum fast response signal can be determined according to the input voltage Vin, the output voltage Vo, and the load frequency.

FIG. 6 is another timing diagram of operation signals of the buck converter 100 in FIG. 1 . The high level time of the maximum quick response signal QRmax is the time required for the response voltage Vqr to rise from the low level to the output voltage Vo. In the period T1, the width of the initial quick response signal QRi is smaller than the width of the maximum quick response signal QRmax, so the quick response signal QR output by the quick response circuit 10 is the initial quick response signal QRi. In the period T2, the width of the initial quick response signal QRi is greater than the width of the maximum quick response signal QRmax, so the quick response signal QR output by the quick response circuit 10 is the maximum quick response signal QRmax. In period T3, the load frequency increases, and the maximum quick response signal generator 18 lowers the width of the maximum quick response signal QRmax due to the increase of the load frequency, so the quick response signal QR output by the quick response circuit 10 is the maximum quick response signal QRmax, to avoid Buck converter 100 experiences circuit overload. In period T4, the load frequency decreases, and the maximum quick response signal generator 18 increases the width of the maximum quick response signal QRmax due to the load frequency decrease, so the quick response signal QR output by the quick response circuit 10 is the initial quick response signal QRi. In this way, the width of the quick response signal QR can be adjusted in time according to the load frequency to avoid voltage overload and achieve the best energy efficiency.

FIG. 7 is a flowchart of a method 700 of operating the buck converter 100 of FIG. 1 . The method 700 includes the following steps: S702: the voltage droop sensor 12 generates a trigger signal Vsen according to the voltage droop of the output voltage Vo; S704: the load frequency sensor 14 outputs the load frequency signal Fs according to the frequency of the load Lo; S706: fast response signal The generator 16 generates an initial quick response according to the trigger signal Vsen Response signal QRi; S708: maximum quick response signal generator 18 generates maximum quick response signal QRmax according to input voltage Vin, trigger signal Vsen, load frequency signal Fs and output voltage Vo; S710: AND gate AND based on initial quick response signal QRi and The maximum quick response signal QRmax generates a quick response signal QR; S712: the compensator 20 generates a compensation signal Vcomp according to the output voltage Vo and the reference voltage Vref; S714: the interleaved logic circuit 30 generates an interleaved signal Vint according to the compensation signal Vcomp; S716: pulse width modulation Signal generators Ton1~TonN generate corresponding pulse width modulation signals PM1~PMN according to the interleaved signal Vint, output voltage Vo and input voltage Vin; S718: OR gates OR1~ORN according to the quick response signal QR and corresponding pulse width modulation Generate signals PM1~PMN to generate corresponding PWM signals PWM1~PWMN; and S720: Power stages PS1~PSN generate an output voltage Vo according to the PWM signals PWM1~PWMN.

The detailed description of the operation method 700 of the buck converter 100 can be found in the preceding paragraphs, and will not be repeated here.

FIG. 8 is a flowchart of a method 800 of operating the maximum fast response signal generator 18 of FIG. 2 . The method 800 includes the following steps: S802: The current source 181 generates a response current Iqr according to the input voltage Vin and the load frequency signal Fs; S804: The comparator 182 outputs a heavy current according to the response voltage Vqr received by the positive input terminal and the output voltage Vo received by the negative input terminal. set signal Vrst; and S806: The flip-flop SR outputs the maximum quick response signal at the output Q of the flip-flop SR according to the fixed voltage VHD received by the input terminal D, the trigger signal Vsen received by the timing terminal CK, and the reset signal Vrst received by the reset terminal R. QRmax.

The detailed description of the operation method 800 of the maximum fast response signal generator 18 can be found in the preceding paragraphs, and will not be repeated here.

To sum up, the step-down converter with fast response circuit of the present invention can effectively avoid the voltage overload problem that may occur in the general fast response circuit during the transient state of the load, and the total inductor current can be recovered after the total inductor current is reduced to the original level. will be pulled high again, so there will be no additional energy buildup. The output voltage will not be pulled higher and higher over time, thus avoiding voltage overload and improving the energy efficiency of the buck converter.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: Buck converter

10: Quick response circuit

12: Voltage droop sensor

14: Load frequency sensor

16: Quick response signal generator

18: Maximum fast response signal generator

20: Compensator

30:Interleaved logic circuit

Ton1~TonN: PWM signal generator

OR1~ORN: OR gate

PS1~PSN: power stage

L1~LN: Inductance

AND: and gate

Vo: output voltage

Vin: input voltage

Vsen: trigger signal

Lo: load

Co: output capacitance

Fs: load frequency signal

I _Lo : load current

Isum: total inductor current

QRi: initial quick response signal

QRmax: maximum quick response signal

QR: Quick Response Signal

Vref: reference voltage

Vcomp: compensation signal

Vint: interlaced signal

PM1~PMN: pulse width modulation signal generation

PWM1~PWMN: pulse width modulation signal

OUT: output terminal

IN: input terminal

Claims (20)

A buck converter, comprising: a fast response circuit, comprising: a voltage droop sensor, coupled to an output terminal, for detecting a voltage droop of an output voltage droop) and generate a trigger signal accordingly; a load frequency sensor (load frequency sensor), coupled to the output terminal, is used to detect a frequency of a load, and output a load frequency signal accordingly; a fast A response signal generator, coupled to the voltage droop sensor, for generating an initial quick response signal according to the trigger signal; a maximum quick response signal generator, coupled to the voltage droop sensor, the load frequency sensor A detector, the output terminal and an input terminal are used to generate a maximum fast response signal according to an input voltage, the trigger signal, the load frequency signal and the output voltage; and an AND gate, coupled to the fast response signal generation A device and the maximum fast response signal generator are used to generate a fast response signal according to the initial fast response signal and the maximum fast response signal; a compensator (compensator) is coupled to the output terminal and used to Voltage and a reference voltage generate a compensation signal; an interleaving logic circuit (interleaving logic), coupled to the compensator, is used to generate an interleaving signal according to the compensation signal; a plurality of pulse width modulation signal generators, each of which The pulse width modulation signal generator is respectively coupled to the interleaving logic circuit, the input terminal and the output terminal, and is used to generate a pulse width modulation signal according to the interleaving signal, the output voltage and the input voltage; a plurality of OR gates , wherein each OR gate is coupled to the AND gate of the fast response circuit and a corresponding pulse width modulation signal generator, and each OR gate is used according to the fast response signal and the corresponding A pulse width modulation generating signal generates a pulse width modulation signal; a plurality of power stages (power stages), each of which is coupled to a corresponding OR gate, is used to generate the pulse width modulation signal according to the corresponding output voltage; a plurality of inductors, each of which is coupled between a corresponding power stage and the output terminal; and an output capacitor, coupled between the output terminal and a ground terminal. The step-down converter as described in claim 1, wherein the initial quick response signal, the maximum quick response signal, the quick response signal, the pulse width modulation generation signal and the plurality of pulse widths generated by the plurality of OR gates The modulation signal is essentially a square wave signal. The step-down converter as claimed in claim 1, wherein the plurality of pulse width modulation signal generators generate the plurality of pulse width modulation generation signals in an interleaved manner. The step-down converter according to claim 1, wherein the fast response signal generator is further used to adjust a width of the initial fast response signal according to a slope of the trigger signal. The step-down converter as claimed in claim 1, wherein the maximum fast response signal generator is further used to adjust a width of the maximum fast response signal according to the input voltage, the output voltage and the load frequency signal. The step-down converter as claimed in claim 1, wherein the AND gate performs an AND logic operation on the maximum fast response signal and the initial fast response signal to generate the fast response signal. The buck converter as claimed in claim 1, wherein each OR gate responds to the fast response signal The OR logic operation is performed on the signal and the corresponding pulse width modulation generating signal to generate the pulse width modulation signal. The buck converter as claimed in claim 1, wherein the compensator generates the compensation signal when the output voltage drops below the reference voltage. The buck converter as described in claim 1, wherein the maximum fast response signal generator includes: a current source for generating a current according to the input voltage and the load frequency signal; a capacitor coupled to the current source and the ground terminal; a switch, including: a first terminal coupled to the current source and the capacitor; a second terminal coupled to the ground terminal; and a control terminal; a comparator for A reset signal is generated according to a response voltage and the output voltage, and the comparator includes: a positive input terminal coupled to the current source, the capacitor and the first terminal of the switch for receiving the response voltage; a negative input terminal for receiving the output voltage; and an output terminal for outputting the reset signal; and a flip-flop for generating the maximum fast response according to a fixed voltage, the trigger signal and the reset signal The signal includes: an input terminal for receiving the fixed voltage; a reset terminal coupled to the output terminal of the comparator for receiving the reset signal; a timing terminal for receiving the trigger signal; An output terminal is used to output the maximum fast response signal; and an inverting output terminal is coupled to the control terminal of the switch. An operation method of a Buck Converter, the Buck Converter includes a fast response circuit, a compensator, an interleaving logic circuit, a plurality of pulse width modulation signal generators, a plurality of OR gates, a plurality of power stage, a plurality of inductors and an output capacitor, the compensator is coupled to an output terminal, the interleaved logic circuit is coupled to the compensator, each pulse width modulation signal generator is respectively coupled to the interleaved logic circuit and An input terminal and the output terminal, each OR gate is respectively coupled to a corresponding pulse width modulation signal generator, a plurality of power stages are coupled to the corresponding plurality of OR gates, each inductance is coupled to a corresponding Between the power stage and the output terminal, the output capacitor is coupled between the output terminal and a ground terminal, the fast response circuit includes a voltage droop sensor, a load frequency sensor, a fast response signal generator device, a maximum fast response signal generator, and a gate, the voltage droop sensor is coupled to the output terminal, the load frequency sensor is coupled to the output terminal, the fast response signal generator is coupled to the The voltage droop sensor, the maximum fast response signal generator is coupled to the voltage droop sensor, the load frequency sensor, the output terminal and the input terminal, and the AND gate is coupled to the fast response signal generator , the maximum fast response signal generator and the plurality of OR gates, the method includes: the voltage droop sensor generates a trigger signal according to the voltage droop of an output voltage; the load frequency sensor outputs a frequency according to the load A load frequency signal; the quick response signal generator generates an initial quick response signal according to the trigger signal; the maximum quick response signal generator generates a maximum quick response signal according to an input voltage, the trigger signal, the load frequency signal and the output voltage a response signal; the AND gate generates a quick response signal according to the initial quick response signal and the maximum quick response signal; The compensator generates a compensation signal according to the output voltage and a reference voltage; the interleaved logic circuit generates an interleaved signal according to the compensation signal; each pulse width modulation signal generator in the plurality of pulse width modulation signal generators according to The interleaving signal, the output voltage and the input voltage generate a pulse width modulation signal; each OR gate in the plurality of OR gates generates a pulse width modulation signal according to the fast response signal and a corresponding pulse width modulation signal variable signal; and the plurality of power stages generates the output voltage according to the plurality of pulse width modulation signals. The method according to claim 10, wherein the initial quick response signal, the maximum quick response signal, the quick response signal, the pulse width modulation generation signal and the pulse width modulation signal are substantially square wave signals. The method as described in claim item 10, wherein the quick response signal generator generates the initial quick response signal according to the trigger signal, comprising: the quick response signal generator adjusts the initial quick response signal according to a slope of the trigger signal of a width. The method as claimed in claim 10 further comprises the plurality of pulse width modulation signal generators generating a plurality of pulse width modulation generation signals in an interleaved manner. The method as described in claim 10, wherein the maximum fast response signal generator generates the maximum fast response signal according to the input voltage, the trigger signal, the load frequency signal and the output voltage, including: the maximum fast response signal generator According to the input voltage, the trigger signal, the load frequency signal signal and the output voltage to adjust a width of the maximum fast response signal. The method as described in claim 10, wherein the AND gate generates the quick response signal according to the initial quick response signal and the maximum quick response signal, including: the AND gate generates the quick response signal to the maximum quick response signal and the initial quick response signal and logic operations are performed to generate the fast response signal. The method as described in claim 10, wherein each OR gate of the plurality of OR gates generates the PWM signal according to the fast response signal and the corresponding PWM generation signal, including: each OR gate The gate performs an OR logic operation on the fast response signal and the corresponding PWM generating signal to generate the PWM signal. The method according to claim 10, wherein the compensator receives the output voltage and the reference voltage and generates the compensation signal accordingly, comprising: when the output voltage drops below the reference voltage, the compensator generates the compensation signal . The method as described in claim 10, wherein the maximum fast response signal generator generating the maximum fast response signal according to the input voltage, the trigger signal, the load frequency signal and the output voltage includes: the maximum fast response signal generator includes A current source, a capacitor, a switch, a comparator and a flip-flop, the capacitor is coupled between the current source and the ground terminal, the switch includes a first terminal coupled to the current source and the capacitor , a second terminal coupled to the ground terminal, and a control terminal, the comparator includes a positive input terminal coupled to the first terminal of the current source, the capacitor and the switch, a negative input terminal and an output end, the flip-flop includes an input end, a reset end Coupled to the output terminal of the comparator, a timing terminal, an output terminal and an inverting output terminal coupled to the control terminal of the switch, the method includes: the current source generates according to the input voltage and the load frequency signal A current; the comparator outputs a reset signal at the output terminal of the comparator according to a response voltage received by the positive input terminal and the output voltage received by the negative input terminal; and the flip-flop receives a reset signal according to the input terminal A fixed voltage, the trigger signal received by the timing terminal, and the reset signal received by the reset terminal output the maximum quick response signal at the output terminal of the flip-flop. A maximum fast response signal generator, comprising: a current source, used to generate a response current according to an input voltage and a load frequency signal; a capacitor, coupled between the current source and a ground terminal; a switch, comprising : a first terminal, coupled to the current source and the capacitor; a second terminal, coupled to the ground terminal; and a control terminal; a comparator, used to generate a weight according to a response voltage and an output voltage A setting signal, the comparator includes: a positive input terminal coupled to the current source, the capacitor and the first terminal of the switch for receiving the response voltage; a negative input terminal for receiving the output voltage; and an output terminal for outputting the reset signal; and a flip-flop for generating a maximum fast response signal according to a fixed voltage, a trigger signal and the reset signal, including: an input terminal for receiving the fixed voltage; a reset terminal coupled to the output terminal of the comparator for receiving the reset signal; a timing terminal for receiving the trigger signal; an output terminal, It is used to output the maximum fast response signal; and an inverting output terminal is coupled to the control terminal of the switch. An operation method of a maximum fast response signal generator, the maximum fast response signal generator includes a current source, a capacitor, a switch, a comparator and a flip-flop, the capacitor is coupled to the current source and a ground terminal Between, the switch includes a first end coupled to the current source and the capacitor, a second end coupled to the ground end, and a control end, the comparator includes a positive input end coupled to the current source , the capacitor and the first end of the switch, a negative input end and an output end, the flip-flop includes an input end, a reset end coupled to the output end of the comparator, a timing end, and a The output terminal and an inverting output terminal are coupled to the control terminal of the switch, and the method includes: the current source generates a response current according to an input voltage and a load frequency signal; the comparator receives a response according to the positive input terminal voltage and an output voltage received by the negative input terminal to output a reset signal at the output terminal of the comparator; and the flip-flop receives a fixed voltage according to the input terminal, the timing terminal receives a trigger signal, and The reset signal received by the reset terminal outputs a maximum fast response signal at the output terminal of the flip-flop.

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