TWI787685B - Three-dimensional integrated circuit assembly and manufacturing method thereof - Google Patents

Abstract

A three-dimensional (3D) integrated circuit assembly and manufacturing method thereof are provided. A conductive adhesive (UV-curable) is coated on a surface of a wafer provided with through-silicon vias (TSVs) and a copper pillar bump array. A photomask is used to irradiate ultraviolet light on the conductive adhesive so that the adhesive layer in an area irradiated with ultraviolet light is cured and conductive particles in the area are in stable contact to form a conductive path, which is used to define a conductive area and a non-conductive area. After the wafer is cut into chips, any of the chips is picked up, and the chip is bonded upside down on a substrate by the conductive adhesive. Finally, a plurality of the chips are sequentially stacked from bottom to top on the chip of the substrate in the same manner to realize the three-dimensional integrated circuit assembly.

Description

Three-dimensional integrated circuit structure and manufacturing method thereof

The invention relates to the technical field of three-dimensional integrated circuit construction, in particular to the three-dimensional integrated circuit construction technology using copper pillar bumps as signal contacts.

With the continuous improvement of semiconductor process technology, the development of integrated circuit miniaturization technology has never stopped. However, in the pursuit of portability and more functions, the area of two-dimensional packaging is limited. To achieve a higher density, it must be stacked in a three-dimensional direction. Therefore, different components are vertically stacked and integrated in a three-dimensional Integrated circuit construction began to receive people's attention.

In the vertically stacked structure, the electrical connection of the three-dimensional integrated circuit is mainly realized by means of TSV technology and signal contact connection. In current technology, copper pillar bump (CPB) can be used as a signal contact in a three-dimensional integrated circuit assembly. This technique utilizes copper pillars as the main axis of conduction and also uses solder as the medium for bonding the copper pillars between different dies. However, with the advent of high-pin (I/O) and fine-pitch (fine pitch) products, under the trend of increasing I/O count and shrinking bump size, solderless copper pillar bumps have been developed. Bulk-to-copper pillar bump (copper-to-copper) direct bonding technology. The solderless copper-to-copper direct bonding technology uses high temperature, long time, and high-pressure bonding force to directly bond the copper pillar bumps between multiple chips to realize the electrical connection of the three-dimensional integrated circuit structure. sexual connection. However, this bonding method is prone to generate an oxide layer near the copper-to-copper contact surface, thereby affecting the electrical connection. In addition, the high joint force required by this method easily leads to the technical problem of warpage of the product.

The present invention proposes a three-dimensional integrated circuit structure and its manufacturing method, using a conductive adhesive layer (ultraviolet-curable) as a medium for bonding copper pillar bumps between the upper and lower wafers, and cooperating with lithography (lithography) procedures on the conductive adhesive The conductive area is formed in the layer, and the conductive area of the conductive adhesive layer is used as the conductive path between the upper and lower wafers in the three-dimensional integrated circuit structure. The present invention can realize a three-dimensional integrated circuit structure with fine pitch and narrow gap (2 μm/2 μm) between chips through the above technical solution.

In order to achieve the above object, the present invention proposes a three-dimensional integrated circuit structure, including: a substrate; a core chip group, the core chip group includes a plurality of chips, and the plurality of chips are stacked upside down on the substrate, wherein each of the plurality of chips is provided with a plurality of through-silicon vias filled with metal to communicate with the front and back sides of each of the chips; and a top chip, the top chip is set upside down on the core chip group ; Wherein each of the wafer and the top wafer is provided with a bump array and a conductive adhesive layer covering the bump array.

Preferably, the conductive adhesive layer includes a conductive area and a non-conductive area, and the projection of the conductive area on the substrate coincides with the projection of the bump array on the substrate.

Preferably, the bumps in the bump array are copper pillar bumps.

Preferably, an under-bump metal pad and a second metal pad are respectively provided on the front and back sides of each wafer corresponding to the positions of the TSVs, and the copper pillar bump array is arranged on the under-bump metal pad above.

Preferably, the bump array is bonded to the second metal pad of the underlying wafer or to the metal pad of the substrate through the conductive adhesive layer.

Preferably, the thickness of the conductive adhesive layer is between 0.5 and 1.5 microns.

Preferably, the height of each copper pillar bump in the copper pillar bump array is between 0.5 and 1.2 microns.

Preferably, the distance between the centers of each copper pillar bump in the copper pillar bump array is between 1.2 and 2 microns.

Preferably, the core chip set includes 2 to 9 chips that are inverted and stacked from bottom to top.

The present invention further proposes a manufacturing method of a three-dimensional integrated circuit assembly, which is used to solve the problem that the existing copper-to-copper direct bonding technology easily generates an oxide layer near the contact surface and affects the electrical connection, as well as the high voltage used during bonding. Together, the product structure is prone to warpage and other technical problems, and at the same time realizes the three-dimensional integrated circuit construction with fine pitch between the centers of bumps and narrow gaps (2 μm / 2 μm) between chips.

In order to achieve the above object, the present invention proposes a three-dimensional integrated circuit manufacturing method. The three-dimensional integrated circuit manufacturing method includes: coating a conductive glue on a wafer provided with through-silicon holes and copper pillar bump arrays; using The photomask irradiates ultraviolet light on the conductive glue to define the conductive area and the non-conductive area; the wafer is cut into a plurality of chips; one of the plurality of chips is picked up, and the The conductive glue bonds the chip upside down on a substrate; and bonds at least two of the plurality of chips upside down on the chip of the substrate.

Preferably, the conductive adhesive is configured to include: 3% by weight of a photoinitiator, 13.5% by weight of an oligomer, 13.5% by weight of a monomer, 69.94% by weight of silver powder, and 0.06% by weight parts of dispersant.

Preferably, the area of the photomask corresponding to the array of copper stud bumps is set as an opening area, and the rest is set as a light-shielding area, so that ultraviolet light can be irradiated through the opening area of the photomask to The conductive glue corresponds to the area of the copper stud bump array.

Preferably, it also includes performing a baking procedure on the substrate and the wafers disposed on the substrate.

Preferably, the baking temperature is between 130°C-150°C.

Please refer to FIG. 1 . FIG. 1 shows a cross-sectional structure of a three-dimensional integrated circuit assembly according to an embodiment of the present invention. The three-dimensional integrated circuit structure includes a top chip 300 , a substrate 100 , and a core chip set 200 between the top chip 300 and the substrate 100 . The top wafer 300 is arranged upside down on the core wafer group 200; the core wafer group 200 includes a plurality of wafers 201, and the plurality of wafers 201 are stacked upside down on the substrate 100; each of the A plurality of chips 201 are provided with a plurality of TSVs 2011 filled with metal to connect the front and back sides of each chip 201; each chip 201 and the top chip 300 are provided with a bump array and A conductive adhesive layer 202 covering the bump array.

In the present invention, the conductive adhesive layer 202 is used as the medium for bonding the bumps 2012 between the top chip 300 and each chip 201, which can avoid the copper pillar bump-to-copper pillar bump direct bonding technology using no solder due to the copper pillar The vicinity of the contact surface of the bump is not covered by the material, which is easy to generate an oxide layer and affect the technical problem of electrical connection. In addition, since the three-dimensional integrated circuit structure proposed by the present invention includes a conductive adhesive layer 202, the non-conductive region 2022 (please refer to FIG. 4 ) of the conductive adhesive layer 202 can be used as an encapsulant, thus eliminating the need for the integrated circuit Fill the underfill in the back-end process of the assembly.

In one embodiment, the bumps 2012 in the bump array are copper pillar bumps.

In one embodiment, an under-bump metal pad 2013 and a second metal pad 2014 are provided on the front and back sides of each chip 201 corresponding to the positions of the TSVs 2011, and the bump 2012 is provided on the bump Block under metal pad 2013 on top.

Please refer to FIG. 1 and FIG. 2 together. FIG. 2 shows a schematic cross-sectional view of a single chip in a three-dimensional integrated circuit structure according to an embodiment of the present invention. In one embodiment, the bumps 2012 of the chip 201 are bonded to the second metal pads 2014 of the underlying chip or to the first metal pads 1001 of the substrate 100 through the conductive adhesive layer 202 .

In one embodiment, the height of each bump 2012 in the bump array is between 0.5 and 1.2 microns. Preferably, the distance D2 between the top chip 300 and each chip 201 in the core chip set 200 in the three-dimensional integrated circuit structure is within 2 microns.

In one embodiment, the distance D1 between the centers of each bump 2012 in the bump array is between 1.2 and 2 microns. The conventional bump butt joint technology using solder has large solder joints, and the problem of solder overflow needs to be considered, so the distance between the centers of each bump is relatively large. In this embodiment, the conductive adhesive layer 202 is used as the medium for bonding the bumps 2012 between the top chip 300 and each chip 201 in the core chip group 200, and the conductive region 2021 is formed in the conductive adhesive layer 202 in cooperation with the photolithography process to realize The conductive adhesive layer 202 is used as the conductive path between the upper and lower wafers, thereby achieving a three-dimensional integrated circuit structure in which the center-to-center distance D1 of each bump 2012 is within 2 microns. In one embodiment, the core chip set 200 includes 2 to 9 chips that are inverted and stacked from bottom to top. The actual number is determined according to the product design, preferably 3-5.

In one embodiment, the thickness of the conductive adhesive layer 202 is between 0.5 and 1.5 microns. Preferably it is 1 micron. When the conductive adhesive layer 202 is evenly coated and its thickness is thin, the stress generated by it is relatively small.

Please refer to FIG. 3 . FIG. 3 shows a schematic diagram of a three-dimensional integrated circuit structure viewed from above the conductive adhesive layer 202 according to an embodiment of the present invention. In one embodiment, the conductive adhesive layer 202 of each of the plurality of chips includes a conductive area 2021 and a non-conductive area 2022, and the projection of the conductive area 2021 on the substrate coincides with the projection of the bump array on the substrate. , to implement the conductive adhesive layer 202 as the conductive path between the upper and lower wafers.

Continuing from the above, for a clearer description, please also refer to FIG. 4 . FIG. 4 is a schematic diagram of the photolithography process of the conductive adhesive layer 202 of the three-dimensional integrated circuit structure according to the embodiment of the present invention. Utilize an ultraviolet light source 10 to irradiate ultraviolet light 12 through a photomask 11 on the conductive adhesive layer 202, and the area where the conductive adhesive layer 202 is irradiated by the ultraviolet light 12 undergoes a chemical reaction and is cured, so that the conductive particles in this area are in stable contact with each other. Form a conductive path. Wherein, the area not irradiated by the ultraviolet light 12 is the non-conductive area 2022 , in this way the conductive area 2021 and the non-conductive area 2022 of the conductive adhesive layer 202 can be defined.

Please refer to the flow chart shown in Figure 5, the present invention further proposes a three-dimensional integrated circuit manufacturing method, including:

S101: Coating a conductive adhesive layer on the wafer provided with TSVs and copper pillar bump arrays.

Preferably, the TSVs are formed by laser drilling or etching. The metal filled in the TSV is copper, which is preferably formed by physical vapor deposition (PVD) or sputtering. The copper pillar bump array is formed through procedures such as under bump metallurgy (UBM) sputtering, dry film lamination and exposure, dry film development, copper plating, film stripping, and UBM etching.

S102: Using a photomask to irradiate ultraviolet light on the conductive adhesive layer to define conductive areas and non-conductive areas.

The area of the photomask corresponding to the array of copper stud bumps is set as an opening area, and the rest is set as a light shielding area for allowing ultraviolet light to irradiate the conductive glue through the opening area of the photomask An area corresponding to the copper pillar bump array.

S103: Cut the wafer into a plurality of wafers.

S104: Then use a die bonder to pick up one of the plurality of chips, and use the conductive adhesive layer to bond the chip upside down on a substrate. In one embodiment, sticking The bonding force of the crystal is preferably set between 50-100 Newtons (N), and the optimum bonding force value must be adjusted according to the thickness of the conductive adhesive layer. In a preferred embodiment of the present invention, when the thickness of the conductive adhesive layer is 1 micron, the pressing force is set to 50N to achieve a better adhesion effect. The present invention utilizes the conductive adhesive layer 202 as the bonding medium for the bumps 2012 between the top chip 300 and each chip 201 in the core chip set 200, which can avoid direct solder-free copper pillar bumps to copper pillar bumps. In the joining technology, due to the high pressing force that must be used during the joining, the product structure is prone to warpage and other technical problems.

In one embodiment, when using a wafer bonding machine to stack and bond wafers on a substrate, it is preferable to design the alignment reference point (fiducial mark) on the edge of the substrate, and design the alignment reference point on the substrate instead of designing it on the substrate. On the wafer, it can avoid the product tilt problem caused by the accumulation of offset when the wafer is stacked.

S105: bonding another three wafers upside down on the wafer of the substrate.

S106: Perform a baking procedure on the substrate and the wafers disposed on the substrate. In one embodiment, the baking temperature is set to 145°C.

In a preferred embodiment, the conductive adhesive is an ultraviolet (UV) curable conductive adhesive, and its components mainly include: photoinitiator, oligomer, monomer, silver powder and the like. The photoinitiator is preferably 2-methyl-4'-(methylthio)-2-morpholinoacetophenone (2-methyl-4'-(methylthio)-2-morpholinopropiophenone). The oligomer is preferably polyurethane resin or acrylic resin. The monomer is preferably 2-hydroxyethyl acrylate (2-hydroxyethyl acrylate). The above ingredients are formulated into UV-curable resin according to the ratio of 10%, 45%, and 45%, and the UV-curable resin is mixed with silver powder according to the ratio of 3:7, and a dispersant of 0.06% by weight of silver powder is added to prepare The ultraviolet light curing conductive adhesive.

The present invention uses the above-mentioned technical means to coat conductive adhesive on the surface of the wafer provided with TSVs and copper pillar bump arrays to form a conductive adhesive layer, and uses photolithography to define conductive regions and In the non-conductive area, after the wafer is cut into wafers, any one of the wafers is picked up, and bonded on a substrate upside down through the conductive adhesive layer, and then on the wafer of the substrate with In the same manner, multiple chips are sequentially stacked to realize the three-dimensional integrated circuit structure.

The three-dimensional integrated circuit structure and its manufacturing method proposed by the present invention introduce a conductive adhesive layer (ultraviolet-curable) as a bump bonding medium between the top chip and each chip in the core chip group, and cooperate with the photolithography process in the conductive The conductive area is formed in the adhesive layer, and the conductive adhesive layer is used as the conductive path between the upper and lower wafers in the three-dimensional integrated circuit structure, so as to solve the problem of the large distance between the centers of the bumps in the conventional solder bump technology. , the large gap between the upper and lower chips, and solder overflow and other technical problems, thus achieving a three-dimensional integrated circuit structure with a fine pitch between the centers of the bumps and a narrow gap (2 μm / 2 μm) between the chips. In addition, it can also solve the warping of the product structure caused by the need to use high-pressure joint force in the conventional copper pillar bump-to-copper pillar bump direct bonding technology without solder, and the lack of material coverage near the joint makes the copper pillar The technical problem that the oxide layer is easily formed between the bumps and affects the electrical connection. In addition, since the three-dimensional integrated circuit structure proposed by the present invention has been introduced into the conductive adhesive layer in the front-end process, the non-conductive area of the conductive adhesive layer can be used as an encapsulant, thus eliminating the need for a subsequent process in the three-dimensional integrated circuit structure. Fill the primer (underfill).

10: UV light source 11: Mask 12: Ultraviolet light 100: Substrate 1001: the first metal pad 200: Core Chipset 201: chip 2011: TSV 2012: bump 2013: Metal pad under bump 2014: Second Metal Pad 2021: Conductive Zone 2022: Non-conductive area 202: Conductive adhesive layer 300: top wafer D1: the distance between the centers of each bump D2: the distance between each chip

FIG. 1 is a schematic cross-sectional view of a three-dimensional integrated circuit structure according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of a single chip in a three-dimensional integrated circuit structure according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of a three-dimensional integrated circuit structure according to an embodiment of the present invention, viewed from above the conductive adhesive layer.

FIG. 4 is a schematic diagram of the photolithography process of the conductive adhesive layer of the three-dimensional integrated circuit structure according to the embodiment of the present invention.

FIG. 5 is a flow chart of manufacturing a three-dimensional integrated circuit assembly according to an embodiment of the present invention.

100: Substrate

1001: the first metal pad

200: Core Chipset

201: chip

2011: TSV

2012: bump

2013: Metal pad under bump

2014: Second Metal Pad

202: Conductive adhesive layer

300: top wafer

D1: the distance between the centers of each bump

D2: the distance between each chip

Claims (10)

A three-dimensional integrated circuit structure, comprising: a substrate; a core chip group, the core chip group includes a plurality of chips, the plurality of chips are stacked upside down on the substrate, wherein each of the plurality of chips A plurality of through-silicon vias filled with metal are provided to communicate with the front and back sides of each of the chips; and a top chip is set upside down on the core chip group; wherein each of the chips and A bump array and a UV-curable conductive adhesive layer covering the bump array are arranged on the front side of the top wafer, and the thickness of the UV-curable conductive adhesive layer is between 0.5 microns and 1.5 microns, wherein the The UV-curable conductive adhesive layer includes a conductive area and a non-conductive area, and the projection of the conductive area on the substrate coincides with the projection of the bump array on the substrate. The three-dimensional integrated circuit structure according to claim 1, wherein the bumps in the bump array are copper pillar bumps. The three-dimensional integrated circuit structure according to claim 2, wherein the front and back sides of each chip are respectively provided with under-bump metal pads and second metal pads corresponding to the positions of the through-silicon vias, and the copper post bumps A block is disposed over the under bump metal pad. The three-dimensional integrated circuit structure according to claim 3, wherein the bump array is bonded to the second metal pad of the underlying wafer or to the metal pad of the substrate through the UV-curable conductive adhesive layer join. The three-dimensional integrated circuit structure as claimed in claim 2, wherein the height of each bump in the bump array is between 0.5 and 1.2 microns. The three-dimensional integrated circuit structure as claimed in claim 2, wherein the distance between the centers of each bump in the bump array is between 1.2 and 2 microns. The three-dimensional integrated circuit assembly as claimed in claim 1, wherein the core chip set includes 2 to 9 chips that are inverted and stacked from bottom to top. A method for manufacturing a three-dimensional integrated circuit, comprising: coating a UV-curable conductive adhesive on a wafer provided with TSVs and copper pillar bump arrays to form a UV-curable conductive adhesive layer, the UV-curable The thickness of the cured conductive adhesive layer is between 0.5 microns and 1.5 microns; using a photomask to irradiate ultraviolet light on the UV-curable conductive adhesive layer to define conductive areas and non-conductive areas; the wafer cutting into a plurality of wafers; picking up one of the plurality of wafers, and bonding the wafer upside down on a substrate through the UV-curable conductive adhesive layer; At least two of the plurality of wafers are bonded upside down on the wafer. The three-dimensional integrated circuit manufacturing method as described in Claim 8, wherein the area of the photomask corresponding to the copper pillar bump array is set as an opening area, and the rest is set as a light-shielding area to prevent ultraviolet rays Light is irradiated to a region of the conductive glue corresponding to the copper stud bump array through the opening region of the photomask. The method for manufacturing a three-dimensional integrated circuit according to claim 8 further includes performing a baking process on the substrate and the wafers stacked on the substrate.

Images