TWI787089B - Semiconductor device - Google Patents

Abstract

A semiconductor device includes a substrate, a driving circuit layer, a memory device and a staircase structure. The memory device includes conductive layers and insulating layers alternating stacked over the conductive layers, bit lines over the conductive layers and the insulating layers, and channel layers through the conductive layers and the insulating layers. The staircase structure is disposed on the substrate and electrically connected to the memory device and the driving circuit layer. The driving circuit layer includes a capacitor structure. The capacitor structure includes a doped portion in the substrate, a first electrode, a first dielectric layer, a second electrode, and a second dielectric layer. The first electrode is disposed on the doped portion, and the bottom portion of the first electrode is within the doped portion. The first dielectric layer is disposed between the first electrode and the doped portion. The second electrode is disposed on the first electrode and a bottom surface of the bottom portion of the second electrode is below a top surface of the substrate. The second dielectric layer is disposed between the first electrode and the second electrode.

Description

semiconductor element

The present disclosure relates to a semiconductor device.

In recent years, the structure of semiconductor elements has been constantly changing, and the storage capacity of semiconductor elements has been increasing. Semiconductor components are used in storage components of many products such as MP3 players, digital cameras, and computer files. As these applications increase, semiconductor elements require larger capacitances to stabilize voltages. In order to satisfy this condition, a semiconductor element having a high capacitance value and a method of manufacturing the same are required.

One technical aspect of the present disclosure is a semiconductor device.

According to some embodiments of the present disclosure, a semiconductor device includes a substrate, a driving circuit layer, a memory device, and a ladder structure. The memory element is located on the substrate. The memory element includes a plurality of conductive layers and a plurality of insulating layers stacked alternately, a plurality of bit lines on the conductive layer and the insulating layer, and a plurality of channel layers passing through the conductive layer and the insulating layer, and each of the channel layers are respectively electrically connected to the bit lines. The ladder structure is located on the substrate, and the ladder structure is electrically connected to the memory element and the driving circuit layer. The driving circuit layer includes a capacitive structure, and the capacitive structure includes a doped part in the substrate, a first electrode, a first dielectric layer, a second electrode and a second dielectric layer. The first electrode is located on the doped portion of the substrate. The first electrode has a bottom portion and a top portion, wherein the bottom portion of the first electrode is located in the doped portion of the substrate. The first dielectric layer is between the first electrode and the doped portion of the substrate. The second electrode is located on the first electrode, wherein the second electrode has a bottom portion and a top portion, the bottom portion of the second electrode is embedded in the first electrode, and the bottom surface of the bottom portion of the second electrode is below the top surface of the substrate. The second dielectric layer is located between the first electrode and the second electrode.

In some embodiments of the present disclosure, the first electrode is wider than the second electrode.

In some embodiments of the present disclosure, a part of the highest top surface of the first electrode is covered by the second electrode, and the rest of the highest top surface of the first electrode is not covered by the second electrode.

In some embodiments of the present disclosure, the thickness of the second electrode is greater than that of the first electrode.

In some embodiments of the present disclosure, the capacitor structure further includes a first doped region and a second doped region located in the substrate, and the doped portion of the substrate further has a portion located between the first doped region and the first electrode .

In some embodiments of the present disclosure, the first dielectric layer contacts the doped portion of the substrate, the first doped region, the second doped region and the first electrode, and the second dielectric layer contacts the first electrode and the second electrode .

In some embodiments of the present disclosure, the capacitor structure further includes a spacer. A spacer is located on a sidewall of the top portion of the second electrode and is separated from the bottom portion of the second electrode.

Another technical aspect of the present disclosure is a semiconductor device.

According to some embodiments of the present disclosure, a semiconductor device includes a substrate, a driving circuit layer, a memory device, and a ladder structure. The memory element is located on the substrate. The memory device includes a plurality of conductive layers and a plurality of channel layers passing through the conductive layers. The ladder structure is located on the substrate, the ladder structure includes a first conductive contact, a second conductive contact and an interconnection structure, the first conductive contact is connected to the interconnection structure and the driving circuit layer, and the second conductive contact is connected to the conductive structure of the interconnection structure and the memory element one of the layers. The driving circuit layer includes a capacitive structure, and the capacitive structure includes a doped part in the substrate, a first electrode and a second electrode. The first electrode is located on the doped portion of the substrate, wherein the lowest bottom surface of the first electrode is below the highest top surface of the doped portion of the substrate. The second electrode is located on the first electrode, the first electrode surrounds the second electrode, the lowest bottom surface of the second electrode is below the highest top surface of the first electrode, and the highest top surface of the first electrode is the highest top surface of the second electrode. Do not overlap.

In some embodiments of the present disclosure, the capacitor structure further includes a first dielectric layer and a second dielectric layer. The first dielectric layer is located between the doped portion of the substrate and the first electrode. The second dielectric layer is located between the first electrode and the second electrode.

In some embodiments of the present disclosure, the capacitor structure further includes a third dielectric layer. The third dielectric layer is located on the second electrode and separated from the first dielectric layer.

According to the above embodiments of the present disclosure, since the doped portion of the substrate can be regarded as a lower electrode and the first electrode can be regarded as an upper electrode, and the first electrode can be regarded as another lower electrode and the second electrode can be regarded as another upper electrode. Through the above configuration, the capacitance value of the capacitor structure can be increased. In addition, the space occupied by the capacitor structure in the semiconductor element can also be reduced.

The following will disclose multiple implementations of the present disclosure with diagrams, and for the sake of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present disclosure. That is to say, in some embodiments of the present disclosure, these practical details are unnecessary, and thus should not be used to limit the present disclosure. In addition, for the sake of simplifying the drawings, some well-known structures and components will be shown in a simple and schematic manner in the drawings. In addition, for the convenience of readers, the size of each element in the drawings is not drawn according to actual scale.

"About," "approximately," or "substantially" as used herein shall generally mean within twenty percent, preferably within ten percent, and more preferably within five percent of a given value or range . Numerical values given herein are approximate, meaning that the meaning of the terms "about", "approximately" or "substantially" can be inferred if not expressly stated.

FIG. 1A shows a perspective view of a semiconductor device 100 according to some embodiments of the present disclosure, and FIG. 1B shows a top view of FIG. 1A . The semiconductor device 100 includes a substrate 102 , a driving circuit layer 104 , a memory device 110 and a ladder structure 120 . The driving circuit layer 104 is located above the substrate 102 . The memory element 110 is located on the substrate 102 . The ladder structure 120 is located on the substrate 102 , and the ladder structure 120 is electrically connected to the memory device 110 and the driving circuit layer 104 .

The substrate 102 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (eg, with p-type or n-type doping) or undoped. The semiconductor material of the substrate 102 may include silicon, germanium, compound semiconductors, alloy semiconductors, or combinations thereof. The aforementioned compound semiconductors include silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide. The aforementioned alloy semiconductors include SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/or GaInAsP.

The driving circuit layer 104 is at least used for providing electrical signals to the conductive layer 111 of the memory device 110 (ie, the word line). The driving circuit layer 104 may be a circuit under array (CuA) layer. In some embodiments, the driving circuit layer 104 includes a plurality of active components (such as transistors), passive components (such as capacitor structures), or other electronic components.

The memory device 110 includes a conductive layer 111 , a channel layer 112 , an insulating layer 113 and a bit line 116 . The conductive layer 111 and the insulating layer 113 are alternately stacked in the memory device 110 in the planes of the direction X and the direction Y. The conductive layer 111 can be regarded as a gate layer or a word line layer. In some embodiments, the conductive layer 111 includes metal (such as tungsten) or other suitable conductive materials, and the insulating layer 113 may include oxides, such as silicon oxide or other suitable dielectric materials. The memory device 110 may include a common source (such as the common source 260 in FIG. 3 ) located between the driving circuit layer 104 and the bottommost insulating layer 113 . Each of the channel layers 112 includes a string of memory cells and is electrically connected to the bit lines 116 through corresponding conductive vias 115 . The channel layer 112 is electrically connected to the common source and the bit line 116 through the stack of the conductive layer 111 and the insulating layer 113 . In some embodiments, the channel layer 112 includes multiple layers, such as a tunneling layer, an electron harvesting layer, and a blocking layer. The tunneling layer may comprise silicon oxide, or a combination of oxide, nitride, and oxide (eg, ONO). The electron harvesting layer may include silicon nitride (SiN) or other materials capable of harvesting electrons. The barrier layer can include silicon oxide, aluminum oxide, and/or combinations thereof. The portion of the conductive layer 111 contacting the outer surface of the channel layer 112 can be regarded as the gate of the memory device 110 . The filling material (eg, tunneling layer, electron harvesting layer, barrier layer, and polysilicon) in each channel layer 112 intersecting the conductive layer 111 can form a string of memory cells along a vertical direction (eg, direction Z).

In some embodiments, a string select line (String Select Line, SSL) 114 can be formed between the conductive layer 111 and the bit line 116, and the string select line 114 controls the electrical connection between the channel layer 112 and the corresponding bit line 116. sexual connection. In some other embodiments, the topmost layer of the conductive layer 111 is used as a string selection line, and the rest of the conductive layer 111 is used as a word line. In some embodiments, as shown in FIG. 1B , the conductive layer 111 further includes a conductive slit 130 . For the conductive slit 130 , a trench is first formed in the conductive layer 111 , and a dielectric layer (such as an oxide layer) is formed on the sidewall and bottom of the trench. Next, the dielectric layer at the bottom of the trench is removed, and a conductive material is filled in the trench to be electrically connected to the underlying common source. Therefore, the common source can be externally connected to a via the conductive slit 130. Source signal source. The conductive slit 130 may comprise the same material as the conductive layer 111 (eg, tungsten).

The ladder structure 120 includes a conductive contact 122 , an interconnection structure 123 and a conductive contact 124 . The ladder structure 120 of the semiconductor device 100 is configured to electrically connect the conductive layer 111 to the driving circuit layer 104 . The stepped structure 120 of the semiconductor device 100 can be used as an extension of the memory device 110 , so that each of the conductive layers 111 can be respectively connected to the corresponding conductive contacts 124 at the landing area 126 . Specifically, the conductive contact 122 connects the interconnection structure 123 and the driving circuit layer 104 , and the conductive contact 124 connects the interconnection structure 123 and the landing area 126 of the conductive layer 111 . Conductive contact 122 may be considered a through-array contact, and conductive contact 124 may be considered a word line contact. The conductive contact 122 and the conductive contact 124 are electrically connected to each other through the interconnection structure 123 . In some embodiments, the conductive layer 111 extends from the memory device 110 to the stepped structure 120 and has a landing pad electrically connected to the conductive contact 124 . In some embodiments, the semiconductor device 100 includes an insulating structure 128 formed above the memory device 110 and the stepped structure 120 , the insulating structure 128 covers the landing area 126 and surrounds a portion of the conductive contact 122 and the conductive contact 124 .

FIG. 2 is a schematic diagram of a semiconductor device 200 including a capacitor structure 250 according to some embodiments of the present disclosure. The semiconductor device 200 includes a substrate 202 , a driving circuit layer 204 , a memory device 210 and a ladder structure 220 . The driving circuit layer 204 is located above the substrate 202 , and the driving circuit layer 204 includes a capacitor structure 250 . The memory device 210 is located above the substrate 202 . The ladder structure 220 is located above the substrate 202 , and the ladder structure 220 is electrically connected to the driving circuit layer 204 and the memory device 210 . The ladder structure 220 includes a conductive layer 221 , a conductive contact 222 , an interconnection structure 223 and a conductive contact 224 . The conductive layers 221 extend from the memory device 210 into the stepped structure 220 , and each of the conductive layers 221 can be respectively connected to the corresponding conductive contacts 224 at the landing area 226 . The conductive contact 222 connects the interconnection structure 223 and the capacitive structure 250 of the driving circuit layer 204 , and the conductive contact 224 connects the interconnection structure 223 and the landing area 226 of the conductive layer 221 . In some embodiments, the memory device 210 corresponds to the memory device 110 of FIGS. 1A and 1B . For example, the memory device 210 may include the conductive layer 111 , the channel layer 112 , the insulating layer 113 , the string selection line 114 , the conductive via 115 and the bit line 116 of the memory device 110 in FIG. 1A and FIG. 1B . The ladder structure 220 is electrically connected to the memory element 210 and the capacitor structure 250 . In detail, the capacitor structure 250 is electrically connected to the memory device 210 through the conductive contact 222 of the ladder structure 220 , the interconnection structure 223 , the conductive contact 224 and the conductive layer 221 .

It should be understood that the configuration and materials of the substrate 202, the memory element 210, and the stepped structure 220 (including the conductive contact 222, the interconnection structure 223, and the conductive contact 224) in FIG. 2 are similar to those of the substrate 102 in FIGS. 1A and 1B. , the configuration and materials of the memory element 110 and the ladder structure 120 (including the conductive contact 122 , the interconnection structure 123 , and the conductive contact 124 ), so the description will not be repeated in the following description.

FIG. 3 is a schematic diagram of a semiconductor device 200 a including a capacitor structure 250 a according to another embodiment of the disclosure. As shown in FIG. 3 , the semiconductor device 200 a includes a substrate 202 , a driving circuit layer 204 , a memory device 210 and a ladder structure 220 . The driving circuit layer 204 is located above the substrate 202 , and the driving circuit layer 204 includes a capacitive structure 250 a, wherein a part of the capacitive structure 250 a is located in the substrate 202 , and another part of the capacitive structure 250 a is located in the driving circuit layer 204 . The memory device 210 is located above the substrate 202 . The ladder structure 220 is located above the substrate 202 , and the ladder structure 220 is electrically connected to the driving circuit layer 204 and the memory device 210 . The ladder structure 220 includes a conductive layer 221 , an interconnect structure 223 , a conductive contact 224 , a conductive contact 228 , an interconnect structure 230 and a common source 260 extending from the memory device 210 . In some embodiments, the configurations of the substrate 202 , the conductive layer 221 , the conductive contacts 224 , the interconnection structure 223 , and the memory device 210 are similar to those of the embodiment shown in FIG. 2 , so the following description will not be repeated.

As shown in FIG. 3 , the driving circuit layer 204 including the capacitive structure 250 a is disposed under the memory element 210 , and the driving circuit layer 204 including the capacitive structure 250 a is electrically connected through the conductive contact 228 of the ladder structure 220 and the interconnection structure 230 to the memory device 210 (for example, the conductive layer 111 in the memory device 110 of FIG. 1A ).

FIG. 4 shows a cross-sectional view of a semiconductor structure 300 according to some embodiments of the present disclosure, and FIG. 5A shows a top view of the capacitor structure C1 of the semiconductor structure 300 in FIG. 4 in the first region 322, wherein FIG. 4 Capacitor structure C1 is a cross-sectional view along line 4-4 in FIG. 5A. FIG. 5B shows a top view along the line segment 5B-5B in FIG. 4, and FIG. 6 shows a top view of the peripheral element C2 of the semiconductor structure 300 in FIG. 4 in the second region 324, wherein the periphery of FIG. 4 Component C2 shows a cross-sectional view along line 4'-4' in FIG. 6 . The capacitive structure C1 of the semiconductor structure 300 in FIGS. 4 to 6 may correspond to the capacitive structure 250 in FIG. 2 or the capacitive structure 250 a in FIG. 3 . That is to say, the capacitive structure C1 of the semiconductor structure 300 in FIGS. 4 to 6 is disposed on the substrate 302 of the semiconductor element, and is electrically connected to the memory element 210 in FIGS. 2 and 3, wherein the substrate 302 corresponds to The substrate 202 of FIG. 2 and FIG. 3 . The peripheral element C2 of the semiconductor structure 300 may connect to different conductive contacts in the ladder structure 220 with the capacitor structure C1 . The semiconductor structure 300 can be disposed on the driving circuit layer 204 in FIGS. 2 and 3 or the driving circuit layer 104 in FIG. 1A, and the semiconductor structure 300 has a first region 322 and a second region 324, wherein the capacitor structure C1 is located in the first region 322 And the peripheral element C2 is located in the second area 324 . The capacitor structure C1 includes a doped portion 306 in the substrate 302 , a first electrode 330 , a first dielectric layer 360 , a second electrode 340 and a second dielectric layer 370 . The first electrode 330 is located on the doped portion 306 of the substrate 302 , and the first electrode 330 has a bottom portion 332 and a top portion 334 , wherein the bottom portion 332 of the first electrode 330 is located in the substrate 302 . The second electrode 340 is located on the first electrode 330 , wherein the second electrode 340 has a bottom portion 342 and a top portion 344 . The bottom portion 342 of the second electrode 340 is embedded in the first electrode 330 , and the bottom surface 341 of the bottom portion 342 of the second electrode 340 is below the highest top surface 303 of the substrate 302 . The first dielectric layer 360 is located under the first electrode 330 and between the doped portion 306 of the substrate 302 and the first electrode 330 . The second dielectric layer 370 is located between the first electrode 330 and the second electrode 340 . In some embodiments of the present disclosure, the doped portion 306 of the substrate 302, the first dielectric layer 360 and the first electrode 330 are regarded as a first capacitor, and the first electrode 330, the second dielectric layer 370 and the second electrode 340 is regarded as the second capacitor. That is, the doped portion 306 of the substrate 302 is the lower electrode of the first capacitor and the first electrode 330 is the upper electrode of the first capacitor, while the first electrode 330 is the lower electrode of the second capacitor and the second electrode 340 is the second electrode. The upper electrode of the capacitor. Through the above configuration, the capacitance value of the capacitance structure C1 can be increased. In addition, the space occupied by the capacitor structure C1 in the semiconductor device (such as the semiconductor device 200 in FIG. 2 or the semiconductor device 200 a in FIG. 3 ) can also be reduced.

The top portion 334 of the first electrode 330 of the capacitive structure C1 extends outward from the bottom portion 332 . The top portion 334 of the first electrode 330 protrudes from the top portion 344 of the second electrode 340 . Specifically, the vertical projection of the top portion 344 of the second electrode 340 on the substrate 302 is located within the vertical projection of the top portion 334 of the first electrode 330 on the substrate 302 . In addition, the vertical projection of the bottom portion 342 of the second electrode 340 on the substrate 302 is also located within the vertical projection of the bottom portion 332 of the first electrode 330 on the substrate 302 . In some embodiments, the lowest bottom surface 341 of the second electrode 340 is below the highest top surface 335 of the first electrode 330 . The top portion 344 of the second electrode 340 has a bottom surface 343 directly above the highest top surface 335 of the first electrode 330 . The highest top surface 345 of the top portion 344 of the second electrode 340 partially covers the top portion 334 of the first electrode 330 . That is, a portion of the highest top surface 335 of the first electrode 330 is covered by the bottom surface 343 of the top portion 344 of the second electrode 340, while the rest of the highest top surface 335 of the first electrode 330 is not covered by the top of the second electrode 340. The bottom surface 343 of the sub-section 344 is covered. In some embodiments, the bottom portion 332 and the top portion 334 of the first electrode 330 have different shapes. For example, the bottom portion 332 of the first electrode 330 has a U-shaped profile, while the top portion 334 of the first electrode 330 has a rectangular profile.

In some embodiments, the first electrode 330 and the second electrode 340 have different cross-sectional shapes. The bottom portion 342 and the top portion 344 of the second electrode 340 may have a rectangular profile but have different thicknesses and widths. In some embodiments, the bottom portion 332 of the first electrode 330 has a first thickness T1, and the second electrode 340 has a second thickness T2, wherein the second thickness T2 is greater than the first thickness T1. For example, the first thickness T1 of the bottom portion 332 of the first electrode 330 is in the range of about 700 angstroms (Å) to about 900 angstroms (for example, 800 Å), and the second thickness T2 of the second electrode 340 is about 1100 Å. Angstroms to about 1300 Angstroms (eg, 1200 Angstroms). When the first thickness T1 of the bottom portion 332 of the first electrode 330 and the second thickness T2 of the second electrode 340 are between the above-mentioned ranges, the second electrode 340 may have the bottom portion 342 and the second thickness filled in the first electrode 330 The top portion 344 above the first electrode 330 to ensure that the second electrode 340 can be located above the first electrode 330 and form a stepped sidewall at the junction of the bottom portion 342 and the top portion 344 of the second electrode 340, thereby increasing the capacitance structure C1 The capacitance value of the second capacitor. In addition, since the junction of the first electrode 330 and the doped portion 306 of the substrate 302 has a stepped sidewall, the capacitance of the first capacitor of the capacitor structure C1 can be increased.

In some embodiments, as shown in FIG. 4 and FIG. 5B , the first electrode 330 of the capacitive structure C1 is wider than the second electrode 340 . The first electrode 330 of the capacitive structure C1 has a merged portion 336 in a top view, so that a conductive contact (eg, the conductive contact 400 ) can be disposed on the first electrode 330 . The merged portion 336 of the capacitive structure C1 has a width W1 less than 1600 Angstroms.

In some embodiments, the substrate 302 has doped regions 304a and 304b. And the doped regions 304a and 304b have the same electrical properties. In some embodiments, the doped portion 306 of the substrate 302 and the doped regions 304 a and 304 b have dopants of different conductivity types. For example, doped portion 306 includes an N-type dopant such as P or As, while doped regions 304a and 304b are P containing a P-type dopant such as boron or boron difluoride (BF ₂ ). Type heavily doped region (P+). Alternatively, the doped portion 306 of the substrate 302 includes P-type dopants, while the doped regions 304a and 304b are heavily N-type doped regions (N+). In some embodiments, the top surfaces 305 of the doped regions 304 a and 304 b are below the highest top surface 335 of the first electrode 330 . In some embodiments, the doped portion 306 of the substrate 302 further has areas A1 and A2, the area A1 is located between the doped region 304a and the first electrode 330, and the area A2 is located between the doped area 304b and the first electrode. Between 330. The highest top surface 307 of the doped portion 306 of the substrate 302 is above the lowest bottom surface 331 of the first electrode 330 .

The semiconductor structure 300 includes an isolation structure 350 within a substrate 302 . The isolation structure 350 adjoins and contacts the doped regions 304 a and 304 b of the substrate 302 . The isolation structure 350 may be a shallow trench isolation (STI) structure to define and electrically isolate active regions, thereby preventing leakage current from flowing between adjacent active regions.

In some embodiments, the first dielectric layer 360 contacts the doped portion 306, the doped regions 304a and 304b, the isolation structure 350 and the first electrode 330, and the second dielectric layer 370 contacts the first electrode 330 and the second electrode 340. In some embodiments, the isolation structure 350 has sidewalls 351 above the doped regions 304 a and 304 b , and the first dielectric layer 360 covers the entirety of the sidewalls 351 of the isolation structure 350 .

The capacitor structure C1 includes a first spacer 380 and a second spacer 390 . The first spacer 380 is located on the sidewall 337 of the top portion 334 of the first electrode 330 and separated from the bottom portion 332 of the first electrode 330 , and the first spacer 380 is located directly above the doped regions 304 a and 304 b of the substrate 302 . The first spacer 380 contacts the first electrode 330 , the first dielectric layer 360 and the second dielectric layer 370 . The second spacer 390 is located on the sidewall 347 of the top portion 344 of the second electrode 340 and separated from the bottom portion 342 of the second electrode 340 . The second spacer 390 contacts the second electrode 340 and the second dielectric layer 370 , and the second spacer 390 and the first electrode 330 are separated by the second dielectric layer 370 .

The capacitor structure C1 of the semiconductor structure 300 includes a conductive contact 400 electrically connected to the first electrode 330 and a conductive contact 410 electrically connected to the second electrode 340 . In some embodiments, different voltages are applied to conductive contact 400 than to conductive contact 410 . For example, the conductive contact 400 electrically connected to the first electrode 330 is connected to the power signal (VDD), and the conductive contact 410 electrically connected to the second electrode 340 is grounded. In addition, the capacitive structure C1 includes a conductive contact 420 electrically connected to the doped regions 304 a and 304 b of the substrate 302 . The conductive contact 420 has the same potential as the conductive contact 410 electrically connected to the second electrode 340 . In other words, the conductive contact 420 electrically connected to the doped regions 304a and 304b and the conductive contact 400 electrically connected to the first electrode 330 of the capacitive structure C1 have different potentials, so that the doped portions adjacent to the doped regions 304a and 304b A potential difference is generated between 306 and the first electrode 330 to form a first capacitor. Likewise, since the conductive contacts 400 and 410 have different potentials, a potential difference is generated between the first electrode 330 and the second electrode 340 to form a second capacitor.

In some embodiments, the semiconductor structure 300 includes an interlayer dielectric (ILD) layer 375 . The interlayer dielectric layer 375 surrounds the conductive contacts 400 , 410 and 420 and covers the isolation structure 350 , the first dielectric layer 360 , the second dielectric layer 370 and the second electrode 340 .

The peripheral element C2 of the semiconductor structure 300 includes a doped portion 306 a of the substrate 302 , a dielectric layer 360 a on the substrate 302 , a first conductive structure 330 a and a second conductive structure 340 a above the first conductive structure 330 a. In addition, the peripheral device C2 further includes doped regions 304c and 304d located in the substrate 302, and the doped portion 306a is located between the doped regions 304c and 304d. In some embodiments, the peripheral element C2 is regarded as another capacitive structure, the conductive structure of the peripheral element C2 (the first conductive structure 330a and the second conductive structure 340a ) is regarded as the upper electrode, and the doped portion 306a of the substrate 302 is regarded as lower electrode. In some other implementations, the peripheral element C2 is regarded as a transistor, the conductive structure of the peripheral element C2 (the first conductive structure 330a and the second conductive structure 340a ) is regarded as the gate, and the doped regions 304c and 304d are regarded as the source /drain, and the doped portion 306a of the substrate 302 is regarded as a channel.

The second conductive structure 340a covers the first conductive structure 330a. Specifically, the vertical projection of the second conductive structure 340 a on the substrate 302 overlaps with the vertical projection of the first conductive structure 330 a on the substrate 302 . The second conductive structure 340a is aligned with the first conductive structure 330a in the vertical direction. Specifically, the sidewall 349 of the second conductive structure 340a is substantially flush with the sidewall 339 of the first conductive structure 330a. In some embodiments, the first conductive structure 330a and the second conductive structure 340a have the same shape. For example, both the first conductive structure 330a and the second conductive structure 340a have a rectangular outline. In some embodiments, the highest top surface 348 of the second conductive structure 340 a of the peripheral element C2 is substantially flush with the highest top surface 345 of the second electrode 340 of the capacitor structure C1 .

In some embodiments, the dielectric layer 360a of the peripheral device C2 is located under the first conductive structure 330a, and the dielectric layer 360a contacts the substrate 302, the doped regions 304c and 304d, the isolation structure 350, and the first conductive structure 330a. The dielectric layer 360 a of the peripheral element C2 only partially covers the sidewall 351 of the isolation structure 350 . That is, at least part of the sidewall 351 of the isolation structure 350 is not covered by the dielectric layer 360a. In some embodiments, the peripheral element C2 includes a spacer 390a, and the spacer 390a is formed on the sidewall 339 of the first conductive structure 330a and the sidewall 349 of the second conductive structure 340a. The spacer 390a contacts the dielectric layer 360a, the first conductive structure 330a and the second conductive structure 340a.

In some embodiments, peripheral element C2 includes conductive contacts 400a and 420b. The conductive contact 400 a is electrically connected to the second conductive structure 340 a , the conductive contact 420 a is electrically connected to the doped region 304 c of the substrate 302 , and the conductive contact 420 b is electrically connected to the doped region 304 d of the substrate 302 . In an embodiment where the peripheral element C2 is a capacitor structure, the conductive contact 420a electrically connected to the doped region 304c has the same potential as the conductive contact 420b electrically connected to the doped region 304d. In an embodiment where the peripheral element C2 is a transistor, the conductive contact 420a electrically connected to the doped region 304c and the conductive contact 420b electrically connected to the doped region 304d have different potentials. In the second region 324 , the interlayer dielectric layer 375 surrounds the conductive contacts 400 a , 420 a and 420 b and covers the isolation structure 350 , the dielectric layer 360 a and the second conductive structure 340 a.

FIG. 7A to FIG. 70 are cross-sectional views of various steps in the method of fabricating the semiconductor structure 300 according to some embodiments of the present disclosure.

Referring to FIG. 7A, a dielectric layer 360a, a conductive layer 330a' and a mask layer 430 are sequentially formed on the substrate 302. Referring to FIG. Next, the mask layer 430, the conductive layer 330a', the dielectric layer 360a and the substrate 302 are etched to form the first recess R1. In some embodiments, as shown in FIG. 7A , the first recess R1 exposes the central portion and the edge portion of the substrate 302 in the first region 322 , and the first recess R1 exposes the edge portion of the substrate 302 in the second region 324 . The substrate 302 has a doped portion 306 located in the first region 322 and a doped portion 306 a located in the second region 324 . In some embodiments, the dielectric layer 360a includes oxide, such as silicon oxide or other suitable dielectric materials. The conductive layer 330a' may include semiconductor material (such as polysilicon), metal or other suitable conductive materials. The mask layer 430 may include nitride, such as silicon nitride or other suitable dielectric materials. In some embodiments, the dielectric layer 360a, the conductive layer 330a' and/or the mask layer 430 are formed by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), Formed by flowable chemical vapor deposition (FCVD), low pressure chemical vapor deposition (LPCVD) or other suitable deposition methods. In some embodiments, etching the mask layer 430, the conductive layer 330a', the dielectric layer 360a, and the substrate 302 may use dry or wet etching.

Referring to FIG. 7A and FIG. 7B , a dielectric material is filled in the first recess R1 to form an isolation structure 350 . In some embodiments, after the isolation structure 350 is formed, a planarization process, such as a chemical mechanical polishing process (CMP), is performed to remove a part of the isolation structure 350 so that the top surface of the isolation structure 350 is aligned with the top surface of the mask layer 430 The surface is roughly even. In some embodiments, the isolation structure 350 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials. The isolation structure 350 can be formed by high density plasma deposition (HDP), chemical vapor deposition (CVD), atomic layer deposition (ALD) or other suitable deposition methods.

Referring to FIG. 7B and FIG. 7C, after the isolation structure 350 is formed, the mask layer 430 is removed, so that the top surface t1 of the conductive layer 330a' and the sidewall of the isolation structure 350 are exposed. In some embodiments, phosphoric acid (H ₃ PO ₄ ) or other suitable etchant may be used to etch the mask layer 430 .

Referring to FIG. 7D, the isolation structure 350 is etched back so that the top surface 353 of the isolation structure 350 is close to the top surface t1 of the conductive layer 330a'. In some embodiments, the top surface 353 of the isolation structure 350 is above the top surface t1 of the conductive layer 330a'. In some other embodiments, the top surface 353 of the isolation structure 350 is substantially flush with the top surface t1 of the conductive layer 330a'. Etching the isolation structure 350 may use wet etching or other suitable etching methods.

Referring to FIG. 7E , a patterned photoresist layer 440 is formed in the first region 322 and the second region 324 . In the first region 322, the patterned photoresist layer 440 covers a part of the isolation structure 350 and exposes the conductive layer 330a'; in the second region 324, the patterned photoresist layer 440 covers the isolation structure 350 and the conductive layer 330a' of the whole. The patterned photoresist layer 440 can be formed by suitable deposition, development and/or etching techniques. Next, using the patterned photoresist layer 440 as an etching mask, the isolation structure 350 and the conductive layer 330a' not covered by the patterned photoresist layer 440 are etched to form the second recess R2 in the first region 322 to expose The substrate 302 and the isolation structure 350 in the first region 322 . In detail, the second recess R2 exposes the surface 355 of the isolation structure 350 and the sidewall 351 perpendicular to the surface 355 and extending upward, wherein the surface 355 of the isolation structure 350 is substantially flush with the highest top surface 303 of the substrate 302 .

Referring to FIG. 7E and FIG. 7F, after forming the second recess R2, the photoresist layer 440 is removed. The photoresist layer 440 can be removed by using a photoresist stripping process, such as an ashing process, an etching process, or other suitable processes. Next, a first dielectric layer 360 is formed conformally in the first region 322 and the second region 324 . In the first region 322, the first dielectric layer 360 covers the isolation structure 350 and the substrate 302; in the second region 324, the first dielectric layer 360 covers the isolation structure 350 and the conductive layer 330a'. In some embodiments, the first dielectric layer 360 has a thickness T3 in the range of about 350 angstroms to 450 angstroms (eg, 400 angstroms). In some embodiments, the first dielectric layer 360 includes oxide, such as silicon oxide or other suitable dielectric materials. The first dielectric layer 360 may include the same material as the dielectric layer 360a. The first dielectric layer 360 can be deposited by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), flowable chemical vapor deposition (FCVD), low pressure chemical vapor deposition (LPCVD) or other suitable deposition methods.

Referring to FIG. 7G , a first conductive layer 330 ′ is formed over the first dielectric layer 360 . In the first region 322, the lowest bottom surface 331 of the first conductive layer 330′ is below the highest top surface 357 of the isolation structure 350; The first thickness T1 of the bottom portion 332' of the first conductive layer 330' (corresponding to the first thickness T1 of the bottom portion 332 of the first electrode 330 in FIG. 800 Angstroms). If the first thickness T1 of the bottom part 332' of the first conductive layer 330' is greater than 900 angstroms, the process cost of manufacturing the capacitor structure will be too high; if the first thickness T1 of the bottom part 332' of the first conductive layer 330' is less than When it is 700 angstroms, the resistance value of the subsequently formed capacitor (the capacitor structure C1 in FIG. 4 ) will be too high, so that the capacitor cannot achieve the desired effect. The first conductive layer 330' may include semiconductor material (such as polysilicon), metal or other suitable conductive materials. In some embodiments, the first conductive layer 330' and the conductive layer 330a' comprise the same material (such as polysilicon). In some embodiments, the first conductive layer 330' is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other suitable deposition methods.

Referring to FIG. 7H, after forming the first conductive layer 330', a planarization process is performed to remove parts of the first conductive layer 330' and the first dielectric layer 360, wherein the planarization process stops at the first dielectric layer 360. In detail, in the first region 322 , the planarization process exposes the isolation structure 350 , the first dielectric layer 360 and the first conductive layer 330 ′, so that the highest top surface of the isolation structure 350 and the highest surface of the first dielectric layer 360 The top surface is substantially flush with the highest top surface of the first conductive layer 330'; in the second region 324, the planarization process exposes the isolation structure 350 and the first dielectric layer 360, so that the top surface of the isolation structure 350 is aligned with the first dielectric layer. The top surface of the electrical layer 360 is substantially flush and there is no first conductive layer 330 ′ in the second region 324 .

Referring to FIG. 7I , the second dielectric layer 370 is formed conformally in the first region 322 and the second region 324 . In the first region 322 , the second dielectric layer 370 covers the isolation structure 350 , the first dielectric layer 360 and the first conductive layer 330 ′; in the second region 324 , the second dielectric layer 370 covers the isolation structure 350 and the first conductive layer 330 ′. The first dielectric layer 360 . In some embodiments, the second dielectric layer 370 has a thickness T4 in the range of about 350 angstroms to 450 angstroms (eg, 400 angstroms). The thickness T4 of the second dielectric layer 370 is substantially equal to the thickness T3 of the first dielectric layer 360 . In some embodiments, the second dielectric layer 370 includes oxide, such as silicon oxide or other suitable dielectric materials. The second dielectric layer 370 may include the same material as the first dielectric layer 360 and/or the dielectric layer 360a. The second dielectric layer 370 can be deposited by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), flowable chemical vapor deposition (FCVD), low pressure chemical vapor deposition (LPCVD) or other suitable deposition methods.

Referring to FIG. 7I and FIG. 7J, a patterned photoresist layer 450 is formed in the first region 322, wherein the patterned photoresist layer 450 covers a part of the second dielectric layer 370, and there is no photoresist layer 450 . The patterned photoresist layer 450 can be formed by suitable deposition, development and/or etching techniques. Next, using the patterned photoresist layer 450 as an etching mask, etch the second dielectric layer 370 not covered by the patterned photoresist layer 450, so as to expose the isolation structure 350, the first dielectric layer in the first region 322, etc. The electrical layer 360 and the first conductive layer 330'. In addition, in the second region 324, the first dielectric layer 360 and the second dielectric layer 370 are removed to expose the isolation structure 350 and the conductive layer 330a'.

Referring to FIGS. 7J and 7K, the photoresist layer 450 in the first region 322 is removed to expose the underlying second dielectric layer 370 . The photoresist layer 450 can be removed by using a photoresist stripping process, such as an ashing process, an etching process, or other suitable processes. Next, a second conductive layer 340' is formed in the first region 322 and the second region 324. Referring to FIG. The second thickness T2 of the second conductive layer 340' (corresponding to the second thickness T2 of the second electrode 340 in FIG. 4 ) is greater than the first thickness T1 of the bottom portion 332' of the first conductive layer 330', wherein the second conductive The second thickness T2 of the layer 340' is in the range of about 1100 angstroms to about 1300 angstroms (eg, 1200 angstroms). If the second thickness T2 of the second conductive layer 340' is greater than 1300 angstroms, the process cost of manufacturing the capacitor structure will be too high; The resistance value of the capacitive structure C1) in the figure will be too high, and the second conductive layer 340' may not be able to fill the opening O1 in the first conductive layer 330', so that the top surface of the second conductive layer 340' cannot accommodate conductive contacts (eg The conductive contact 410 in FIG. 4 ), so that the capacitance cannot achieve the expected effect. The second conductive layer 340' may include semiconductor material (such as polysilicon), metal or other suitable conductive materials. The second conductive layer 340' may include the same material as the first conductive layer 330' (such as polysilicon). In some embodiments, the second conductive layer 340' is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other suitable deposition methods.

Referring to FIG. 7K and FIG. 7L , a patterned photoresist layer 460 is formed in the first region 322 and the second region 324 . In the first region 322, the patterned photoresist layer 460 covers a part of the second dielectric layer 370; in the second region 324, the patterned photoresist layer 460 covers a part of the second conductive layer 340'. The patterned photoresist layer 460 can be formed by suitable deposition, development and/or etching techniques. Next, using the patterned photoresist layer 460 as an etching mask, the second conductive layer 340' not covered by the patterned photoresist layer 460 is etched. In the first region 322, the first conductive layer 330' and the second conductive layer 340' are etched to define the first electrode 330 and the second electrode 340, and expose the isolation structure 350, the first dielectric layer 360 and the first electrode 330 . The sidewall 337 of the first electrode 330 and the sidewall 347 of the second electrode 340 are also exposed. In addition, in the second region 324, the conductive layer 330a' and the second conductive layer 340' are etched to define the first conductive structure 330a and the second conductive structure 340a, and expose the isolation structure 350 and the dielectric layer 360a. Subsequently, the substrate 302 is doped to form doped regions 304 a and 304 b located in the first region 322 and doped regions 304 c and 304 d located in the second region 324 in the substrate 302 .

In some embodiments of the present disclosure, the etch process of FIG. 7L defines capacitive structure C1. Specifically, the capacitor structure C1 includes a first capacitor and a second capacitor, the doped portion 306 of the substrate 302 is the lower electrode of the first capacitor, the first electrode 330 is the upper electrode of the first capacitor and the lower electrode of the second capacitor, And the second electrode 340 is the upper electrode of the second capacitor. In addition, the etch process of FIG. 7L defines peripheral element C2. In some embodiments where the peripheral element C2 is regarded as a transistor, the conductive structures of the peripheral element C2 (the first conductive structure 330a and the second conductive structure 340a ) are regarded as gates, and the doped regions 304c and 304d are regarded as source/drain electrodes. pole, and the doped portion 306a of the substrate 302 is considered a channel. In some embodiments where the peripheral element C2 is regarded as another capacitive structure, the conductive structures of the peripheral element C2 (the first conductive structure 330a and the second conductive structure 340a ) are regarded as the upper electrode, and the doped portion 306a of the substrate 302 is regarded as the upper electrode. lower electrode.

Referring to FIG. 7L and FIG. 7M, the photoresist layer 460 is removed to expose the second electrode 340 in the first region 322 and the second conductive structure 340a in the second region 324 . The photoresist layer 460 can be removed by using a photoresist stripping process, such as an ashing process, an etching process, or other suitable processes. Next, a first spacer 380 and a second spacer 390 are formed in the first region 322 and a spacer is formed in the second region 324 . In detail, in the first region 322, the first spacer 380 is formed on the opposite sidewall 337 of the first electrode 330 and the second spacer 390 is formed on the opposite sidewall 339 of the second electrode 340; in the second region 324 In this case, a spacer 390a is formed on the opposite sidewall 339 of the first conductive structure 330a and the opposite sidewall 349 of the second conductive structure 340a. The first spacer 380, the second spacer 390, and the spacer _390a may comprise one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, _SiCN , _SiCxOyNz , or combinations thereof. The first spacer 380, the second spacer 390, and the spacer 390a can be deposited by plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), sub-atmospheric pressure chemical vapor deposition (SACVD), or other suitable The deposition method is formed.

In some embodiments, the doped regions 304 a - 304 d of FIG. 7L are lightly doped regions (LDDs). After the first spacer 380 , the second spacer 390 and the spacer 390 a are formed, an ion implantation process is performed to dope the lightly doped region. Then, an annealing process may be performed to activate the implanted dopants in the doped regions 304a to 304d. In this case, the doped regions 304a to 304d are heavily doped to form heavily doped regions, wherein the doped regions 304a to 304d and the substrate 302 have dopants of different conductivity types.

An interlayer dielectric (ILD) layer 375 is formed over the substrate 302 . In the first region 322, the interlayer dielectric layer 375 covers the isolation structure 350, the first dielectric layer 360, the second dielectric layer 370, and the second electrode 340; in the second region 324, the interlayer dielectric layer 375 covers the isolation structure 350, a dielectric layer 360a, and a second conductive structure 340a. In some embodiments, the interlayer dielectric layer 375 includes silicon oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluoride silicon glass (FSG), or other suitable dielectric materials. The interlayer dielectric layer 375 may include silicon oxynitride, silicon nitride, compounds including Si, O, C, and/or H (for example, silicon oxide, SiCOH, and SiOC), low dielectric constant dielectric materials (dielectric constant Dielectric materials with a thermal silicon oxide of less than about 3.9) or organic materials such as polymers. The ILD layer 375 can be formed by chemical vapor deposition (CVD), high density plasma deposition (HDP) or other suitable deposition methods. In some embodiments, after forming the interlayer dielectric layer 375 , a planarization process is performed to remove a portion of the interlayer dielectric layer 375 .

Referring to FIG. 7N, after forming the interlayer dielectric layer 375, the interlayer dielectric layer 375 is etched to form contact openings 405, 405a, 415, 425 and 425a. In the first region 322, the contact opening 405 exposes the first electrode 330, the contact opening 415 exposes the second electrode 340 and the contact opening 425 exposes the doped regions 304a and 304b; in the second region 324, the contact opening 405a exposes the second conductive Structure 340a and contact opening 425a expose doped regions 304c and 304d.

Referring to FIG. 7N and FIG. 7O, the interlayer dielectric layer 375 is continuously etched to form a plurality of trenches in the interlayer dielectric layer, and the trenches are respectively connected to the contact openings 405, 405a, 415, 425, and 425a. In some embodiments, the etching process includes an etching step using plasma etching and using a suitable etchant, such as a fluorine-containing etchant, to selectively etch the ILD layer 375 .

Returning to FIG. 4, after the etching process in FIG. 7O is completed, conductive material is filled in the trenches and contact openings 405, 405a, 415, 425, and 425a to form conductive contacts 400, 400a, 410, 420a, and 420b. Subsequently, a planarization process is performed to remove excess portions of the conductive material so that the conductive contacts 400, 400a, 410, 420a, and 420b are coplanar. Specifically, in the first region 322, the conductive contact 400 is formed on the first electrode 330, the conductive contact 410 is formed on the second electrode 340, and the conductive contact 420 is formed on the doped regions 304a and 304b; in the second region In 324, a conductive contact 400a is formed on the second conductive structure 340a, a conductive contact 420a is formed on the doped region 304c, and a conductive contact 420b is formed on the doped region 304d. In this way, a semiconductor structure 300 as shown in FIG. 4 can be obtained.

FIG. 8 shows a cross-sectional view of a semiconductor structure 500 according to another embodiment of the present disclosure, FIG. 9 shows a top view of the capacitor structure C1' of the semiconductor structure 300 of FIG. The top view of the peripheral element C2' of the semiconductor structure 300, wherein the capacitor structure C1' in FIG. 8 shows the cross-sectional view along the line 8-8 in FIG. Sectional view along line 8'-8'. The capacitor structure C1' of the semiconductor structure 500 in FIGS. 8 to 10 may correspond to the capacitor structure 250 in FIG. 2 or the capacitor structure 250a in FIG. 3 . That is to say, the capacitive structure C1' of the semiconductor structure 500 in FIGS. 8 to 10 is disposed on the substrate 502 of the semiconductor element, and is electrically connected to the memory element 210 in FIGS. 2 and 3, wherein the substrate 502 corresponds to Substrate 202 in FIGS. 2 and 3 . The peripheral element C2' of the semiconductor structure 500 may be connected to different conductive contacts in the ladder structure 220 with the capacitor structure C1'. The semiconductor structure 500 can be disposed on the driving circuit layer 204 in FIGS. 2 and 3 or the driving circuit layer 104 in FIG. 1A , and the semiconductor structure 300 has a first region 522 and a second region 524 , wherein. The capacitor structure C1' is located in the first area 522 and the peripheral element C2' is located in the second area 524. The capacitive structure C1' includes a doped portion 506 in a substrate 502, a first electrode 530, a first dielectric layer 560, a second electrode 540, and a second dielectric layer 370. The first electrode 530 is located on the doped portion 506 of the substrate 502, and the first electrode 530 has a bottom portion 532 and a top portion 534, wherein the bottom portion 532 of the first electrode 530 is located in the substrate 502, and the second electrode 540 is located on the first on the electrode 530. The top portion 534 of the first electrode 530 surrounds the second electrode 540 , and the lowest bottom surface 541 of the second electrode 540 is below the highest top surface 535 of the first electrode 530 . The first dielectric layer 560 is located under the first electrode 530 and between the doped portion 506 of the substrate 502 and the first electrode 530 . The second dielectric layer 570 is located between the first electrode 530 and the second electrode 540 . The highest top surface 535 of the first electrode 530 does not overlap with the highest top surface 545 of the second electrode 540 . In some embodiments of the present disclosure, the doped portion 506 of the substrate 502, the first dielectric layer 560 and the first electrode 530 are regarded as a first capacitor, and the first electrode 530, the second dielectric layer 570 and the second electrode 540 is regarded as the second capacitor. That is, the doped portion 506 of the substrate 502 is the lower electrode of the first capacitor and the first electrode 530 is the upper electrode of the first capacitor, while the first electrode 530 is the lower electrode of the second capacitor and the second electrode 540 is the second electrode. The upper electrode of the capacitor. Through the above configuration, the capacitance value of the capacitance structure C1' can be increased. In addition, the space occupied by the capacitor structure C1' in the semiconductor device (such as the semiconductor device 200 in FIG. 2 or the semiconductor device 200a in FIG. 3 ) can also be reduced.

The first electrode 530 of the capacitive structure C1' has a bottom portion 532 and a top portion 534. The bottom portion 532 of the first electrode 530 is located below the second electrode 540 , and the width of the bottom portion 532 of the first electrode 530 is wider than that of the second electrode 540 . The second electrode 540 is surrounded by the top portion 534 of the first electrode 530 and protrudes from the top portion 534 of the first electrode 530 in a vertical direction. That is to say, the top surface 545 of the second electrode 540 is above the highest top surface 535 of the first electrode 530 . In some embodiments, the vertical projection of the second electrode 540 on the substrate 502 is located within the vertical projection of the first electrode 530 on the substrate 502 . In addition, the highest top surface 545 of the second electrode 540 does not overlap with the highest top surface 535 of the first electrode 530 . Specifically, the vertical projection of the highest top surface 545 of the second electrode 540 on the substrate 502 is separated from the vertical projection of the highest top surface 535 of the first electrode 530 on the substrate 502 . In some embodiments, the second electrode 540 partially covers the bottom portion 532 of the first electrode 530 . That is, a part of the lowest bottom surface 533 of the first electrode 530 is covered by the bottom surface 541 of the second electrode 540 , while the rest of the lowest bottom surface 533 of the first electrode 530 is not covered by the bottom surface 541 of the second electrode 540 . In some embodiments, the first electrode 530 and the second electrode 540 have different cross-sectional shapes. For example, the first electrode 530 has a U-shaped profile, while the second electrode 540 has a rectangular profile. In some embodiments, the bottom portion 532 of the first electrode 530 has a first thickness T5, and the second electrode 540 has a second thickness T6. The first thickness T5 of the bottom portion 532 of the first electrode 530 is in the range of about 700 angstroms (Å) to about 900 angstroms (for example, 800 angstroms), and the second thickness T6 of the second electrode 540 is about 700 angstroms (Å). to about 900 angstroms (eg, 800 angstroms). When the first thickness T5 of the bottom portion 532 of the first electrode 530 and the second thickness T6 of the second electrode 540 are within the above-mentioned range, the second electrode 540 can fill the opening O2 in the first electrode 530 to ensure that the second electrode 540 The junction of the first electrode 530 and the second electrode 540 forms a stepped sidewall, thereby increasing the capacitance of the capacitor structure C1 ′. In some embodiments, the second thickness T6 of the second electrode 540 is greater than or substantially equal to the first thickness T5 of the first electrode 530 . In some embodiments, the junction of the bottom portion 532 and the top portion 534 of the first electrode 530 has a stepped sidewall, which can increase the capacitance of the second capacitor of the capacitor structure C1'. In addition, since the junction of the first electrode 530 and the doped portion 506 of the substrate 502 has a stepped sidewall, the capacitance of the first capacitor of the capacitor structure C1' can be increased.

In some embodiments, the substrate 502 has doped regions 504a and 504b, and the doped regions 504a and 504b have the same electrical property. In addition, the doped regions 504 a and 504 b have electrical properties different from those of the substrate 502 . The top surfaces 505 of the doped regions 504 a and 504 b are below the highest top surface 535 of the first electrode 530 . The isolation structure 550 adjoins and contacts the doped regions 504 a and 504 b of the substrate 502 . In some embodiments, the doped portion 506 of the substrate 502 further has blocks A1' and A2', the block A1' is directly below the doped region 504a, and the block A2' is directly below the doped region 504b. In other words, the regions A1' and A2' of the doped portion 506 of the substrate 502 are located between the isolation structure 550 and the first electrode 530. The highest top surface 507 of the doped portion 506 of the substrate 502 is above the lowest bottom surface 533 of the first electrode 530 . It should be understood that the materials and configurations of the substrate 502, doped regions 504a and 504b, and isolation structure 550 in FIGS. 8 to 10 are similar to those of the substrate 302, doped regions 304a and 304b and The isolation structure 350 will not be repeated in the following description for the sake of simplicity.

In some embodiments, the capacitive structure C1' includes a dielectric layer 590 over the second electrode 540. The first dielectric layer 560 contacts the substrate 502, the doped regions 504a and 504b, the isolation structure 550, and the first electrode 530, and the second dielectric layer 570 contacts the isolation structure 550, the first dielectric layer 560, the first electrode 530, and the second electrode 540 . In some embodiments, the first dielectric layer 560 contacts the sidewall 551 of the isolation structure 550 , and the second dielectric layer 570 contacts the top surface 553 of the isolation structure 550 . The dielectric layer 590 contacts the second electrode 540 and is separated from the first electrode 530 . In some embodiments, the peripheral element C2' includes a dielectric layer 590a over the substrate 502 in the second region 524. The dielectric layer 590 a is located under the conductive structure 580 , and the dielectric layer 590 a contacts the doped regions 504 c and 504 d , the isolation structure 550 and the conductive structure 580 .

The capacitor structure C1' of the semiconductor structure 500 includes a conductive contact 600 electrically connected to the first electrode 530 and a conductive contact 610 electrically connected to the second electrode 540. In some embodiments, different voltages are applied to conductive contact 600 than to conductive contact 610 . For example, the conductive contact 600 electrically connected to the first electrode 530 is connected to the power signal (VDD), and the conductive contact 610 electrically connected to the second electrode 540 is grounded. In addition, the capacitive structure C1' includes a conductive contact 620 electrically connecting the doped regions 504a and 504b of the substrate 502 . The conductive contact 620 has the same potential as the conductive contact 610 electrically connected to the second electrode 540 . In other words, the conductive contact 620 electrically connected to the doped regions 504a and 504b and the conductive contact 600 electrically connected to the first electrode 530 of the capacitive structure C1′ have different potentials, so that the doped regions adjacent to the doped regions 504a and 504b A potential difference is generated between the portion 506 and the first electrode 530 to form a first capacitance. Likewise, since the conductive contacts 600 and 610 have different potentials, a potential difference is generated between the first electrode 530 and the second electrode 540 to form a second capacitor.

In some embodiments, the semiconductor structure 500 includes an interlayer dielectric layer 575 . The interlayer dielectric layer 575 surrounds the conductive contacts 600 , 610 and 620 and covers the isolation structure 550 , the second dielectric layer 570 , and the dielectric layer 590 .

The peripheral component C2' of the semiconductor structure 500 includes a doped portion 506a on the substrate 502, a dielectric layer 590a on the substrate 302, and a conductive structure 580 on the dielectric layer 590a. In addition, the peripheral device C2' further includes doped regions 504c and 504d located in the substrate 302, and the doped portion 506a is located between the doped regions 504c and 504d. In some embodiments, the peripheral element C2' is regarded as another capacitive structure, the conductive structure 580 of the peripheral element C2' is regarded as the upper electrode, and the doped portion 506a of the substrate 502 is regarded as the lower electrode. In some other embodiments, the peripheral element C2' is regarded as a transistor, the conductive structure 580 of the peripheral element C2' is regarded as a gate, the doped regions 504c and 504d are regarded as a source/drain, and the doping of the substrate 502 Section 506a is considered a channel.

The top surface 581 of the conductive structure 580 is above the top surface 545 of the second electrode 540 of the capacitive structure C1'. In some embodiments, the bottom surface 583 of the conductive structure 580 is substantially flush with the top surface 545 of the second electrode 540 of the capacitive structure C1'. In some embodiments, conductive structure 580 has a rectangular outline. In some embodiments, the peripheral element C2' includes a spacer 630, and the spacer 630 is formed on the sidewall 589 of the conductive structure 580. Spacer 630 contacts dielectric layer 590 and conductive structure 580 and separates doped regions 504c and 504d.

In some embodiments, peripheral element C2' includes conductive contacts 610a, 620a, and 620b. The conductive contact 610 a is electrically connected to the conductive structure 580 , the conductive contact 620 a is electrically connected to the doped region 504 c of the substrate 502 , and the conductive contact 620 b is electrically connected to the doped region 504 d of the substrate 502 . In an embodiment where the peripheral element C2' is a capacitor structure, the conductive contact 620a electrically connected to the doped region 504c has the same potential as the conductive contact 620b electrically connected to the doped region 504d. In an embodiment where the peripheral component C2' is a transistor, the conductive contact 620a electrically connected to the doped region 504c and the conductive contact 620b electrically connected to the doped region 504d have different potentials. In the second region 524 , the interlayer dielectric layer 575 surrounds the conductive contacts 610 a , 620 a and 620 b and covers the isolation structure 550 , the dielectric layer 570 a , the dielectric layer 590 and the conductive structure 580 .

FIG. 11A to FIG. 110 are cross-sectional views of various steps in the method of fabricating the semiconductor structure 500 according to some embodiments of the present disclosure.

Referring to FIG. 11A, a dielectric layer 560a and a mask layer 640 are sequentially formed on the substrate 502, wherein the mask layer 640 is in contact with the dielectric layer 560a. Next, the mask layer 640, the dielectric layer 560a and the substrate 502 are etched to form the recess R3. In some embodiments, as shown in FIG. 11A , the recess R3 exposes the central portion and the edge portion of the substrate 502 located in the first region 522 , and the recess R3 exposes the edge portion of the substrate 502 located in the second region 524 . The substrate 502 has a doped portion 506 located in the first region 522 and a doped portion 506 a located in the second region 524 . In some embodiments, the materials and manufacturing methods of the dielectric layer 560a and the mask layer 640 in FIG. 11A are similar to the dielectric layer 360a and the mask layer 430 in FIG. 7A respectively, so for the sake of simplicity, the following Description will not repeat the description.

Referring to FIG. 11A and FIG. 11B , a dielectric material is filled in the recess R3 to form an isolation structure 550 . In some embodiments, after the isolation structure 550 is formed, a planarization process, such as a chemical mechanical polishing process (CMP), is performed to remove a part of the isolation structure 550 so that the top surface of the isolation structure 550 is aligned with the top surface of the mask layer 640 The surface is roughly even.

Referring to FIG. 11C , the isolation structure 550 is etched back to expose the sidewall 641 of the mask layer 640 . In addition, the isolation structure 550 is etched back so that the top surface 553 of the isolation structure 550 is close to the top surface t2 of the dielectric layer 560 a. Etching the isolation structure 550 may use wet etching or other suitable etching methods.

Referring to FIG. 11C and FIG. 11D, after etching the isolation structure 550, the mask layer 640 is removed to expose the dielectric layer 560a. In some embodiments, phosphoric acid (H ₃ PO ₄ ) or other suitable etchant may be used to remove the mask layer 640 .

Referring to FIG. 11E , a patterned photoresist layer 650 is formed in the first region 522 and the second region 524 . In the first region 522, the patterned photoresist layer 650 covers the isolation structure 550 and a part of the dielectric layer 560a, and exposes the rest of the dielectric layer 560a; in the second region 524, the patterned photoresist layer 650 It covers the whole of the isolation structure 550 and the dielectric layer 560a. The patterned photoresist layer 650 can be formed by suitable deposition, development and/or etching techniques. Next, using the patterned photoresist layer 650 as an etching mask, the dielectric layer 560a not covered by the patterned photoresist layer 650 is etched to form a recess R4 in the first region 522 to expose the substrate of the first region 522 502 and the sidewall 561 of the dielectric layer 560a.

Referring to FIG. 11E and FIG. 11F , after forming the second recess R2 , the photoresist layer 650 is removed. The photoresist layer 650 can be removed by using a photoresist stripping process, such as an ashing process, an etching process, or other suitable processes. Next, a first dielectric layer 560 is formed in the recess R4. In some embodiments, the first dielectric layer 560 may be formed through a thermal oxidation process, so that the first dielectric layer 560 is continuously grown on the sidewall 561 of the dielectric layer 560 a and formed on the substrate 502 . In some embodiments, the first dielectric layer 560 has a thickness T7 in a range of about 350 angstroms to 450 angstroms (eg, 400 angstroms).

Referring to FIG. 11G , a first conductive layer 530 ′ is formed over the first dielectric layer 560 . In the first region 522, the lowest bottom surface 533 of the first conductive layer 530' is below the highest top surface 553 of the isolation structure 550; The thickness T5 of the bottom portion 532' of the first conductive layer 530' (corresponding to the first thickness T5 of the bottom portion 532 of the first electrode 530 in FIG. ). If the thickness T5 of the bottom part 532' of the first conductive layer 530' is greater than 900 angstroms, the process cost of manufacturing the capacitor structure will be too high; if the thickness T5 of the bottom part 532' of the first conductive layer 530' is less than 700 angstroms, The resistance value of the subsequently formed capacitor (the capacitor structure C1' in FIG. 4 ) will be too high, so that the capacitor cannot achieve the desired effect. The first conductive layer 530' may include semiconductor material (such as polysilicon), metal or other suitable conductive materials. In some embodiments, the material and manufacturing method of the first conductive layer 530' in FIG. 11G are similar to the first electrode 330 in FIG. 7G, so for the sake of simplicity, the following description will not be repeated.

Referring to FIG. 11G and FIG. 11H, after forming the first conductive layer 530', a planarization process is performed to remove a part of the first conductive layer 530' and define the first electrode 530, wherein the planarization process stops at the isolation Structure 550. In detail, in the first region 522, the planarization process exposes the isolation structure 550, the first dielectric layer 560 and the first electrode 530, so that the highest top surface 553 of the isolation structure 550, the highest top surface of the first dielectric layer 560 The surface 563 is substantially flush with the highest top surface 535 of the first electrode 530; in the second region 524, the planarization process exposes the isolation structure 550 and the dielectric layer 560a, so that the top surface 553 of the isolation structure 550 and the dielectric layer 560a The top surface is substantially flush and there is no first conductive layer 530 ′ in the second region 524 .

Referring to FIG. 11I, a second dielectric layer 570 is formed in the first region 522 and a dielectric layer 570a is formed in the second region 524. Referring to FIG. In the first region 522, the second dielectric layer 570 covers the isolation structure 550, the first dielectric layer 560 and the first electrode 530, and part of the second dielectric layer 570 and the first dielectric layer 560 are covered by the first electrode. 530 ; in the second region 524 , the dielectric layer 570 a covers the isolation structure 550 and the first dielectric layer 560 . In some embodiments, the second dielectric layer 570 and the dielectric layer 570a have a thickness T8 ranging from about 350 angstroms to 450 angstroms (eg, 400 angstroms). The thickness T8 of the second dielectric layer 570 and the dielectric layer 570 a is substantially equal to the thickness T7 of the first dielectric layer 560 . In some embodiments, the material and process method of the second dielectric layer 570 and the dielectric layer 570a in Figure 11I are similar to the second dielectric layer 370 in Figure 7I, so for the sake of simplicity, the following description will be The description will not be repeated.

Referring to FIG. 11J, after forming the second dielectric layer 570 and the dielectric layer 570a, the second conductive layer 540' is formed in the first region 522 and the second region 524. Referring to FIG. The material and manufacturing method of the second conductive layer 540' in FIG. 11J are similar to the second conductive layer 340' in FIG. 7K, so for the sake of simplicity, the following description will not be repeated.

Referring to Figures 11J and 11K, after forming the second conductive layer 540', a planarization process is performed to remove a part of the second conductive layer 540' to define the second electrode 540, wherein the planarization process stops at the first Two dielectric layers 570 and a dielectric layer 570a. Specifically, in the first region 522, the planarization process exposes the second dielectric layer 570 and the second electrode 540, so that the highest top surface 571 of the second dielectric layer 570 and the highest top surface 545 of the second electrode 540 are approximately flush; in the second region 524 , the planarization process exposes the dielectric layer 570 a such that there is no second conductive layer 540 ′ in the second region 524 . In some embodiments of the present disclosure, the etch process of FIG. 11K defines capacitive structure C1'. Specifically, the capacitor structure C1' includes a first capacitor and a second capacitor, the doped portion 506 of the substrate 502 is the lower electrode of the first capacitor, and the first electrode 530 is the upper electrode of the first capacitor and the lower electrode of the second capacitor. , and the second electrode 540 is the upper electrode of the second capacitor. In some embodiments, the second thickness T6 of the second electrode 540 is in the range of about 700 angstroms to about 900 angstroms (eg, 800 angstroms). If the second thickness T6 of the second electrode 540 is greater than 900 angstroms, the process cost of manufacturing the capacitor structure will be too high; The resistance value of C1′) will be too high, and the second electrode 540 may not be able to fill the opening O2 in the first electrode 530 so that the top surface of the second electrode 540 cannot accommodate a conductive contact (such as the conductive contact 610 in FIG. 8 ), As a result, the capacitor cannot achieve the expected effect. In some embodiments, the second thickness T6 of the second electrode 540 is greater than or substantially equal to the first thickness T5 of the first electrode 530 .

Referring to FIG. 11L , a patterned photoresist layer 660 is formed in the first region 522 and the second region 524 . In the first region 522, the patterned photoresist layer 660 covers the second dielectric layer 570 and the second electrode 540; in the second region 524, the patterned photoresist layer 660 covers a part of the dielectric layer 570a. Next, using the patterned photoresist layer 660 as an etching mask, the dielectric layer 570a not covered by the patterned photoresist layer 660 is etched. In the second region 524, the dielectric layer 570a and the dielectric layer 560a are etched to expose the isolation structure 550 and the substrate 502, while the structure of the first region 522 is substantially unchanged.

Referring to FIG. 11M, a dielectric layer 590 is formed in the first region 522 and a dielectric layer 590a is formed in the second region 524. Referring to FIG. In the first region 522, the dielectric layer 590 covers and contacts the second electrode 540, and the dielectric layer 590 is above the second dielectric layer 570; in the second region 524, the dielectric layer 590a covers the substrate 502, and the dielectric layer 590 a The top surface 591 of the electrical layer 590a is below the top surface 571 of the dielectric layer 570a. In some embodiments, the dielectric layer 590 and the dielectric layer 590a have a thickness T9 ranging from about 350 angstroms to 450 angstroms (eg, 400 angstroms). The thickness T9 of the dielectric layer 590 and the dielectric layer 590 a is substantially equal to the thickness of the first dielectric layer 560 and/or the thickness of the second dielectric layer 570 . In some embodiments, the dielectric layer 590 and the dielectric layer 590a include oxide, such as silicon oxide or other suitable dielectric materials. The dielectric layer 590 and the dielectric layer 590 a may include the same material as the first dielectric layer 560 and/or the second dielectric layer 570 . The dielectric layer 590 can be formed by thermal oxidation deposition, chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable deposition methods.

Referring to FIG. 11N, after forming the dielectric layer 590, a conductive layer 580' is formed in the first region 522 and the second region 524. Referring to FIG. In the first region 522, the conductive layer 580' is formed on the second electrode 540 and contacts the second dielectric layer 570 and the dielectric layer 590; in the second region 524, the conductive layer 580' is formed on the substrate 502, And contact the second dielectric layer 570 , the isolation structure 550 and the dielectric layer 590 . In some embodiments, the conductive layer 580' has a thickness T10 in the range of about 700 angstroms (Å) to about 900 angstroms (eg, 800 Å). The conductive layer 580' may include semiconductor material (such as polysilicon), metal or other suitable conductive materials. In some embodiments, the conductive layer 580' and the first electrode 530 and/or the second electrode 540 include the same material (such as polysilicon). In some embodiments, the conductive layer 580' is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable deposition methods.

Referring to FIG. 11N and FIG. 11O, a patterned photoresist layer 670 is formed in the second region 524 to cover a portion of the conductive layer 580'. The patterned photoresist layer 670 can be formed by suitable deposition, development and/or etching techniques. Next, using the patterned photoresist layer 670 as an etching mask, the conductive layer 580' not covered by the patterned photoresist layer 670 is etched. In the first region 522, the conductive layer 580' is fully etched to expose the second dielectric layer 570 and the dielectric layer 590; in the second region 524, a part of the conductive layer 580' is etched to define the conductive structure 580 , and expose the second dielectric layer 570 , the isolation structure 550 and the dielectric layer 590 . Subsequently, the substrate 502 is doped to form doped regions 504 a to 504 d on the substrate 502 . In some embodiments of the present disclosure, the etch process of FIG. 110 defines peripheral element C2'. In some embodiments where peripheral element C2' is considered a transistor, conductive structure 580 of peripheral element C2' is considered a gate, doped regions 504c and 504d are considered source/drains, and doped portion 506a of substrate 502 considered as a channel. In some embodiments where the peripheral element C2' is considered another capacitive structure, the conductive structure 580 of the peripheral element C2' is considered the upper electrode and the doped portion 506a of the substrate 502 is considered the lower electrode.

Returning to FIG. 8 , after the process of FIG. 110 is completed, the photoresist layer 670 is removed to expose the conductive structure 580 . Next, spacers 630 are formed on opposite sidewalls 589 of the conductive structure 580 in the second region 524 . An interlayer dielectric layer 575 is formed over the substrate 502 to cover the second dielectric layer 570 and the dielectric layer 590 in the first region 522, and to cover the isolation structure 550, the dielectric layer 570a and the dielectric layer in the second region 524. Layer 590a. After forming the ILD layer 575 , conductive contacts 600 , 610 , 610 a , 620 , 620 a , and 620 b are formed in the ILD layer 575 . Specifically, in the first region 522, the conductive contact 600 is formed on the first electrode 530, the conductive contact 610 is formed on the second electrode 540, and the conductive contact 620 is formed on the doped regions 504a and 504b; in the second region In 524, conductive contact 610a is formed on conductive structure 580, conductive contact 620a is formed on doped region 504c, and conductive contact 620b is formed on doped region 504d. In this way, a semiconductor structure 500 as shown in FIG. 8 can be obtained.

It should be understood that the material, configuration and formation method of the interlayer dielectric layer 575 and the conductive contacts (conductive contacts 600, 610, 610a, 620, 620a, and 620b) are similar to those of the interlayer dielectric layer 375 and the conductive contacts (conductive contacts 400, 400a, 410, 420, 420a, and 420b), so the description will not be repeated here.

In the above embodiments of the present disclosure, the capacitor structure includes a first capacitor and a second capacitor, wherein the first capacitor includes the doped portion of the substrate and the first electrode, the second capacitor includes the first electrode and the second electrode, and the second electrode The bottom part of the bottom part is embedded in the first electrode, which can reduce the capacitance area of the capacitance structure and increase the capacitance value. Since memory elements (such as 3D NAND memory elements) have multiple layers of conductive layers (ie, word lines), it is necessary to provide a higher current for memory elements to maintain operation, so a capacitor structure with a larger capacitance value is required for memory Each word line of the body device provides electrical signals. The capacitor structure of some embodiments of the present disclosure can occupy less space in the memory device and meet the above-mentioned requirement for larger capacitance.

Although this disclosure has been disclosed as above in the form of implementation, it is not intended to limit this disclosure. Anyone who is familiar with this technology can make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, the protection of this disclosure The scope shall be defined by the appended patent application scope.

100: Semiconductor components 102: Substrate 104: Driving circuit layer 110: memory components 111: conductive layer 112: Channel layer 113: insulation layer 114: string selection line 115: Conductive via 116: bit line 120: Ladder structure 122: Conductive contact 123:Interconnect structure 124: Conductive contact 126: Landing Zone 128: Insulation structure 130: conductive slit 200: Semiconductor components 200a: Semiconductor components 202: Substrate 204: Driving circuit layer 210: memory components 220: ladder structure 221: conductive layer 222: Conductive contact 223:Interconnect structure 224: Conductive contact 226: Landing Zone 228: Conductive contact 230:Interconnect structure 250: capacitor structure 250a: capacitor structure 260: Shared source 300: Semiconductor Structures 302: Substrate 303: top surface 304a: Doped region 304b: doped region 304c: doped region 304d: doped region 305: top surface 306: doping part 306a: doping part 307: top surface 322: The first area 324: second area 330: first electrode 330': the first conductive layer 330a: first conductive structure 330a': conductive layer 331: Bottom 332: Bottom part 332': Bottom part 334: top part 335: top surface 336: merge part 337: side wall 339: side wall 340: second electrode 340': second conductive layer 340a: Second Conductive Structure 341: Bottom 342: Bottom part 343: Bottom 344: top part 345: top surface 347: side wall 348: top surface 349: side wall 350: Isolation structure 351: side wall 353: top surface 357: top surface 360: the first dielectric layer 360a: dielectric layer 370: second dielectric layer 375: interlayer dielectric layer 380: first spacer 390: second spacer 390a: spacer 400: conductive contact 400a: Conductive contact 405: contact opening 405a: contact opening 410: Conductive contact 415: contact opening 420: conductive contact 420a: Conductive contact 420b: Conductive contact 425: contact opening 425a: contact opening 430: mask layer 440: photoresist layer 450: photoresist layer 460: photoresist layer 500: Semiconductor Structures 502: Substrate 504a: Doped region 504b: Doped region 504c: doped region 504d: doped region 505: top surface 506: doping part 506a: doping part 507: top surface 522: The first area 524: second area 530: first electrode 530': the first conductive layer 532: Bottom part 532': Bottom part 533: Bottom 534: top part 535: top surface 540: second electrode 540': second conductive layer 541: Bottom 545: top surface 550: Isolation structure 551: side wall 553: top surface 560: the first dielectric layer 560a: dielectric layer 561: side wall 563: top surface 570: second dielectric layer 570a: dielectric layer 571: top surface 575: interlayer dielectric layer 580: Conductive structure 580': conductive layer 581: top surface 583: Bottom 589: side wall 590: dielectric layer 590a: dielectric layer 591: top surface 600: conductive contact 610: Conductive contact 610a: Conductive contact 620: conductive contact 620a: Conductive contact 620b: Conductive contact 630: spacer 640: mask layer 641: side wall 650: photoresist layer 660: photoresist layer 670: photoresist layer 4-4: Line segment 4’-4’: line segment 5B-5B: Line segment 8-8: Line segment 8’-8’: line segment A1: block A1': block A2: block A2': block C1: capacitor structure C2: peripheral components C1': capacitor structure C2': Peripheral components O1: Open O2: Open R1: first depression R2: second depression R3: concave R4: sunken t1: top surface t2: top surface T1: first thickness T2: second thickness T3: Thickness T4: Thickness T5: Thickness T6: Thickness T7: Thickness T8: Thickness T9: Thickness T10: Thickness X: direction Y: Direction Z: Direction

In order to make the above and other purposes, features, advantages and embodiments of the present disclosure more comprehensible, the accompanying drawings are described as follows: FIG. 1A illustrates a perspective view of a semiconductor device according to some embodiments of the present disclosure; Figure 1B shows the top view of Figure 1A; FIG. 2 shows a schematic diagram of a semiconductor device including a capacitor structure according to some embodiments of the present disclosure; FIG. 3 shows a schematic diagram of a semiconductor device including a capacitor structure according to another embodiment of the present disclosure; FIG. 4 illustrates a cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure; FIG. 5A shows a top view of the capacitor structure of the semiconductor structure of FIG. 4; Figure 5B shows a top view along the line segment 5B-5B in Figure 4; FIG. 6 shows a top view of peripheral components of the semiconductor structure of FIG. 4; FIG. 7A to FIG. 7O are cross-sectional views of various steps in the manufacturing method of the semiconductor structure according to some embodiments of the present disclosure; FIG. 8 illustrates a cross-sectional view of a semiconductor structure according to another embodiment of the present disclosure; FIG. 9 shows a top view of the capacitor structure of the semiconductor structure of FIG. 8; FIG. 10 illustrates a top view of peripheral components of the semiconductor structure of FIG. 8; and FIG. 11A to FIG. 110 are cross-sectional views of various steps in a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.

Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none

300: Semiconductor Structures

302: Substrate

303: top surface

304a: Doped region

304b: doped region

304c: doped region

304d: doped region

305: top surface

306: doping part

306a: doping part

307: top surface

322: The first area

324: second area

330: first electrode

330a: first conductive structure

331: Bottom

332: Bottom part

334: top part

335: top surface

337: side wall

339: side wall

340: second electrode

340a: Second Conductive Structure

341: Bottom

342: Bottom part

343: Bottom

344: top part

345: top surface

347: side wall

348: top surface

349: side wall

350: Isolation structure

351: side wall

360: the first dielectric layer

360a: dielectric layer

370: second dielectric layer

375: interlayer dielectric layer

380: first spacer

390: second spacer

390a: spacer

400: conductive contact

400a: Conductive contact

410: Conductive contact

420: conductive contact

420a: Conductive contact

420b: Conductive contact

A1: block

A2: block

C1: capacitor structure

C2: peripheral components

T1: first thickness

T2: second thickness

5B-5B: Line segment

Claims (10)

A semiconductor element comprising: a substrate; a driving circuit layer located on the substrate; A memory element is located on the substrate, and the memory element includes: a plurality of conductive layers and a plurality of insulating layers stacked alternately; a plurality of bit lines located on the conductive layers and the insulating layers; a plurality of channel layers passing through the conductive layers and the insulating layers, and each of the channel layers is electrically connected to the bit lines; and A ladder structure is located on the substrate, and the ladder structure is electrically connected to the memory element and the driving circuit layer, wherein the driving circuit layer includes a capacitor structure, and the capacitor structure includes: a doped portion within the substrate; a first electrode located on the doped portion of the substrate, the first electrode having a bottom portion and a top portion, wherein the bottom portion of the first electrode is located within the doped portion of the substrate; a first dielectric layer located between the first electrode and the doped portion of the substrate; A second electrode located on the first electrode, wherein the second electrode has a bottom portion and a top portion, the bottom portion of the second electrode is embedded in the first electrode, and the bottom portion of the second electrode a bottom surface of the portion is below a top surface of the substrate; and A second dielectric layer is located between the first electrode and the second electrode. The semiconductor device according to claim 1, wherein the first electrode is wider than the second electrode. The semiconductor device as claimed in claim 1, wherein a part of a highest top surface of the first electrode is covered by the second electrode, and the rest of the highest top surface of the first electrode is not covered by the second electrode. The semiconductor device as claimed in claim 1, wherein a thickness of the second electrode is greater than a thickness of the first electrode. The semiconductor device as described in claim 1, wherein the capacitor structure further comprises: A first doped region and a second doped region are located in the substrate, and the doped portion of the substrate further has a region between the first doped region and the first electrode. The semiconductor device as claimed in claim 1, wherein the first dielectric layer contacts the doped portion of the substrate, the first doped region, the second doped region and the first electrode, and the second dielectric layer The electrical layer is in contact with the first electrode and the second electrode. The semiconductor device as described in claim 1, wherein the capacitor structure further comprises: A spacer is located on the sidewall of the top portion of the second electrode and separated from the bottom portion of the second electrode. A semiconductor element comprising: a substrate; a driving circuit layer located on the substrate; A memory element is located on the substrate, and the memory element includes: a plurality of conductive layers; and a plurality of channel layers vertically passing through the conductive layers; and A ladder structure located on the substrate, the ladder structure includes a first conductive contact, a second conductive contact and an interconnection structure, the first conductive contact connects the interconnection structure and the driving circuit layer, the second conductive Contacting one of the conductive layers connecting the interconnection structure and the memory element, wherein the driving circuit layer includes a capacitor structure, and the capacitor structure includes: a doped portion within the substrate; a first electrode on the doped portion of the substrate, wherein a lowest bottom surface of the first electrode is below a highest top surface of the doped portion of the substrate; and a second electrode located on the first electrode, wherein the first electrode surrounds the second electrode, a lowest bottom surface of the second electrode is below a highest top surface of the first electrode, and a The highest top surface does not overlap with a highest top surface of the second electrode. The semiconductor device as claimed in item 8, wherein the capacitor structure further comprises: a first dielectric layer between the doped portion of the substrate and the first electrode; and A second dielectric layer is located between the first electrode and the second electrode. The semiconductor device as claimed in item 9, wherein the capacitor structure further comprises: A third dielectric layer is located on the second electrode, and the third dielectric layer is separated from the first dielectric layer.

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