TWI787086B - Wafer bonding structure and method of manufacturing the same - Google Patents

Abstract

A wafer bonding structure is provided in the present invention, including a substrate, a recess formed in the substrate, a bonding pad in the recess, and a first metal barrier layer, a second metal barrier layer and a dielectric barrier layer sequentially formed between the sidewall of the bonding pad and the inner sidewall of the recess, and the first metal barrier layer is further formed between the bottom of the bonding pad and the bottom of the recess, wherein the thickness of the first metal barrier layer is smaller than the thickness of the second metal barrier layer, and the thickness of the first metal barrier layer is smaller than the thickness of the dielectric barrier layer.

Description

Wafer bonding structure and manufacturing method thereof

The present invention relates to a wafer bonding structure, more specifically, it relates to a wafer bonding structure with multiple barrier layers and a manufacturing method thereof.

The interconnect structure is the communication bridge between chips, from traditional wire bonding, flip chip package, micro bump (µbump), to through silicon via (TSV) ), redistribution layer (redistribution layer, RDL), silicon bridge chip (silicon bridge chip) and other technologies, the interconnection structure and technology are also evolving with the continuous improvement of chip performance and the continuous miniaturization of component sizes. However, as the dimensions of semiconductor components continue to shrink, it is no longer cost-effective to develop smaller technology nodes, although technically feasible. In this regard, multi-chip stacking technology has been proposed by the industry as a solution, such as the 2.5D~3D advanced packaging technology that is currently being actively developed.

Usually, the realization of 2.5D~3D chip stacking benefits from the mature through-silicon via (TSV) technology. However, the generally large volume of TSVs limits their scalability in high-density architectures. In addition, the process of filling TSVs with metal is quite complicated and requires a lot of technical expertise. Therefore, the industry has introduced a hybrid bonding technology. For example, the industry has achieved the bonding of CMOS image sensor wafers and image sensor processor wafers through copper hybrid bonding components. Multi-point direct connection and the effect of further enhancing the pixel density. Compared with existing stacking/bonding methods, hybrid bonding technology can further reduce the bonding pitch to provide more I/O counts, higher bandwidth and lower power consumption.

Although the hybrid bonding technology has good development prospects, there are still many problems to be overcome in today's hybrid bonding technology. For example, when the bonding pitch is smaller than a certain scale (such as <5µm), it is easy to produce an obvious overlay shift between the bonding parts, which will cause the copper in the bonding part to diffuse to the adjacent oxide Copper Contamination Problems in Silicon Substrates.

In view of the problems of alignment and contamination encountered in the above-mentioned conventional technologies, the present invention provides a novel wafer bonding structure, which is characterized in that there are multi-layer barrier layers around the copper bonding parts, which can simultaneously When the misalignment occurs, it can prevent the copper in the bond from diffusing into the adjacent substrate and maintain the required contact area.

One aspect of the present invention is to provide a wafer bonding structure comprising a substrate, a groove formed on the substrate, a bonding pad located in the groove, a first metal barrier layer, a first Two metal barrier layers and a dielectric barrier layer are sequentially formed between the sidewall of the bonding pad and the inner sidewall of the recess, and the first metal barrier layer is further formed between the bottom surface of the bonding pad and the recess. Between the bottom surfaces of the grooves, wherein the thickness of the first metal barrier layer is smaller than the thickness of the second metal barrier layer, and the thickness of the first metal barrier layer is smaller than the thickness of the dielectric barrier layer.

Another aspect of the present invention is to provide a method for manufacturing a wafer bonding structure, the steps of which include providing a substrate, forming a groove on the substrate, forming a dielectric barrier layer on the inner sidewall of the groove, and forming a dielectric barrier layer on the inner sidewall of the groove. A second metal barrier layer is formed on the inner sidewall of the dielectric barrier layer, a first metal barrier layer is formed on the inner sidewall of the second metal barrier layer and the bottom surface of the groove, and a first metal barrier layer is formed on the first metal barrier layer. A bonding pad is formed on the metal barrier layer, wherein the thickness of the first metal barrier layer is smaller than the thickness of the second metal barrier layer, and the thickness of the first metal barrier layer is smaller than the thickness of the dielectric barrier layer .

These and other objects of the present invention will become more apparent to the reader after reading the following detailed description of the preferred embodiment which is depicted in various drawings and drawings.

Exemplary embodiments of the present invention will now be described in detail below, which will illustrate the described features with reference to the accompanying drawings for readers to understand and achieve technical effects. Readers will understand that the description herein is by way of illustration only and is not intended to limit the present case. Various embodiments of the present application and various features that do not conflict with each other in the embodiments can be combined or rearranged in various ways. Without departing from the spirit and scope of the present invention, modifications, equivalents or improvements to the present invention will be understood by those skilled in the art and are intended to be included within the scope of the present invention.

Readers should be able to easily understand that the meanings of "on", "on" and "above" in this case should be interpreted in a broad way so that "on" not only means "directly on "Something "on" also includes the meaning of "on" something with an intervening feature or layer in between, and "on" or "over" not only means "on" something or The meaning of "over" and may also include its meaning of "on" or "over" something without intervening features or layers in between (ie, directly on something). In addition, spatial relative terms such as "under", "beneath", "lower", "above", "upper", etc. may be used herein for convenience of description to describe the relationship between one element or feature and another. The relationship of one or more elements or features as shown in the drawings.

As used herein, the term "substrate" refers to a material onto which subsequent materials are added. The substrate itself can be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate can include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic or a sapphire wafer.

As used herein, the term "layer" refers to a portion of material that includes regions having a thickness. A layer may extend over the entirety of the underlying or overlying structure, or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any horizontal faces at the top and bottom surfaces. Layers may extend horizontally, vertically and/or along sloped surfaces. A substrate can be a layer, can comprise one or more layers, and/or can have one or more layers thereon, above, and/or below. Layers may include multiple layers. For example, interconnect layers may include one or more conductor and contact layers (in which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

Readers can usually understand a term at least in part from its usage in context. For example, the term "one or more" as used herein may be used in the singular to describe any feature, structure or characteristic or may be used in the plural to describe a combination of features, structures or characteristics, depending at least in part on the context. Similarly, terms such as "a," "an," "the" or "said" may equally be read to convey either the singular usage or the plural usage, depending at least in part on the context. Additionally, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, but may allow for the presence of additional factors not necessarily explicitly described, again depending at least in part on context.

Readers can better understand that when words such as "comprising" and/or "comprising" are used in this specification, it clearly states the existence of the stated features, regions, integers, steps, operations, elements and/or components, but does not The existence or addition of one or more other features, regions, integers, steps, operations, elements, components and/or combinations thereof is not excluded.

Now the following preferred embodiments will illustrate the steps of the method for manufacturing the wafer bonding structure in the present invention according to the schematic cross-sectional views of FIGS. 1 to 7 .

Please refer to FIG. 1 , firstly, at the beginning of the process, a semiconductor substrate 100 is provided as a basis for manufacturing a semiconductor structure. In the embodiment of the present invention, the substrate 100 is preferably a wafer, such as a silicon wafer on which the semiconductor back-end-of-line process (BEOL) has been completed, and has semiconductor elements, multi-layer metal interconnection layers, and intermetallic dielectric layers inside it. , the substrate 100 in the figure can be regarded as the topmost dielectric layer or passivation layer on the wafer, and its material can be silicon oxide, but not limited thereto. In order to simplify the illustration and avoid obscuring the focus of the present invention, other base components will not be shown in the illustration. Refer back to Figure 1. A photolithography process is performed to remove part of the substrate 100 to form a groove 104 on the substrate 100 as a space for forming a bonding pad. As shown in the figure, the bottom surface of the groove 104 exposes a pre-formed via 102 in the substrate 100 , and the bottom area of the groove 104 is preferably larger than the top area of the via 102 .

Please refer to Figure 2. After the groove 104 is formed, a conformal dielectric barrier material layer 106 is then formed on the groove 104 and the surface of the substrate 100 . In the embodiment of the present invention, the material of the dielectric barrier material layer 106 can be silicon nitride or silicon carbonitride, preferably silicon nitride, which can be formed by plasma-assisted chemical vapor deposition (PECVD). The dielectric layer made of silicon nitride has a diffusion barrier effect on copper ions, and can be used as a barrier layer for bonding pads to be formed later.

Please refer to Figure 3. After the dielectric barrier material layer 106 is formed, an anisotropic etch-back process is then performed to remove the dielectric barrier material layer 106 on the horizontal plane, leaving only the dielectric barrier layer 107 on the inner sidewall of the groove 104, And the bottom surface of the groove 104 and the hole guide 102 are exposed.

Please refer to Figure 4. After the dielectric barrier layer 107 is formed on the inner sidewall of the groove 104 , a conformal metal barrier material layer 108 is then formed on the surface of the groove 104 , the substrate 100 and the dielectric barrier layer 107 . In the embodiment of the present invention, the material of the metal barrier material layer 108 may preferably be tantalum or tantalum nitride, which can be formed by a physical vapor deposition (PVD) process. The metal barrier layer made of tantalum or tantalum nitride has a diffusion barrier effect on copper ions, and it can also be used as a barrier layer for bonding pads to be formed later.

Please refer to Figure 5. After the metal barrier material layer 108 is formed, similarly, an anisotropic etch-back process is then performed to remove the metal barrier material layer 108 on the horizontal plane, leaving only the metal barrier material on the inner sidewall of the dielectric barrier layer 107. The barrier layer 109 is exposed, and the bottom surface of the groove 104 and the hole guide 102 are exposed.

Please refer to Figure 6. After the metal barrier layer 109 is formed on the inner sidewall of the dielectric barrier layer 107, another layer of conformal metal barrier material layer is then formed on the surface of the groove 104, the substrate 100, the dielectric barrier layer 107 and the metal barrier layer 109. 110. The material of the metal barrier material layer 110 can be tantalum, tantalum nitride or tantalum nitride/tantalum composite layer, which can be formed by physical vapor deposition (PVD) process. The metal barrier material layer 110 made of tantalum and/or tantalum nitride can also be used as the barrier layer of the bonding pad to be formed later, but it should be noted that in the embodiment of the present invention, the dielectric barrier layer 107 formed above The thickness or the thickness of the metal barrier layer 109 is at least six times the thickness of the metal barrier material layer 110 . For example, in one embodiment, the thickness of the dielectric barrier layer 107 or the metal barrier layer 109 is 0.16 μm, and the thickness of the metal barrier material layer 110 may be 0.02 μm. This is because the role of the thicker dielectric barrier layer 107 and the metal barrier layer 109 in the present invention is to reduce the adverse effect brought by the bonding pad when the alignment shift (overlay shift) occurs in the butt joint. Further description will be given in subsequent embodiments.

Refer back to Figure 6. After the metal barrier material layer 110 is formed, a bonding pad material layer 112 is then formed on the metal barrier material layer 110 . In the embodiment of the present invention, the material of the bonding pad material layer 112 is preferably copper, which can be formed by first forming a layer of copper seed layer on the surface of the metal barrier material layer 110 by PVD process, and then by electroplating process. The bonding pad material layer 112 is formed on the copper seed layer so that the bonding pad material layer 112 completely fills the groove 104 .

Please refer to Figure 7. After the metal barrier material layer 110 and the bonding pad material layer 112 are formed, a chemical mechanical planarization (CMP) process is then performed to remove the metal barrier material layer 110 and the bonding pad material layer 112 outside the groove 104, thus A bonding pad 113 and a metal barrier layer 111 located in the groove 104 are formed.

It can be seen from FIG. 7 that in the embodiment of the present invention, the final wafer bonding structure includes a copper bonding pad 113, a tantalum or tantalum nitride material (No. 1) Metal barrier layer 111, a (second) metal barrier layer 109 made of tantalum material and a dielectric barrier layer 107 made of silicon nitride, wherein the metal barrier layer 111 is located on the sidewall of the bonding pad 113 and the bond Between the bottom surface of the bonding pad 113 and the bottom surface of the groove, the inner and outer surfaces thereof are directly connected to the hole guide member 102 and the bonding pad 113 respectively. The metal barrier layer 109 and the dielectric barrier layer 107 are located outside in the form of sidewalls. It should be noted that in the embodiment of the present invention, although the material of the metal barrier layer 111 and the metal barrier layer 109 are similar and both serve as metal barrier layers, the thickness of the outer metal barrier layer 109 is much greater than that of the inner metal barrier layer 111. Thickness (at least six times that). Likewise, the thickness of the outer dielectric barrier layer 107 is much greater (at least six times) than the thickness of the inner metal barrier layer 111 . The barrier layer structure design with multiple layers of different materials and different thicknesses is different from the design of a single-layer thin tantalum metal barrier layer in the prior art, and its effect will be described in the following embodiments.

Now, the steps of the method for fabricating the wafer bonding structure in another embodiment of the present invention will be described below according to the cross-sectional schematic diagrams of FIGS. 8-11 .

Please refer to Figure 8. Different from the foregoing embodiments, in this embodiment, the etch-back process is not performed first after the dielectric barrier material layer 206 is formed, but a conformal dielectric barrier material layer 206 and a metal layer are sequentially formed on the groove 204. barrier material layer 208 . Likewise, the material of the dielectric barrier material layer 106 is preferably silicon nitride, which can be formed by a plasma-assisted chemical vapor deposition (PECVD) process. The metal barrier material layer 208 is preferably made of tantalum, which can be formed by a physical vapor deposition (PVD) process.

Please refer to Figure 9. After the dielectric barrier material layer 206 and the metal barrier material layer 208 are formed, an anisotropic etch-back process is then performed to remove the metal barrier material layer 208 on the horizontal plane, leaving only the inner sidewall of the dielectric barrier layer 206 The (second) metal barrier layer 209 on the groove 204 is exposed, and the dielectric barrier material layer 206 on the bottom surface of the groove 204 is exposed.

Please refer to Figure 10. After the metal barrier layer 209 is formed, another anisotropic etch-back process is performed to remove the dielectric barrier material layer 206 not covered by the metal barrier layer 209 on the horizontal plane, leaving only the inner sidewall of the groove 204 and the dielectric barrier layer 207 on the bottom surface, and part of the bottom surface of the groove 204 and the hole guide 202 are exposed. It can be seen from FIG. 10 that the dielectric barrier layer 207 formed in this way will be L-shaped in a cross-sectional view, which has a horizontal portion 207a extending inward, and the metal barrier layer 209 is located at this horizontal portion. 207a without contacting the substrate 200. It should be noted that the height of the metal barrier layer 209 may be higher than, lower than or even with the height of the dielectric barrier layer 207 , but not limited thereto.

Please refer to Figure 11. After the dielectric barrier layer 207 and the metal barrier layer 209 are formed, another (first) metal barrier layer 211 and bonding pads 213 are then formed in the groove 204 . The material and formation method of the metal barrier layer 211 and the bonding pad 213 are the same as those of the foregoing embodiments. The material of the metal barrier layer 211 can be tantalum, tantalum nitride or tantalum nitride/tantalum composite layer, which can be formed by PVD process. . The bonding pad 213 is preferably made of copper, which can be formed by first forming a layer of copper seed layer on the surface of the metal barrier layer 211 by PVD process, and then forming a bonding pad on the copper seed layer by electroplating process. to form. The horizontal portion 207 a of the dielectric barrier layer 207 extending toward the bonding pad 213 on the bottom surface of the groove 204 is in contact with the metal barrier layer 211 .

It can be seen from FIG. 11 that in the embodiment of the present invention, the final wafer bonding structure includes a copper bonding pad 213, a tantalum or tantalum nitride material ( First) a metal barrier layer 211, a (second) metal barrier layer 209 made of tantalum material, and a dielectric barrier layer 207 made of silicon nitride with an L-shaped cross section, wherein the metal barrier layer 211 is located on the bonding pad On the sidewall of 213 and between the bottom surface of the bonding pad 213 and the bottom surface of the groove, the inner and outer surfaces thereof are directly connected to the hole guide 202 and the bonding pad 213 respectively. The metal barrier layer 209 and the dielectric barrier layer 107 are located on the outside in the form of sidewalls, and the metal barrier layer 209 is located on the horizontal portion 207a of the dielectric barrier layer 207, and the horizontal portion 207a extends to the inside and is connected to the metal barrier layer. 211 contacts. It should be noted that in the embodiment of the present invention, similarly, although the material of the metal barrier layer 211 is similar to that of the metal barrier layer 209, the thickness of the outer metal barrier layer 209 is much greater than the thickness of the inner metal barrier layer 211 (at least its six times). Likewise, the thickness of the outer dielectric barrier layer 207 is much greater (at least six times) than the thickness of the inner metal barrier layer 211 . The barrier layer structure design with multiple layers of different materials and different thicknesses is different from the design of a single-layer thin tantalum metal barrier layer in the prior art, and its effect will be described in the following embodiments.

Finally, please refer to FIG. 12 , which is a schematic cross-sectional view of the butt joint of two wafer bonding structures according to an embodiment of the present invention. In the current implementation, the butt joint accuracy of the hybrid bonding technology is only about 0.3µm, so when the pitch size of the hybrid bonded parts is less than 5µm, it is inevitable that there will be obvious gaps between the bonded parts. Alignment offset (overlay shift). It can be seen from Fig. 12 that according to the wafer bonding structure of the present invention, due to the misalignment, the part of the bonding pad 213a that should be in contact with the corresponding bonding pad 213b will be in contact with the surrounding of the bonding pad 213b The metal barrier layer 211 is in contact with the metal barrier layer 209, and vice versa. The advantages of such a wafer bonding structure design are as follows:

(1) First of all, in the conventional technology, since there is only a thin barrier layer around the traditional bonding pad, part of the offset bonding pad will directly contact with the opposing silicon oxide substrate. Copper ions from the bonding pad diffuse into the opposing substrate, causing reliability issues. In contrast, two layers of thick barrier layers, the metal barrier layer 209 and the dielectric barrier layer 207, are designed around the wafer bonding structure of the present invention. If the two barrier layers are in contact, the copper ions will still be blocked and will not enter into the opposing substrate to cause reliability problems.

(2) Secondly, due to the predetermined conductive contact area of the bonding pad after the misalignment is reduced, it is easy to cause electrical changes and reliability problems of the components. In the wafer bonding structure of the present invention, since a thick tantalum or tantalum nitride metal barrier layer 209 is provided on the outside, the offset bonding pad will still be in contact with the metal barrier layer 209 in the opposite substrate. . The conductivity of tantalum or tantalum nitride material is not as high as that of copper, but it still maintains a good free path of conduction. In this way, when a serious misalignment occurs, the contact resistance will not increase significantly due to the reduction of the conductive area, maintaining the electrical performance and reliability of the device.

(3) Furthermore, unlike the bonding pads in the prior art where only a thin barrier layer is provided around the bonding pad, multiple barrier layers, namely the first metal barrier layer, are provided around the wafer bonding structure of the present invention. 211 , the second metal barrier layer 209 and the dielectric barrier layer 207 , and the materials of these barrier layers are sequentially set according to the coefficient of thermal expansion (CTE). For example, the thermal expansion coefficient of the copper material of the central bonding pad is about 17ppm/°C, and the thermal expansion coefficient of the tantalum material of the first metal barrier layer 211 and the second metal barrier layer 209 is about 6.3ppm/°C, The thermal expansion coefficient of the silicon nitride material of the dielectric barrier layer 207 is about 3ppm/°C, while the thermal expansion coefficient of the silicon oxide material of the surrounding substrate 200 is about 1ppm/°C, so it can be seen that the wafer bonding structure of the present invention The coefficient of thermal expansion decreases from the center to the periphery. Such a gradient design of the thermal expansion coefficient can effectively avoid stress or layer structure peeling problems caused by thermal cycles in the manufacturing process.

(4) Finally, regarding the design of the L-shaped dielectric barrier layer 207 in the second embodiment of the present invention, its advantage is that in addition to providing a thermal expansion coefficient gradient feature in the direction perpendicular to the substrate, the dielectric material of the amorphous state and silicon nitride The horizontal part 207a of the resistance barrier layer 207 is blocked between the metal barrier layer 209 and the substrate 200, which can prevent the copper ions of the bonding pads 213a, 213b from possibly going along the columnar crystal grain boundary of tantalum in the metal barrier layer 209 The possibility of the path spreading to the substrate 200 further improves its barrier efficacy.

It can be seen from the above embodiments that the wafer bonding structure proposed by the present invention has the characteristics of a multi-layer barrier layer, which is designed to have a specific relative thickness and material, which can maintain the barrier when the alignment shift occurs during the bonding process. The barrier effect, the avoidance of a large increase in contact resistance, and the effect of avoiding excessive concentration of thermal stress are both novel and progressive inventions. The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: base 102: Guide hole 104: Groove 106: dielectric barrier material layer 107: Dielectric barrier layer 108: (Second) metal barrier material layer 109: (second) metal barrier layer 110: (first) metal barrier material layer 111: (first) metal barrier layer 112: Bonding pad material layer 113: Bonding pad 200: base 202: guide hole 204: Groove 206: dielectric barrier material layer 207: Dielectric barrier layer 207a: Horizontal part 208: (Second) metal barrier material layer 209: (second) metal barrier layer 211: (first) metal barrier layer 213, 213a, 213b: bonding pads

This specification contains drawings and constitutes a part of this specification, so that readers can have a further understanding of the embodiments of the present invention. The drawings depict some embodiments of the invention and together with the description herein explain its principles. In these diagrams: Figures 1 to 7 are schematic cross-sectional views of a method for manufacturing a wafer bonding structure according to a preferred embodiment of the present invention; FIG. 8 to FIG. 11 are cross-sectional schematic diagrams of a method for manufacturing a wafer bonding structure according to another embodiment of the present invention; and FIG. 12 is a schematic cross-sectional view of the docking of two wafer bonding structures according to an embodiment of the present invention. It should be noted that all the diagrams in this manual are illustrations in nature. For the sake of clarity and convenience of illustration, the size and proportion of each component in the diagram may be exaggerated or reduced. Generally speaking, the The same reference symbols will be used to designate corresponding or similar component features in modified or different embodiments.

100: base

102: Guide hole

107: Dielectric barrier layer

109: (Second) metal barrier layer

111: (first) metal barrier layer

113: Bonding pad

Claims (14)

A wafer bonding structure comprising: a base; a groove formed on the substrate; a bond pad located in the recess; and A first metal barrier layer, a second metal barrier layer, and a dielectric barrier layer are sequentially formed between the sidewall of the bonding pad and the inner sidewall of the groove, and the first metal barrier layer It is further formed between the bottom surface of the bonding pad and the bottom surface of the groove, wherein the thickness of the first metal barrier layer is less than the thickness of the second metal barrier layer, and the thickness of the first metal barrier layer is less than The thickness of the dielectric barrier layer. The wafer bonding structure described in item 1 of the scope of the patent application further includes a via hole located in the substrate below the groove, and the via hole and the bonding pad respectively contact the first metal barrier layer both inside and outside. The wafer bonding structure described in item 1 of the scope of the patent application, wherein the dielectric barrier layer has a horizontal portion extending toward the bonding pad on the bottom surface of the groove, and the horizontal portion is in contact with the first metal barrier layer contact, and the second metal barrier layer is located on the horizontal portion without contacting the substrate. The wafer bonding structure described in claim 1, wherein the thickness of the second barrier metal layer is at least six times the thickness of the first barrier metal layer. The wafer bonding structure described in claim 1, wherein the thickness of the dielectric barrier layer is at least six times the thickness of the first metal barrier layer. The wafer bonding structure described in claim 1 of the patent application, wherein the material of the bonding pad is copper. In the wafer bonding structure described in claim 1 of the patent application, the material of the first metal barrier layer is tantalum nitride, tantalum or tantalum nitride/tantalum composite layer. In the wafer bonding structure described in item 1 of the scope of the patent application, the material of the second metal barrier layer is tantalum. The wafer bonding structure described in item 1 of the scope of the patent application, wherein the material of the dielectric barrier layer is silicon nitride or silicon carbonitride. A method for manufacturing a wafer bonding structure, comprising: provide a base; forming a groove on the base; forming a dielectric barrier layer on the inner sidewall of the groove; forming a second metal barrier layer on the inner sidewall of the dielectric barrier layer; forming a first metal barrier layer on the inner sidewall of the second metal barrier layer and the bottom surface of the groove; and A bonding pad is formed on the first metal barrier layer, wherein the thickness of the first metal barrier layer is smaller than the thickness of the second metal barrier layer, and the thickness of the first metal barrier layer is smaller than the dielectric resistance The thickness of the barrier layer. The method for manufacturing a wafer bonding structure as described in item 10 of the scope of the patent application, wherein the step of forming the dielectric barrier layer on the inner sidewall of the groove includes: forming a conformal layer of dielectric barrier material on the substrate and the surface of the recess; and An anisotropic etching process is performed to remove the dielectric barrier material layer on the horizontal plane, leaving the dielectric barrier layer on the inner sidewall of the groove. The method for manufacturing a wafer bonding structure as described in item 10 of the scope of the patent application, wherein the step of forming the second metal barrier layer on the inner sidewall of the dielectric barrier layer includes: forming a conformal second metal barrier material layer on the substrate and the surface of the dielectric barrier layer; and An anisotropic etching process is performed to remove the second metal barrier material layer on the horizontal plane, leaving the second metal barrier layer on the inner sidewall of the dielectric barrier layer. The manufacturing method of the wafer bonding structure as described in item 10 of the patent scope, wherein the first metal barrier layer is formed on the inner sidewall of the second metal barrier layer and the bottom surface of the groove, and the first metal barrier layer is formed on the bottom surface of the groove. The step of forming the bonding pad on the first metal barrier layer includes: forming a conformal first metal barrier material layer on surfaces of the substrate, the dielectric barrier layer, and the second metal barrier layer; forming a bonding pad material layer on the first metal barrier material layer, wherein the bonding pad material layer fills the groove; and performing a chemical mechanical planarization process to remove the bonding pad material layer and the first metal barrier material layer outside the groove, leaving the first metal barrier layer and the bonding pad in the groove . The method for manufacturing a wafer bonding structure as described in claim 10 of the patent application, wherein the dielectric barrier layer is formed on the inner sidewall of the groove and the second metal is formed on the inner sidewall of the dielectric barrier layer The steps of the barrier layer include: forming a conformal layer of dielectric barrier material on the substrate and the surface of the groove; forming a conformal second metal barrier material layer on the surface of the dielectric barrier material layer; performing a first anisotropic etching process to remove the second metal barrier material layer on the horizontal plane, leaving the second metal barrier layer on the inner sidewall of the dielectric barrier material layer; and performing a second anisotropic etching process to remove the dielectric barrier material layer not covered by the second metal barrier layer on the horizontal plane, leaving the dielectric barrier layer on the inner sidewall and the bottom surface of the groove .

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