TWI785236B - Gallium nitride transistor with improved termination structure - Google Patents

Abstract

A gallium nitride transistor includes one or more P-type hole injection structures that are positioned between the gate and the drain. The P-type hole injection structures are configured to inject holes in the transistor channel to combine with trapped carriers (e.g., electrons) so the electrical conductivity of the channel is less susceptible to previous voltage potentials applied to the transistor.

Description

GaN Transistor with Improved Termination Structure

The present invention relates generally to semiconductor devices, and in particular to gallium nitride (GaN) based devices.

In semiconductor technology, GaN is used to form various integrated circuit devices, such as high-power field effect transistors, metal insulator semiconductor field effect transistors (metal insulator semiconductor field effect transistors, MISFETs), high-frequency transistors, high-power Schottky base rectifier and high electron mobility transistor (high electron mobility transistor, HEMT). These devices can be formed by growing epitaxial layers, which can be grown on silicon, silicon carbide, sapphire, gallium nitride, or other substrates. Heteroepitaxial junctions of AlGaN and GaN are often used to form devices. This structure is known to form a two-dimensional electron gas (2DEG) with high electron mobility at the junction. Sometimes, additional layers are added to improve or modify the charge density and mobility of electrons in the 2DEG. In some applications, improved termination structures with improved reliability and/or performance of GaN devices may be desired.

Some embodiments of the present invention relate to gallium gallium nitride (GaN) based transistors that include one or more hole injection structures to mitigate trapped carriers causing current collapse influence. The GaN transistor includes source, gate and drain connections to the substrate. A channel is formed between the source and the drain and allows or blocks current flow through the channel depending on the voltage potential applied between the source and the gate. One or more p-type layers are formed on the substrate and positioned in the channel. The P-type layers are configured to inject holes in the channel to combine with and neutralize the trapped carriers. Neutralizing the trapped carriers makes the channel more conductive and less susceptible to previous voltage potentials applied to the transistor.

In some embodiments, a transistor includes a semiconductor substrate and a source region formed in the substrate and including a source electrode in contact with a portion of the substrate. A drain region is formed in the substrate and separated from the source region. A gate region is formed in the substrate and includes a gate stack in contact with a portion of the substrate, wherein the gate region is positioned between the source region and the drain region. A hole injection region is formed in the substrate and includes a P-type layer in contact with a portion of the substrate, wherein the hole injection region is located between the gate region and the drain region. A dielectric layer is formed over and in contact with a first portion of the P-type layer. a continuous metal layer (1) formed over and in contact with the drain region of the substrate to form a drain electrode, (2) formed over and in contact with a second portion of the p-type layer to form a hole An injection electrode is (3) formed over a portion of the dielectric layer in contact therewith to form a field plate for the hole injection region.

In some embodiments, the continuous metal layer extends across the drain region of the substrate, adjoins a first side surface of the P-type layer and extends across a first region of a top surface of the P-type layer. In various embodiments, the dielectric layer extends across a surface of the substrate, is adjacent to a second side surface of the P-type layer and extends across a second region of the top surface of the P-type layer. In some embodiments, the field plate extends across the dielectric layer and terminates before becoming coplanar with the second side surface of the P-type layer.

In some embodiments, the continuous metal layer is in ohmic contact with the P-type layer. exist In various embodiments, the transistor further includes a plurality of individual hole injection regions formed along a length of the drain region. In various embodiments, the hole injection region is a first hole injection region, and a second hole injection region is formed in the substrate and positioned between the first hole injection region and the gate region .

In some embodiments, the second hole injection region includes a P-type layer in contact with a portion of the substrate and not in ohmic contact with the continuous metal layer. In various embodiments, the continuous metal layer is formed over approximately one-half of a top surface of the P-type layer, and the dielectric layer is formed over a remaining portion of the top surface of the P-type layer. In some embodiments, the semiconductor substrate includes gallium nitride.

In some embodiments, a transistor includes a semiconductor substrate and a source region formed in the substrate and including a source electrode in contact with a portion of the substrate. A drain region is formed in the substrate and separated from the source region. A gate region is formed in the substrate and includes a gate stack in contact with a portion of the substrate, wherein the gate region is positioned between the source region and the drain region. A hole injection region is formed in the substrate and includes a P-type layer in contact with a portion of the substrate, wherein the hole injection region is located between the gate region and the drain region. A dielectric layer extends across a first region of a top surface of the P-type layer. a metal layer (1) extending across a drain region of the substrate to form a drain electrode, (2) extending across a second region of the top surface of the p-type layer to form a hole injection electrode, and ( 3) Extending across a portion of the dielectric layer to form a field plate.

In some embodiments, the field plate is a hole injection region field plate. In various embodiments, the metal layer extends across the drain region of the substrate, is adjacent to a first side surface of the P-type layer, and extends across the second region of the top surface of the P-type layer to form The holes are injected into the electrodes. In some embodiments, the dielectric layer extends across a surface of the substrate, together with the P-type layer The second side surface of the P-type layer is adjacent to and extends across the first region of the top surface of the P-type layer. In various embodiments, the field plate extends across the first region of the dielectric layer and terminates before becoming coplanar with the second side surface of the p-type layer.

In some embodiments, the metal layer is in ohmic contact with the P-type layer. In various embodiments, the transistor further includes a plurality of individual hole injection regions formed along a length of the drain region. In some embodiments, the hole injection region is a first hole injection region, and a second hole injection region is formed in the substrate and positioned between the first hole injection region and the gate region . In various embodiments, the second hole injection region includes a P-type layer in contact with a portion of the substrate and not in ohmic contact with the continuous metal layer.

In some embodiments, a transistor includes a semiconductor substrate and a source region formed in the substrate and including a source electrode in contact with a portion of the substrate. A drain region is formed in the substrate and separated from the source region. A gate region is formed in the substrate and includes a gate stack in contact with a portion of the substrate, wherein the gate region is positioned between the source region and the drain region. A floating hole injection region is formed in the substrate and includes a P-type layer in contact with a portion of the substrate, wherein the hole injection region is located between the gate region and the drain region.

For a better understanding of the nature and advantages of the present invention, reference should be made to the following description and accompanying drawings. It should be understood, however, that each of the drawings is provided for the purpose of illustration only and is not intended as a definition of the limits of the scope of the invention. Also, in general, and unless it is evident to the contrary from the description that elements are generally identical or at least similar in function or purpose, elements in different figures in the description use the same reference numerals.

100: Transistor

105: Substrate

110: Effect area

115: Inactive area

120: source terminal

125: gate terminal

130: drain terminal

205: Transistor unit

210: source region

215: gate area

220: Drain area

225: Drift zone

230: Hole injector

235: Source bus bar

240: Gate busbar

245: drain bus

305: first floor

310: second floor

315: third floor

320: gate stack

323: ohmic metal layer

325: P-type layer

327: Source ohmic contact

330: Source ohmic pad

333: drain contact/drain electrode

335: Drain ohmic pad

340: metal layer/MG layer

345: metal layer/M0 layer

350: metal layer/M1 layer

355: Metal layer/M2 layer

360: through hole

365: source field plate

370: gate electrode

375: Hole Injection Electrode

380: M0 source field plate

385:M0 drain field plate/second field plate

390: M1 source field plate

395:M1 middle drain plate/third field plate

400: Transistor

430: Hole Injector

450: Gap

600: Transistor

630: Hole injector

805: P-type structure contact

900: Transistor

905: dielectric layer

910: opening

930: Hole injector

1100:transistor

1105: dielectric layer

1110a: P-type GaN structure

1110b: P-type GaN structure

1110c: P-type GaN structure

1130: Hole injector

1200: Transistor

1205: Floating P-type GaN structure

1300: Transistor

1305: Floating P-type GaN structure

1400: Transistor

1405: P-type GaN structure

1500: Transistor

1505: Ohmic contact area

1510: dielectric layer

1515: field board

1530: Hole injector

1535: Symmetry line

1540: High field strength area

1545: Floating Hole Injector

1550: source side edge

1600: Transistor

1605: Substrate

1610: Source Ohmic Metal Pad

1615: gate electrode

1620:Drain ohmic metal pad/drain

1625: Interacting two-dimensional electron gas (2DEG) region

1630a: P-type GaN island

1630b: P-type GaN island

1635: District

A-A: line

B-B: cross section

C-C: Partial cross-sectional view

1 illustrates a simplified plan view of a GaN-based semiconductor transistor 100 in accordance with an embodiment of the present invention; 2 illustrates an enlarged partial plan view of the active region of the GaN-based semiconductor transistor shown in FIG. 1; FIG. 3 illustrates a partial cross-sectional view across line A-A on the transistor cell illustrated in FIG. 2; FIG. A simplified plan view of the drain region of a GaN-based transistor according to an embodiment of the invention; FIG. 5 illustrates a partial cross-sectional view across the transistor shown in FIG. 4; FIG. 6 illustrates a GaN-based transistor according to an embodiment of the invention. Simplified plan view of the drain region of the crystal; FIG. 7 illustrates a partial cross-sectional view across the transistor shown in FIG. 6; FIG. 8 illustrates cross-section B-B of the transistor shown in FIG. 7; FIG. Partial cross-sectional view of a GaN-based transistor of an embodiment; FIG. 10 illustrates a partial cross-sectional view C-C across the transistor shown in FIG. 9; FIG. 11 illustrates a portion of a GaN-based transistor according to an embodiment of the invention Cross-sectional view; FIG. 12 illustrates a simplified plan view of a GaN-based transistor according to an embodiment of the invention; FIG. 13 illustrates a simplified plan view of a GaN-based transistor according to an embodiment of the invention; FIG. 14 illustrates an implementation according to the invention Simplified plan view of an example GaN-based transistor; FIG. 15 illustrates a portion of a GaN-based transistor according to an embodiment of the invention cross-sectional view; and FIG. 16 illustrates a plan view of a GaN-based transistor according to an embodiment of the present invention.

Cross References to Related Applications

This application claims the priority of U.S. Provisional Patent Application No. 62/661,585, "GALLIUM NITRIDE TRANSISTOR WITH IMPROVED TERMINATION," filed on April 23, 2018. The U.S. Provisional Patent Application This case is hereby incorporated by reference in its entirety for all purposes.

Certain embodiments of the present invention relate to GaN-based enhancement mode field effect transistors having a hole injection structure that injects holes in the channel to alleviate "current collapse" in the transistor. Current collapse is an undesirable "memory" effect in which the conduction current of a device may depend on previously applied voltages and also on how long those previously applied voltages existed. More specifically, during operation of the transistor, electrons (called trapped carriers) are trapped in the epitaxial layer and/or dielectric layer and repel other electrons flowing through the transistor channel, making It is more difficult to conduct current through the 2DEG layer, causing the resistance across the channel to increase. In some embodiments, one or more hole injection structures are added to inject holes in the channel so that the holes combine with and neutralize the trapped electrons. Fewer trapped electrons lead to lower resistance in the channel, thereby mitigating the memory effect.

Some embodiments of the present invention relate to GaN-based transistors having a P-type hole injection structure formed adjacent to a drain contact. The hole injection electrode can be formed on the P-type hole injection structure, so the hole injection electrode is electrically coupled to the drain ohmic metal. In other embodiments, the P-type hole injection structure can be electrically isolated from the drain ohmic metal, and can be capacitively coupled to the drain ohmic metal. belongs to.

In order to better understand the characteristics and aspects of GaN-based transistors with P-type hole injection structures according to the present invention, the following sections are provided by discussing some specific implementations of semiconductor devices according to embodiments of the present invention. Other content background of the present invention. These embodiments are merely examples, and other embodiments may be used in other semiconductor devices, such as, but not limited to, gallium arsenide, indium phosphide, and other types of semiconductor materials.

FIG. 1 illustrates a simplified plan view of a GaN-based transistor 100 . As shown in FIG. 1 , the transistor 100 is constructed on a substrate 105 . Transistor 100 may have an active region 110 surrounded by an inactive region 115 including a source terminal 120, a gate terminal 125, and a drain terminal 130 for forming electrical connections to the transistor. Active region 110 may have one or more transistor "cells" that repeat across the active region, as discussed in more detail herein. Transistor 100 is an illustrative example of a GaN transistor with a hole injector in accordance with an embodiment of the present invention, but those skilled in the art will appreciate that in other embodiments GaN transistor 100 may have features different from those described herein. The size, shape and configuration of the specific examples set forth herein, and the present invention is in no way limited to the examples set forth herein.

2 illustrates an enlarged partial plan view of a drain region 220 of a GaN-based transistor that may form a portion of active region 110 of transistor 100 in FIG. 1 . 3 illustrates a partial cross-sectional view across line A-A of drain region 220 of FIG. 2 and also shows a cross-sectional view of source region 210 and gate region 215 of transistor cell 205 . The following description will refer to FIG. 2 and FIG. 3 at the same time.

In some embodiments, the drift region 225 is disposed between the source region 210 and the drain region 220 to withstand high voltages. A channel region is formed in the 2DEG under the gate stack 320 and is configured to block or conduct current depending on the voltage applied between the gate terminal 125 (see FIG. 1 ) and the source terminal 120 . One or more hole injectors 230 are positioned adjacent to the drift region 225 and are configured to inject electrical Holes are injected into the channel to combine with the trapped electrons, as described in more detail below.

As illustrated in FIG. 3 , in some embodiments, the substrate 105 may include a first layer 305 that may include silicon carbide, sapphire, aluminum nitride, or other materials. The second layer 310 is disposed on the first layer 305 and may include gallium nitride or other materials. The third layer 315 is disposed on the second layer 310 and may include other Group III nitrides such as, but not limited to, Aluminum Nitride, Indium Nitride, and Group III Nitrides such as Aluminum Gallium Nitride and Indium Gallium Nitride. Composite stacking of alloys. In one embodiment, the third layer 315 is Al _0.20 Ga _0.80 N.

In some embodiments, a two-dimensional electron gas (2DEG) sensing layer is formed within the substrate 105 and may be positioned adjacent to the interface between the second layer 310 and the third layer 315 . In some embodiments, the 2DEG layer is induced by a combination of piezoelectric effects (stress), bandgap differentials, and/or polarized charges. For example, there may be a reduction in the conduction band at the surface, where it drops below the Fermi level to create a potential well filled with electrons. In some embodiments, the 2DEG sensing layer comprises AlGaN in the range of Al _0.25 Ga _0.75 N, for example, about 20 nm thick. In alternative embodiments, the 2DEG sensing layer may comprise AlN, AlGaInN, or another material. In some embodiments, the 2DEG sensing layer includes a thin boundary layer with high Al content and a thicker layer with less Al content. In some embodiments, the 2DEG sensing layer may have a GaN capping layer, while in other embodiments, the 2DEG sensing layer may not have a GaN capping layer.

In some embodiments, one or more gate stacks 320 are formed on the substrate 105 to form gate structures. For example, gate stack 320 may include several compound semiconductor layers (eg, 3N layers), each of which may include nitrogen and one or more elements from the third row of the periodic table, such as aluminum or gallium or indium, etc. Wait. These layers can be doped or undoped. If these layers are doped, they may be doped with N-type or P-type dopants. In some embodiments, the gate stack 320 can be an insulated gate, a Schottky gate, a PN gate, a recessed gate, or other types of gates.

In some embodiments, one or more hole injectors 230 are formed on the substrate 105 . The hole injector 230 may be formed with a P-type layer 325 disposed on the substrate 105 . In some embodiments, the P-type layer 325 may be formed using gallium nitride doped with a P-type dopant, which may be magnesium, as a non-limiting example. P-type layer 325 may act as a hole injector during operation of the semiconductor device to improve the performance and/or reliability of transistor 100, as described in more detail herein.

Ohmic metal layer 323 may be deposited and patterned to form ohmic contacts to substrate 105 , including source ohmic contact 327 formed between source ohmic pad 330 and substrate 105 , source ohmic contact 327 formed between drain ohmic pad 335 and Drain contact 333 between substrate 105, and other required areas. In some embodiments, the ohmic metal layer 323 may include aluminum, titanium, nickel, gold, or other metals. After depositing and patterning the ohmic metal layer 323, the ohmic metal layer can be annealed to form a low resistance electrical connection between the remaining ohmic metal and the 2DEG sensing layer that can be exposed in the ohmic contact regions (eg, source and drain) pieces.

Additional sequentially deposited metal layers may include MG layer (gate metal layer) 340, M0 layer 345, M1 layer 350, M2 layer 355, etc., which may be patterned using commercially available processes. To electrically insulate metal layers 340, 345, 350, and 355 from each other and/or from substrate 105, one or more intervening dielectric layers may be used. In some embodiments, the dielectric layer may include, but is not limited to, silicon nitride (eg, Si3N4, Si2N, or SN) or silicon oxide (eg, SiO2 or the like), which may be deposited and patterned. In some embodiments, the intervening dielectric layers each comprise only a single layer of insulator material, while in other embodiments each layer may comprise a plurality of layers. For example, chemical mechanical polishing or other techniques may be used to planarize the insulator layer.

In some embodiments, the MG layer 340 may be used to form the MG source field plate 365 , the gate electrode 370 and the hole injection electrode 375 . In various embodiments, hole injection electrodes 375 may be positioned in close proximity to and in electrical contact with drain ohmic pad 335 so that hole injector 230 and drain ohmic pad 335 have substantially the same voltage.

In some embodiments, M0 layer 345 may be used to form M0 source field plate 380 and M0 drain field plate 385 . In various embodiments, M1 layer 350 may be used to form M1 source field plate 390 and M1 intermediate drain plate 395 . In some embodiments, M2 layer 355 may be used to form source bus 235 , gate bus 240 and drain bus 245 . A source bus 235 electrically couples the source ohmic pad 330 of each transistor cell 205 to the source terminal 120 (see FIG. 1 ). Gate bus 240 electrically couples gate electrode 370 of each transistor cell 205 to gate terminal 125 (see FIG. 1 ). Drain bus 245 electrically couples drain ohmic pad 335 of each transistor cell 205 to drain terminal 130 (see FIG. 1 ).

In some embodiments, one or more vias 360 may be formed through one or more of the intervening insulator layers to electrically connect the one or more metal layers 340, 345, 350, and 355 to each other.

In some embodiments, transistor 100 responds to an applied electric field under gate stack 320 to control the conductivity of the underlying 2DEG channel. The conductivity of the channel is dependent on the voltage potential applied between gate terminal 125 (see FIG. 1 ) and source terminal 120 . The gate terminal 125 can be considered to control the opening and closing of the physical gate. The voltage applied to gate terminal 125 allows electrons and/or holes to flow between source terminal 120 and drain terminal 130 or blocks their passage by creating or eliminating a 2DEG channel under the gate. The conductivity of the channel is affected by the magnitude of the applied voltage potential between gate terminal 125 (see FIG. 1 ) and source terminal 120 .

In some embodiments, during operation of transistor 100, electrons (commonly referred to as "trapped carriers") are trapped and repelled in the epitaxial and/or dielectric layers within substrate 105. Other electrons flow through the drift region 225 , thereby more preventing current from flowing between the source terminal 120 and the drain terminal 130 . This phenomenon causes an increase in resistance (eg, an increase in R _DS ON ) in the drift region 225 and is often referred to as "dynamic Rdson" or "current collapse." Dynamic Rdson is an undesirable "memory" effect in which the conduction current of the device may depend on previously applied voltages between source terminal 120 and drain terminal 130, and also on how long these previously applied voltages existed.

More specifically, when the transistor is turned on again after being turned off, the resistance of the drift region 225 may increase for a certain period of time. In order to prevent the dynamic Rdson increase, in the embodiments illustrated in FIGS. 1 and 2, a plurality of hole injector 230 islands of P-type GaN are placed next to the drain ohmic pad 335 and electrically coupled to the drain Ohmic metal, hole injection electrodes 375 are formed in the MG layer 340 . Each hole injector 230 injects holes into the drift region 225 near the drain region 220 . The holes combine with the trapped electrons and neutralize them, preventing or at least moderating the collapse of the current flow.

In one embodiment, each hole injector 230 island may be between 0.5 and 5 microns square, but in other embodiments each island may be between 0.75 and 2 microns square, and in one implementation In one example, each island is between 0.9 and 1.1 square microns, however, those skilled in the art will appreciate that the present invention is not limited to square geometries or the aforementioned dimensions, and electrodes having other geometries and/or dimensions may be used. hole injector.

As discussed above with respect to FIG. 1 , transistor 100 may be configured in a repeating unit, examples of which are illustrated in FIGS. 2 and 3 . Each cell may include a source, a gate, a drain and one or more hole injection structures. Adjacent cells may use the same drain and may have their own gate and source terminals. Similarly, adjacent cells can use the same source and have their own drain terminals. In some embodiments, the transistor structure includes a plurality of interdigitated source and drain fingers, and a gate structure is disposed between each source finger and drain finger. Thus, as shown in FIG. 3 , drift region 225 may be formed on either side of drain region 220 .

4 illustrates a simplified plan view of a drain region 220 of a GaN-based transistor 400 according to another embodiment of the present invention. Transistor 400 is constructed similarly to transistor 100 illustrated in FIGS. 1-3 (like numerals refer to like elements), however, transistor 400 has a plurality of capacitively coupled hole injectors, as described in more detail below. . 5 illustrates a partial cross-sectional view across transistor 400, the cross-section being made in a region of the transistor similar to the cross-section illustrated in FIG. 3 (like numbers refer to like elements). The following description will refer to FIG. 4 and FIG. 5 at the same time.

Similar to the embodiment illustrated in FIGS. 1-3 , transistor 400 includes one or more hole injectors 430 formed on substrate 105 . The hole injector 430 may be formed with a P-type layer 325 disposed on the substrate 105 . In some embodiments, the p-type layer 325 may be formed using aluminum gallium nitride or a combination of gallium nitride doped with a p-type dopant such as magnesium. P-type layer 325 may act as a hole injector during operation of the semiconductor device to improve the performance and/or reliability of transistor 400, as described in more detail herein.

Compared with transistor 100 in FIGS. 1-3 , transistor 400 in FIGS. 4 and 5 includes hole injector 430 but does not have hole injection electrode 375 (see FIG. 3 ) and hole injector 430 The spacing away from the drain ohmic pad 335 electrically isolates the hole injector 430 from the drain ohmic pad 335 . More specifically, hole injector 430 of transistor 400 includes only P-type layer 325 and no hole injector electrode (eg, no metal present on top of P-type layer 325). Additionally, the hole injector 430 of the transistor 400 includes a gap 450 positioned between the P-type layer 325 and the drain ohmic pad 335, wherein the gap is filled with a dielectric material that creates an electrically floating hole injector. As used herein, the term "floating hole injector" shall mean that the hole injection structure (e.g., a P-type GaN region) is not ohmically coupled to the source, gate or drain electrodes, but is instead capacitively coupled The combination of direct or capacitive coupling and leakage current enables the floating hole injector to inject holes in the drift region 225 .

6 illustrates a simplified plan view of a drain region 220 of a GaN-based transistor 600 according to another embodiment of the present invention. Transistor 600 is constructed similarly to transistor 100 illustrated in FIGS. 1-3 (like numerals refer to like elements), however, transistor 600 has a plurality of hole injectors 630 in the shape of bars, and the drain ohmic metal Acting as both a drain ohmic electrode and a hole injector electrode, as described in more detail below. 7 illustrates a partial cross-sectional view across a transistor 600, made in a region of the transistor similar to the cross-section illustrated in FIG. 3 (like numbers refer to like elements). The following description will refer to both FIG. 6 and FIG. 7 .

Similar to the embodiments illustrated in FIGS. 1-3 , transistor 600 includes one or more hole injectors 630 formed on substrate 105 . The hole injector 630 may be formed with a P-type layer 325 disposed on the substrate 105, however, instead of being a square island positioned on either side of the drain contact 333, the P-type layer is disposed across the drain contact Extending and extending into repeating strips of drift region 225 formed on either side of the drain contact.

Compared to transistor 100 in FIGS. 1-3 , transistor 600 in FIGS. 6 and 7 includes hole injector 630 but does not have hole injection electrode 375 formed separately as shown in FIG. 3 . More specifically, the drain ohmic pad 335 forms both the drain ohmic contact 333 and the hole injection electrode. This is more clearly illustrated in FIG. 8, which is cross-section B-B of transistor 600 illustrated in FIG. As shown in FIG. 8 , repeating P-type layers 325 are formed on the substrate 105 . The drain ohmic pad 335 is in contact with both the drain contact 333 and the P-type structure contact 805 . Therefore, the drain ohmic pad 335 electrically couples the P-type layer 325 to the drain contact 333 .

FIG. 9 illustrates a partial cross-sectional view of a GaN-based transistor 900 according to another embodiment of the invention. Transistor 900 is constructed similarly to transistor 600 illustrated in FIGS. 6-8 (like numbers refer to like elements), however, transistor 900 has dielectric layer 905 formed over P-type layer 325 in the shape of a stripe, And the drain ohmic pad 335 serves as the drain ohmic electrode and the hole injection Both implant electrodes, as described in more detail below. FIG. 10 illustrates a partial cross-sectional view C-C across the transistor 900 illustrated in FIG. 9 . The following description will refer to FIG. 9 and FIG. 10 at the same time.

Similar to the embodiments illustrated in FIGS. 6-8 , transistor 900 includes one or more hole injectors 930 formed on substrate 105 . The hole injector 930 may be formed with a P-type layer 325 disposed on the substrate 105 . P-type layer 325 may be disposed in repeating strips extending across drain contact 333 and into drift region 225 formed on either side of the drain contact.

Compared to transistor 600 in FIGS. 6-8 , transistor 900 in FIGS. 9 and 10 includes dielectric layer 905 formed over P-type layer 325 and portions of substrate 105 . An opening 910 is formed in the dielectric layer 905 and a drain ohmic pad 335 is formed on top of the dielectric layer and within the opening 910 to make electrical contact with the P-type layer 325 . In some embodiments, opening 910 may extend across the space between P-type layers 325, thereby exposing a portion of substrate 105 so that drain ohmic pad 335 may form drain contact 333 between each P-type layer. . Other embodiments may have different configurations of openings formed in the dielectric layer 905 such that the drain ohmic pad 335 may form both the hole injector electrode and the drain electrode. Since the drain ohmic pad 335 is in contact with both the drain contact 333 and the P-type layer 325 , the drain ohmic metal layer electrically couples the P-type layer 325 to the drain contact 333 .

11 illustrates a partial cross-sectional view of a GaN-based transistor 1100 according to another embodiment of the invention. Transistor 1100 is constructed similarly to transistor 900 illustrated in FIG. 9 and FIG. , as described in more detail below.

Similar to the embodiments illustrated in FIGS. 9 and 10 , transistor 1100 includes one or more hole injectors 1130 formed on substrate 105 . The hole injector 1130 can be formed with a P-type layer 325 disposed on the substrate 105 . P-type layer 325 may be configured in repeating islands disposed on either side of drain contact 333 . Transistor 1100 includes a dielectric layer covering the entirety of each p-type layer 325 1105, so it is electrically insulated from the drain ohmic pad 335. A drain ohmic pad 335 extends between the P-type layers 325 to make contact with the substrate 105 forming the drain contact 333 . The drain ohmic pad 335 also extends over the top of the P-type layer 325 with the dielectric layer 1105 positioned between the drain-ohmic metal layer and the P-type layer. Therefore, the hole injector 1130 is electrically insulated from the drain ohmic pad 335 , and the hole injector uses capacitive coupling to the drain ohmic pad 335 to enable the P-type layer 325 to inject holes in the drift region 225 .

Continuing to refer to FIG. 11 , in some embodiments, the electric field at the drain edges of source field plates 365, 380, and/or 390 may be higher than the surrounding regions, and as a result these regions may cause trapped Higher concentration of carriers. Thus, in some embodiments, positioning one or more floating P-type GaN structures 1110 a . Efficient and/or effective neutralization of carriers.

More specifically, in some embodiments, floating P-type GaN structures 1110a . . . 1110c are configured to inject holes in drift region 225 in the presence of a high electric field, as further described herein and in FIGS. 13 and 14 . A detailed description. In some embodiments, P-type GaN structures 1110a . . . 1110c may be formed using gallium nitride doped with a P-type dopant, which may be, for example, magnesium.

FIG. 12 illustrates a simplified plan view of a GaN-based transistor 1200 according to another embodiment of the invention. Transistor 1200 is constructed similarly to transistor 1100 illustrated in FIG. 11 (like numbers refer to like elements), however, instead of having a plurality of floating P-type GaN structure, transistor 1200 has a plurality of floating P-type GaN structures 1205 positioned under and aligned with the drain edge of a single source field plate 380 . More specifically, in the embodiment illustrated in FIG. 12, in the drift region 225, a plurality of floating P-type GaN structures 1205 are partially positioned under the M0 source field plate 380 and completely positioned under M1 source field plate 390 under. In other embodiments, the floating P-type GaN structure 1205 may be placed within the drift region 225 in a different position than that shown in FIG. 12 . In some embodiments, the floating P-type GaN structure 1205 may perform the same function as the P-type GaN structure 325 described in more detail above (see FIG. 11 ). In some embodiments, the floating P-type GaN structure 1205 may be formed using gallium nitride doped with a P-type dopant, which may be, for example, magnesium.

13 illustrates a simplified plan view of a GaN-based transistor 1300 according to another embodiment of the invention. Transistor 1300 is constructed similarly to transistor 1100 illustrated in FIG. 11 (like numbers refer to like elements), however, instead of having a plurality of floating P-type GaN structure, transistor 1300 has a plurality of floating P-type GaN structures 1305 positioned under and aligned with the drain edge of a single source field plate 390 . More specifically, in the illustrated embodiment, in FIG. 13 , a plurality of floating P-type GaN structures 1305 are positioned partially under M1 source field plate 390 in drift region 225 . In other embodiments, the floating P-type GaN structure 1305 may be placed within the drift region 225 in a different position than that shown in FIG. 13 . In some embodiments, the floating P-type GaN structure 1305 may perform the same function as the P-type GaN structure 325 described in more detail above (see FIG. 11 ). In some embodiments, the floating P-type GaN structure 1305 may be formed using gallium nitride doped with a P-type dopant, which may be, for example, magnesium.

14 illustrates a simplified plan view of a GaN-based transistor 1400 according to another embodiment of the invention. Transistor 1400 is constructed similarly to transistor 100 illustrated in FIGS. 1-3 (like numerals refer to like elements), however, transistor 1400 has a gate electrode 370 in drift region 225 adjacent to the source field Plates 365, 380 and 390 and a plurality of P-type GaN structures 1405 positioned thereunder. In the illustrated embodiment, in FIG. 14, the P-type GaN structure 1405 is centered on the first edge of the MG source field plate 365 closest to the gate electrode 370, however, on its In other embodiments, it may be positioned anywhere adjacent to the gate electrode 370 .

In some embodiments, the P-type GaN structure 1405 can adopt a potential close to the gate electrode by capacitive coupling or leakage. Trapping of electrons can be caused by high electric fields that accelerate hot electrons into the dielectric or substrate region. The P-type GaN structure 1405 can prevent high voltages and high electric fields in the drift region from reaching the gate region and reduce the amount of trapping that occurs in that region. This reduced carrier injection can reduce the dynamic Rdson effect and increase the lifetime of the product. Although transistor 1400 is similar to transistor 100 illustrated in FIGS. Or the structure of 1100 or any other configuration.

15 illustrates a partial cross-sectional view of a GaN-based transistor 1500 according to another embodiment of the invention. Transistor 1500 is constructed similarly to transistor 1100 illustrated in FIG. 11 (like numerals refer to like elements), which includes a P-type layer ohmically coupled to the drain terminal, however, transistor 1500 has a layer covering only P-type layer 325. A portion of the dielectric layer 1510 and the drain ohmic pad 335 are in ohmic contact with the P-type layer, as described in more detail below. Additionally, transistor 1500 includes a floating hole injector 1545 positioned on the source side of drain contact 333 .

Similar to the embodiment illustrated in FIG. 11 , transistor 1500 includes one or more hole injectors 1530 formed on substrate 105 . Each hole injector 1530 may be formed with a P-type layer 325 disposed on the substrate 105 . In FIG. 15, the line of symmetry 1535 is used to show only the right portion of the mirror image of the left and right portions of the drain region. P-type layer 325 may be configured in repeating islands disposed on both sides (ie, left and right) of drain contact 333 .

Transistor 1500 includes a dielectric layer 1510 covering a portion of each P-type layer 325 , the remainder of each P-type layer forming an ohmic contact region 1505 with drain resistor pad 335 . In the illustrated embodiment, in FIG. 15, the dielectric layer 1510 covers approximately half of the P-type layer 325. One, however in other embodiments it may cover more or less than half of the p-type layer.

In some embodiments, the drain ohmic pad 335 can be configured as a continuous metal layer that is (1) formed over and in contact with the drain region 220 of the substrate 105 to form the drain electrode 333, (2) formed on A second portion of the p-type layer 325 is formed over and in contact with a hole injection electrode 375, and (3) a portion of the dielectric layer 1510 is formed over and in contact with a portion of the dielectric layer 1510 to form a field plate 1515 for the hole injection region. In other embodiments, one or more separate but electrically coupled metal layers may be used instead of the aforementioned continuous metal layer. In the illustrated embodiment, in FIG. 15 , field plate 1515 extends across at least a portion of dielectric layer 1510 , and in some embodiments until it is coplanar with source-side edge 1550 of P-type layer 325 , In other embodiments, it extends past the source side edge of the P-type layer 325 . In one embodiment, the field plate 1515 extends between 0.125 and 2 microns beyond the source side edge 1550 of the P-type layer, but in other embodiments it extends beyond between 0.2 and 0.75 microns.

In some embodiments, a plurality of individual hole injectors 1530 are formed along the length of the drain region 220, thereby forming a series of sequential hole injector islands. Drain ohmic pads 335 may also extend between individual P-type layers 325 to make contact with the substrate 105 forming part of the drain contacts 333, similar to the structure illustrated in FIG. 10 .

In some embodiments, the second field plate 385 can be positioned above the field plate 1515 and the third field plate 395 can be positioned above the second field plate. The distal ends of the field plates 1515, 385, and 395 may create a region of high field strength 1540 identified by a dashed circle.

In some embodiments, the optional floating hole injector 1545 may be formed from a portion of the P-type layer 325 . The floating hole injector 1545 is non-ohmically coupled to the drain ohmic pad 335 and capacitively coupled to the drain ohmic pad. Floating hole injector 1545 may be positioned between hole injector 1530 and the gate region (see FIG. 11 ).

FIG. 16 illustrates a plan view of a GaN-based transistor 1600 according to another embodiment of the invention. Transistor 1600 is constructed similar to transistor 100 illustrated in FIGS. 1-3 , however, transistor 1600 includes a gate structure formed using P-type GaN islands, as described in more detail below. A GaN-based transistor 1600 is fabricated on a substrate 1605, which may be similar to substrate 105 in FIG. between metal pads. Under the gate electrode 1615, one or more P-type GaN islands 1630a, 1630b may be disposed on the substrate 1605 with a gap therebetween. In various embodiments, a single gate electrode 1615 can be formed across one or more P-type GaN islands 1630a, 1630b, and a contact between the gate electrode and the P-type GaN islands can be formed.

When zero voltage is applied to the gate electrode 1615 relative to the source ohmic metal pad 1610 , current flows through the 2DEG layer between the P-type GaN islands 1630 a , 1630 b in region 1635 . When a positive gate voltage is applied, a 2DEG is formed under the P-type GaN islands 1630a, 1630b, and current can flow under the gate across the entire width of the active 2DEG region. If the gate electrode 1615 is negatively biased relative to the source ohmic metal pad 1610, the gap between the P-type GaN islands 1630a, 1630b will form a reverse-biased junction around the P-type GaN islands. This reverse bias condition forms a depletion region around each P-type GaN island 1630a, 1630b and restricts electron flow through region 1635. The more negative gate electrode 1615 is biased against source ohmic metal pad 1610, the more resistive region 1635 becomes until transistor 1600 pinches off all current flow. Thus, the P-type GaN islands 1630a, 1630b form gate structures that control the flow of current through the transistor channel. This also allows the structure to block the voltage applied to the drain 1620 and thus limit the electric field on the source side of the gate. This is a similar electric field confinement effect achieved by the floating P-type GaN structure 1205 illustrated in FIG. 12 .

In the foregoing specification, embodiments of the invention have been described with reference to numerous specific details that may vary from implementation to implementation. Therefore, it should be used in an illustrative rather than restrictive sense Treat instructions and diagrams in a sense. The single and exclusive indicator of the scope of the invention and what is contemplated by the applicant to be the scope of the invention is the literal and equivalent of the set of claims in this application in the specific form that yields such claimed scope including any subsequent correction. effect range.

100: Transistor

105: Substrate

110: Effect area

115: Inactive area

120: source terminal

125: gate terminal

130: drain terminal

Claims (18)

A transistor comprising: a semiconductor substrate; a source region formed in the substrate and including a source electrode in contact with a portion of the substrate; a drain region formed in the substrate and connected to the substrate The source region is separated; a gate region is formed in the substrate and includes a gate stack in contact with a portion of the substrate, the gate region is positioned between the source region and the drain region; an electrical A hole injection region, which is formed in the substrate and includes a P-type layer in contact with a part of the substrate, the hole injection region is positioned between the gate region and the drain region; a dielectric layer, formed over and in contact with a first portion of the p-type layer; and a continuous metal layer made of a homogeneous material, and the homogeneous material (1) is formed over and in contact with the drain region of the substrate to forming a drain electrode, (2) formed over and in direct contact with a second portion of the p-type layer to form a hole injection electrode, and (3) formed over a portion of the dielectric layer in contact with it to form A field plate for the hole injection region. The transistor of claim 1, wherein the continuous metal layer extends across the drain region of the substrate, adjoins a first side surface of the P-type layer and spans a first region of a top surface of the P-type layer extend. The transistor of claim 2, wherein the dielectric layer extends across a surface of the substrate, adjoins a second side surface of the P-type layer and extends across a second region of the top surface of the P-type layer. The transistor of claim 3, wherein the field plate extends across the dielectric layer and terminates before becoming coplanar with the second side surface of the P-type layer. The transistor according to claim 1, wherein the continuous metal layer is in ohmic contact with the P-type layer. The transistor according to claim 1, further comprising a plurality of individual hole injection regions formed along a length of the drain region. The transistor according to claim 1, wherein the hole injection region is a first hole injection region, and a second hole injection region is formed in the substrate and positioned between the first hole injection region and the gate between districts. The transistor according to claim 7, wherein the second hole injection region includes a P-type layer in contact with a portion of the substrate and not in ohmic contact with the continuous metal layer. The transistor of claim 1, wherein the continuous metal layer is formed over about one-half of a top surface of the p-type layer, and the dielectric layer is formed over a remaining portion of the top surface of the p-type layer above. The transistor according to claim 1, wherein the semiconductor substrate comprises gallium nitride. A transistor comprising: A semiconductor substrate; a source region formed in the substrate and including a source electrode in contact with a portion of the substrate; a drain region formed in the substrate and separated from the source region; a gate a pole region formed in the substrate and including a gate stack in contact with a portion of the substrate, the gate region positioned between the source region and the drain region; a hole injection region formed in The substrate includes a P-type layer in contact with a portion of the substrate, the hole injection region is positioned between the gate region and the drain region; a dielectric layer spans a top of the P-type layer a first region of the surface extends; and a metal layer (1) extends across a drain region of the substrate to form a drain electrode, (2) adjoins a first side surface of the p-type layer, and A second region directly contacting the top surface of the p-type layer extends to form a hole injection electrode, and (3) extends across a portion of the dielectric layer to form a field plate. The transistor according to claim 11, wherein the field plate is a field plate in a hole injection region. The transistor of claim 11, wherein the dielectric layer extends across a surface of the substrate, is adjacent to a second side surface of the P-type layer and extends across the first region of the top surface of the P-type layer. The transistor of claim 13, wherein the field plate extends across the first region of the dielectric layer and terminates before becoming coplanar with the second side surface of the P-type layer. The transistor according to claim 11, wherein the metal layer is in ohmic contact with the P-type layer. The transistor according to claim 11, further comprising a plurality of individual hole injection regions formed along a length of the drain region. The transistor according to claim 11, wherein the hole injection region is a first hole injection region, and a second hole injection region is formed in the substrate and positioned between the first hole injection region and the gate between districts. The transistor according to claim 17, wherein the second hole injection region includes a P-type layer in contact with a portion of the substrate and not in ohmic contact with the continuous metal layer.

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